2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
71 #include <sys/param.h>
73 #include <sys/endian.h>
74 #include <sys/interrupt.h>
75 #include <sys/kernel.h>
77 #include <sys/malloc.h>
81 #include <sys/serialize.h>
82 #include <sys/serialize2.h>
83 #include <sys/socket.h>
84 #include <sys/sockio.h>
85 #include <sys/sysctl.h>
86 #include <sys/systm.h>
89 #include <net/ethernet.h>
91 #include <net/if_arp.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
94 #include <net/ifq_var.h>
95 #include <net/toeplitz.h>
96 #include <net/toeplitz2.h>
97 #include <net/vlan/if_vlan_var.h>
98 #include <net/vlan/if_vlan_ether.h>
99 #include <net/if_poll.h>
101 #include <netinet/in_systm.h>
102 #include <netinet/in.h>
103 #include <netinet/ip.h>
104 #include <netinet/tcp.h>
105 #include <netinet/udp.h>
107 #include <bus/pci/pcivar.h>
108 #include <bus/pci/pcireg.h>
110 #include <dev/netif/ig_hal/e1000_api.h>
111 #include <dev/netif/ig_hal/e1000_82571.h>
112 #include <dev/netif/emx/if_emx.h>
115 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
117 if (sc->rss_debug >= lvl) \
118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
120 #else /* !EMX_RSS_DEBUG */
121 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
122 #endif /* EMX_RSS_DEBUG */
124 #define EMX_NAME "Intel(R) PRO/1000 "
126 #define EMX_DEVICE(id) \
127 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
128 #define EMX_DEVICE_NULL { 0, 0, NULL }
130 static const struct emx_device {
135 EMX_DEVICE(82571EB_COPPER),
136 EMX_DEVICE(82571EB_FIBER),
137 EMX_DEVICE(82571EB_SERDES),
138 EMX_DEVICE(82571EB_SERDES_DUAL),
139 EMX_DEVICE(82571EB_SERDES_QUAD),
140 EMX_DEVICE(82571EB_QUAD_COPPER),
141 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
142 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
143 EMX_DEVICE(82571EB_QUAD_FIBER),
144 EMX_DEVICE(82571PT_QUAD_COPPER),
146 EMX_DEVICE(82572EI_COPPER),
147 EMX_DEVICE(82572EI_FIBER),
148 EMX_DEVICE(82572EI_SERDES),
152 EMX_DEVICE(82573E_IAMT),
155 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
156 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
157 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
163 /* required last entry */
167 static int emx_probe(device_t);
168 static int emx_attach(device_t);
169 static int emx_detach(device_t);
170 static int emx_shutdown(device_t);
171 static int emx_suspend(device_t);
172 static int emx_resume(device_t);
174 static void emx_init(void *);
175 static void emx_stop(struct emx_softc *);
176 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
177 static void emx_start(struct ifnet *);
179 static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
181 static void emx_watchdog(struct ifnet *);
182 static void emx_media_status(struct ifnet *, struct ifmediareq *);
183 static int emx_media_change(struct ifnet *);
184 static void emx_timer(void *);
185 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
186 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
187 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
189 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
193 static void emx_intr(void *);
194 static void emx_rxeof(struct emx_softc *, int, int);
195 static void emx_txeof(struct emx_softc *);
196 static void emx_tx_collect(struct emx_softc *);
197 static void emx_tx_purge(struct emx_softc *);
198 static void emx_enable_intr(struct emx_softc *);
199 static void emx_disable_intr(struct emx_softc *);
201 static int emx_dma_alloc(struct emx_softc *);
202 static void emx_dma_free(struct emx_softc *);
203 static void emx_init_tx_ring(struct emx_softc *);
204 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
205 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
206 static int emx_create_tx_ring(struct emx_softc *);
207 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
208 static void emx_destroy_tx_ring(struct emx_softc *, int);
209 static void emx_destroy_rx_ring(struct emx_softc *,
210 struct emx_rxdata *, int);
211 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
212 static int emx_encap(struct emx_softc *, struct mbuf **);
213 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
214 static int emx_txcsum(struct emx_softc *, struct mbuf *,
215 uint32_t *, uint32_t *);
217 static int emx_is_valid_eaddr(const uint8_t *);
218 static int emx_reset(struct emx_softc *);
219 static void emx_setup_ifp(struct emx_softc *);
220 static void emx_init_tx_unit(struct emx_softc *);
221 static void emx_init_rx_unit(struct emx_softc *);
222 static void emx_update_stats(struct emx_softc *);
223 static void emx_set_promisc(struct emx_softc *);
224 static void emx_disable_promisc(struct emx_softc *);
225 static void emx_set_multi(struct emx_softc *);
226 static void emx_update_link_status(struct emx_softc *);
227 static void emx_smartspeed(struct emx_softc *);
228 static void emx_set_itr(struct emx_softc *, uint32_t);
230 static void emx_print_debug_info(struct emx_softc *);
231 static void emx_print_nvm_info(struct emx_softc *);
232 static void emx_print_hw_stats(struct emx_softc *);
234 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
235 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
236 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
237 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
238 static void emx_add_sysctl(struct emx_softc *);
240 static void emx_serialize_skipmain(struct emx_softc *);
241 static void emx_deserialize_skipmain(struct emx_softc *);
243 /* Management and WOL Support */
244 static void emx_get_mgmt(struct emx_softc *);
245 static void emx_rel_mgmt(struct emx_softc *);
246 static void emx_get_hw_control(struct emx_softc *);
247 static void emx_rel_hw_control(struct emx_softc *);
248 static void emx_enable_wol(device_t);
250 static device_method_t emx_methods[] = {
251 /* Device interface */
252 DEVMETHOD(device_probe, emx_probe),
253 DEVMETHOD(device_attach, emx_attach),
254 DEVMETHOD(device_detach, emx_detach),
255 DEVMETHOD(device_shutdown, emx_shutdown),
256 DEVMETHOD(device_suspend, emx_suspend),
257 DEVMETHOD(device_resume, emx_resume),
261 static driver_t emx_driver = {
264 sizeof(struct emx_softc),
267 static devclass_t emx_devclass;
269 DECLARE_DUMMY_MODULE(if_emx);
270 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
271 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
276 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
277 static int emx_rxd = EMX_DEFAULT_RXD;
278 static int emx_txd = EMX_DEFAULT_TXD;
279 static int emx_smart_pwr_down = 0;
281 /* Controls whether promiscuous also shows bad packets */
282 static int emx_debug_sbp = FALSE;
284 static int emx_82573_workaround = 1;
285 static int emx_msi_enable = 1;
287 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
288 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
289 TUNABLE_INT("hw.emx.txd", &emx_txd);
290 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
291 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
292 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
293 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
295 /* Global used in WOL setup with multiport cards */
296 static int emx_global_quad_port_a = 0;
298 /* Set this to one to display debug statistics */
299 static int emx_display_debug_stats = 0;
301 #if !defined(KTR_IF_EMX)
302 #define KTR_IF_EMX KTR_ALL
304 KTR_INFO_MASTER(if_emx);
305 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin", 0);
306 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end", 0);
307 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet", 0);
308 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet", 0);
309 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean", 0);
310 #define logif(name) KTR_LOG(if_emx_ ## name)
313 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
315 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
316 /* DD bit must be cleared */
317 rxd->rxd_staterr = 0;
321 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
323 /* Ignore Checksum bit is set */
324 if (staterr & E1000_RXD_STAT_IXSM)
327 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
329 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
331 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
332 E1000_RXD_STAT_TCPCS) {
333 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
335 CSUM_FRAG_NOT_CHECKED;
336 mp->m_pkthdr.csum_data = htons(0xffff);
340 static __inline struct pktinfo *
341 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
342 uint32_t mrq, uint32_t hash, uint32_t staterr)
344 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
345 case EMX_RXDMRQ_IPV4_TCP:
346 pi->pi_netisr = NETISR_IP;
348 pi->pi_l3proto = IPPROTO_TCP;
351 case EMX_RXDMRQ_IPV6_TCP:
352 pi->pi_netisr = NETISR_IPV6;
354 pi->pi_l3proto = IPPROTO_TCP;
357 case EMX_RXDMRQ_IPV4:
358 if (staterr & E1000_RXD_STAT_IXSM)
362 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
363 E1000_RXD_STAT_TCPCS) {
364 pi->pi_netisr = NETISR_IP;
366 pi->pi_l3proto = IPPROTO_UDP;
374 m->m_flags |= M_HASH;
375 m->m_pkthdr.hash = toeplitz_hash(hash);
380 emx_probe(device_t dev)
382 const struct emx_device *d;
385 vid = pci_get_vendor(dev);
386 did = pci_get_device(dev);
388 for (d = emx_devices; d->desc != NULL; ++d) {
389 if (vid == d->vid && did == d->did) {
390 device_set_desc(dev, d->desc);
391 device_set_async_attach(dev, TRUE);
399 emx_attach(device_t dev)
401 struct emx_softc *sc = device_get_softc(dev);
402 struct ifnet *ifp = &sc->arpcom.ac_if;
403 int error = 0, i, msi_enable;
405 uint16_t eeprom_data, device_id, apme_mask;
408 lwkt_serialize_init(&sc->main_serialize);
409 lwkt_serialize_init(&sc->tx_serialize);
410 for (i = 0; i < EMX_NRX_RING; ++i)
411 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
414 sc->serializes[i++] = &sc->main_serialize;
415 sc->serializes[i++] = &sc->tx_serialize;
416 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
417 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
418 KKASSERT(i == EMX_NSERIALIZE);
420 callout_init_mp(&sc->timer);
422 sc->dev = sc->osdep.dev = dev;
425 * Determine hardware and mac type
427 sc->hw.vendor_id = pci_get_vendor(dev);
428 sc->hw.device_id = pci_get_device(dev);
429 sc->hw.revision_id = pci_get_revid(dev);
430 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
431 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
433 if (e1000_set_mac_type(&sc->hw))
436 /* Enable bus mastering */
437 pci_enable_busmaster(dev);
442 sc->memory_rid = EMX_BAR_MEM;
443 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
444 &sc->memory_rid, RF_ACTIVE);
445 if (sc->memory == NULL) {
446 device_printf(dev, "Unable to allocate bus resource: memory\n");
450 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
451 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
453 /* XXX This is quite goofy, it is not actually used */
454 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
459 msi_enable = emx_msi_enable;
460 ksnprintf(env, sizeof(env), "hw.%s.msi.enable",
461 device_get_nameunit(dev));
462 kgetenv_int(env, &msi_enable);
465 sc->intr_type = EMX_INTR_TYPE_LEGACY;
466 intr_flags = RF_SHAREABLE | RF_ACTIVE;
471 ksnprintf(env, sizeof(env), "hw.%s.msi.cpu",
472 device_get_nameunit(dev));
473 kgetenv_int(env, &cpu);
477 if (pci_alloc_msi(dev, &sc->intr_rid, 1, cpu) == 0) {
478 intr_flags &= ~RF_SHAREABLE;
479 sc->intr_type = EMX_INTR_TYPE_MSI;
483 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
485 if (sc->intr_res == NULL) {
486 device_printf(dev, "Unable to allocate bus resource: "
492 /* Save PCI command register for Shared Code */
493 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
494 sc->hw.back = &sc->osdep;
496 /* Do Shared Code initialization */
497 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
498 device_printf(dev, "Setup of Shared code failed\n");
502 e1000_get_bus_info(&sc->hw);
504 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
505 sc->hw.phy.autoneg_wait_to_complete = FALSE;
506 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
509 * Interrupt throttle rate
511 if (emx_int_throttle_ceil == 0) {
512 sc->int_throttle_ceil = 0;
514 int throttle = emx_int_throttle_ceil;
517 throttle = EMX_DEFAULT_ITR;
519 /* Recalculate the tunable value to get the exact frequency. */
520 throttle = 1000000000 / 256 / throttle;
522 /* Upper 16bits of ITR is reserved and should be zero */
523 if (throttle & 0xffff0000)
524 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
526 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
529 e1000_init_script_state_82541(&sc->hw, TRUE);
530 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
533 if (sc->hw.phy.media_type == e1000_media_type_copper) {
534 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
535 sc->hw.phy.disable_polarity_correction = FALSE;
536 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
539 /* Set the frame limits assuming standard ethernet sized frames. */
540 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
541 sc->min_frame_size = ETHER_MIN_LEN;
543 /* This controls when hardware reports transmit completion status. */
544 sc->hw.mac.report_tx_early = 1;
546 /* Calculate # of RX rings */
548 sc->rx_ring_cnt = EMX_NRX_RING;
551 sc->rx_ring_inuse = sc->rx_ring_cnt;
553 /* Allocate RX/TX rings' busdma(9) stuffs */
554 error = emx_dma_alloc(sc);
558 /* Allocate multicast array memory. */
559 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
562 /* Indicate SOL/IDER usage */
563 if (e1000_check_reset_block(&sc->hw)) {
565 "PHY reset is blocked due to SOL/IDER session.\n");
569 * Start from a known state, this is important in reading the
570 * nvm and mac from that.
572 e1000_reset_hw(&sc->hw);
574 /* Make sure we have a good EEPROM before we read from it */
575 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
577 * Some PCI-E parts fail the first check due to
578 * the link being in sleep state, call it again,
579 * if it fails a second time its a real issue.
581 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
583 "The EEPROM Checksum Is Not Valid\n");
589 /* Copy the permanent MAC address out of the EEPROM */
590 if (e1000_read_mac_addr(&sc->hw) < 0) {
591 device_printf(dev, "EEPROM read error while reading MAC"
596 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
597 device_printf(dev, "Invalid MAC address\n");
602 /* Determine if we have to control management hardware */
603 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
608 apme_mask = EMX_EEPROM_APME;
610 switch (sc->hw.mac.type) {
617 case e1000_80003es2lan:
618 if (sc->hw.bus.func == 1) {
619 e1000_read_nvm(&sc->hw,
620 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
622 e1000_read_nvm(&sc->hw,
623 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
628 e1000_read_nvm(&sc->hw,
629 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
632 if (eeprom_data & apme_mask)
633 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
636 * We have the eeprom settings, now apply the special cases
637 * where the eeprom may be wrong or the board won't support
638 * wake on lan on a particular port
640 device_id = pci_get_device(dev);
642 case E1000_DEV_ID_82571EB_FIBER:
644 * Wake events only supported on port A for dual fiber
645 * regardless of eeprom setting
647 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
652 case E1000_DEV_ID_82571EB_QUAD_COPPER:
653 case E1000_DEV_ID_82571EB_QUAD_FIBER:
654 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
655 /* if quad port sc, disable WoL on all but port A */
656 if (emx_global_quad_port_a != 0)
658 /* Reset for multiple quad port adapters */
659 if (++emx_global_quad_port_a == 4)
660 emx_global_quad_port_a = 0;
664 /* XXX disable wol */
667 /* Setup OS specific network interface */
670 /* Add sysctl tree, must after em_setup_ifp() */
673 /* Reset the hardware */
674 error = emx_reset(sc);
676 device_printf(dev, "Unable to reset the hardware\n");
680 /* Initialize statistics */
681 emx_update_stats(sc);
683 sc->hw.mac.get_link_status = 1;
684 emx_update_link_status(sc);
686 sc->spare_tx_desc = EMX_TX_SPARE;
689 * Keep following relationship between spare_tx_desc, oact_tx_desc
691 * (spare_tx_desc + EMX_TX_RESERVED) <=
692 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
694 sc->oact_tx_desc = sc->num_tx_desc / 8;
695 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
696 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
697 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
698 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
700 sc->tx_int_nsegs = sc->num_tx_desc / 16;
701 if (sc->tx_int_nsegs < sc->oact_tx_desc)
702 sc->tx_int_nsegs = sc->oact_tx_desc;
704 /* Non-AMT based hardware can now take control from firmware */
705 if (sc->has_manage && !sc->has_amt)
706 emx_get_hw_control(sc);
708 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
709 &sc->intr_tag, &sc->main_serialize);
711 device_printf(dev, "Failed to register interrupt handler");
712 ether_ifdetach(&sc->arpcom.ac_if);
716 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
717 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
725 emx_detach(device_t dev)
727 struct emx_softc *sc = device_get_softc(dev);
729 if (device_is_attached(dev)) {
730 struct ifnet *ifp = &sc->arpcom.ac_if;
732 ifnet_serialize_all(ifp);
736 e1000_phy_hw_reset(&sc->hw);
739 emx_rel_hw_control(sc);
742 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
743 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
747 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
749 ifnet_deserialize_all(ifp);
753 emx_rel_hw_control(sc);
755 bus_generic_detach(dev);
757 if (sc->intr_res != NULL) {
758 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
762 if (sc->intr_type == EMX_INTR_TYPE_MSI)
763 pci_release_msi(dev);
765 if (sc->memory != NULL) {
766 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
772 /* Free sysctl tree */
773 if (sc->sysctl_tree != NULL)
774 sysctl_ctx_free(&sc->sysctl_ctx);
780 emx_shutdown(device_t dev)
782 return emx_suspend(dev);
786 emx_suspend(device_t dev)
788 struct emx_softc *sc = device_get_softc(dev);
789 struct ifnet *ifp = &sc->arpcom.ac_if;
791 ifnet_serialize_all(ifp);
796 emx_rel_hw_control(sc);
799 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
800 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
804 ifnet_deserialize_all(ifp);
806 return bus_generic_suspend(dev);
810 emx_resume(device_t dev)
812 struct emx_softc *sc = device_get_softc(dev);
813 struct ifnet *ifp = &sc->arpcom.ac_if;
815 ifnet_serialize_all(ifp);
821 ifnet_deserialize_all(ifp);
823 return bus_generic_resume(dev);
827 emx_start(struct ifnet *ifp)
829 struct emx_softc *sc = ifp->if_softc;
832 ASSERT_SERIALIZED(&sc->tx_serialize);
834 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
837 if (!sc->link_active) {
838 ifq_purge(&ifp->if_snd);
842 while (!ifq_is_empty(&ifp->if_snd)) {
843 /* Now do we at least have a minimal? */
844 if (EMX_IS_OACTIVE(sc)) {
846 if (EMX_IS_OACTIVE(sc)) {
847 ifp->if_flags |= IFF_OACTIVE;
848 sc->no_tx_desc_avail1++;
854 m_head = ifq_dequeue(&ifp->if_snd, NULL);
858 if (emx_encap(sc, &m_head)) {
864 /* Send a copy of the frame to the BPF listener */
865 ETHER_BPF_MTAP(ifp, m_head);
867 /* Set timeout in case hardware has problems transmitting. */
868 ifp->if_timer = EMX_TX_TIMEOUT;
873 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
875 struct emx_softc *sc = ifp->if_softc;
876 struct ifreq *ifr = (struct ifreq *)data;
877 uint16_t eeprom_data = 0;
878 int max_frame_size, mask, reinit;
881 ASSERT_IFNET_SERIALIZED_ALL(ifp);
885 switch (sc->hw.mac.type) {
888 * 82573 only supports jumbo frames
889 * if ASPM is disabled.
891 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
893 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
894 max_frame_size = ETHER_MAX_LEN;
899 /* Limit Jumbo Frame size */
903 case e1000_80003es2lan:
904 max_frame_size = 9234;
908 max_frame_size = MAX_JUMBO_FRAME_SIZE;
911 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
917 ifp->if_mtu = ifr->ifr_mtu;
918 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
921 if (ifp->if_flags & IFF_RUNNING)
926 if (ifp->if_flags & IFF_UP) {
927 if ((ifp->if_flags & IFF_RUNNING)) {
928 if ((ifp->if_flags ^ sc->if_flags) &
929 (IFF_PROMISC | IFF_ALLMULTI)) {
930 emx_disable_promisc(sc);
936 } else if (ifp->if_flags & IFF_RUNNING) {
939 sc->if_flags = ifp->if_flags;
944 if (ifp->if_flags & IFF_RUNNING) {
945 emx_disable_intr(sc);
948 if (!(ifp->if_flags & IFF_NPOLLING))
955 /* Check SOL/IDER usage */
956 if (e1000_check_reset_block(&sc->hw)) {
957 device_printf(sc->dev, "Media change is"
958 " blocked due to SOL/IDER session.\n");
964 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
969 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
970 if (mask & IFCAP_HWCSUM) {
971 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
974 if (mask & IFCAP_VLAN_HWTAGGING) {
975 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
978 if (mask & IFCAP_RSS) {
979 ifp->if_capenable ^= IFCAP_RSS;
982 if (reinit && (ifp->if_flags & IFF_RUNNING))
987 error = ether_ioctl(ifp, command, data);
994 emx_watchdog(struct ifnet *ifp)
996 struct emx_softc *sc = ifp->if_softc;
998 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1001 * The timer is set to 5 every time start queues a packet.
1002 * Then txeof keeps resetting it as long as it cleans at
1003 * least one descriptor.
1004 * Finally, anytime all descriptors are clean the timer is
1008 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1009 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1011 * If we reach here, all TX jobs are completed and
1012 * the TX engine should have been idled for some time.
1013 * We don't need to call if_devstart() here.
1015 ifp->if_flags &= ~IFF_OACTIVE;
1021 * If we are in this routine because of pause frames, then
1022 * don't reset the hardware.
1024 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1025 ifp->if_timer = EMX_TX_TIMEOUT;
1029 if (e1000_check_for_link(&sc->hw) == 0)
1030 if_printf(ifp, "watchdog timeout -- resetting\n");
1033 sc->watchdog_events++;
1037 if (!ifq_is_empty(&ifp->if_snd))
1044 struct emx_softc *sc = xsc;
1045 struct ifnet *ifp = &sc->arpcom.ac_if;
1046 device_t dev = sc->dev;
1050 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1055 * Packet Buffer Allocation (PBA)
1056 * Writing PBA sets the receive portion of the buffer
1057 * the remainder is used for the transmit buffer.
1059 switch (sc->hw.mac.type) {
1060 /* Total Packet Buffer on these is 48K */
1063 case e1000_80003es2lan:
1064 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1067 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1068 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1072 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1076 /* Devices before 82547 had a Packet Buffer of 64K. */
1077 if (sc->max_frame_size > 8192)
1078 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1080 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1082 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1084 /* Get the latest mac address, User can use a LAA */
1085 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1087 /* Put the address into the Receive Address Array */
1088 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1091 * With the 82571 sc, RAR[0] may be overwritten
1092 * when the other port is reset, we make a duplicate
1093 * in RAR[14] for that eventuality, this assures
1094 * the interface continues to function.
1096 if (sc->hw.mac.type == e1000_82571) {
1097 e1000_set_laa_state_82571(&sc->hw, TRUE);
1098 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1099 E1000_RAR_ENTRIES - 1);
1102 /* Initialize the hardware */
1103 if (emx_reset(sc)) {
1104 device_printf(dev, "Unable to reset the hardware\n");
1105 /* XXX emx_stop()? */
1108 emx_update_link_status(sc);
1110 /* Setup VLAN support, basic and offload if available */
1111 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1113 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1116 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1117 ctrl |= E1000_CTRL_VME;
1118 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1121 /* Set hardware offload abilities */
1122 if (ifp->if_capenable & IFCAP_TXCSUM)
1123 ifp->if_hwassist = EMX_CSUM_FEATURES;
1125 ifp->if_hwassist = 0;
1127 /* Configure for OS presence */
1130 /* Prepare transmit descriptors and buffers */
1131 emx_init_tx_ring(sc);
1132 emx_init_tx_unit(sc);
1134 /* Setup Multicast table */
1138 * Adjust # of RX ring to be used based on IFCAP_RSS
1140 if (ifp->if_capenable & IFCAP_RSS)
1141 sc->rx_ring_inuse = sc->rx_ring_cnt;
1143 sc->rx_ring_inuse = 1;
1145 /* Prepare receive descriptors and buffers */
1146 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1147 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1149 "Could not setup receive structures\n");
1154 emx_init_rx_unit(sc);
1156 /* Don't lose promiscuous settings */
1157 emx_set_promisc(sc);
1159 ifp->if_flags |= IFF_RUNNING;
1160 ifp->if_flags &= ~IFF_OACTIVE;
1162 callout_reset(&sc->timer, hz, emx_timer, sc);
1163 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1165 /* MSI/X configuration for 82574 */
1166 if (sc->hw.mac.type == e1000_82574) {
1169 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1170 tmp |= E1000_CTRL_EXT_PBA_CLR;
1171 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1174 * Set the IVAR - interrupt vector routing.
1175 * Each nibble represents a vector, high bit
1176 * is enable, other 3 bits are the MSIX table
1177 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1178 * Link (other) to 2, hence the magic number.
1180 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1183 #ifdef IFPOLL_ENABLE
1185 * Only enable interrupts if we are not polling, make sure
1186 * they are off otherwise.
1188 if (ifp->if_flags & IFF_NPOLLING)
1189 emx_disable_intr(sc);
1191 #endif /* IFPOLL_ENABLE */
1192 emx_enable_intr(sc);
1194 /* AMT based hardware can now take control from firmware */
1195 if (sc->has_manage && sc->has_amt)
1196 emx_get_hw_control(sc);
1198 /* Don't reset the phy next time init gets called */
1199 sc->hw.phy.reset_disable = TRUE;
1205 struct emx_softc *sc = xsc;
1206 struct ifnet *ifp = &sc->arpcom.ac_if;
1210 ASSERT_SERIALIZED(&sc->main_serialize);
1212 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1214 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1220 * XXX: some laptops trigger several spurious interrupts
1221 * on emx(4) when in the resume cycle. The ICR register
1222 * reports all-ones value in this case. Processing such
1223 * interrupts would lead to a freeze. I don't know why.
1225 if (reg_icr == 0xffffffff) {
1230 if (ifp->if_flags & IFF_RUNNING) {
1232 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1235 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1236 lwkt_serialize_enter(
1237 &sc->rx_data[i].rx_serialize);
1238 emx_rxeof(sc, i, -1);
1239 lwkt_serialize_exit(
1240 &sc->rx_data[i].rx_serialize);
1243 if (reg_icr & E1000_ICR_TXDW) {
1244 lwkt_serialize_enter(&sc->tx_serialize);
1246 if (!ifq_is_empty(&ifp->if_snd))
1248 lwkt_serialize_exit(&sc->tx_serialize);
1252 /* Link status change */
1253 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1254 emx_serialize_skipmain(sc);
1256 callout_stop(&sc->timer);
1257 sc->hw.mac.get_link_status = 1;
1258 emx_update_link_status(sc);
1260 /* Deal with TX cruft when link lost */
1263 callout_reset(&sc->timer, hz, emx_timer, sc);
1265 emx_deserialize_skipmain(sc);
1268 if (reg_icr & E1000_ICR_RXO)
1275 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1277 struct emx_softc *sc = ifp->if_softc;
1279 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1281 emx_update_link_status(sc);
1283 ifmr->ifm_status = IFM_AVALID;
1284 ifmr->ifm_active = IFM_ETHER;
1286 if (!sc->link_active)
1289 ifmr->ifm_status |= IFM_ACTIVE;
1291 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1292 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1293 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1295 switch (sc->link_speed) {
1297 ifmr->ifm_active |= IFM_10_T;
1300 ifmr->ifm_active |= IFM_100_TX;
1304 ifmr->ifm_active |= IFM_1000_T;
1307 if (sc->link_duplex == FULL_DUPLEX)
1308 ifmr->ifm_active |= IFM_FDX;
1310 ifmr->ifm_active |= IFM_HDX;
1315 emx_media_change(struct ifnet *ifp)
1317 struct emx_softc *sc = ifp->if_softc;
1318 struct ifmedia *ifm = &sc->media;
1320 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1322 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1325 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1327 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1328 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1334 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1335 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1339 sc->hw.mac.autoneg = FALSE;
1340 sc->hw.phy.autoneg_advertised = 0;
1341 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1342 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1344 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1348 sc->hw.mac.autoneg = FALSE;
1349 sc->hw.phy.autoneg_advertised = 0;
1350 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1351 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1353 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1357 if_printf(ifp, "Unsupported media type\n");
1362 * As the speed/duplex settings my have changed we need to
1365 sc->hw.phy.reset_disable = FALSE;
1373 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1375 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1377 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1378 struct e1000_tx_desc *ctxd = NULL;
1379 struct mbuf *m_head = *m_headp;
1380 uint32_t txd_upper, txd_lower, cmd = 0;
1381 int maxsegs, nsegs, i, j, first, last = 0, error;
1383 if (m_head->m_len < EMX_TXCSUM_MINHL &&
1384 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1386 * Make sure that ethernet header and ip.ip_hl are in
1387 * contiguous memory, since if TXCSUM is enabled, later
1388 * TX context descriptor's setup need to access ip.ip_hl.
1390 error = emx_txcsum_pullup(sc, m_headp);
1392 KKASSERT(*m_headp == NULL);
1398 txd_upper = txd_lower = 0;
1401 * Capture the first descriptor index, this descriptor
1402 * will have the index of the EOP which is the only one
1403 * that now gets a DONE bit writeback.
1405 first = sc->next_avail_tx_desc;
1406 tx_buffer = &sc->tx_buf[first];
1407 tx_buffer_mapped = tx_buffer;
1408 map = tx_buffer->map;
1410 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1411 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n"));
1412 if (maxsegs > EMX_MAX_SCATTER)
1413 maxsegs = EMX_MAX_SCATTER;
1415 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1416 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1418 if (error == ENOBUFS)
1419 sc->mbuf_alloc_failed++;
1421 sc->no_tx_dma_setup++;
1427 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1430 sc->tx_nsegs += nsegs;
1432 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1433 /* TX csum offloading will consume one TX desc */
1434 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1436 i = sc->next_avail_tx_desc;
1438 /* Set up our transmit descriptors */
1439 for (j = 0; j < nsegs; j++) {
1440 tx_buffer = &sc->tx_buf[i];
1441 ctxd = &sc->tx_desc_base[i];
1443 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1444 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1445 txd_lower | segs[j].ds_len);
1446 ctxd->upper.data = htole32(txd_upper);
1449 if (++i == sc->num_tx_desc)
1453 sc->next_avail_tx_desc = i;
1455 KKASSERT(sc->num_tx_desc_avail > nsegs);
1456 sc->num_tx_desc_avail -= nsegs;
1458 /* Handle VLAN tag */
1459 if (m_head->m_flags & M_VLANTAG) {
1460 /* Set the vlan id. */
1461 ctxd->upper.fields.special =
1462 htole16(m_head->m_pkthdr.ether_vlantag);
1464 /* Tell hardware to add tag */
1465 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1468 tx_buffer->m_head = m_head;
1469 tx_buffer_mapped->map = tx_buffer->map;
1470 tx_buffer->map = map;
1472 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1476 * Report Status (RS) is turned on
1477 * every tx_int_nsegs descriptors.
1479 cmd = E1000_TXD_CMD_RS;
1482 * Keep track of the descriptor, which will
1483 * be written back by hardware.
1485 sc->tx_dd[sc->tx_dd_tail] = last;
1486 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1487 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1491 * Last Descriptor of Packet needs End Of Packet (EOP)
1493 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1496 * Advance the Transmit Descriptor Tail (TDT), this tells
1497 * the E1000 that this frame is available to transmit.
1499 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1505 emx_set_promisc(struct emx_softc *sc)
1507 struct ifnet *ifp = &sc->arpcom.ac_if;
1510 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1512 if (ifp->if_flags & IFF_PROMISC) {
1513 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1514 /* Turn this on if you want to see bad packets */
1516 reg_rctl |= E1000_RCTL_SBP;
1517 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1518 } else if (ifp->if_flags & IFF_ALLMULTI) {
1519 reg_rctl |= E1000_RCTL_MPE;
1520 reg_rctl &= ~E1000_RCTL_UPE;
1521 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1526 emx_disable_promisc(struct emx_softc *sc)
1530 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1532 reg_rctl &= ~E1000_RCTL_UPE;
1533 reg_rctl &= ~E1000_RCTL_MPE;
1534 reg_rctl &= ~E1000_RCTL_SBP;
1535 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1539 emx_set_multi(struct emx_softc *sc)
1541 struct ifnet *ifp = &sc->arpcom.ac_if;
1542 struct ifmultiaddr *ifma;
1543 uint32_t reg_rctl = 0;
1548 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1550 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1551 if (ifma->ifma_addr->sa_family != AF_LINK)
1554 if (mcnt == EMX_MCAST_ADDR_MAX)
1557 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1558 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1562 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1563 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1564 reg_rctl |= E1000_RCTL_MPE;
1565 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1567 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1572 * This routine checks for link status and updates statistics.
1575 emx_timer(void *xsc)
1577 struct emx_softc *sc = xsc;
1578 struct ifnet *ifp = &sc->arpcom.ac_if;
1580 ifnet_serialize_all(ifp);
1582 emx_update_link_status(sc);
1583 emx_update_stats(sc);
1585 /* Reset LAA into RAR[0] on 82571 */
1586 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1587 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1589 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1590 emx_print_hw_stats(sc);
1594 callout_reset(&sc->timer, hz, emx_timer, sc);
1596 ifnet_deserialize_all(ifp);
1600 emx_update_link_status(struct emx_softc *sc)
1602 struct e1000_hw *hw = &sc->hw;
1603 struct ifnet *ifp = &sc->arpcom.ac_if;
1604 device_t dev = sc->dev;
1605 uint32_t link_check = 0;
1607 /* Get the cached link value or read phy for real */
1608 switch (hw->phy.media_type) {
1609 case e1000_media_type_copper:
1610 if (hw->mac.get_link_status) {
1611 /* Do the work to read phy */
1612 e1000_check_for_link(hw);
1613 link_check = !hw->mac.get_link_status;
1614 if (link_check) /* ESB2 fix */
1615 e1000_cfg_on_link_up(hw);
1621 case e1000_media_type_fiber:
1622 e1000_check_for_link(hw);
1623 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1626 case e1000_media_type_internal_serdes:
1627 e1000_check_for_link(hw);
1628 link_check = sc->hw.mac.serdes_has_link;
1631 case e1000_media_type_unknown:
1636 /* Now check for a transition */
1637 if (link_check && sc->link_active == 0) {
1638 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1642 * Check if we should enable/disable SPEED_MODE bit on
1645 if (sc->link_speed != SPEED_1000 &&
1646 (hw->mac.type == e1000_82571 ||
1647 hw->mac.type == e1000_82572)) {
1650 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1651 tarc0 &= ~EMX_TARC_SPEED_MODE;
1652 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1655 device_printf(dev, "Link is up %d Mbps %s\n",
1657 ((sc->link_duplex == FULL_DUPLEX) ?
1658 "Full Duplex" : "Half Duplex"));
1660 sc->link_active = 1;
1662 ifp->if_baudrate = sc->link_speed * 1000000;
1663 ifp->if_link_state = LINK_STATE_UP;
1664 if_link_state_change(ifp);
1665 } else if (!link_check && sc->link_active == 1) {
1666 ifp->if_baudrate = sc->link_speed = 0;
1667 sc->link_duplex = 0;
1669 device_printf(dev, "Link is Down\n");
1670 sc->link_active = 0;
1672 /* Link down, disable watchdog */
1675 ifp->if_link_state = LINK_STATE_DOWN;
1676 if_link_state_change(ifp);
1681 emx_stop(struct emx_softc *sc)
1683 struct ifnet *ifp = &sc->arpcom.ac_if;
1686 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1688 emx_disable_intr(sc);
1690 callout_stop(&sc->timer);
1692 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1696 * Disable multiple receive queues.
1699 * We should disable multiple receive queues before
1700 * resetting the hardware.
1702 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1704 e1000_reset_hw(&sc->hw);
1705 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1707 for (i = 0; i < sc->num_tx_desc; i++) {
1708 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1710 if (tx_buffer->m_head != NULL) {
1711 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1712 m_freem(tx_buffer->m_head);
1713 tx_buffer->m_head = NULL;
1717 for (i = 0; i < sc->rx_ring_inuse; ++i)
1718 emx_free_rx_ring(sc, &sc->rx_data[i]);
1722 sc->csum_iphlen = 0;
1730 emx_reset(struct emx_softc *sc)
1732 device_t dev = sc->dev;
1733 uint16_t rx_buffer_size;
1735 /* Set up smart power down as default off on newer adapters. */
1736 if (!emx_smart_pwr_down &&
1737 (sc->hw.mac.type == e1000_82571 ||
1738 sc->hw.mac.type == e1000_82572)) {
1739 uint16_t phy_tmp = 0;
1741 /* Speed up time to link by disabling smart power down. */
1742 e1000_read_phy_reg(&sc->hw,
1743 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1744 phy_tmp &= ~IGP02E1000_PM_SPD;
1745 e1000_write_phy_reg(&sc->hw,
1746 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1750 * These parameters control the automatic generation (Tx) and
1751 * response (Rx) to Ethernet PAUSE frames.
1752 * - High water mark should allow for at least two frames to be
1753 * received after sending an XOFF.
1754 * - Low water mark works best when it is very near the high water mark.
1755 * This allows the receiver to restart by sending XON when it has
1756 * drained a bit. Here we use an arbitary value of 1500 which will
1757 * restart after one full frame is pulled from the buffer. There
1758 * could be several smaller frames in the buffer and if so they will
1759 * not trigger the XON until their total number reduces the buffer
1761 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1763 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1765 sc->hw.fc.high_water = rx_buffer_size -
1766 roundup2(sc->max_frame_size, 1024);
1767 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1769 if (sc->hw.mac.type == e1000_80003es2lan)
1770 sc->hw.fc.pause_time = 0xFFFF;
1772 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1773 sc->hw.fc.send_xon = TRUE;
1774 sc->hw.fc.requested_mode = e1000_fc_full;
1776 /* Issue a global reset */
1777 e1000_reset_hw(&sc->hw);
1778 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1780 if (e1000_init_hw(&sc->hw) < 0) {
1781 device_printf(dev, "Hardware Initialization Failed\n");
1785 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1786 e1000_get_phy_info(&sc->hw);
1787 e1000_check_for_link(&sc->hw);
1793 emx_setup_ifp(struct emx_softc *sc)
1795 struct ifnet *ifp = &sc->arpcom.ac_if;
1797 if_initname(ifp, device_get_name(sc->dev),
1798 device_get_unit(sc->dev));
1800 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1801 ifp->if_init = emx_init;
1802 ifp->if_ioctl = emx_ioctl;
1803 ifp->if_start = emx_start;
1804 #ifdef IFPOLL_ENABLE
1805 ifp->if_qpoll = emx_qpoll;
1807 ifp->if_watchdog = emx_watchdog;
1808 ifp->if_serialize = emx_serialize;
1809 ifp->if_deserialize = emx_deserialize;
1810 ifp->if_tryserialize = emx_tryserialize;
1812 ifp->if_serialize_assert = emx_serialize_assert;
1814 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1815 ifq_set_ready(&ifp->if_snd);
1817 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1819 ifp->if_capabilities = IFCAP_HWCSUM |
1820 IFCAP_VLAN_HWTAGGING |
1822 if (sc->rx_ring_cnt > 1)
1823 ifp->if_capabilities |= IFCAP_RSS;
1824 ifp->if_capenable = ifp->if_capabilities;
1825 ifp->if_hwassist = EMX_CSUM_FEATURES;
1828 * Tell the upper layer(s) we support long frames.
1830 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1833 * Specify the media types supported by this sc and register
1834 * callbacks to update media and link information
1836 ifmedia_init(&sc->media, IFM_IMASK,
1837 emx_media_change, emx_media_status);
1838 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1839 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1840 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1842 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1844 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1845 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1847 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1848 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1850 if (sc->hw.phy.type != e1000_phy_ife) {
1851 ifmedia_add(&sc->media,
1852 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1853 ifmedia_add(&sc->media,
1854 IFM_ETHER | IFM_1000_T, 0, NULL);
1857 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1858 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1862 * Workaround for SmartSpeed on 82541 and 82547 controllers
1865 emx_smartspeed(struct emx_softc *sc)
1869 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1870 sc->hw.mac.autoneg == 0 ||
1871 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1874 if (sc->smartspeed == 0) {
1876 * If Master/Slave config fault is asserted twice,
1877 * we assume back-to-back
1879 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1880 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1882 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1883 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1884 e1000_read_phy_reg(&sc->hw,
1885 PHY_1000T_CTRL, &phy_tmp);
1886 if (phy_tmp & CR_1000T_MS_ENABLE) {
1887 phy_tmp &= ~CR_1000T_MS_ENABLE;
1888 e1000_write_phy_reg(&sc->hw,
1889 PHY_1000T_CTRL, phy_tmp);
1891 if (sc->hw.mac.autoneg &&
1892 !e1000_phy_setup_autoneg(&sc->hw) &&
1893 !e1000_read_phy_reg(&sc->hw,
1894 PHY_CONTROL, &phy_tmp)) {
1895 phy_tmp |= MII_CR_AUTO_NEG_EN |
1896 MII_CR_RESTART_AUTO_NEG;
1897 e1000_write_phy_reg(&sc->hw,
1898 PHY_CONTROL, phy_tmp);
1903 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1904 /* If still no link, perhaps using 2/3 pair cable */
1905 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1906 phy_tmp |= CR_1000T_MS_ENABLE;
1907 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1908 if (sc->hw.mac.autoneg &&
1909 !e1000_phy_setup_autoneg(&sc->hw) &&
1910 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1911 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1912 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1916 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1917 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1922 emx_create_tx_ring(struct emx_softc *sc)
1924 device_t dev = sc->dev;
1925 struct emx_txbuf *tx_buffer;
1926 int error, i, tsize;
1929 * Validate number of transmit descriptors. It must not exceed
1930 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1932 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1933 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) {
1934 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1935 EMX_DEFAULT_TXD, emx_txd);
1936 sc->num_tx_desc = EMX_DEFAULT_TXD;
1938 sc->num_tx_desc = emx_txd;
1942 * Allocate Transmit Descriptor ring
1944 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1946 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1947 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1948 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1949 &sc->tx_desc_paddr);
1950 if (sc->tx_desc_base == NULL) {
1951 device_printf(dev, "Unable to allocate tx_desc memory\n");
1955 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1956 M_DEVBUF, M_WAITOK | M_ZERO);
1959 * Create DMA tags for tx buffers
1961 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1962 1, 0, /* alignment, bounds */
1963 BUS_SPACE_MAXADDR, /* lowaddr */
1964 BUS_SPACE_MAXADDR, /* highaddr */
1965 NULL, NULL, /* filter, filterarg */
1966 EMX_TSO_SIZE, /* maxsize */
1967 EMX_MAX_SCATTER, /* nsegments */
1968 EMX_MAX_SEGSIZE, /* maxsegsize */
1969 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1970 BUS_DMA_ONEBPAGE, /* flags */
1973 device_printf(dev, "Unable to allocate TX DMA tag\n");
1974 kfree(sc->tx_buf, M_DEVBUF);
1980 * Create DMA maps for tx buffers
1982 for (i = 0; i < sc->num_tx_desc; i++) {
1983 tx_buffer = &sc->tx_buf[i];
1985 error = bus_dmamap_create(sc->txtag,
1986 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1989 device_printf(dev, "Unable to create TX DMA map\n");
1990 emx_destroy_tx_ring(sc, i);
1998 emx_init_tx_ring(struct emx_softc *sc)
2000 /* Clear the old ring contents */
2001 bzero(sc->tx_desc_base,
2002 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2005 sc->next_avail_tx_desc = 0;
2006 sc->next_tx_to_clean = 0;
2007 sc->num_tx_desc_avail = sc->num_tx_desc;
2011 emx_init_tx_unit(struct emx_softc *sc)
2013 uint32_t tctl, tarc, tipg = 0;
2016 /* Setup the Base and Length of the Tx Descriptor Ring */
2017 bus_addr = sc->tx_desc_paddr;
2018 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2019 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2020 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2021 (uint32_t)(bus_addr >> 32));
2022 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2023 (uint32_t)bus_addr);
2024 /* Setup the HW Tx Head and Tail descriptor pointers */
2025 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2026 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2028 /* Set the default values for the Tx Inter Packet Gap timer */
2029 switch (sc->hw.mac.type) {
2030 case e1000_80003es2lan:
2031 tipg = DEFAULT_82543_TIPG_IPGR1;
2032 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2033 E1000_TIPG_IPGR2_SHIFT;
2037 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2038 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2039 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2041 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2042 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2043 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2047 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2049 /* NOTE: 0 is not allowed for TIDV */
2050 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2051 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2053 if (sc->hw.mac.type == e1000_82571 ||
2054 sc->hw.mac.type == e1000_82572) {
2055 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2056 tarc |= EMX_TARC_SPEED_MODE;
2057 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2058 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2059 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2061 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2062 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2064 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2067 /* Program the Transmit Control Register */
2068 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2069 tctl &= ~E1000_TCTL_CT;
2070 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2071 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2072 tctl |= E1000_TCTL_MULR;
2074 /* This write will effectively turn on the transmit unit. */
2075 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2079 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2081 struct emx_txbuf *tx_buffer;
2084 /* Free Transmit Descriptor ring */
2085 if (sc->tx_desc_base) {
2086 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2087 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2089 bus_dma_tag_destroy(sc->tx_desc_dtag);
2091 sc->tx_desc_base = NULL;
2094 if (sc->tx_buf == NULL)
2097 for (i = 0; i < ndesc; i++) {
2098 tx_buffer = &sc->tx_buf[i];
2100 KKASSERT(tx_buffer->m_head == NULL);
2101 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2103 bus_dma_tag_destroy(sc->txtag);
2105 kfree(sc->tx_buf, M_DEVBUF);
2110 * The offload context needs to be set when we transfer the first
2111 * packet of a particular protocol (TCP/UDP). This routine has been
2112 * enhanced to deal with inserted VLAN headers.
2114 * If the new packet's ether header length, ip header length and
2115 * csum offloading type are same as the previous packet, we should
2116 * avoid allocating a new csum context descriptor; mainly to take
2117 * advantage of the pipeline effect of the TX data read request.
2119 * This function returns number of TX descrptors allocated for
2123 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2124 uint32_t *txd_upper, uint32_t *txd_lower)
2126 struct e1000_context_desc *TXD;
2127 struct emx_txbuf *tx_buffer;
2128 struct ether_vlan_header *eh;
2130 int curr_txd, ehdrlen, csum_flags;
2131 uint32_t cmd, hdr_len, ip_hlen;
2135 * Determine where frame payload starts.
2136 * Jump over vlan headers if already present,
2137 * helpful for QinQ too.
2139 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2140 ("emx_txcsum_pullup is not called (eh)?\n"));
2141 eh = mtod(mp, struct ether_vlan_header *);
2142 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2143 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2144 ("emx_txcsum_pullup is not called (evh)?\n"));
2145 etype = ntohs(eh->evl_proto);
2146 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2148 etype = ntohs(eh->evl_encap_proto);
2149 ehdrlen = ETHER_HDR_LEN;
2153 * We only support TCP/UDP for IPv4 for the moment.
2154 * TODO: Support SCTP too when it hits the tree.
2156 if (etype != ETHERTYPE_IP)
2159 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2160 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2162 /* NOTE: We could only safely access ip.ip_vhl part */
2163 ip = (struct ip *)(mp->m_data + ehdrlen);
2164 ip_hlen = ip->ip_hl << 2;
2166 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2168 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2169 sc->csum_flags == csum_flags) {
2171 * Same csum offload context as the previous packets;
2174 *txd_upper = sc->csum_txd_upper;
2175 *txd_lower = sc->csum_txd_lower;
2180 * Setup a new csum offload context.
2183 curr_txd = sc->next_avail_tx_desc;
2184 tx_buffer = &sc->tx_buf[curr_txd];
2185 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2189 /* Setup of IP header checksum. */
2190 if (csum_flags & CSUM_IP) {
2192 * Start offset for header checksum calculation.
2193 * End offset for header checksum calculation.
2194 * Offset of place to put the checksum.
2196 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2197 TXD->lower_setup.ip_fields.ipcse =
2198 htole16(ehdrlen + ip_hlen - 1);
2199 TXD->lower_setup.ip_fields.ipcso =
2200 ehdrlen + offsetof(struct ip, ip_sum);
2201 cmd |= E1000_TXD_CMD_IP;
2202 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2204 hdr_len = ehdrlen + ip_hlen;
2206 if (csum_flags & CSUM_TCP) {
2208 * Start offset for payload checksum calculation.
2209 * End offset for payload checksum calculation.
2210 * Offset of place to put the checksum.
2212 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2213 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2214 TXD->upper_setup.tcp_fields.tucso =
2215 hdr_len + offsetof(struct tcphdr, th_sum);
2216 cmd |= E1000_TXD_CMD_TCP;
2217 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2218 } else if (csum_flags & CSUM_UDP) {
2220 * Start offset for header checksum calculation.
2221 * End offset for header checksum calculation.
2222 * Offset of place to put the checksum.
2224 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2225 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2226 TXD->upper_setup.tcp_fields.tucso =
2227 hdr_len + offsetof(struct udphdr, uh_sum);
2228 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2231 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2232 E1000_TXD_DTYP_D; /* Data descr */
2234 /* Save the information for this csum offloading context */
2235 sc->csum_ehlen = ehdrlen;
2236 sc->csum_iphlen = ip_hlen;
2237 sc->csum_flags = csum_flags;
2238 sc->csum_txd_upper = *txd_upper;
2239 sc->csum_txd_lower = *txd_lower;
2241 TXD->tcp_seg_setup.data = htole32(0);
2242 TXD->cmd_and_length =
2243 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2245 if (++curr_txd == sc->num_tx_desc)
2248 KKASSERT(sc->num_tx_desc_avail > 0);
2249 sc->num_tx_desc_avail--;
2251 sc->next_avail_tx_desc = curr_txd;
2256 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2258 struct mbuf *m = *m0;
2259 struct ether_header *eh;
2262 sc->tx_csum_try_pullup++;
2264 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2266 if (__predict_false(!M_WRITABLE(m))) {
2267 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2268 sc->tx_csum_drop1++;
2273 eh = mtod(m, struct ether_header *);
2275 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2276 len += EVL_ENCAPLEN;
2278 if (m->m_len < len) {
2279 sc->tx_csum_drop2++;
2287 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2288 sc->tx_csum_pullup1++;
2289 m = m_pullup(m, ETHER_HDR_LEN);
2291 sc->tx_csum_pullup1_failed++;
2297 eh = mtod(m, struct ether_header *);
2299 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2300 len += EVL_ENCAPLEN;
2302 if (m->m_len < len) {
2303 sc->tx_csum_pullup2++;
2304 m = m_pullup(m, len);
2306 sc->tx_csum_pullup2_failed++;
2316 emx_txeof(struct emx_softc *sc)
2318 struct ifnet *ifp = &sc->arpcom.ac_if;
2319 struct emx_txbuf *tx_buffer;
2320 int first, num_avail;
2322 if (sc->tx_dd_head == sc->tx_dd_tail)
2325 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2328 num_avail = sc->num_tx_desc_avail;
2329 first = sc->next_tx_to_clean;
2331 while (sc->tx_dd_head != sc->tx_dd_tail) {
2332 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2333 struct e1000_tx_desc *tx_desc;
2335 tx_desc = &sc->tx_desc_base[dd_idx];
2336 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2337 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2339 if (++dd_idx == sc->num_tx_desc)
2342 while (first != dd_idx) {
2347 tx_buffer = &sc->tx_buf[first];
2348 if (tx_buffer->m_head) {
2350 bus_dmamap_unload(sc->txtag,
2352 m_freem(tx_buffer->m_head);
2353 tx_buffer->m_head = NULL;
2356 if (++first == sc->num_tx_desc)
2363 sc->next_tx_to_clean = first;
2364 sc->num_tx_desc_avail = num_avail;
2366 if (sc->tx_dd_head == sc->tx_dd_tail) {
2371 if (!EMX_IS_OACTIVE(sc)) {
2372 ifp->if_flags &= ~IFF_OACTIVE;
2374 /* All clean, turn off the timer */
2375 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2381 emx_tx_collect(struct emx_softc *sc)
2383 struct ifnet *ifp = &sc->arpcom.ac_if;
2384 struct emx_txbuf *tx_buffer;
2385 int tdh, first, num_avail, dd_idx = -1;
2387 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2390 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2391 if (tdh == sc->next_tx_to_clean)
2394 if (sc->tx_dd_head != sc->tx_dd_tail)
2395 dd_idx = sc->tx_dd[sc->tx_dd_head];
2397 num_avail = sc->num_tx_desc_avail;
2398 first = sc->next_tx_to_clean;
2400 while (first != tdh) {
2405 tx_buffer = &sc->tx_buf[first];
2406 if (tx_buffer->m_head) {
2408 bus_dmamap_unload(sc->txtag,
2410 m_freem(tx_buffer->m_head);
2411 tx_buffer->m_head = NULL;
2414 if (first == dd_idx) {
2415 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2416 if (sc->tx_dd_head == sc->tx_dd_tail) {
2421 dd_idx = sc->tx_dd[sc->tx_dd_head];
2425 if (++first == sc->num_tx_desc)
2428 sc->next_tx_to_clean = first;
2429 sc->num_tx_desc_avail = num_avail;
2431 if (!EMX_IS_OACTIVE(sc)) {
2432 ifp->if_flags &= ~IFF_OACTIVE;
2434 /* All clean, turn off the timer */
2435 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2441 * When Link is lost sometimes there is work still in the TX ring
2442 * which will result in a watchdog, rather than allow that do an
2443 * attempted cleanup and then reinit here. Note that this has been
2444 * seens mostly with fiber adapters.
2447 emx_tx_purge(struct emx_softc *sc)
2449 struct ifnet *ifp = &sc->arpcom.ac_if;
2451 if (!sc->link_active && ifp->if_timer) {
2453 if (ifp->if_timer) {
2454 if_printf(ifp, "Link lost, TX pending, reinit\n");
2462 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2465 bus_dma_segment_t seg;
2467 struct emx_rxbuf *rx_buffer;
2470 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2472 rdata->mbuf_cluster_failed++;
2474 if_printf(&sc->arpcom.ac_if,
2475 "Unable to allocate RX mbuf\n");
2479 m->m_len = m->m_pkthdr.len = MCLBYTES;
2481 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2482 m_adj(m, ETHER_ALIGN);
2484 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2485 rdata->rx_sparemap, m,
2486 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2490 if_printf(&sc->arpcom.ac_if,
2491 "Unable to load RX mbuf\n");
2496 rx_buffer = &rdata->rx_buf[i];
2497 if (rx_buffer->m_head != NULL)
2498 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2500 map = rx_buffer->map;
2501 rx_buffer->map = rdata->rx_sparemap;
2502 rdata->rx_sparemap = map;
2504 rx_buffer->m_head = m;
2505 rx_buffer->paddr = seg.ds_addr;
2507 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2512 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2514 device_t dev = sc->dev;
2515 struct emx_rxbuf *rx_buffer;
2516 int i, error, rsize;
2519 * Validate number of receive descriptors. It must not exceed
2520 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2522 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2523 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) {
2524 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2525 EMX_DEFAULT_RXD, emx_rxd);
2526 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2528 rdata->num_rx_desc = emx_rxd;
2532 * Allocate Receive Descriptor ring
2534 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2536 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2537 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2538 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2539 &rdata->rx_desc_paddr);
2540 if (rdata->rx_desc == NULL) {
2541 device_printf(dev, "Unable to allocate rx_desc memory\n");
2545 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2546 M_DEVBUF, M_WAITOK | M_ZERO);
2549 * Create DMA tag for rx buffers
2551 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2552 1, 0, /* alignment, bounds */
2553 BUS_SPACE_MAXADDR, /* lowaddr */
2554 BUS_SPACE_MAXADDR, /* highaddr */
2555 NULL, NULL, /* filter, filterarg */
2556 MCLBYTES, /* maxsize */
2558 MCLBYTES, /* maxsegsize */
2559 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2562 device_printf(dev, "Unable to allocate RX DMA tag\n");
2563 kfree(rdata->rx_buf, M_DEVBUF);
2564 rdata->rx_buf = NULL;
2569 * Create spare DMA map for rx buffers
2571 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2572 &rdata->rx_sparemap);
2574 device_printf(dev, "Unable to create spare RX DMA map\n");
2575 bus_dma_tag_destroy(rdata->rxtag);
2576 kfree(rdata->rx_buf, M_DEVBUF);
2577 rdata->rx_buf = NULL;
2582 * Create DMA maps for rx buffers
2584 for (i = 0; i < rdata->num_rx_desc; i++) {
2585 rx_buffer = &rdata->rx_buf[i];
2587 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2590 device_printf(dev, "Unable to create RX DMA map\n");
2591 emx_destroy_rx_ring(sc, rdata, i);
2599 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2603 for (i = 0; i < rdata->num_rx_desc; i++) {
2604 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2606 if (rx_buffer->m_head != NULL) {
2607 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2608 m_freem(rx_buffer->m_head);
2609 rx_buffer->m_head = NULL;
2613 if (rdata->fmp != NULL)
2614 m_freem(rdata->fmp);
2620 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2624 /* Reset descriptor ring */
2625 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2627 /* Allocate new ones. */
2628 for (i = 0; i < rdata->num_rx_desc; i++) {
2629 error = emx_newbuf(sc, rdata, i, 1);
2634 /* Setup our descriptor pointers */
2635 rdata->next_rx_desc_to_check = 0;
2641 emx_init_rx_unit(struct emx_softc *sc)
2643 struct ifnet *ifp = &sc->arpcom.ac_if;
2645 uint32_t rctl, itr, rfctl;
2649 * Make sure receives are disabled while setting
2650 * up the descriptor ring
2652 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2653 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2656 * Set the interrupt throttling rate. Value is calculated
2657 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2659 if (sc->int_throttle_ceil)
2660 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2663 emx_set_itr(sc, itr);
2665 /* Use extended RX descriptor */
2666 rfctl = E1000_RFCTL_EXTEN;
2668 /* Disable accelerated ackknowledge */
2669 if (sc->hw.mac.type == e1000_82574)
2670 rfctl |= E1000_RFCTL_ACK_DIS;
2672 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2675 * Receive Checksum Offload for TCP and UDP
2677 * Checksum offloading is also enabled if multiple receive
2678 * queue is to be supported, since we need it to figure out
2681 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) {
2684 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2688 * PCSD must be enabled to enable multiple
2691 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2693 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2697 * Configure multiple receive queue (RSS)
2699 if (ifp->if_capenable & IFCAP_RSS) {
2700 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2703 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING,
2704 ("invalid number of RX ring (%d)",
2705 sc->rx_ring_inuse));
2709 * When we reach here, RSS has already been disabled
2710 * in emx_stop(), so we could safely configure RSS key
2711 * and redirect table.
2717 toeplitz_get_key(key, sizeof(key));
2718 for (i = 0; i < EMX_NRSSRK; ++i) {
2721 rssrk = EMX_RSSRK_VAL(key, i);
2722 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2724 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2728 * Configure RSS redirect table in following fashion:
2729 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2732 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2735 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT;
2736 reta |= q << (8 * i);
2738 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2740 for (i = 0; i < EMX_NRETA; ++i)
2741 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2744 * Enable multiple receive queues.
2745 * Enable IPv4 RSS standard hash functions.
2746 * Disable RSS interrupt.
2748 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2749 E1000_MRQC_ENABLE_RSS_2Q |
2750 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2751 E1000_MRQC_RSS_FIELD_IPV4);
2755 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2756 * long latencies are observed, like Lenovo X60. This
2757 * change eliminates the problem, but since having positive
2758 * values in RDTR is a known source of problems on other
2759 * platforms another solution is being sought.
2761 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2762 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2763 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2766 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2767 struct emx_rxdata *rdata = &sc->rx_data[i];
2770 * Setup the Base and Length of the Rx Descriptor Ring
2772 bus_addr = rdata->rx_desc_paddr;
2773 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2774 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2775 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2776 (uint32_t)(bus_addr >> 32));
2777 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2778 (uint32_t)bus_addr);
2781 * Setup the HW Rx Head and Tail Descriptor Pointers
2783 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2784 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2785 sc->rx_data[i].num_rx_desc - 1);
2788 /* Setup the Receive Control Register */
2789 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2790 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2791 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2792 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2794 /* Make sure VLAN Filters are off */
2795 rctl &= ~E1000_RCTL_VFE;
2797 /* Don't store bad paket */
2798 rctl &= ~E1000_RCTL_SBP;
2801 rctl |= E1000_RCTL_SZ_2048;
2803 if (ifp->if_mtu > ETHERMTU)
2804 rctl |= E1000_RCTL_LPE;
2806 rctl &= ~E1000_RCTL_LPE;
2808 /* Enable Receives */
2809 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2813 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2815 struct emx_rxbuf *rx_buffer;
2818 /* Free Receive Descriptor ring */
2819 if (rdata->rx_desc) {
2820 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2821 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2822 rdata->rx_desc_dmap);
2823 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2825 rdata->rx_desc = NULL;
2828 if (rdata->rx_buf == NULL)
2831 for (i = 0; i < ndesc; i++) {
2832 rx_buffer = &rdata->rx_buf[i];
2834 KKASSERT(rx_buffer->m_head == NULL);
2835 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2837 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2838 bus_dma_tag_destroy(rdata->rxtag);
2840 kfree(rdata->rx_buf, M_DEVBUF);
2841 rdata->rx_buf = NULL;
2845 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2847 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2848 struct ifnet *ifp = &sc->arpcom.ac_if;
2850 emx_rxdesc_t *current_desc;
2853 struct mbuf_chain chain[MAXCPU];
2855 i = rdata->next_rx_desc_to_check;
2856 current_desc = &rdata->rx_desc[i];
2857 staterr = le32toh(current_desc->rxd_staterr);
2859 if (!(staterr & E1000_RXD_STAT_DD))
2862 ether_input_chain_init(chain);
2864 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2865 struct pktinfo *pi = NULL, pi0;
2866 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2867 struct mbuf *m = NULL;
2872 mp = rx_buf->m_head;
2875 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2876 * needs to access the last received byte in the mbuf.
2878 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2879 BUS_DMASYNC_POSTREAD);
2881 len = le16toh(current_desc->rxd_length);
2882 if (staterr & E1000_RXD_STAT_EOP) {
2889 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2891 uint32_t mrq, rss_hash;
2894 * Save several necessary information,
2895 * before emx_newbuf() destroy it.
2897 if ((staterr & E1000_RXD_STAT_VP) && eop)
2898 vlan = le16toh(current_desc->rxd_vlan);
2900 mrq = le32toh(current_desc->rxd_mrq);
2901 rss_hash = le32toh(current_desc->rxd_rss);
2903 EMX_RSS_DPRINTF(sc, 10,
2904 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2905 ring_idx, mrq, rss_hash);
2907 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2912 /* Assign correct length to the current fragment */
2915 if (rdata->fmp == NULL) {
2916 mp->m_pkthdr.len = len;
2917 rdata->fmp = mp; /* Store the first mbuf */
2921 * Chain mbuf's together
2923 rdata->lmp->m_next = mp;
2924 rdata->lmp = rdata->lmp->m_next;
2925 rdata->fmp->m_pkthdr.len += len;
2929 rdata->fmp->m_pkthdr.rcvif = ifp;
2932 if (ifp->if_capenable & IFCAP_RXCSUM)
2933 emx_rxcsum(staterr, rdata->fmp);
2935 if (staterr & E1000_RXD_STAT_VP) {
2936 rdata->fmp->m_pkthdr.ether_vlantag =
2938 rdata->fmp->m_flags |= M_VLANTAG;
2944 if (ifp->if_capenable & IFCAP_RSS) {
2945 pi = emx_rssinfo(m, &pi0, mrq,
2948 #ifdef EMX_RSS_DEBUG
2955 emx_setup_rxdesc(current_desc, rx_buf);
2956 if (rdata->fmp != NULL) {
2957 m_freem(rdata->fmp);
2965 ether_input_chain(ifp, m, pi, chain);
2967 /* Advance our pointers to the next descriptor. */
2968 if (++i == rdata->num_rx_desc)
2971 current_desc = &rdata->rx_desc[i];
2972 staterr = le32toh(current_desc->rxd_staterr);
2974 rdata->next_rx_desc_to_check = i;
2976 ether_input_dispatch(chain);
2978 /* Advance the E1000's Receive Queue "Tail Pointer". */
2980 i = rdata->num_rx_desc - 1;
2981 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2985 emx_enable_intr(struct emx_softc *sc)
2987 uint32_t ims_mask = IMS_ENABLE_MASK;
2989 lwkt_serialize_handler_enable(&sc->main_serialize);
2992 if (sc->hw.mac.type == e1000_82574) {
2993 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2994 ims_mask |= EM_MSIX_MASK;
2997 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3001 emx_disable_intr(struct emx_softc *sc)
3003 if (sc->hw.mac.type == e1000_82574)
3004 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3005 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3007 lwkt_serialize_handler_disable(&sc->main_serialize);
3011 * Bit of a misnomer, what this really means is
3012 * to enable OS management of the system... aka
3013 * to disable special hardware management features
3016 emx_get_mgmt(struct emx_softc *sc)
3018 /* A shared code workaround */
3019 if (sc->has_manage) {
3020 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3021 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3023 /* disable hardware interception of ARP */
3024 manc &= ~(E1000_MANC_ARP_EN);
3026 /* enable receiving management packets to the host */
3027 manc |= E1000_MANC_EN_MNG2HOST;
3028 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3029 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3030 manc2h |= E1000_MNG2HOST_PORT_623;
3031 manc2h |= E1000_MNG2HOST_PORT_664;
3032 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3034 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3039 * Give control back to hardware management
3040 * controller if there is one.
3043 emx_rel_mgmt(struct emx_softc *sc)
3045 if (sc->has_manage) {
3046 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3048 /* re-enable hardware interception of ARP */
3049 manc |= E1000_MANC_ARP_EN;
3050 manc &= ~E1000_MANC_EN_MNG2HOST;
3052 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3057 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3058 * For ASF and Pass Through versions of f/w this means that
3059 * the driver is loaded. For AMT version (only with 82573)
3060 * of the f/w this means that the network i/f is open.
3063 emx_get_hw_control(struct emx_softc *sc)
3065 /* Let firmware know the driver has taken over */
3066 if (sc->hw.mac.type == e1000_82573) {
3069 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3070 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3071 swsm | E1000_SWSM_DRV_LOAD);
3075 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3076 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3077 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3083 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3084 * For ASF and Pass Through versions of f/w this means that the
3085 * driver is no longer loaded. For AMT version (only with 82573)
3086 * of the f/w this means that the network i/f is closed.
3089 emx_rel_hw_control(struct emx_softc *sc)
3091 if (!sc->control_hw)
3095 /* Let firmware taken over control of h/w */
3096 if (sc->hw.mac.type == e1000_82573) {
3099 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3100 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3101 swsm & ~E1000_SWSM_DRV_LOAD);
3105 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3106 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3107 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3112 emx_is_valid_eaddr(const uint8_t *addr)
3114 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3116 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3123 * Enable PCI Wake On Lan capability
3126 emx_enable_wol(device_t dev)
3128 uint16_t cap, status;
3131 /* First find the capabilities pointer*/
3132 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3134 /* Read the PM Capabilities */
3135 id = pci_read_config(dev, cap, 1);
3136 if (id != PCIY_PMG) /* Something wrong */
3140 * OK, we have the power capabilities,
3141 * so now get the status register
3143 cap += PCIR_POWER_STATUS;
3144 status = pci_read_config(dev, cap, 2);
3145 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3146 pci_write_config(dev, cap, status, 2);
3150 emx_update_stats(struct emx_softc *sc)
3152 struct ifnet *ifp = &sc->arpcom.ac_if;
3154 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3155 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3156 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3157 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3159 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3160 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3161 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3162 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3164 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3165 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3166 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3167 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3168 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3169 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3170 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3171 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3172 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3173 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3174 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3175 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3176 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3177 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3178 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3179 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3180 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3181 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3182 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3183 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3185 /* For the 64-bit byte counters the low dword must be read first. */
3186 /* Both registers clear on the read of the high dword */
3188 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3189 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3191 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3192 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3193 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3194 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3195 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3197 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3198 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3200 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3201 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3202 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3203 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3204 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3205 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3206 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3207 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3208 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3209 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3211 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3212 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3213 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3214 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3215 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3216 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3218 ifp->if_collisions = sc->stats.colc;
3221 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3222 sc->stats.crcerrs + sc->stats.algnerrc +
3223 sc->stats.ruc + sc->stats.roc +
3224 sc->stats.mpc + sc->stats.cexterr;
3227 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3228 sc->watchdog_events;
3232 emx_print_debug_info(struct emx_softc *sc)
3234 device_t dev = sc->dev;
3235 uint8_t *hw_addr = sc->hw.hw_addr;
3237 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3238 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3239 E1000_READ_REG(&sc->hw, E1000_CTRL),
3240 E1000_READ_REG(&sc->hw, E1000_RCTL));
3241 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3242 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3243 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3244 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3245 sc->hw.fc.high_water, sc->hw.fc.low_water);
3246 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3247 E1000_READ_REG(&sc->hw, E1000_TIDV),
3248 E1000_READ_REG(&sc->hw, E1000_TADV));
3249 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3250 E1000_READ_REG(&sc->hw, E1000_RDTR),
3251 E1000_READ_REG(&sc->hw, E1000_RADV));
3252 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3253 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3254 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3255 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3256 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3257 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3258 device_printf(dev, "Num Tx descriptors avail = %d\n",
3259 sc->num_tx_desc_avail);
3260 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3261 sc->no_tx_desc_avail1);
3262 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3263 sc->no_tx_desc_avail2);
3264 device_printf(dev, "Std mbuf failed = %ld\n",
3265 sc->mbuf_alloc_failed);
3266 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3267 sc->rx_data[0].mbuf_cluster_failed);
3268 device_printf(dev, "Driver dropped packets = %ld\n",
3270 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3271 sc->no_tx_dma_setup);
3273 device_printf(dev, "TXCSUM try pullup = %lu\n",
3274 sc->tx_csum_try_pullup);
3275 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3276 sc->tx_csum_pullup1);
3277 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3278 sc->tx_csum_pullup1_failed);
3279 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3280 sc->tx_csum_pullup2);
3281 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3282 sc->tx_csum_pullup2_failed);
3283 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3285 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3290 emx_print_hw_stats(struct emx_softc *sc)
3292 device_t dev = sc->dev;
3294 device_printf(dev, "Excessive collisions = %lld\n",
3295 (long long)sc->stats.ecol);
3296 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3297 device_printf(dev, "Symbol errors = %lld\n",
3298 (long long)sc->stats.symerrs);
3300 device_printf(dev, "Sequence errors = %lld\n",
3301 (long long)sc->stats.sec);
3302 device_printf(dev, "Defer count = %lld\n",
3303 (long long)sc->stats.dc);
3304 device_printf(dev, "Missed Packets = %lld\n",
3305 (long long)sc->stats.mpc);
3306 device_printf(dev, "Receive No Buffers = %lld\n",
3307 (long long)sc->stats.rnbc);
3308 /* RLEC is inaccurate on some hardware, calculate our own. */
3309 device_printf(dev, "Receive Length Errors = %lld\n",
3310 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3311 device_printf(dev, "Receive errors = %lld\n",
3312 (long long)sc->stats.rxerrc);
3313 device_printf(dev, "Crc errors = %lld\n",
3314 (long long)sc->stats.crcerrs);
3315 device_printf(dev, "Alignment errors = %lld\n",
3316 (long long)sc->stats.algnerrc);
3317 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3318 (long long)sc->stats.cexterr);
3319 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3320 device_printf(dev, "watchdog timeouts = %ld\n",
3321 sc->watchdog_events);
3322 device_printf(dev, "XON Rcvd = %lld\n",
3323 (long long)sc->stats.xonrxc);
3324 device_printf(dev, "XON Xmtd = %lld\n",
3325 (long long)sc->stats.xontxc);
3326 device_printf(dev, "XOFF Rcvd = %lld\n",
3327 (long long)sc->stats.xoffrxc);
3328 device_printf(dev, "XOFF Xmtd = %lld\n",
3329 (long long)sc->stats.xofftxc);
3330 device_printf(dev, "Good Packets Rcvd = %lld\n",
3331 (long long)sc->stats.gprc);
3332 device_printf(dev, "Good Packets Xmtd = %lld\n",
3333 (long long)sc->stats.gptc);
3337 emx_print_nvm_info(struct emx_softc *sc)
3339 uint16_t eeprom_data;
3342 /* Its a bit crude, but it gets the job done */
3343 kprintf("\nInterface EEPROM Dump:\n");
3344 kprintf("Offset\n0x0000 ");
3345 for (i = 0, j = 0; i < 32; i++, j++) {
3346 if (j == 8) { /* Make the offset block */
3348 kprintf("\n0x00%x0 ",row);
3350 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3351 kprintf("%04x ", eeprom_data);
3357 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3359 struct emx_softc *sc;
3364 error = sysctl_handle_int(oidp, &result, 0, req);
3365 if (error || !req->newptr)
3368 sc = (struct emx_softc *)arg1;
3369 ifp = &sc->arpcom.ac_if;
3371 ifnet_serialize_all(ifp);
3374 emx_print_debug_info(sc);
3377 * This value will cause a hex dump of the
3378 * first 32 16-bit words of the EEPROM to
3382 emx_print_nvm_info(sc);
3384 ifnet_deserialize_all(ifp);
3390 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3395 error = sysctl_handle_int(oidp, &result, 0, req);
3396 if (error || !req->newptr)
3400 struct emx_softc *sc = (struct emx_softc *)arg1;
3401 struct ifnet *ifp = &sc->arpcom.ac_if;
3403 ifnet_serialize_all(ifp);
3404 emx_print_hw_stats(sc);
3405 ifnet_deserialize_all(ifp);
3411 emx_add_sysctl(struct emx_softc *sc)
3413 #ifdef EMX_RSS_DEBUG
3418 sysctl_ctx_init(&sc->sysctl_ctx);
3419 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3420 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3421 device_get_nameunit(sc->dev),
3423 if (sc->sysctl_tree == NULL) {
3424 device_printf(sc->dev, "can't add sysctl node\n");
3428 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3429 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3430 emx_sysctl_debug_info, "I", "Debug Information");
3432 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3433 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3434 emx_sysctl_stats, "I", "Statistics");
3436 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3437 OID_AUTO, "rxd", CTLFLAG_RD,
3438 &sc->rx_data[0].num_rx_desc, 0, NULL);
3439 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3440 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3442 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3443 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3444 sc, 0, emx_sysctl_int_throttle, "I",
3445 "interrupt throttling rate");
3446 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3447 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3448 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3449 "# segments per TX interrupt");
3451 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3452 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD,
3453 &sc->rx_ring_inuse, 0, "RX ring in use");
3455 #ifdef EMX_RSS_DEBUG
3456 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3457 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3458 0, "RSS debug level");
3459 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3460 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3461 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3462 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3464 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3470 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3472 struct emx_softc *sc = (void *)arg1;
3473 struct ifnet *ifp = &sc->arpcom.ac_if;
3474 int error, throttle;
3476 throttle = sc->int_throttle_ceil;
3477 error = sysctl_handle_int(oidp, &throttle, 0, req);
3478 if (error || req->newptr == NULL)
3480 if (throttle < 0 || throttle > 1000000000 / 256)
3485 * Set the interrupt throttling rate in 256ns increments,
3486 * recalculate sysctl value assignment to get exact frequency.
3488 throttle = 1000000000 / 256 / throttle;
3490 /* Upper 16bits of ITR is reserved and should be zero */
3491 if (throttle & 0xffff0000)
3495 ifnet_serialize_all(ifp);
3498 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3500 sc->int_throttle_ceil = 0;
3502 if (ifp->if_flags & IFF_RUNNING)
3503 emx_set_itr(sc, throttle);
3505 ifnet_deserialize_all(ifp);
3508 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3509 sc->int_throttle_ceil);
3515 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3517 struct emx_softc *sc = (void *)arg1;
3518 struct ifnet *ifp = &sc->arpcom.ac_if;
3521 segs = sc->tx_int_nsegs;
3522 error = sysctl_handle_int(oidp, &segs, 0, req);
3523 if (error || req->newptr == NULL)
3528 ifnet_serialize_all(ifp);
3531 * Don't allow int_tx_nsegs to become:
3532 * o Less the oact_tx_desc
3533 * o Too large that no TX desc will cause TX interrupt to
3534 * be generated (OACTIVE will never recover)
3535 * o Too small that will cause tx_dd[] overflow
3537 if (segs < sc->oact_tx_desc ||
3538 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3539 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3543 sc->tx_int_nsegs = segs;
3546 ifnet_deserialize_all(ifp);
3552 emx_dma_alloc(struct emx_softc *sc)
3557 * Create top level busdma tag
3559 error = bus_dma_tag_create(NULL, 1, 0,
3560 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3562 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3563 0, &sc->parent_dtag);
3565 device_printf(sc->dev, "could not create top level DMA tag\n");
3570 * Allocate transmit descriptors ring and buffers
3572 error = emx_create_tx_ring(sc);
3574 device_printf(sc->dev, "Could not setup transmit structures\n");
3579 * Allocate receive descriptors ring and buffers
3581 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3582 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3584 device_printf(sc->dev,
3585 "Could not setup receive structures\n");
3593 emx_dma_free(struct emx_softc *sc)
3597 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3599 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3600 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3601 sc->rx_data[i].num_rx_desc);
3604 /* Free top level busdma tag */
3605 if (sc->parent_dtag != NULL)
3606 bus_dma_tag_destroy(sc->parent_dtag);
3610 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3612 struct emx_softc *sc = ifp->if_softc;
3615 case IFNET_SERIALIZE_ALL:
3616 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0);
3619 case IFNET_SERIALIZE_MAIN:
3620 lwkt_serialize_enter(&sc->main_serialize);
3623 case IFNET_SERIALIZE_TX:
3624 lwkt_serialize_enter(&sc->tx_serialize);
3627 case IFNET_SERIALIZE_RX(0):
3628 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize);
3631 case IFNET_SERIALIZE_RX(1):
3632 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize);
3636 panic("%s unsupported serialize type\n", ifp->if_xname);
3641 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3643 struct emx_softc *sc = ifp->if_softc;
3646 case IFNET_SERIALIZE_ALL:
3647 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0);
3650 case IFNET_SERIALIZE_MAIN:
3651 lwkt_serialize_exit(&sc->main_serialize);
3654 case IFNET_SERIALIZE_TX:
3655 lwkt_serialize_exit(&sc->tx_serialize);
3658 case IFNET_SERIALIZE_RX(0):
3659 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize);
3662 case IFNET_SERIALIZE_RX(1):
3663 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize);
3667 panic("%s unsupported serialize type\n", ifp->if_xname);
3672 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3674 struct emx_softc *sc = ifp->if_softc;
3677 case IFNET_SERIALIZE_ALL:
3678 return lwkt_serialize_array_try(sc->serializes,
3681 case IFNET_SERIALIZE_MAIN:
3682 return lwkt_serialize_try(&sc->main_serialize);
3684 case IFNET_SERIALIZE_TX:
3685 return lwkt_serialize_try(&sc->tx_serialize);
3687 case IFNET_SERIALIZE_RX(0):
3688 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize);
3690 case IFNET_SERIALIZE_RX(1):
3691 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize);
3694 panic("%s unsupported serialize type\n", ifp->if_xname);
3699 emx_serialize_skipmain(struct emx_softc *sc)
3701 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3705 emx_deserialize_skipmain(struct emx_softc *sc)
3707 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3713 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3714 boolean_t serialized)
3716 struct emx_softc *sc = ifp->if_softc;
3720 case IFNET_SERIALIZE_ALL:
3722 for (i = 0; i < EMX_NSERIALIZE; ++i)
3723 ASSERT_SERIALIZED(sc->serializes[i]);
3725 for (i = 0; i < EMX_NSERIALIZE; ++i)
3726 ASSERT_NOT_SERIALIZED(sc->serializes[i]);
3730 case IFNET_SERIALIZE_MAIN:
3732 ASSERT_SERIALIZED(&sc->main_serialize);
3734 ASSERT_NOT_SERIALIZED(&sc->main_serialize);
3737 case IFNET_SERIALIZE_TX:
3739 ASSERT_SERIALIZED(&sc->tx_serialize);
3741 ASSERT_NOT_SERIALIZED(&sc->tx_serialize);
3744 case IFNET_SERIALIZE_RX(0):
3746 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3748 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3751 case IFNET_SERIALIZE_RX(1):
3753 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3755 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3759 panic("%s unsupported serialize type\n", ifp->if_xname);
3763 #endif /* INVARIANTS */
3765 #ifdef IFPOLL_ENABLE
3768 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3770 struct emx_softc *sc = ifp->if_softc;
3773 ASSERT_SERIALIZED(&sc->main_serialize);
3775 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3776 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3777 emx_serialize_skipmain(sc);
3779 callout_stop(&sc->timer);
3780 sc->hw.mac.get_link_status = 1;
3781 emx_update_link_status(sc);
3782 callout_reset(&sc->timer, hz, emx_timer, sc);
3784 emx_deserialize_skipmain(sc);
3789 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3791 struct emx_softc *sc = ifp->if_softc;
3793 ASSERT_SERIALIZED(&sc->tx_serialize);
3796 if (!ifq_is_empty(&ifp->if_snd))
3801 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3803 struct emx_softc *sc = ifp->if_softc;
3804 struct emx_rxdata *rdata = arg;
3806 ASSERT_SERIALIZED(&rdata->rx_serialize);
3808 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3812 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3814 struct emx_softc *sc = ifp->if_softc;
3816 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3821 info->ifpi_status.status_func = emx_qpoll_status;
3822 info->ifpi_status.serializer = &sc->main_serialize;
3824 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3825 info->ifpi_tx[0].arg = NULL;
3826 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3828 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3829 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3830 info->ifpi_rx[i].arg = &sc->rx_data[i];
3831 info->ifpi_rx[i].serializer =
3832 &sc->rx_data[i].rx_serialize;
3835 if (ifp->if_flags & IFF_RUNNING)
3836 emx_disable_intr(sc);
3837 } else if (ifp->if_flags & IFF_RUNNING) {
3838 emx_enable_intr(sc);
3842 #endif /* IFPOLL_ENABLE */
3845 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3847 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3848 if (sc->hw.mac.type == e1000_82574) {
3852 * When using MSIX interrupts we need to
3853 * throttle using the EITR register
3855 for (i = 0; i < 4; ++i)
3856 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);