2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
71 #include <sys/param.h>
73 #include <sys/endian.h>
74 #include <sys/interrupt.h>
75 #include <sys/kernel.h>
77 #include <sys/malloc.h>
81 #include <sys/serialize.h>
82 #include <sys/serialize2.h>
83 #include <sys/socket.h>
84 #include <sys/sockio.h>
85 #include <sys/sysctl.h>
86 #include <sys/systm.h>
89 #include <net/ethernet.h>
91 #include <net/if_arp.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
94 #include <net/ifq_var.h>
95 #include <net/toeplitz.h>
96 #include <net/toeplitz2.h>
97 #include <net/vlan/if_vlan_var.h>
98 #include <net/vlan/if_vlan_ether.h>
99 #include <net/if_poll.h>
101 #include <netinet/in_systm.h>
102 #include <netinet/in.h>
103 #include <netinet/ip.h>
104 #include <netinet/tcp.h>
105 #include <netinet/udp.h>
107 #include <bus/pci/pcivar.h>
108 #include <bus/pci/pcireg.h>
110 #include <dev/netif/ig_hal/e1000_api.h>
111 #include <dev/netif/ig_hal/e1000_82571.h>
112 #include <dev/netif/emx/if_emx.h>
115 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
117 if (sc->rss_debug >= lvl) \
118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
120 #else /* !EMX_RSS_DEBUG */
121 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
122 #endif /* EMX_RSS_DEBUG */
124 #define EMX_NAME "Intel(R) PRO/1000 "
126 #define EMX_DEVICE(id) \
127 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
128 #define EMX_DEVICE_NULL { 0, 0, NULL }
130 static const struct emx_device {
135 EMX_DEVICE(82571EB_COPPER),
136 EMX_DEVICE(82571EB_FIBER),
137 EMX_DEVICE(82571EB_SERDES),
138 EMX_DEVICE(82571EB_SERDES_DUAL),
139 EMX_DEVICE(82571EB_SERDES_QUAD),
140 EMX_DEVICE(82571EB_QUAD_COPPER),
141 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
142 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
143 EMX_DEVICE(82571EB_QUAD_FIBER),
144 EMX_DEVICE(82571PT_QUAD_COPPER),
146 EMX_DEVICE(82572EI_COPPER),
147 EMX_DEVICE(82572EI_FIBER),
148 EMX_DEVICE(82572EI_SERDES),
152 EMX_DEVICE(82573E_IAMT),
155 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
156 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
157 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
163 /* required last entry */
167 static int emx_probe(device_t);
168 static int emx_attach(device_t);
169 static int emx_detach(device_t);
170 static int emx_shutdown(device_t);
171 static int emx_suspend(device_t);
172 static int emx_resume(device_t);
174 static void emx_init(void *);
175 static void emx_stop(struct emx_softc *);
176 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
177 static void emx_start(struct ifnet *);
179 static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
181 static void emx_watchdog(struct ifnet *);
182 static void emx_media_status(struct ifnet *, struct ifmediareq *);
183 static int emx_media_change(struct ifnet *);
184 static void emx_timer(void *);
185 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
186 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
187 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
189 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
193 static void emx_intr(void *);
194 static void emx_rxeof(struct emx_softc *, int, int);
195 static void emx_txeof(struct emx_softc *);
196 static void emx_tx_collect(struct emx_softc *);
197 static void emx_tx_purge(struct emx_softc *);
198 static void emx_enable_intr(struct emx_softc *);
199 static void emx_disable_intr(struct emx_softc *);
201 static int emx_dma_alloc(struct emx_softc *);
202 static void emx_dma_free(struct emx_softc *);
203 static void emx_init_tx_ring(struct emx_softc *);
204 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
205 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
206 static int emx_create_tx_ring(struct emx_softc *);
207 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
208 static void emx_destroy_tx_ring(struct emx_softc *, int);
209 static void emx_destroy_rx_ring(struct emx_softc *,
210 struct emx_rxdata *, int);
211 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
212 static int emx_encap(struct emx_softc *, struct mbuf **);
213 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
214 static int emx_txcsum(struct emx_softc *, struct mbuf *,
215 uint32_t *, uint32_t *);
217 static int emx_is_valid_eaddr(const uint8_t *);
218 static int emx_reset(struct emx_softc *);
219 static void emx_setup_ifp(struct emx_softc *);
220 static void emx_init_tx_unit(struct emx_softc *);
221 static void emx_init_rx_unit(struct emx_softc *);
222 static void emx_update_stats(struct emx_softc *);
223 static void emx_set_promisc(struct emx_softc *);
224 static void emx_disable_promisc(struct emx_softc *);
225 static void emx_set_multi(struct emx_softc *);
226 static void emx_update_link_status(struct emx_softc *);
227 static void emx_smartspeed(struct emx_softc *);
228 static void emx_set_itr(struct emx_softc *, uint32_t);
230 static void emx_print_debug_info(struct emx_softc *);
231 static void emx_print_nvm_info(struct emx_softc *);
232 static void emx_print_hw_stats(struct emx_softc *);
234 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
235 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
236 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
237 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
238 static void emx_add_sysctl(struct emx_softc *);
240 static void emx_serialize_skipmain(struct emx_softc *);
241 static void emx_deserialize_skipmain(struct emx_softc *);
243 /* Management and WOL Support */
244 static void emx_get_mgmt(struct emx_softc *);
245 static void emx_rel_mgmt(struct emx_softc *);
246 static void emx_get_hw_control(struct emx_softc *);
247 static void emx_rel_hw_control(struct emx_softc *);
248 static void emx_enable_wol(device_t);
250 static device_method_t emx_methods[] = {
251 /* Device interface */
252 DEVMETHOD(device_probe, emx_probe),
253 DEVMETHOD(device_attach, emx_attach),
254 DEVMETHOD(device_detach, emx_detach),
255 DEVMETHOD(device_shutdown, emx_shutdown),
256 DEVMETHOD(device_suspend, emx_suspend),
257 DEVMETHOD(device_resume, emx_resume),
261 static driver_t emx_driver = {
264 sizeof(struct emx_softc),
267 static devclass_t emx_devclass;
269 DECLARE_DUMMY_MODULE(if_emx);
270 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
271 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
276 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
277 static int emx_rxd = EMX_DEFAULT_RXD;
278 static int emx_txd = EMX_DEFAULT_TXD;
279 static int emx_smart_pwr_down = 0;
281 /* Controls whether promiscuous also shows bad packets */
282 static int emx_debug_sbp = FALSE;
284 static int emx_82573_workaround = 1;
285 static int emx_msi_enable = 1;
287 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
288 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
289 TUNABLE_INT("hw.emx.txd", &emx_txd);
290 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
291 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
292 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
293 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
295 /* Global used in WOL setup with multiport cards */
296 static int emx_global_quad_port_a = 0;
298 /* Set this to one to display debug statistics */
299 static int emx_display_debug_stats = 0;
301 #if !defined(KTR_IF_EMX)
302 #define KTR_IF_EMX KTR_ALL
304 KTR_INFO_MASTER(if_emx);
305 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
306 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
307 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
308 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
309 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
310 #define logif(name) KTR_LOG(if_emx_ ## name)
313 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
315 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
316 /* DD bit must be cleared */
317 rxd->rxd_staterr = 0;
321 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
323 /* Ignore Checksum bit is set */
324 if (staterr & E1000_RXD_STAT_IXSM)
327 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
329 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
331 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
332 E1000_RXD_STAT_TCPCS) {
333 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
335 CSUM_FRAG_NOT_CHECKED;
336 mp->m_pkthdr.csum_data = htons(0xffff);
340 static __inline struct pktinfo *
341 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
342 uint32_t mrq, uint32_t hash, uint32_t staterr)
344 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
345 case EMX_RXDMRQ_IPV4_TCP:
346 pi->pi_netisr = NETISR_IP;
348 pi->pi_l3proto = IPPROTO_TCP;
351 case EMX_RXDMRQ_IPV6_TCP:
352 pi->pi_netisr = NETISR_IPV6;
354 pi->pi_l3proto = IPPROTO_TCP;
357 case EMX_RXDMRQ_IPV4:
358 if (staterr & E1000_RXD_STAT_IXSM)
362 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
363 E1000_RXD_STAT_TCPCS) {
364 pi->pi_netisr = NETISR_IP;
366 pi->pi_l3proto = IPPROTO_UDP;
374 m->m_flags |= M_HASH;
375 m->m_pkthdr.hash = toeplitz_hash(hash);
380 emx_probe(device_t dev)
382 const struct emx_device *d;
385 vid = pci_get_vendor(dev);
386 did = pci_get_device(dev);
388 for (d = emx_devices; d->desc != NULL; ++d) {
389 if (vid == d->vid && did == d->did) {
390 device_set_desc(dev, d->desc);
391 device_set_async_attach(dev, TRUE);
399 emx_attach(device_t dev)
401 struct emx_softc *sc = device_get_softc(dev);
402 struct ifnet *ifp = &sc->arpcom.ac_if;
405 uint16_t eeprom_data, device_id, apme_mask;
407 lwkt_serialize_init(&sc->main_serialize);
408 lwkt_serialize_init(&sc->tx_serialize);
409 for (i = 0; i < EMX_NRX_RING; ++i)
410 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
413 sc->serializes[i++] = &sc->main_serialize;
414 sc->serializes[i++] = &sc->tx_serialize;
415 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
416 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
417 KKASSERT(i == EMX_NSERIALIZE);
419 callout_init_mp(&sc->timer);
421 sc->dev = sc->osdep.dev = dev;
424 * Determine hardware and mac type
426 sc->hw.vendor_id = pci_get_vendor(dev);
427 sc->hw.device_id = pci_get_device(dev);
428 sc->hw.revision_id = pci_get_revid(dev);
429 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
430 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
432 if (e1000_set_mac_type(&sc->hw))
435 /* Enable bus mastering */
436 pci_enable_busmaster(dev);
441 sc->memory_rid = EMX_BAR_MEM;
442 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
443 &sc->memory_rid, RF_ACTIVE);
444 if (sc->memory == NULL) {
445 device_printf(dev, "Unable to allocate bus resource: memory\n");
449 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
450 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
452 /* XXX This is quite goofy, it is not actually used */
453 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
458 sc->intr_type = pci_alloc_1intr(dev, emx_msi_enable,
459 &sc->intr_rid, &intr_flags);
461 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
463 if (sc->intr_res == NULL) {
464 device_printf(dev, "Unable to allocate bus resource: "
470 /* Save PCI command register for Shared Code */
471 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
472 sc->hw.back = &sc->osdep;
474 /* Do Shared Code initialization */
475 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
476 device_printf(dev, "Setup of Shared code failed\n");
480 e1000_get_bus_info(&sc->hw);
482 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
483 sc->hw.phy.autoneg_wait_to_complete = FALSE;
484 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
487 * Interrupt throttle rate
489 if (emx_int_throttle_ceil == 0) {
490 sc->int_throttle_ceil = 0;
492 int throttle = emx_int_throttle_ceil;
495 throttle = EMX_DEFAULT_ITR;
497 /* Recalculate the tunable value to get the exact frequency. */
498 throttle = 1000000000 / 256 / throttle;
500 /* Upper 16bits of ITR is reserved and should be zero */
501 if (throttle & 0xffff0000)
502 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
504 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
507 e1000_init_script_state_82541(&sc->hw, TRUE);
508 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
511 if (sc->hw.phy.media_type == e1000_media_type_copper) {
512 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
513 sc->hw.phy.disable_polarity_correction = FALSE;
514 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
517 /* Set the frame limits assuming standard ethernet sized frames. */
518 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
519 sc->min_frame_size = ETHER_MIN_LEN;
521 /* This controls when hardware reports transmit completion status. */
522 sc->hw.mac.report_tx_early = 1;
524 /* Calculate # of RX rings */
526 sc->rx_ring_cnt = EMX_NRX_RING;
529 sc->rx_ring_inuse = sc->rx_ring_cnt;
531 /* Allocate RX/TX rings' busdma(9) stuffs */
532 error = emx_dma_alloc(sc);
536 /* Allocate multicast array memory. */
537 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
540 /* Indicate SOL/IDER usage */
541 if (e1000_check_reset_block(&sc->hw)) {
543 "PHY reset is blocked due to SOL/IDER session.\n");
547 * Start from a known state, this is important in reading the
548 * nvm and mac from that.
550 e1000_reset_hw(&sc->hw);
552 /* Make sure we have a good EEPROM before we read from it */
553 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
555 * Some PCI-E parts fail the first check due to
556 * the link being in sleep state, call it again,
557 * if it fails a second time its a real issue.
559 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
561 "The EEPROM Checksum Is Not Valid\n");
567 /* Copy the permanent MAC address out of the EEPROM */
568 if (e1000_read_mac_addr(&sc->hw) < 0) {
569 device_printf(dev, "EEPROM read error while reading MAC"
574 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
575 device_printf(dev, "Invalid MAC address\n");
580 /* Determine if we have to control management hardware */
581 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
586 apme_mask = EMX_EEPROM_APME;
588 switch (sc->hw.mac.type) {
595 case e1000_80003es2lan:
596 if (sc->hw.bus.func == 1) {
597 e1000_read_nvm(&sc->hw,
598 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
600 e1000_read_nvm(&sc->hw,
601 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
606 e1000_read_nvm(&sc->hw,
607 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
610 if (eeprom_data & apme_mask)
611 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
614 * We have the eeprom settings, now apply the special cases
615 * where the eeprom may be wrong or the board won't support
616 * wake on lan on a particular port
618 device_id = pci_get_device(dev);
620 case E1000_DEV_ID_82571EB_FIBER:
622 * Wake events only supported on port A for dual fiber
623 * regardless of eeprom setting
625 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
630 case E1000_DEV_ID_82571EB_QUAD_COPPER:
631 case E1000_DEV_ID_82571EB_QUAD_FIBER:
632 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
633 /* if quad port sc, disable WoL on all but port A */
634 if (emx_global_quad_port_a != 0)
636 /* Reset for multiple quad port adapters */
637 if (++emx_global_quad_port_a == 4)
638 emx_global_quad_port_a = 0;
642 /* XXX disable wol */
645 /* Setup OS specific network interface */
648 /* Add sysctl tree, must after em_setup_ifp() */
651 /* Reset the hardware */
652 error = emx_reset(sc);
654 device_printf(dev, "Unable to reset the hardware\n");
658 /* Initialize statistics */
659 emx_update_stats(sc);
661 sc->hw.mac.get_link_status = 1;
662 emx_update_link_status(sc);
664 sc->spare_tx_desc = EMX_TX_SPARE;
667 * Keep following relationship between spare_tx_desc, oact_tx_desc
669 * (spare_tx_desc + EMX_TX_RESERVED) <=
670 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
672 sc->oact_tx_desc = sc->num_tx_desc / 8;
673 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
674 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
675 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
676 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
678 sc->tx_int_nsegs = sc->num_tx_desc / 16;
679 if (sc->tx_int_nsegs < sc->oact_tx_desc)
680 sc->tx_int_nsegs = sc->oact_tx_desc;
682 /* Non-AMT based hardware can now take control from firmware */
683 if (sc->has_manage && !sc->has_amt)
684 emx_get_hw_control(sc);
686 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
687 &sc->intr_tag, &sc->main_serialize);
689 device_printf(dev, "Failed to register interrupt handler");
690 ether_ifdetach(&sc->arpcom.ac_if);
694 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
695 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
703 emx_detach(device_t dev)
705 struct emx_softc *sc = device_get_softc(dev);
707 if (device_is_attached(dev)) {
708 struct ifnet *ifp = &sc->arpcom.ac_if;
710 ifnet_serialize_all(ifp);
714 e1000_phy_hw_reset(&sc->hw);
717 emx_rel_hw_control(sc);
720 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
721 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
725 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
727 ifnet_deserialize_all(ifp);
731 emx_rel_hw_control(sc);
733 bus_generic_detach(dev);
735 if (sc->intr_res != NULL) {
736 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
740 if (sc->intr_type == PCI_INTR_TYPE_MSI)
741 pci_release_msi(dev);
743 if (sc->memory != NULL) {
744 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
750 /* Free sysctl tree */
751 if (sc->sysctl_tree != NULL)
752 sysctl_ctx_free(&sc->sysctl_ctx);
758 emx_shutdown(device_t dev)
760 return emx_suspend(dev);
764 emx_suspend(device_t dev)
766 struct emx_softc *sc = device_get_softc(dev);
767 struct ifnet *ifp = &sc->arpcom.ac_if;
769 ifnet_serialize_all(ifp);
774 emx_rel_hw_control(sc);
777 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
778 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
782 ifnet_deserialize_all(ifp);
784 return bus_generic_suspend(dev);
788 emx_resume(device_t dev)
790 struct emx_softc *sc = device_get_softc(dev);
791 struct ifnet *ifp = &sc->arpcom.ac_if;
793 ifnet_serialize_all(ifp);
799 ifnet_deserialize_all(ifp);
801 return bus_generic_resume(dev);
805 emx_start(struct ifnet *ifp)
807 struct emx_softc *sc = ifp->if_softc;
810 ASSERT_SERIALIZED(&sc->tx_serialize);
812 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
815 if (!sc->link_active) {
816 ifq_purge(&ifp->if_snd);
820 while (!ifq_is_empty(&ifp->if_snd)) {
821 /* Now do we at least have a minimal? */
822 if (EMX_IS_OACTIVE(sc)) {
824 if (EMX_IS_OACTIVE(sc)) {
825 ifp->if_flags |= IFF_OACTIVE;
826 sc->no_tx_desc_avail1++;
832 m_head = ifq_dequeue(&ifp->if_snd, NULL);
836 if (emx_encap(sc, &m_head)) {
842 /* Send a copy of the frame to the BPF listener */
843 ETHER_BPF_MTAP(ifp, m_head);
845 /* Set timeout in case hardware has problems transmitting. */
846 ifp->if_timer = EMX_TX_TIMEOUT;
851 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
853 struct emx_softc *sc = ifp->if_softc;
854 struct ifreq *ifr = (struct ifreq *)data;
855 uint16_t eeprom_data = 0;
856 int max_frame_size, mask, reinit;
859 ASSERT_IFNET_SERIALIZED_ALL(ifp);
863 switch (sc->hw.mac.type) {
866 * 82573 only supports jumbo frames
867 * if ASPM is disabled.
869 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
871 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
872 max_frame_size = ETHER_MAX_LEN;
877 /* Limit Jumbo Frame size */
881 case e1000_80003es2lan:
882 max_frame_size = 9234;
886 max_frame_size = MAX_JUMBO_FRAME_SIZE;
889 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
895 ifp->if_mtu = ifr->ifr_mtu;
896 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
899 if (ifp->if_flags & IFF_RUNNING)
904 if (ifp->if_flags & IFF_UP) {
905 if ((ifp->if_flags & IFF_RUNNING)) {
906 if ((ifp->if_flags ^ sc->if_flags) &
907 (IFF_PROMISC | IFF_ALLMULTI)) {
908 emx_disable_promisc(sc);
914 } else if (ifp->if_flags & IFF_RUNNING) {
917 sc->if_flags = ifp->if_flags;
922 if (ifp->if_flags & IFF_RUNNING) {
923 emx_disable_intr(sc);
926 if (!(ifp->if_flags & IFF_NPOLLING))
933 /* Check SOL/IDER usage */
934 if (e1000_check_reset_block(&sc->hw)) {
935 device_printf(sc->dev, "Media change is"
936 " blocked due to SOL/IDER session.\n");
942 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
947 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
948 if (mask & IFCAP_HWCSUM) {
949 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
952 if (mask & IFCAP_VLAN_HWTAGGING) {
953 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
956 if (mask & IFCAP_RSS) {
957 ifp->if_capenable ^= IFCAP_RSS;
960 if (reinit && (ifp->if_flags & IFF_RUNNING))
965 error = ether_ioctl(ifp, command, data);
972 emx_watchdog(struct ifnet *ifp)
974 struct emx_softc *sc = ifp->if_softc;
976 ASSERT_IFNET_SERIALIZED_ALL(ifp);
979 * The timer is set to 5 every time start queues a packet.
980 * Then txeof keeps resetting it as long as it cleans at
981 * least one descriptor.
982 * Finally, anytime all descriptors are clean the timer is
986 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
987 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
989 * If we reach here, all TX jobs are completed and
990 * the TX engine should have been idled for some time.
991 * We don't need to call if_devstart() here.
993 ifp->if_flags &= ~IFF_OACTIVE;
999 * If we are in this routine because of pause frames, then
1000 * don't reset the hardware.
1002 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1003 ifp->if_timer = EMX_TX_TIMEOUT;
1007 if (e1000_check_for_link(&sc->hw) == 0)
1008 if_printf(ifp, "watchdog timeout -- resetting\n");
1011 sc->watchdog_events++;
1015 if (!ifq_is_empty(&ifp->if_snd))
1022 struct emx_softc *sc = xsc;
1023 struct ifnet *ifp = &sc->arpcom.ac_if;
1024 device_t dev = sc->dev;
1028 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1033 * Packet Buffer Allocation (PBA)
1034 * Writing PBA sets the receive portion of the buffer
1035 * the remainder is used for the transmit buffer.
1037 switch (sc->hw.mac.type) {
1038 /* Total Packet Buffer on these is 48K */
1041 case e1000_80003es2lan:
1042 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1045 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1046 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1050 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1054 /* Devices before 82547 had a Packet Buffer of 64K. */
1055 if (sc->max_frame_size > 8192)
1056 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1058 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1060 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1062 /* Get the latest mac address, User can use a LAA */
1063 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1065 /* Put the address into the Receive Address Array */
1066 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1069 * With the 82571 sc, RAR[0] may be overwritten
1070 * when the other port is reset, we make a duplicate
1071 * in RAR[14] for that eventuality, this assures
1072 * the interface continues to function.
1074 if (sc->hw.mac.type == e1000_82571) {
1075 e1000_set_laa_state_82571(&sc->hw, TRUE);
1076 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1077 E1000_RAR_ENTRIES - 1);
1080 /* Initialize the hardware */
1081 if (emx_reset(sc)) {
1082 device_printf(dev, "Unable to reset the hardware\n");
1083 /* XXX emx_stop()? */
1086 emx_update_link_status(sc);
1088 /* Setup VLAN support, basic and offload if available */
1089 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1091 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1094 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1095 ctrl |= E1000_CTRL_VME;
1096 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1099 /* Set hardware offload abilities */
1100 if (ifp->if_capenable & IFCAP_TXCSUM)
1101 ifp->if_hwassist = EMX_CSUM_FEATURES;
1103 ifp->if_hwassist = 0;
1105 /* Configure for OS presence */
1108 /* Prepare transmit descriptors and buffers */
1109 emx_init_tx_ring(sc);
1110 emx_init_tx_unit(sc);
1112 /* Setup Multicast table */
1116 * Adjust # of RX ring to be used based on IFCAP_RSS
1118 if (ifp->if_capenable & IFCAP_RSS)
1119 sc->rx_ring_inuse = sc->rx_ring_cnt;
1121 sc->rx_ring_inuse = 1;
1123 /* Prepare receive descriptors and buffers */
1124 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1125 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1127 "Could not setup receive structures\n");
1132 emx_init_rx_unit(sc);
1134 /* Don't lose promiscuous settings */
1135 emx_set_promisc(sc);
1137 ifp->if_flags |= IFF_RUNNING;
1138 ifp->if_flags &= ~IFF_OACTIVE;
1140 callout_reset(&sc->timer, hz, emx_timer, sc);
1141 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1143 /* MSI/X configuration for 82574 */
1144 if (sc->hw.mac.type == e1000_82574) {
1147 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1148 tmp |= E1000_CTRL_EXT_PBA_CLR;
1149 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1152 * Set the IVAR - interrupt vector routing.
1153 * Each nibble represents a vector, high bit
1154 * is enable, other 3 bits are the MSIX table
1155 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1156 * Link (other) to 2, hence the magic number.
1158 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1161 #ifdef IFPOLL_ENABLE
1163 * Only enable interrupts if we are not polling, make sure
1164 * they are off otherwise.
1166 if (ifp->if_flags & IFF_NPOLLING)
1167 emx_disable_intr(sc);
1169 #endif /* IFPOLL_ENABLE */
1170 emx_enable_intr(sc);
1172 /* AMT based hardware can now take control from firmware */
1173 if (sc->has_manage && sc->has_amt)
1174 emx_get_hw_control(sc);
1176 /* Don't reset the phy next time init gets called */
1177 sc->hw.phy.reset_disable = TRUE;
1183 struct emx_softc *sc = xsc;
1184 struct ifnet *ifp = &sc->arpcom.ac_if;
1188 ASSERT_SERIALIZED(&sc->main_serialize);
1190 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1192 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1198 * XXX: some laptops trigger several spurious interrupts
1199 * on emx(4) when in the resume cycle. The ICR register
1200 * reports all-ones value in this case. Processing such
1201 * interrupts would lead to a freeze. I don't know why.
1203 if (reg_icr == 0xffffffff) {
1208 if (ifp->if_flags & IFF_RUNNING) {
1210 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1213 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1214 lwkt_serialize_enter(
1215 &sc->rx_data[i].rx_serialize);
1216 emx_rxeof(sc, i, -1);
1217 lwkt_serialize_exit(
1218 &sc->rx_data[i].rx_serialize);
1221 if (reg_icr & E1000_ICR_TXDW) {
1222 lwkt_serialize_enter(&sc->tx_serialize);
1224 if (!ifq_is_empty(&ifp->if_snd))
1226 lwkt_serialize_exit(&sc->tx_serialize);
1230 /* Link status change */
1231 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1232 emx_serialize_skipmain(sc);
1234 callout_stop(&sc->timer);
1235 sc->hw.mac.get_link_status = 1;
1236 emx_update_link_status(sc);
1238 /* Deal with TX cruft when link lost */
1241 callout_reset(&sc->timer, hz, emx_timer, sc);
1243 emx_deserialize_skipmain(sc);
1246 if (reg_icr & E1000_ICR_RXO)
1253 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1255 struct emx_softc *sc = ifp->if_softc;
1257 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1259 emx_update_link_status(sc);
1261 ifmr->ifm_status = IFM_AVALID;
1262 ifmr->ifm_active = IFM_ETHER;
1264 if (!sc->link_active)
1267 ifmr->ifm_status |= IFM_ACTIVE;
1269 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1270 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1271 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1273 switch (sc->link_speed) {
1275 ifmr->ifm_active |= IFM_10_T;
1278 ifmr->ifm_active |= IFM_100_TX;
1282 ifmr->ifm_active |= IFM_1000_T;
1285 if (sc->link_duplex == FULL_DUPLEX)
1286 ifmr->ifm_active |= IFM_FDX;
1288 ifmr->ifm_active |= IFM_HDX;
1293 emx_media_change(struct ifnet *ifp)
1295 struct emx_softc *sc = ifp->if_softc;
1296 struct ifmedia *ifm = &sc->media;
1298 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1300 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1303 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1305 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1306 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1312 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1313 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1317 sc->hw.mac.autoneg = FALSE;
1318 sc->hw.phy.autoneg_advertised = 0;
1319 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1320 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1322 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1326 sc->hw.mac.autoneg = FALSE;
1327 sc->hw.phy.autoneg_advertised = 0;
1328 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1329 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1331 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1335 if_printf(ifp, "Unsupported media type\n");
1340 * As the speed/duplex settings my have changed we need to
1343 sc->hw.phy.reset_disable = FALSE;
1351 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1353 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1355 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1356 struct e1000_tx_desc *ctxd = NULL;
1357 struct mbuf *m_head = *m_headp;
1358 uint32_t txd_upper, txd_lower, cmd = 0;
1359 int maxsegs, nsegs, i, j, first, last = 0, error;
1361 if (m_head->m_len < EMX_TXCSUM_MINHL &&
1362 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1364 * Make sure that ethernet header and ip.ip_hl are in
1365 * contiguous memory, since if TXCSUM is enabled, later
1366 * TX context descriptor's setup need to access ip.ip_hl.
1368 error = emx_txcsum_pullup(sc, m_headp);
1370 KKASSERT(*m_headp == NULL);
1376 txd_upper = txd_lower = 0;
1379 * Capture the first descriptor index, this descriptor
1380 * will have the index of the EOP which is the only one
1381 * that now gets a DONE bit writeback.
1383 first = sc->next_avail_tx_desc;
1384 tx_buffer = &sc->tx_buf[first];
1385 tx_buffer_mapped = tx_buffer;
1386 map = tx_buffer->map;
1388 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1389 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n"));
1390 if (maxsegs > EMX_MAX_SCATTER)
1391 maxsegs = EMX_MAX_SCATTER;
1393 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1394 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1396 if (error == ENOBUFS)
1397 sc->mbuf_alloc_failed++;
1399 sc->no_tx_dma_setup++;
1405 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1408 sc->tx_nsegs += nsegs;
1410 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1411 /* TX csum offloading will consume one TX desc */
1412 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1414 i = sc->next_avail_tx_desc;
1416 /* Set up our transmit descriptors */
1417 for (j = 0; j < nsegs; j++) {
1418 tx_buffer = &sc->tx_buf[i];
1419 ctxd = &sc->tx_desc_base[i];
1421 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1422 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1423 txd_lower | segs[j].ds_len);
1424 ctxd->upper.data = htole32(txd_upper);
1427 if (++i == sc->num_tx_desc)
1431 sc->next_avail_tx_desc = i;
1433 KKASSERT(sc->num_tx_desc_avail > nsegs);
1434 sc->num_tx_desc_avail -= nsegs;
1436 /* Handle VLAN tag */
1437 if (m_head->m_flags & M_VLANTAG) {
1438 /* Set the vlan id. */
1439 ctxd->upper.fields.special =
1440 htole16(m_head->m_pkthdr.ether_vlantag);
1442 /* Tell hardware to add tag */
1443 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1446 tx_buffer->m_head = m_head;
1447 tx_buffer_mapped->map = tx_buffer->map;
1448 tx_buffer->map = map;
1450 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1454 * Report Status (RS) is turned on
1455 * every tx_int_nsegs descriptors.
1457 cmd = E1000_TXD_CMD_RS;
1460 * Keep track of the descriptor, which will
1461 * be written back by hardware.
1463 sc->tx_dd[sc->tx_dd_tail] = last;
1464 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1465 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1469 * Last Descriptor of Packet needs End Of Packet (EOP)
1471 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1474 * Advance the Transmit Descriptor Tail (TDT), this tells
1475 * the E1000 that this frame is available to transmit.
1477 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1483 emx_set_promisc(struct emx_softc *sc)
1485 struct ifnet *ifp = &sc->arpcom.ac_if;
1488 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1490 if (ifp->if_flags & IFF_PROMISC) {
1491 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1492 /* Turn this on if you want to see bad packets */
1494 reg_rctl |= E1000_RCTL_SBP;
1495 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1496 } else if (ifp->if_flags & IFF_ALLMULTI) {
1497 reg_rctl |= E1000_RCTL_MPE;
1498 reg_rctl &= ~E1000_RCTL_UPE;
1499 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1504 emx_disable_promisc(struct emx_softc *sc)
1508 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1510 reg_rctl &= ~E1000_RCTL_UPE;
1511 reg_rctl &= ~E1000_RCTL_MPE;
1512 reg_rctl &= ~E1000_RCTL_SBP;
1513 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1517 emx_set_multi(struct emx_softc *sc)
1519 struct ifnet *ifp = &sc->arpcom.ac_if;
1520 struct ifmultiaddr *ifma;
1521 uint32_t reg_rctl = 0;
1526 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1528 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1529 if (ifma->ifma_addr->sa_family != AF_LINK)
1532 if (mcnt == EMX_MCAST_ADDR_MAX)
1535 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1536 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1540 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1541 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1542 reg_rctl |= E1000_RCTL_MPE;
1543 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1545 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1550 * This routine checks for link status and updates statistics.
1553 emx_timer(void *xsc)
1555 struct emx_softc *sc = xsc;
1556 struct ifnet *ifp = &sc->arpcom.ac_if;
1558 ifnet_serialize_all(ifp);
1560 emx_update_link_status(sc);
1561 emx_update_stats(sc);
1563 /* Reset LAA into RAR[0] on 82571 */
1564 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1565 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1567 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1568 emx_print_hw_stats(sc);
1572 callout_reset(&sc->timer, hz, emx_timer, sc);
1574 ifnet_deserialize_all(ifp);
1578 emx_update_link_status(struct emx_softc *sc)
1580 struct e1000_hw *hw = &sc->hw;
1581 struct ifnet *ifp = &sc->arpcom.ac_if;
1582 device_t dev = sc->dev;
1583 uint32_t link_check = 0;
1585 /* Get the cached link value or read phy for real */
1586 switch (hw->phy.media_type) {
1587 case e1000_media_type_copper:
1588 if (hw->mac.get_link_status) {
1589 /* Do the work to read phy */
1590 e1000_check_for_link(hw);
1591 link_check = !hw->mac.get_link_status;
1592 if (link_check) /* ESB2 fix */
1593 e1000_cfg_on_link_up(hw);
1599 case e1000_media_type_fiber:
1600 e1000_check_for_link(hw);
1601 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1604 case e1000_media_type_internal_serdes:
1605 e1000_check_for_link(hw);
1606 link_check = sc->hw.mac.serdes_has_link;
1609 case e1000_media_type_unknown:
1614 /* Now check for a transition */
1615 if (link_check && sc->link_active == 0) {
1616 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1620 * Check if we should enable/disable SPEED_MODE bit on
1623 if (sc->link_speed != SPEED_1000 &&
1624 (hw->mac.type == e1000_82571 ||
1625 hw->mac.type == e1000_82572)) {
1628 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1629 tarc0 &= ~EMX_TARC_SPEED_MODE;
1630 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1633 device_printf(dev, "Link is up %d Mbps %s\n",
1635 ((sc->link_duplex == FULL_DUPLEX) ?
1636 "Full Duplex" : "Half Duplex"));
1638 sc->link_active = 1;
1640 ifp->if_baudrate = sc->link_speed * 1000000;
1641 ifp->if_link_state = LINK_STATE_UP;
1642 if_link_state_change(ifp);
1643 } else if (!link_check && sc->link_active == 1) {
1644 ifp->if_baudrate = sc->link_speed = 0;
1645 sc->link_duplex = 0;
1647 device_printf(dev, "Link is Down\n");
1648 sc->link_active = 0;
1650 /* Link down, disable watchdog */
1653 ifp->if_link_state = LINK_STATE_DOWN;
1654 if_link_state_change(ifp);
1659 emx_stop(struct emx_softc *sc)
1661 struct ifnet *ifp = &sc->arpcom.ac_if;
1664 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1666 emx_disable_intr(sc);
1668 callout_stop(&sc->timer);
1670 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1674 * Disable multiple receive queues.
1677 * We should disable multiple receive queues before
1678 * resetting the hardware.
1680 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1682 e1000_reset_hw(&sc->hw);
1683 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1685 for (i = 0; i < sc->num_tx_desc; i++) {
1686 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1688 if (tx_buffer->m_head != NULL) {
1689 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1690 m_freem(tx_buffer->m_head);
1691 tx_buffer->m_head = NULL;
1695 for (i = 0; i < sc->rx_ring_inuse; ++i)
1696 emx_free_rx_ring(sc, &sc->rx_data[i]);
1700 sc->csum_iphlen = 0;
1708 emx_reset(struct emx_softc *sc)
1710 device_t dev = sc->dev;
1711 uint16_t rx_buffer_size;
1713 /* Set up smart power down as default off on newer adapters. */
1714 if (!emx_smart_pwr_down &&
1715 (sc->hw.mac.type == e1000_82571 ||
1716 sc->hw.mac.type == e1000_82572)) {
1717 uint16_t phy_tmp = 0;
1719 /* Speed up time to link by disabling smart power down. */
1720 e1000_read_phy_reg(&sc->hw,
1721 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1722 phy_tmp &= ~IGP02E1000_PM_SPD;
1723 e1000_write_phy_reg(&sc->hw,
1724 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1728 * These parameters control the automatic generation (Tx) and
1729 * response (Rx) to Ethernet PAUSE frames.
1730 * - High water mark should allow for at least two frames to be
1731 * received after sending an XOFF.
1732 * - Low water mark works best when it is very near the high water mark.
1733 * This allows the receiver to restart by sending XON when it has
1734 * drained a bit. Here we use an arbitary value of 1500 which will
1735 * restart after one full frame is pulled from the buffer. There
1736 * could be several smaller frames in the buffer and if so they will
1737 * not trigger the XON until their total number reduces the buffer
1739 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1741 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1743 sc->hw.fc.high_water = rx_buffer_size -
1744 roundup2(sc->max_frame_size, 1024);
1745 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1747 if (sc->hw.mac.type == e1000_80003es2lan)
1748 sc->hw.fc.pause_time = 0xFFFF;
1750 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1751 sc->hw.fc.send_xon = TRUE;
1752 sc->hw.fc.requested_mode = e1000_fc_full;
1754 /* Issue a global reset */
1755 e1000_reset_hw(&sc->hw);
1756 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1758 if (e1000_init_hw(&sc->hw) < 0) {
1759 device_printf(dev, "Hardware Initialization Failed\n");
1763 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1764 e1000_get_phy_info(&sc->hw);
1765 e1000_check_for_link(&sc->hw);
1771 emx_setup_ifp(struct emx_softc *sc)
1773 struct ifnet *ifp = &sc->arpcom.ac_if;
1775 if_initname(ifp, device_get_name(sc->dev),
1776 device_get_unit(sc->dev));
1778 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1779 ifp->if_init = emx_init;
1780 ifp->if_ioctl = emx_ioctl;
1781 ifp->if_start = emx_start;
1782 #ifdef IFPOLL_ENABLE
1783 ifp->if_qpoll = emx_qpoll;
1785 ifp->if_watchdog = emx_watchdog;
1786 ifp->if_serialize = emx_serialize;
1787 ifp->if_deserialize = emx_deserialize;
1788 ifp->if_tryserialize = emx_tryserialize;
1790 ifp->if_serialize_assert = emx_serialize_assert;
1792 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1793 ifq_set_ready(&ifp->if_snd);
1795 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1797 ifp->if_capabilities = IFCAP_HWCSUM |
1798 IFCAP_VLAN_HWTAGGING |
1800 if (sc->rx_ring_cnt > 1)
1801 ifp->if_capabilities |= IFCAP_RSS;
1802 ifp->if_capenable = ifp->if_capabilities;
1803 ifp->if_hwassist = EMX_CSUM_FEATURES;
1806 * Tell the upper layer(s) we support long frames.
1808 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1811 * Specify the media types supported by this sc and register
1812 * callbacks to update media and link information
1814 ifmedia_init(&sc->media, IFM_IMASK,
1815 emx_media_change, emx_media_status);
1816 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1817 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1818 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1820 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1822 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1823 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1825 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1826 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1828 if (sc->hw.phy.type != e1000_phy_ife) {
1829 ifmedia_add(&sc->media,
1830 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1831 ifmedia_add(&sc->media,
1832 IFM_ETHER | IFM_1000_T, 0, NULL);
1835 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1836 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1840 * Workaround for SmartSpeed on 82541 and 82547 controllers
1843 emx_smartspeed(struct emx_softc *sc)
1847 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1848 sc->hw.mac.autoneg == 0 ||
1849 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1852 if (sc->smartspeed == 0) {
1854 * If Master/Slave config fault is asserted twice,
1855 * we assume back-to-back
1857 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1858 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1860 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1861 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1862 e1000_read_phy_reg(&sc->hw,
1863 PHY_1000T_CTRL, &phy_tmp);
1864 if (phy_tmp & CR_1000T_MS_ENABLE) {
1865 phy_tmp &= ~CR_1000T_MS_ENABLE;
1866 e1000_write_phy_reg(&sc->hw,
1867 PHY_1000T_CTRL, phy_tmp);
1869 if (sc->hw.mac.autoneg &&
1870 !e1000_phy_setup_autoneg(&sc->hw) &&
1871 !e1000_read_phy_reg(&sc->hw,
1872 PHY_CONTROL, &phy_tmp)) {
1873 phy_tmp |= MII_CR_AUTO_NEG_EN |
1874 MII_CR_RESTART_AUTO_NEG;
1875 e1000_write_phy_reg(&sc->hw,
1876 PHY_CONTROL, phy_tmp);
1881 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1882 /* If still no link, perhaps using 2/3 pair cable */
1883 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1884 phy_tmp |= CR_1000T_MS_ENABLE;
1885 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1886 if (sc->hw.mac.autoneg &&
1887 !e1000_phy_setup_autoneg(&sc->hw) &&
1888 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1889 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1890 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1894 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1895 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1900 emx_create_tx_ring(struct emx_softc *sc)
1902 device_t dev = sc->dev;
1903 struct emx_txbuf *tx_buffer;
1904 int error, i, tsize;
1907 * Validate number of transmit descriptors. It must not exceed
1908 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1910 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1911 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) {
1912 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1913 EMX_DEFAULT_TXD, emx_txd);
1914 sc->num_tx_desc = EMX_DEFAULT_TXD;
1916 sc->num_tx_desc = emx_txd;
1920 * Allocate Transmit Descriptor ring
1922 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1924 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1925 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1926 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1927 &sc->tx_desc_paddr);
1928 if (sc->tx_desc_base == NULL) {
1929 device_printf(dev, "Unable to allocate tx_desc memory\n");
1933 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1934 M_DEVBUF, M_WAITOK | M_ZERO);
1937 * Create DMA tags for tx buffers
1939 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1940 1, 0, /* alignment, bounds */
1941 BUS_SPACE_MAXADDR, /* lowaddr */
1942 BUS_SPACE_MAXADDR, /* highaddr */
1943 NULL, NULL, /* filter, filterarg */
1944 EMX_TSO_SIZE, /* maxsize */
1945 EMX_MAX_SCATTER, /* nsegments */
1946 EMX_MAX_SEGSIZE, /* maxsegsize */
1947 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1948 BUS_DMA_ONEBPAGE, /* flags */
1951 device_printf(dev, "Unable to allocate TX DMA tag\n");
1952 kfree(sc->tx_buf, M_DEVBUF);
1958 * Create DMA maps for tx buffers
1960 for (i = 0; i < sc->num_tx_desc; i++) {
1961 tx_buffer = &sc->tx_buf[i];
1963 error = bus_dmamap_create(sc->txtag,
1964 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1967 device_printf(dev, "Unable to create TX DMA map\n");
1968 emx_destroy_tx_ring(sc, i);
1976 emx_init_tx_ring(struct emx_softc *sc)
1978 /* Clear the old ring contents */
1979 bzero(sc->tx_desc_base,
1980 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
1983 sc->next_avail_tx_desc = 0;
1984 sc->next_tx_to_clean = 0;
1985 sc->num_tx_desc_avail = sc->num_tx_desc;
1989 emx_init_tx_unit(struct emx_softc *sc)
1991 uint32_t tctl, tarc, tipg = 0;
1994 /* Setup the Base and Length of the Tx Descriptor Ring */
1995 bus_addr = sc->tx_desc_paddr;
1996 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
1997 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
1998 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
1999 (uint32_t)(bus_addr >> 32));
2000 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2001 (uint32_t)bus_addr);
2002 /* Setup the HW Tx Head and Tail descriptor pointers */
2003 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2004 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2006 /* Set the default values for the Tx Inter Packet Gap timer */
2007 switch (sc->hw.mac.type) {
2008 case e1000_80003es2lan:
2009 tipg = DEFAULT_82543_TIPG_IPGR1;
2010 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2011 E1000_TIPG_IPGR2_SHIFT;
2015 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2016 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2017 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2019 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2020 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2021 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2025 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2027 /* NOTE: 0 is not allowed for TIDV */
2028 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2029 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2031 if (sc->hw.mac.type == e1000_82571 ||
2032 sc->hw.mac.type == e1000_82572) {
2033 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2034 tarc |= EMX_TARC_SPEED_MODE;
2035 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2036 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2037 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2039 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2040 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2042 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2045 /* Program the Transmit Control Register */
2046 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2047 tctl &= ~E1000_TCTL_CT;
2048 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2049 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2050 tctl |= E1000_TCTL_MULR;
2052 /* This write will effectively turn on the transmit unit. */
2053 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2057 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2059 struct emx_txbuf *tx_buffer;
2062 /* Free Transmit Descriptor ring */
2063 if (sc->tx_desc_base) {
2064 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2065 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2067 bus_dma_tag_destroy(sc->tx_desc_dtag);
2069 sc->tx_desc_base = NULL;
2072 if (sc->tx_buf == NULL)
2075 for (i = 0; i < ndesc; i++) {
2076 tx_buffer = &sc->tx_buf[i];
2078 KKASSERT(tx_buffer->m_head == NULL);
2079 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2081 bus_dma_tag_destroy(sc->txtag);
2083 kfree(sc->tx_buf, M_DEVBUF);
2088 * The offload context needs to be set when we transfer the first
2089 * packet of a particular protocol (TCP/UDP). This routine has been
2090 * enhanced to deal with inserted VLAN headers.
2092 * If the new packet's ether header length, ip header length and
2093 * csum offloading type are same as the previous packet, we should
2094 * avoid allocating a new csum context descriptor; mainly to take
2095 * advantage of the pipeline effect of the TX data read request.
2097 * This function returns number of TX descrptors allocated for
2101 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2102 uint32_t *txd_upper, uint32_t *txd_lower)
2104 struct e1000_context_desc *TXD;
2105 struct emx_txbuf *tx_buffer;
2106 struct ether_vlan_header *eh;
2108 int curr_txd, ehdrlen, csum_flags;
2109 uint32_t cmd, hdr_len, ip_hlen;
2113 * Determine where frame payload starts.
2114 * Jump over vlan headers if already present,
2115 * helpful for QinQ too.
2117 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2118 ("emx_txcsum_pullup is not called (eh)?\n"));
2119 eh = mtod(mp, struct ether_vlan_header *);
2120 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2121 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2122 ("emx_txcsum_pullup is not called (evh)?\n"));
2123 etype = ntohs(eh->evl_proto);
2124 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2126 etype = ntohs(eh->evl_encap_proto);
2127 ehdrlen = ETHER_HDR_LEN;
2131 * We only support TCP/UDP for IPv4 for the moment.
2132 * TODO: Support SCTP too when it hits the tree.
2134 if (etype != ETHERTYPE_IP)
2137 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2138 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2140 /* NOTE: We could only safely access ip.ip_vhl part */
2141 ip = (struct ip *)(mp->m_data + ehdrlen);
2142 ip_hlen = ip->ip_hl << 2;
2144 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2146 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2147 sc->csum_flags == csum_flags) {
2149 * Same csum offload context as the previous packets;
2152 *txd_upper = sc->csum_txd_upper;
2153 *txd_lower = sc->csum_txd_lower;
2158 * Setup a new csum offload context.
2161 curr_txd = sc->next_avail_tx_desc;
2162 tx_buffer = &sc->tx_buf[curr_txd];
2163 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2167 /* Setup of IP header checksum. */
2168 if (csum_flags & CSUM_IP) {
2170 * Start offset for header checksum calculation.
2171 * End offset for header checksum calculation.
2172 * Offset of place to put the checksum.
2174 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2175 TXD->lower_setup.ip_fields.ipcse =
2176 htole16(ehdrlen + ip_hlen - 1);
2177 TXD->lower_setup.ip_fields.ipcso =
2178 ehdrlen + offsetof(struct ip, ip_sum);
2179 cmd |= E1000_TXD_CMD_IP;
2180 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2182 hdr_len = ehdrlen + ip_hlen;
2184 if (csum_flags & CSUM_TCP) {
2186 * Start offset for payload checksum calculation.
2187 * End offset for payload checksum calculation.
2188 * Offset of place to put the checksum.
2190 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2191 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2192 TXD->upper_setup.tcp_fields.tucso =
2193 hdr_len + offsetof(struct tcphdr, th_sum);
2194 cmd |= E1000_TXD_CMD_TCP;
2195 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2196 } else if (csum_flags & CSUM_UDP) {
2198 * Start offset for header checksum calculation.
2199 * End offset for header checksum calculation.
2200 * Offset of place to put the checksum.
2202 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2203 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2204 TXD->upper_setup.tcp_fields.tucso =
2205 hdr_len + offsetof(struct udphdr, uh_sum);
2206 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2209 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2210 E1000_TXD_DTYP_D; /* Data descr */
2212 /* Save the information for this csum offloading context */
2213 sc->csum_ehlen = ehdrlen;
2214 sc->csum_iphlen = ip_hlen;
2215 sc->csum_flags = csum_flags;
2216 sc->csum_txd_upper = *txd_upper;
2217 sc->csum_txd_lower = *txd_lower;
2219 TXD->tcp_seg_setup.data = htole32(0);
2220 TXD->cmd_and_length =
2221 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2223 if (++curr_txd == sc->num_tx_desc)
2226 KKASSERT(sc->num_tx_desc_avail > 0);
2227 sc->num_tx_desc_avail--;
2229 sc->next_avail_tx_desc = curr_txd;
2234 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2236 struct mbuf *m = *m0;
2237 struct ether_header *eh;
2240 sc->tx_csum_try_pullup++;
2242 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2244 if (__predict_false(!M_WRITABLE(m))) {
2245 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2246 sc->tx_csum_drop1++;
2251 eh = mtod(m, struct ether_header *);
2253 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2254 len += EVL_ENCAPLEN;
2256 if (m->m_len < len) {
2257 sc->tx_csum_drop2++;
2265 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2266 sc->tx_csum_pullup1++;
2267 m = m_pullup(m, ETHER_HDR_LEN);
2269 sc->tx_csum_pullup1_failed++;
2275 eh = mtod(m, struct ether_header *);
2277 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2278 len += EVL_ENCAPLEN;
2280 if (m->m_len < len) {
2281 sc->tx_csum_pullup2++;
2282 m = m_pullup(m, len);
2284 sc->tx_csum_pullup2_failed++;
2294 emx_txeof(struct emx_softc *sc)
2296 struct ifnet *ifp = &sc->arpcom.ac_if;
2297 struct emx_txbuf *tx_buffer;
2298 int first, num_avail;
2300 if (sc->tx_dd_head == sc->tx_dd_tail)
2303 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2306 num_avail = sc->num_tx_desc_avail;
2307 first = sc->next_tx_to_clean;
2309 while (sc->tx_dd_head != sc->tx_dd_tail) {
2310 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2311 struct e1000_tx_desc *tx_desc;
2313 tx_desc = &sc->tx_desc_base[dd_idx];
2314 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2315 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2317 if (++dd_idx == sc->num_tx_desc)
2320 while (first != dd_idx) {
2325 tx_buffer = &sc->tx_buf[first];
2326 if (tx_buffer->m_head) {
2328 bus_dmamap_unload(sc->txtag,
2330 m_freem(tx_buffer->m_head);
2331 tx_buffer->m_head = NULL;
2334 if (++first == sc->num_tx_desc)
2341 sc->next_tx_to_clean = first;
2342 sc->num_tx_desc_avail = num_avail;
2344 if (sc->tx_dd_head == sc->tx_dd_tail) {
2349 if (!EMX_IS_OACTIVE(sc)) {
2350 ifp->if_flags &= ~IFF_OACTIVE;
2352 /* All clean, turn off the timer */
2353 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2359 emx_tx_collect(struct emx_softc *sc)
2361 struct ifnet *ifp = &sc->arpcom.ac_if;
2362 struct emx_txbuf *tx_buffer;
2363 int tdh, first, num_avail, dd_idx = -1;
2365 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2368 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2369 if (tdh == sc->next_tx_to_clean)
2372 if (sc->tx_dd_head != sc->tx_dd_tail)
2373 dd_idx = sc->tx_dd[sc->tx_dd_head];
2375 num_avail = sc->num_tx_desc_avail;
2376 first = sc->next_tx_to_clean;
2378 while (first != tdh) {
2383 tx_buffer = &sc->tx_buf[first];
2384 if (tx_buffer->m_head) {
2386 bus_dmamap_unload(sc->txtag,
2388 m_freem(tx_buffer->m_head);
2389 tx_buffer->m_head = NULL;
2392 if (first == dd_idx) {
2393 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2394 if (sc->tx_dd_head == sc->tx_dd_tail) {
2399 dd_idx = sc->tx_dd[sc->tx_dd_head];
2403 if (++first == sc->num_tx_desc)
2406 sc->next_tx_to_clean = first;
2407 sc->num_tx_desc_avail = num_avail;
2409 if (!EMX_IS_OACTIVE(sc)) {
2410 ifp->if_flags &= ~IFF_OACTIVE;
2412 /* All clean, turn off the timer */
2413 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2419 * When Link is lost sometimes there is work still in the TX ring
2420 * which will result in a watchdog, rather than allow that do an
2421 * attempted cleanup and then reinit here. Note that this has been
2422 * seens mostly with fiber adapters.
2425 emx_tx_purge(struct emx_softc *sc)
2427 struct ifnet *ifp = &sc->arpcom.ac_if;
2429 if (!sc->link_active && ifp->if_timer) {
2431 if (ifp->if_timer) {
2432 if_printf(ifp, "Link lost, TX pending, reinit\n");
2440 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2443 bus_dma_segment_t seg;
2445 struct emx_rxbuf *rx_buffer;
2448 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2450 rdata->mbuf_cluster_failed++;
2452 if_printf(&sc->arpcom.ac_if,
2453 "Unable to allocate RX mbuf\n");
2457 m->m_len = m->m_pkthdr.len = MCLBYTES;
2459 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2460 m_adj(m, ETHER_ALIGN);
2462 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2463 rdata->rx_sparemap, m,
2464 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2468 if_printf(&sc->arpcom.ac_if,
2469 "Unable to load RX mbuf\n");
2474 rx_buffer = &rdata->rx_buf[i];
2475 if (rx_buffer->m_head != NULL)
2476 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2478 map = rx_buffer->map;
2479 rx_buffer->map = rdata->rx_sparemap;
2480 rdata->rx_sparemap = map;
2482 rx_buffer->m_head = m;
2483 rx_buffer->paddr = seg.ds_addr;
2485 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2490 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2492 device_t dev = sc->dev;
2493 struct emx_rxbuf *rx_buffer;
2494 int i, error, rsize;
2497 * Validate number of receive descriptors. It must not exceed
2498 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2500 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2501 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) {
2502 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2503 EMX_DEFAULT_RXD, emx_rxd);
2504 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2506 rdata->num_rx_desc = emx_rxd;
2510 * Allocate Receive Descriptor ring
2512 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2514 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2515 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2516 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2517 &rdata->rx_desc_paddr);
2518 if (rdata->rx_desc == NULL) {
2519 device_printf(dev, "Unable to allocate rx_desc memory\n");
2523 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2524 M_DEVBUF, M_WAITOK | M_ZERO);
2527 * Create DMA tag for rx buffers
2529 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2530 1, 0, /* alignment, bounds */
2531 BUS_SPACE_MAXADDR, /* lowaddr */
2532 BUS_SPACE_MAXADDR, /* highaddr */
2533 NULL, NULL, /* filter, filterarg */
2534 MCLBYTES, /* maxsize */
2536 MCLBYTES, /* maxsegsize */
2537 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2540 device_printf(dev, "Unable to allocate RX DMA tag\n");
2541 kfree(rdata->rx_buf, M_DEVBUF);
2542 rdata->rx_buf = NULL;
2547 * Create spare DMA map for rx buffers
2549 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2550 &rdata->rx_sparemap);
2552 device_printf(dev, "Unable to create spare RX DMA map\n");
2553 bus_dma_tag_destroy(rdata->rxtag);
2554 kfree(rdata->rx_buf, M_DEVBUF);
2555 rdata->rx_buf = NULL;
2560 * Create DMA maps for rx buffers
2562 for (i = 0; i < rdata->num_rx_desc; i++) {
2563 rx_buffer = &rdata->rx_buf[i];
2565 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2568 device_printf(dev, "Unable to create RX DMA map\n");
2569 emx_destroy_rx_ring(sc, rdata, i);
2577 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2581 for (i = 0; i < rdata->num_rx_desc; i++) {
2582 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2584 if (rx_buffer->m_head != NULL) {
2585 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2586 m_freem(rx_buffer->m_head);
2587 rx_buffer->m_head = NULL;
2591 if (rdata->fmp != NULL)
2592 m_freem(rdata->fmp);
2598 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2602 /* Reset descriptor ring */
2603 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2605 /* Allocate new ones. */
2606 for (i = 0; i < rdata->num_rx_desc; i++) {
2607 error = emx_newbuf(sc, rdata, i, 1);
2612 /* Setup our descriptor pointers */
2613 rdata->next_rx_desc_to_check = 0;
2619 emx_init_rx_unit(struct emx_softc *sc)
2621 struct ifnet *ifp = &sc->arpcom.ac_if;
2623 uint32_t rctl, itr, rfctl;
2627 * Make sure receives are disabled while setting
2628 * up the descriptor ring
2630 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2631 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2634 * Set the interrupt throttling rate. Value is calculated
2635 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2637 if (sc->int_throttle_ceil)
2638 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2641 emx_set_itr(sc, itr);
2643 /* Use extended RX descriptor */
2644 rfctl = E1000_RFCTL_EXTEN;
2646 /* Disable accelerated ackknowledge */
2647 if (sc->hw.mac.type == e1000_82574)
2648 rfctl |= E1000_RFCTL_ACK_DIS;
2650 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2653 * Receive Checksum Offload for TCP and UDP
2655 * Checksum offloading is also enabled if multiple receive
2656 * queue is to be supported, since we need it to figure out
2659 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) {
2662 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2666 * PCSD must be enabled to enable multiple
2669 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2671 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2675 * Configure multiple receive queue (RSS)
2677 if (ifp->if_capenable & IFCAP_RSS) {
2678 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2681 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING,
2682 ("invalid number of RX ring (%d)",
2683 sc->rx_ring_inuse));
2687 * When we reach here, RSS has already been disabled
2688 * in emx_stop(), so we could safely configure RSS key
2689 * and redirect table.
2695 toeplitz_get_key(key, sizeof(key));
2696 for (i = 0; i < EMX_NRSSRK; ++i) {
2699 rssrk = EMX_RSSRK_VAL(key, i);
2700 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2702 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2706 * Configure RSS redirect table in following fashion:
2707 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2710 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2713 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT;
2714 reta |= q << (8 * i);
2716 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2718 for (i = 0; i < EMX_NRETA; ++i)
2719 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2722 * Enable multiple receive queues.
2723 * Enable IPv4 RSS standard hash functions.
2724 * Disable RSS interrupt.
2726 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2727 E1000_MRQC_ENABLE_RSS_2Q |
2728 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2729 E1000_MRQC_RSS_FIELD_IPV4);
2733 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2734 * long latencies are observed, like Lenovo X60. This
2735 * change eliminates the problem, but since having positive
2736 * values in RDTR is a known source of problems on other
2737 * platforms another solution is being sought.
2739 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2740 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2741 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2744 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2745 struct emx_rxdata *rdata = &sc->rx_data[i];
2748 * Setup the Base and Length of the Rx Descriptor Ring
2750 bus_addr = rdata->rx_desc_paddr;
2751 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2752 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2753 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2754 (uint32_t)(bus_addr >> 32));
2755 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2756 (uint32_t)bus_addr);
2759 * Setup the HW Rx Head and Tail Descriptor Pointers
2761 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2762 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2763 sc->rx_data[i].num_rx_desc - 1);
2766 /* Setup the Receive Control Register */
2767 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2768 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2769 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2770 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2772 /* Make sure VLAN Filters are off */
2773 rctl &= ~E1000_RCTL_VFE;
2775 /* Don't store bad paket */
2776 rctl &= ~E1000_RCTL_SBP;
2779 rctl |= E1000_RCTL_SZ_2048;
2781 if (ifp->if_mtu > ETHERMTU)
2782 rctl |= E1000_RCTL_LPE;
2784 rctl &= ~E1000_RCTL_LPE;
2786 /* Enable Receives */
2787 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2791 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2793 struct emx_rxbuf *rx_buffer;
2796 /* Free Receive Descriptor ring */
2797 if (rdata->rx_desc) {
2798 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2799 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2800 rdata->rx_desc_dmap);
2801 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2803 rdata->rx_desc = NULL;
2806 if (rdata->rx_buf == NULL)
2809 for (i = 0; i < ndesc; i++) {
2810 rx_buffer = &rdata->rx_buf[i];
2812 KKASSERT(rx_buffer->m_head == NULL);
2813 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2815 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2816 bus_dma_tag_destroy(rdata->rxtag);
2818 kfree(rdata->rx_buf, M_DEVBUF);
2819 rdata->rx_buf = NULL;
2823 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2825 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2826 struct ifnet *ifp = &sc->arpcom.ac_if;
2828 emx_rxdesc_t *current_desc;
2832 i = rdata->next_rx_desc_to_check;
2833 current_desc = &rdata->rx_desc[i];
2834 staterr = le32toh(current_desc->rxd_staterr);
2836 if (!(staterr & E1000_RXD_STAT_DD))
2839 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2840 struct pktinfo *pi = NULL, pi0;
2841 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2842 struct mbuf *m = NULL;
2847 mp = rx_buf->m_head;
2850 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2851 * needs to access the last received byte in the mbuf.
2853 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2854 BUS_DMASYNC_POSTREAD);
2856 len = le16toh(current_desc->rxd_length);
2857 if (staterr & E1000_RXD_STAT_EOP) {
2864 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2866 uint32_t mrq, rss_hash;
2869 * Save several necessary information,
2870 * before emx_newbuf() destroy it.
2872 if ((staterr & E1000_RXD_STAT_VP) && eop)
2873 vlan = le16toh(current_desc->rxd_vlan);
2875 mrq = le32toh(current_desc->rxd_mrq);
2876 rss_hash = le32toh(current_desc->rxd_rss);
2878 EMX_RSS_DPRINTF(sc, 10,
2879 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2880 ring_idx, mrq, rss_hash);
2882 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2887 /* Assign correct length to the current fragment */
2890 if (rdata->fmp == NULL) {
2891 mp->m_pkthdr.len = len;
2892 rdata->fmp = mp; /* Store the first mbuf */
2896 * Chain mbuf's together
2898 rdata->lmp->m_next = mp;
2899 rdata->lmp = rdata->lmp->m_next;
2900 rdata->fmp->m_pkthdr.len += len;
2904 rdata->fmp->m_pkthdr.rcvif = ifp;
2907 if (ifp->if_capenable & IFCAP_RXCSUM)
2908 emx_rxcsum(staterr, rdata->fmp);
2910 if (staterr & E1000_RXD_STAT_VP) {
2911 rdata->fmp->m_pkthdr.ether_vlantag =
2913 rdata->fmp->m_flags |= M_VLANTAG;
2919 if (ifp->if_capenable & IFCAP_RSS) {
2920 pi = emx_rssinfo(m, &pi0, mrq,
2923 #ifdef EMX_RSS_DEBUG
2930 emx_setup_rxdesc(current_desc, rx_buf);
2931 if (rdata->fmp != NULL) {
2932 m_freem(rdata->fmp);
2940 ether_input_pkt(ifp, m, pi);
2942 /* Advance our pointers to the next descriptor. */
2943 if (++i == rdata->num_rx_desc)
2946 current_desc = &rdata->rx_desc[i];
2947 staterr = le32toh(current_desc->rxd_staterr);
2949 rdata->next_rx_desc_to_check = i;
2951 /* Advance the E1000's Receive Queue "Tail Pointer". */
2953 i = rdata->num_rx_desc - 1;
2954 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2958 emx_enable_intr(struct emx_softc *sc)
2960 uint32_t ims_mask = IMS_ENABLE_MASK;
2962 lwkt_serialize_handler_enable(&sc->main_serialize);
2965 if (sc->hw.mac.type == e1000_82574) {
2966 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2967 ims_mask |= EM_MSIX_MASK;
2970 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
2974 emx_disable_intr(struct emx_softc *sc)
2976 if (sc->hw.mac.type == e1000_82574)
2977 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
2978 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2980 lwkt_serialize_handler_disable(&sc->main_serialize);
2984 * Bit of a misnomer, what this really means is
2985 * to enable OS management of the system... aka
2986 * to disable special hardware management features
2989 emx_get_mgmt(struct emx_softc *sc)
2991 /* A shared code workaround */
2992 if (sc->has_manage) {
2993 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2994 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2996 /* disable hardware interception of ARP */
2997 manc &= ~(E1000_MANC_ARP_EN);
2999 /* enable receiving management packets to the host */
3000 manc |= E1000_MANC_EN_MNG2HOST;
3001 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3002 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3003 manc2h |= E1000_MNG2HOST_PORT_623;
3004 manc2h |= E1000_MNG2HOST_PORT_664;
3005 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3007 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3012 * Give control back to hardware management
3013 * controller if there is one.
3016 emx_rel_mgmt(struct emx_softc *sc)
3018 if (sc->has_manage) {
3019 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3021 /* re-enable hardware interception of ARP */
3022 manc |= E1000_MANC_ARP_EN;
3023 manc &= ~E1000_MANC_EN_MNG2HOST;
3025 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3030 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3031 * For ASF and Pass Through versions of f/w this means that
3032 * the driver is loaded. For AMT version (only with 82573)
3033 * of the f/w this means that the network i/f is open.
3036 emx_get_hw_control(struct emx_softc *sc)
3038 /* Let firmware know the driver has taken over */
3039 if (sc->hw.mac.type == e1000_82573) {
3042 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3043 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3044 swsm | E1000_SWSM_DRV_LOAD);
3048 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3049 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3050 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3056 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3057 * For ASF and Pass Through versions of f/w this means that the
3058 * driver is no longer loaded. For AMT version (only with 82573)
3059 * of the f/w this means that the network i/f is closed.
3062 emx_rel_hw_control(struct emx_softc *sc)
3064 if (!sc->control_hw)
3068 /* Let firmware taken over control of h/w */
3069 if (sc->hw.mac.type == e1000_82573) {
3072 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3073 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3074 swsm & ~E1000_SWSM_DRV_LOAD);
3078 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3079 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3080 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3085 emx_is_valid_eaddr(const uint8_t *addr)
3087 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3089 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3096 * Enable PCI Wake On Lan capability
3099 emx_enable_wol(device_t dev)
3101 uint16_t cap, status;
3104 /* First find the capabilities pointer*/
3105 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3107 /* Read the PM Capabilities */
3108 id = pci_read_config(dev, cap, 1);
3109 if (id != PCIY_PMG) /* Something wrong */
3113 * OK, we have the power capabilities,
3114 * so now get the status register
3116 cap += PCIR_POWER_STATUS;
3117 status = pci_read_config(dev, cap, 2);
3118 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3119 pci_write_config(dev, cap, status, 2);
3123 emx_update_stats(struct emx_softc *sc)
3125 struct ifnet *ifp = &sc->arpcom.ac_if;
3127 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3128 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3129 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3130 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3132 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3133 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3134 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3135 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3137 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3138 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3139 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3140 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3141 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3142 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3143 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3144 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3145 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3146 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3147 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3148 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3149 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3150 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3151 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3152 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3153 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3154 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3155 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3156 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3158 /* For the 64-bit byte counters the low dword must be read first. */
3159 /* Both registers clear on the read of the high dword */
3161 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3162 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3164 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3165 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3166 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3167 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3168 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3170 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3171 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3173 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3174 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3175 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3176 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3177 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3178 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3179 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3180 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3181 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3182 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3184 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3185 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3186 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3187 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3188 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3189 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3191 ifp->if_collisions = sc->stats.colc;
3194 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3195 sc->stats.crcerrs + sc->stats.algnerrc +
3196 sc->stats.ruc + sc->stats.roc +
3197 sc->stats.mpc + sc->stats.cexterr;
3200 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3201 sc->watchdog_events;
3205 emx_print_debug_info(struct emx_softc *sc)
3207 device_t dev = sc->dev;
3208 uint8_t *hw_addr = sc->hw.hw_addr;
3210 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3211 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3212 E1000_READ_REG(&sc->hw, E1000_CTRL),
3213 E1000_READ_REG(&sc->hw, E1000_RCTL));
3214 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3215 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3216 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3217 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3218 sc->hw.fc.high_water, sc->hw.fc.low_water);
3219 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3220 E1000_READ_REG(&sc->hw, E1000_TIDV),
3221 E1000_READ_REG(&sc->hw, E1000_TADV));
3222 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3223 E1000_READ_REG(&sc->hw, E1000_RDTR),
3224 E1000_READ_REG(&sc->hw, E1000_RADV));
3225 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3226 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3227 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3228 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3229 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3230 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3231 device_printf(dev, "Num Tx descriptors avail = %d\n",
3232 sc->num_tx_desc_avail);
3233 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3234 sc->no_tx_desc_avail1);
3235 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3236 sc->no_tx_desc_avail2);
3237 device_printf(dev, "Std mbuf failed = %ld\n",
3238 sc->mbuf_alloc_failed);
3239 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3240 sc->rx_data[0].mbuf_cluster_failed);
3241 device_printf(dev, "Driver dropped packets = %ld\n",
3243 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3244 sc->no_tx_dma_setup);
3246 device_printf(dev, "TXCSUM try pullup = %lu\n",
3247 sc->tx_csum_try_pullup);
3248 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3249 sc->tx_csum_pullup1);
3250 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3251 sc->tx_csum_pullup1_failed);
3252 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3253 sc->tx_csum_pullup2);
3254 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3255 sc->tx_csum_pullup2_failed);
3256 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3258 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3263 emx_print_hw_stats(struct emx_softc *sc)
3265 device_t dev = sc->dev;
3267 device_printf(dev, "Excessive collisions = %lld\n",
3268 (long long)sc->stats.ecol);
3269 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3270 device_printf(dev, "Symbol errors = %lld\n",
3271 (long long)sc->stats.symerrs);
3273 device_printf(dev, "Sequence errors = %lld\n",
3274 (long long)sc->stats.sec);
3275 device_printf(dev, "Defer count = %lld\n",
3276 (long long)sc->stats.dc);
3277 device_printf(dev, "Missed Packets = %lld\n",
3278 (long long)sc->stats.mpc);
3279 device_printf(dev, "Receive No Buffers = %lld\n",
3280 (long long)sc->stats.rnbc);
3281 /* RLEC is inaccurate on some hardware, calculate our own. */
3282 device_printf(dev, "Receive Length Errors = %lld\n",
3283 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3284 device_printf(dev, "Receive errors = %lld\n",
3285 (long long)sc->stats.rxerrc);
3286 device_printf(dev, "Crc errors = %lld\n",
3287 (long long)sc->stats.crcerrs);
3288 device_printf(dev, "Alignment errors = %lld\n",
3289 (long long)sc->stats.algnerrc);
3290 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3291 (long long)sc->stats.cexterr);
3292 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3293 device_printf(dev, "watchdog timeouts = %ld\n",
3294 sc->watchdog_events);
3295 device_printf(dev, "XON Rcvd = %lld\n",
3296 (long long)sc->stats.xonrxc);
3297 device_printf(dev, "XON Xmtd = %lld\n",
3298 (long long)sc->stats.xontxc);
3299 device_printf(dev, "XOFF Rcvd = %lld\n",
3300 (long long)sc->stats.xoffrxc);
3301 device_printf(dev, "XOFF Xmtd = %lld\n",
3302 (long long)sc->stats.xofftxc);
3303 device_printf(dev, "Good Packets Rcvd = %lld\n",
3304 (long long)sc->stats.gprc);
3305 device_printf(dev, "Good Packets Xmtd = %lld\n",
3306 (long long)sc->stats.gptc);
3310 emx_print_nvm_info(struct emx_softc *sc)
3312 uint16_t eeprom_data;
3315 /* Its a bit crude, but it gets the job done */
3316 kprintf("\nInterface EEPROM Dump:\n");
3317 kprintf("Offset\n0x0000 ");
3318 for (i = 0, j = 0; i < 32; i++, j++) {
3319 if (j == 8) { /* Make the offset block */
3321 kprintf("\n0x00%x0 ",row);
3323 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3324 kprintf("%04x ", eeprom_data);
3330 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3332 struct emx_softc *sc;
3337 error = sysctl_handle_int(oidp, &result, 0, req);
3338 if (error || !req->newptr)
3341 sc = (struct emx_softc *)arg1;
3342 ifp = &sc->arpcom.ac_if;
3344 ifnet_serialize_all(ifp);
3347 emx_print_debug_info(sc);
3350 * This value will cause a hex dump of the
3351 * first 32 16-bit words of the EEPROM to
3355 emx_print_nvm_info(sc);
3357 ifnet_deserialize_all(ifp);
3363 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3368 error = sysctl_handle_int(oidp, &result, 0, req);
3369 if (error || !req->newptr)
3373 struct emx_softc *sc = (struct emx_softc *)arg1;
3374 struct ifnet *ifp = &sc->arpcom.ac_if;
3376 ifnet_serialize_all(ifp);
3377 emx_print_hw_stats(sc);
3378 ifnet_deserialize_all(ifp);
3384 emx_add_sysctl(struct emx_softc *sc)
3386 #ifdef EMX_RSS_DEBUG
3391 sysctl_ctx_init(&sc->sysctl_ctx);
3392 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3393 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3394 device_get_nameunit(sc->dev),
3396 if (sc->sysctl_tree == NULL) {
3397 device_printf(sc->dev, "can't add sysctl node\n");
3401 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3402 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3403 emx_sysctl_debug_info, "I", "Debug Information");
3405 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3406 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3407 emx_sysctl_stats, "I", "Statistics");
3409 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3410 OID_AUTO, "rxd", CTLFLAG_RD,
3411 &sc->rx_data[0].num_rx_desc, 0, NULL);
3412 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3413 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3415 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3416 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3417 sc, 0, emx_sysctl_int_throttle, "I",
3418 "interrupt throttling rate");
3419 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3420 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3421 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3422 "# segments per TX interrupt");
3424 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3425 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD,
3426 &sc->rx_ring_inuse, 0, "RX ring in use");
3428 #ifdef EMX_RSS_DEBUG
3429 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3430 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3431 0, "RSS debug level");
3432 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3433 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3434 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3435 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3437 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3443 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3445 struct emx_softc *sc = (void *)arg1;
3446 struct ifnet *ifp = &sc->arpcom.ac_if;
3447 int error, throttle;
3449 throttle = sc->int_throttle_ceil;
3450 error = sysctl_handle_int(oidp, &throttle, 0, req);
3451 if (error || req->newptr == NULL)
3453 if (throttle < 0 || throttle > 1000000000 / 256)
3458 * Set the interrupt throttling rate in 256ns increments,
3459 * recalculate sysctl value assignment to get exact frequency.
3461 throttle = 1000000000 / 256 / throttle;
3463 /* Upper 16bits of ITR is reserved and should be zero */
3464 if (throttle & 0xffff0000)
3468 ifnet_serialize_all(ifp);
3471 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3473 sc->int_throttle_ceil = 0;
3475 if (ifp->if_flags & IFF_RUNNING)
3476 emx_set_itr(sc, throttle);
3478 ifnet_deserialize_all(ifp);
3481 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3482 sc->int_throttle_ceil);
3488 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3490 struct emx_softc *sc = (void *)arg1;
3491 struct ifnet *ifp = &sc->arpcom.ac_if;
3494 segs = sc->tx_int_nsegs;
3495 error = sysctl_handle_int(oidp, &segs, 0, req);
3496 if (error || req->newptr == NULL)
3501 ifnet_serialize_all(ifp);
3504 * Don't allow int_tx_nsegs to become:
3505 * o Less the oact_tx_desc
3506 * o Too large that no TX desc will cause TX interrupt to
3507 * be generated (OACTIVE will never recover)
3508 * o Too small that will cause tx_dd[] overflow
3510 if (segs < sc->oact_tx_desc ||
3511 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3512 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3516 sc->tx_int_nsegs = segs;
3519 ifnet_deserialize_all(ifp);
3525 emx_dma_alloc(struct emx_softc *sc)
3530 * Create top level busdma tag
3532 error = bus_dma_tag_create(NULL, 1, 0,
3533 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3535 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3536 0, &sc->parent_dtag);
3538 device_printf(sc->dev, "could not create top level DMA tag\n");
3543 * Allocate transmit descriptors ring and buffers
3545 error = emx_create_tx_ring(sc);
3547 device_printf(sc->dev, "Could not setup transmit structures\n");
3552 * Allocate receive descriptors ring and buffers
3554 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3555 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3557 device_printf(sc->dev,
3558 "Could not setup receive structures\n");
3566 emx_dma_free(struct emx_softc *sc)
3570 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3572 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3573 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3574 sc->rx_data[i].num_rx_desc);
3577 /* Free top level busdma tag */
3578 if (sc->parent_dtag != NULL)
3579 bus_dma_tag_destroy(sc->parent_dtag);
3583 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3585 struct emx_softc *sc = ifp->if_softc;
3588 case IFNET_SERIALIZE_ALL:
3589 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0);
3592 case IFNET_SERIALIZE_MAIN:
3593 lwkt_serialize_enter(&sc->main_serialize);
3596 case IFNET_SERIALIZE_TX:
3597 lwkt_serialize_enter(&sc->tx_serialize);
3600 case IFNET_SERIALIZE_RX(0):
3601 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize);
3604 case IFNET_SERIALIZE_RX(1):
3605 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize);
3609 panic("%s unsupported serialize type\n", ifp->if_xname);
3614 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3616 struct emx_softc *sc = ifp->if_softc;
3619 case IFNET_SERIALIZE_ALL:
3620 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0);
3623 case IFNET_SERIALIZE_MAIN:
3624 lwkt_serialize_exit(&sc->main_serialize);
3627 case IFNET_SERIALIZE_TX:
3628 lwkt_serialize_exit(&sc->tx_serialize);
3631 case IFNET_SERIALIZE_RX(0):
3632 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize);
3635 case IFNET_SERIALIZE_RX(1):
3636 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize);
3640 panic("%s unsupported serialize type\n", ifp->if_xname);
3645 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3647 struct emx_softc *sc = ifp->if_softc;
3650 case IFNET_SERIALIZE_ALL:
3651 return lwkt_serialize_array_try(sc->serializes,
3654 case IFNET_SERIALIZE_MAIN:
3655 return lwkt_serialize_try(&sc->main_serialize);
3657 case IFNET_SERIALIZE_TX:
3658 return lwkt_serialize_try(&sc->tx_serialize);
3660 case IFNET_SERIALIZE_RX(0):
3661 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize);
3663 case IFNET_SERIALIZE_RX(1):
3664 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize);
3667 panic("%s unsupported serialize type\n", ifp->if_xname);
3672 emx_serialize_skipmain(struct emx_softc *sc)
3674 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3678 emx_deserialize_skipmain(struct emx_softc *sc)
3680 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3686 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3687 boolean_t serialized)
3689 struct emx_softc *sc = ifp->if_softc;
3693 case IFNET_SERIALIZE_ALL:
3695 for (i = 0; i < EMX_NSERIALIZE; ++i)
3696 ASSERT_SERIALIZED(sc->serializes[i]);
3698 for (i = 0; i < EMX_NSERIALIZE; ++i)
3699 ASSERT_NOT_SERIALIZED(sc->serializes[i]);
3703 case IFNET_SERIALIZE_MAIN:
3705 ASSERT_SERIALIZED(&sc->main_serialize);
3707 ASSERT_NOT_SERIALIZED(&sc->main_serialize);
3710 case IFNET_SERIALIZE_TX:
3712 ASSERT_SERIALIZED(&sc->tx_serialize);
3714 ASSERT_NOT_SERIALIZED(&sc->tx_serialize);
3717 case IFNET_SERIALIZE_RX(0):
3719 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3721 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3724 case IFNET_SERIALIZE_RX(1):
3726 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3728 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3732 panic("%s unsupported serialize type\n", ifp->if_xname);
3736 #endif /* INVARIANTS */
3738 #ifdef IFPOLL_ENABLE
3741 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3743 struct emx_softc *sc = ifp->if_softc;
3746 ASSERT_SERIALIZED(&sc->main_serialize);
3748 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3749 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3750 emx_serialize_skipmain(sc);
3752 callout_stop(&sc->timer);
3753 sc->hw.mac.get_link_status = 1;
3754 emx_update_link_status(sc);
3755 callout_reset(&sc->timer, hz, emx_timer, sc);
3757 emx_deserialize_skipmain(sc);
3762 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3764 struct emx_softc *sc = ifp->if_softc;
3766 ASSERT_SERIALIZED(&sc->tx_serialize);
3769 if (!ifq_is_empty(&ifp->if_snd))
3774 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3776 struct emx_softc *sc = ifp->if_softc;
3777 struct emx_rxdata *rdata = arg;
3779 ASSERT_SERIALIZED(&rdata->rx_serialize);
3781 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3785 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3787 struct emx_softc *sc = ifp->if_softc;
3789 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3794 info->ifpi_status.status_func = emx_qpoll_status;
3795 info->ifpi_status.serializer = &sc->main_serialize;
3797 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3798 info->ifpi_tx[0].arg = NULL;
3799 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3801 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3802 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3803 info->ifpi_rx[i].arg = &sc->rx_data[i];
3804 info->ifpi_rx[i].serializer =
3805 &sc->rx_data[i].rx_serialize;
3808 if (ifp->if_flags & IFF_RUNNING)
3809 emx_disable_intr(sc);
3810 } else if (ifp->if_flags & IFF_RUNNING) {
3811 emx_enable_intr(sc);
3815 #endif /* IFPOLL_ENABLE */
3818 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3820 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3821 if (sc->hw.mac.type == e1000_82574) {
3825 * When using MSIX interrupts we need to
3826 * throttle using the EITR register
3828 for (i = 0; i < 4; ++i)
3829 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);