2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
65 #include <machine/pmap_inval.h>
67 #include <machine/md_var.h> /* setidt() */
68 #include <machine_base/icu/icu.h> /* IPIs */
69 #include <machine_base/isa/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 typedef int (*mptable_iter_func)(void *, const void *, int);
175 * this code MUST be enabled here and in mpboot.s.
176 * it follows the very early stages of AP boot by placing values in CMOS ram.
177 * it NORMALLY will never be needed and thus the primitive method for enabling.
180 #if defined(CHECK_POINTS)
181 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
182 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
184 #define CHECK_INIT(D); \
185 CHECK_WRITE(0x34, (D)); \
186 CHECK_WRITE(0x35, (D)); \
187 CHECK_WRITE(0x36, (D)); \
188 CHECK_WRITE(0x37, (D)); \
189 CHECK_WRITE(0x38, (D)); \
190 CHECK_WRITE(0x39, (D));
192 #define CHECK_PRINT(S); \
193 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
202 #else /* CHECK_POINTS */
204 #define CHECK_INIT(D)
205 #define CHECK_PRINT(S)
207 #endif /* CHECK_POINTS */
210 * Values to send to the POST hardware.
212 #define MP_BOOTADDRESS_POST 0x10
213 #define MP_PROBE_POST 0x11
214 #define MPTABLE_PASS1_POST 0x12
216 #define MP_START_POST 0x13
217 #define MP_ENABLE_POST 0x14
218 #define MPTABLE_PASS2_POST 0x15
220 #define START_ALL_APS_POST 0x16
221 #define INSTALL_AP_TRAMP_POST 0x17
222 #define START_AP_POST 0x18
224 #define MP_ANNOUNCE_POST 0x19
226 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227 int current_postcode;
229 /** XXX FIXME: what system files declare these??? */
230 extern struct region_descriptor r_gdt, r_idt;
232 int mp_naps; /* # of Applications processors */
233 #ifdef SMP /* APIC-IO */
234 static int mp_nbusses; /* # of busses */
235 int mp_napics; /* # of IO APICs */
236 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
237 u_int32_t *io_apic_versions;
241 u_int32_t cpu_apic_versions[MAXCPU];
243 extern int64_t tsc_offsets[];
245 extern u_long ebda_addr;
247 #ifdef SMP /* APIC-IO */
248 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
252 * APIC ID logical/physical mapping structures.
253 * We oversize these to simplify boot-time config.
255 int cpu_num_to_apic_id[NAPICID];
256 #ifdef SMP /* APIC-IO */
257 int io_num_to_apic_id[NAPICID];
259 int apic_id_to_logical[NAPICID];
261 /* AP uses this during bootstrap. Do not staticize. */
265 /* Hotwire a 0->4MB V==P mapping */
266 extern pt_entry_t *KPTphys;
269 * SMP page table page. Setup by locore to point to a page table
270 * page from which we allocate per-cpu privatespace areas io_apics,
274 #define IO_MAPPING_START_INDEX \
275 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
277 extern pt_entry_t *SMPpt;
278 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
280 struct pcb stoppcbs[MAXCPU];
282 static basetable_entry basetable_entry_types[] =
284 {0, 20, "Processor"},
292 * Local data and functions.
295 static u_int boot_address;
296 static u_int base_memory;
297 static int mp_finish;
299 static void mp_enable(u_int boot_addr);
301 static int mptable_iterate_entries(const mpcth_t,
302 mptable_iter_func, void *);
303 static int mptable_probe(void);
304 static int mptable_search(void);
305 static int mptable_check(vm_paddr_t);
306 static int mptable_search_sig(u_int32_t target, int count);
307 static int mptable_hyperthread_fixup(u_int, int);
308 #ifdef SMP /* APIC-IO */
309 static void mptable_pass1(struct mptable_pos *);
310 static void mptable_pass2(struct mptable_pos *);
311 static void mptable_default(int type);
312 static void mptable_fix(void);
314 static int mptable_map(struct mptable_pos *, vm_paddr_t);
315 static void mptable_unmap(struct mptable_pos *);
316 static void mptable_imcr(struct mptable_pos *);
318 static int mptable_lapic_probe(struct lapic_enumerator *);
319 static void mptable_lapic_enumerate(struct lapic_enumerator *);
320 static void mptable_lapic_default(void);
322 #ifdef SMP /* APIC-IO */
323 static void setup_apic_irq_mapping(void);
324 static int apic_int_is_bus_type(int intr, int bus_type);
326 static int start_all_aps(u_int boot_addr);
327 static void install_ap_tramp(u_int boot_addr);
328 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
329 static int smitest(void);
331 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
332 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
333 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
336 * Calculate usable address in base memory for AP trampoline code.
339 mp_bootaddress(u_int basemem)
341 POSTCODE(MP_BOOTADDRESS_POST);
343 base_memory = basemem;
345 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
346 if ((base_memory - boot_address) < bootMP_size)
347 boot_address -= 4096; /* not enough, lower by 4k */
358 mpfps_paddr = mptable_search();
359 if (mptable_check(mpfps_paddr))
366 * Look for an Intel MP spec table (ie, SMP capable hardware).
375 * Make sure our SMPpt[] page table is big enough to hold all the
378 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
380 POSTCODE(MP_PROBE_POST);
382 /* see if EBDA exists */
383 if (ebda_addr != 0) {
384 /* search first 1K of EBDA */
385 target = (u_int32_t)ebda_addr;
386 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
389 /* last 1K of base memory, effective 'top of base' passed in */
390 target = (u_int32_t)(base_memory - 0x400);
391 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
395 /* search the BIOS */
396 target = (u_int32_t)BIOS_BASE;
397 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
400 /* search the extended BIOS */
401 target = (u_int32_t)BIOS_BASE2;
402 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
409 struct mptable_check_cbarg {
415 mptable_check_callback(void *xarg, const void *pos, int type)
417 const struct PROCENTRY *ent;
418 struct mptable_check_cbarg *arg = xarg;
424 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
428 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
429 if (arg->found_bsp) {
430 kprintf("more than one BSP in base MP table\n");
439 mptable_check(vm_paddr_t mpfps_paddr)
441 struct mptable_pos mpt;
442 struct mptable_check_cbarg arg;
446 if (mpfps_paddr == 0)
449 error = mptable_map(&mpt, mpfps_paddr);
453 if (mpt.mp_fps->mpfb1 != 0)
461 if (cth->apic_address == 0)
464 bzero(&arg, sizeof(arg));
465 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
467 if (arg.cpu_count == 0) {
468 kprintf("MP table contains no processor entries\n");
470 } else if (!arg.found_bsp) {
471 kprintf("MP table does not contains BSP entry\n");
481 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
483 int count, total_size;
484 const void *position;
486 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
487 total_size = cth->base_table_length - sizeof(struct MPCTH);
488 position = (const uint8_t *)cth + sizeof(struct MPCTH);
489 count = cth->entry_count;
494 KKASSERT(total_size >= 0);
495 if (total_size == 0) {
496 kprintf("invalid base MP table, "
497 "entry count and length mismatch\n");
501 type = *(const uint8_t *)position;
503 case 0: /* processor_entry */
504 case 1: /* bus_entry */
505 case 2: /* io_apic_entry */
506 case 3: /* int_entry */
507 case 4: /* int_entry */
510 kprintf("unknown base MP table entry type %d\n", type);
514 if (total_size < basetable_entry_types[type].length) {
515 kprintf("invalid base MP table length, "
516 "does not contain all entries\n");
519 total_size -= basetable_entry_types[type].length;
521 error = func(arg, position, type);
525 position = (const uint8_t *)position +
526 basetable_entry_types[type].length;
533 * Startup the SMP processors.
538 POSTCODE(MP_START_POST);
539 mp_enable(boot_address);
544 * Print various information about the SMP system hardware and setup.
551 POSTCODE(MP_ANNOUNCE_POST);
553 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
554 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
555 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
556 for (x = 1; x <= mp_naps; ++x) {
557 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
558 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
561 if (apic_io_enable) {
562 for (x = 0; x < mp_napics; ++x) {
563 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
564 kprintf(", version: 0x%08x", io_apic_versions[x]);
565 kprintf(", at 0x%08lx\n", io_apic_address[x]);
568 kprintf(" Warning: APIC I/O disabled\n");
573 * AP cpu's call this to sync up protected mode.
575 * WARNING! We must ensure that the cpu is sufficiently initialized to
576 * be able to use to the FP for our optimized bzero/bcopy code before
577 * we enter more mainstream C code.
579 * WARNING! %fs is not set up on entry. This routine sets up %fs.
585 int x, myid = bootAP;
587 struct mdglobaldata *md;
588 struct privatespace *ps;
590 ps = &CPU_prvspace[myid];
592 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
593 gdt_segs[GPROC0_SEL].ssd_base =
594 (int) &ps->mdglobaldata.gd_common_tss;
595 ps->mdglobaldata.mi.gd_prvspace = ps;
597 for (x = 0; x < NGDT; x++) {
598 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
601 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
602 r_gdt.rd_base = (int) &gdt[myid * NGDT];
603 lgdt(&r_gdt); /* does magic intra-segment return */
608 mdcpu->gd_currentldt = _default_ldt;
610 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
611 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
613 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
615 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
616 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
617 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
618 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
619 md->gd_common_tssd = *md->gd_tss_gdt;
623 * Set to a known state:
624 * Set by mpboot.s: CR0_PG, CR0_PE
625 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
628 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
630 pmap_set_opt(); /* PSE/4MB pages, etc */
632 /* set up CPU registers and state */
635 /* set up FPU state on the AP */
636 npxinit(__INITIAL_NPXCW__);
638 /* set up SSE registers */
642 /*******************************************************************
643 * local functions and data
647 * start the SMP system
650 mp_enable(u_int boot_addr)
654 vm_paddr_t mpfps_paddr;
655 struct mptable_pos mpt;
657 POSTCODE(MP_ENABLE_POST);
661 mpfps_paddr = mptable_probe();
663 mptable_map(&mpt, mpfps_paddr);
667 if (apic_io_enable) {
670 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
672 mptable_map(&mpt, mpfps_paddr);
675 * Examine the MP table for needed info
682 /* Post scan cleanup */
685 setup_apic_irq_mapping();
687 /* fill the LOGICAL io_apic_versions table */
688 for (apic = 0; apic < mp_napics; ++apic) {
689 ux = io_apic_read(apic, IOAPIC_VER);
690 io_apic_versions[apic] = ux;
691 io_apic_set_id(apic, IO_TO_ID(apic));
694 /* program each IO APIC in the system */
695 for (apic = 0; apic < mp_napics; ++apic)
696 if (io_apic_setup(apic) < 0)
697 panic("IO APIC setup failure");
702 * These are required for SMP operation
705 /* install a 'Spurious INTerrupt' vector */
706 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
707 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
709 /* install an inter-CPU IPI for TLB invalidation */
710 setidt(XINVLTLB_OFFSET, Xinvltlb,
711 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
713 /* install an inter-CPU IPI for IPIQ messaging */
714 setidt(XIPIQ_OFFSET, Xipiq,
715 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
717 /* install a timer vector */
718 setidt(XTIMER_OFFSET, Xtimer,
719 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
721 /* install an inter-CPU IPI for CPU stop/restart */
722 setidt(XCPUSTOP_OFFSET, Xcpustop,
723 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
725 /* start each Application Processor */
726 start_all_aps(boot_addr);
731 * look for the MP spec signature
734 /* string defined by the Intel MP Spec as identifying the MP table */
735 #define MP_SIG 0x5f504d5f /* _MP_ */
736 #define NEXT(X) ((X) += 4)
738 mptable_search_sig(u_int32_t target, int count)
744 KKASSERT(target != 0);
746 map_size = count * sizeof(u_int32_t);
747 addr = pmap_mapdev((vm_paddr_t)target, map_size);
750 for (x = 0; x < count; NEXT(x)) {
751 if (addr[x] == MP_SIG) {
752 /* make array index a byte index */
753 ret = target + (x * sizeof(u_int32_t));
758 pmap_unmapdev((vm_offset_t)addr, map_size);
763 typedef struct BUSDATA {
765 enum busTypes bus_type;
768 typedef struct INTDATA {
778 typedef struct BUSTYPENAME {
783 static bus_type_name bus_type_table[] =
789 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"},
793 {UNKNOWN_BUSTYPE, "---"},
794 {UNKNOWN_BUSTYPE, "---"},
795 {UNKNOWN_BUSTYPE, "---"},
796 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"},
801 {UNKNOWN_BUSTYPE, "---"},
803 {UNKNOWN_BUSTYPE, "---"}
805 /* from MP spec v1.4, table 5-1 */
806 static int default_data[7][5] =
808 /* nbus, id0, type0, id1, type1 */
809 {1, 0, ISA, 255, 255},
810 {1, 0, EISA, 255, 255},
811 {1, 0, EISA, 255, 255},
812 {1, 0, MCA, 255, 255},
814 {2, 0, EISA, 1, PCI},
820 static bus_datum *bus_data;
822 /* the IO INT data, one entry per possible APIC INTerrupt */
823 static io_int *io_apic_ints;
826 static int processor_entry (const struct PROCENTRY *entry, int cpu);
827 static int bus_entry (const struct BUSENTRY *entry, int bus);
828 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
829 static int int_entry (const struct INTENTRY *entry, int intr);
830 static int lookup_bus_type (char *name);
833 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
835 const struct IOAPICENTRY *ioapic_ent;
838 case 1: /* bus_entry */
842 case 2: /* io_apic_entry */
844 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
845 io_apic_address[mp_napics++] =
846 (vm_offset_t)ioapic_ent->apic_address;
850 case 3: /* int_entry */
858 * 1st pass on motherboard's Intel MP specification table.
867 mptable_pass1(struct mptable_pos *mpt)
872 POSTCODE(MPTABLE_PASS1_POST);
875 KKASSERT(fps != NULL);
877 /* clear various tables */
878 for (x = 0; x < NAPICID; ++x)
879 io_apic_address[x] = ~0; /* IO APIC address table */
885 /* check for use of 'default' configuration */
886 if (fps->mpfb1 != 0) {
887 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
888 mp_nbusses = default_data[fps->mpfb1 - 1][0];
894 error = mptable_iterate_entries(mpt->mp_cth,
895 mptable_ioapic_pass1_callback, NULL);
897 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
901 struct mptable_ioapic2_cbarg {
908 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
910 struct mptable_ioapic2_cbarg *arg = xarg;
914 if (bus_entry(pos, arg->bus))
919 if (io_apic_entry(pos, arg->apic))
924 if (int_entry(pos, arg->intr))
932 * 2nd pass on motherboard's Intel MP specification table.
935 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
936 * IO_TO_ID(N), logical IO to APIC ID table
941 mptable_pass2(struct mptable_pos *mpt)
943 struct mptable_ioapic2_cbarg arg;
947 POSTCODE(MPTABLE_PASS2_POST);
950 KKASSERT(fps != NULL);
952 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
954 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
955 M_DEVBUF, M_WAITOK | M_ZERO);
956 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
958 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
961 for (x = 0; x < mp_napics; x++)
962 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
964 /* clear various tables */
965 for (x = 0; x < NAPICID; ++x) {
966 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
967 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
970 /* clear bus data table */
971 for (x = 0; x < mp_nbusses; ++x)
972 bus_data[x].bus_id = 0xff;
974 /* clear IO APIC INT table */
975 for (x = 0; x < (nintrs + 1); ++x) {
976 io_apic_ints[x].int_type = 0xff;
977 io_apic_ints[x].int_vector = 0xff;
980 /* check for use of 'default' configuration */
981 if (fps->mpfb1 != 0) {
982 mptable_default(fps->mpfb1);
986 bzero(&arg, sizeof(arg));
987 error = mptable_iterate_entries(mpt->mp_cth,
988 mptable_ioapic_pass2_callback, &arg);
990 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
994 * Check if we should perform a hyperthreading "fix-up" to
995 * enumerate any logical CPU's that aren't already listed
998 * XXX: We assume that all of the physical CPUs in the
999 * system have the same number of logical CPUs.
1001 * XXX: We assume that APIC ID's are allocated such that
1002 * the APIC ID's for a physical processor are aligned
1003 * with the number of logical CPU's in the processor.
1006 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1008 int i, id, lcpus_max, logical_cpus;
1010 if ((cpu_feature & CPUID_HTT) == 0)
1013 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1017 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1019 * INSTRUCTION SET REFERENCE, A-M (#253666)
1020 * Page 3-181, Table 3-20
1021 * "The nearest power-of-2 integer that is not smaller
1022 * than EBX[23:16] is the number of unique initial APIC
1023 * IDs reserved for addressing different logical
1024 * processors in a physical package."
1026 for (i = 0; ; ++i) {
1027 if ((1 << i) >= lcpus_max) {
1034 KKASSERT(cpu_count != 0);
1035 if (cpu_count == lcpus_max) {
1036 /* We have nothing to fix */
1038 } else if (cpu_count == 1) {
1039 /* XXX this may be incorrect */
1040 logical_cpus = lcpus_max;
1042 int cur, prev, dist;
1045 * Calculate the distances between two nearest
1046 * APIC IDs. If all such distances are same,
1047 * then it is the number of missing cpus that
1048 * we are going to fill later.
1050 dist = cur = prev = -1;
1051 for (id = 0; id < MAXCPU; ++id) {
1052 if ((id_mask & 1 << id) == 0)
1057 int new_dist = cur - prev;
1063 * Make sure that all distances
1064 * between two nearest APIC IDs
1067 if (dist != new_dist)
1075 /* Must be power of 2 */
1076 if (dist & (dist - 1))
1079 /* Can't exceed CPU package capacity */
1080 if (dist > lcpus_max)
1081 logical_cpus = lcpus_max;
1083 logical_cpus = dist;
1087 * For each APIC ID of a CPU that is set in the mask,
1088 * scan the other candidate APIC ID's for this
1089 * physical processor. If any of those ID's are
1090 * already in the table, then kill the fixup.
1092 for (id = 0; id < MAXCPU; id++) {
1093 if ((id_mask & 1 << id) == 0)
1095 /* First, make sure we are on a logical_cpus boundary. */
1096 if (id % logical_cpus != 0)
1098 for (i = id + 1; i < id + logical_cpus; i++)
1099 if ((id_mask & 1 << i) != 0)
1102 return logical_cpus;
1106 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1110 vm_size_t cth_mapsz = 0;
1112 bzero(mpt, sizeof(*mpt));
1114 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1115 if (fps->pap != 0) {
1117 * Map configuration table header to get
1118 * the base table size
1120 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1121 cth_mapsz = cth->base_table_length;
1122 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1124 if (cth_mapsz < sizeof(*cth)) {
1125 kprintf("invalid base MP table length %d\n",
1127 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1132 * Map the base table
1134 cth = pmap_mapdev(fps->pap, cth_mapsz);
1139 mpt->mp_cth_mapsz = cth_mapsz;
1145 mptable_unmap(struct mptable_pos *mpt)
1147 if (mpt->mp_cth != NULL) {
1148 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1150 mpt->mp_cth_mapsz = 0;
1152 if (mpt->mp_fps != NULL) {
1153 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1159 assign_apic_irq(int apic, int intpin, int irq)
1163 if (int_to_apicintpin[irq].ioapic != -1)
1164 panic("assign_apic_irq: inconsistent table");
1166 int_to_apicintpin[irq].ioapic = apic;
1167 int_to_apicintpin[irq].int_pin = intpin;
1168 int_to_apicintpin[irq].apic_address = ioapic[apic];
1169 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1171 for (x = 0; x < nintrs; x++) {
1172 if ((io_apic_ints[x].int_type == 0 ||
1173 io_apic_ints[x].int_type == 3) &&
1174 io_apic_ints[x].int_vector == 0xff &&
1175 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1176 io_apic_ints[x].dst_apic_int == intpin)
1177 io_apic_ints[x].int_vector = irq;
1182 revoke_apic_irq(int irq)
1188 if (int_to_apicintpin[irq].ioapic == -1)
1189 panic("revoke_apic_irq: inconsistent table");
1191 oldapic = int_to_apicintpin[irq].ioapic;
1192 oldintpin = int_to_apicintpin[irq].int_pin;
1194 int_to_apicintpin[irq].ioapic = -1;
1195 int_to_apicintpin[irq].int_pin = 0;
1196 int_to_apicintpin[irq].apic_address = NULL;
1197 int_to_apicintpin[irq].redirindex = 0;
1199 for (x = 0; x < nintrs; x++) {
1200 if ((io_apic_ints[x].int_type == 0 ||
1201 io_apic_ints[x].int_type == 3) &&
1202 io_apic_ints[x].int_vector != 0xff &&
1203 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1204 io_apic_ints[x].dst_apic_int == oldintpin)
1205 io_apic_ints[x].int_vector = 0xff;
1213 allocate_apic_irq(int intr)
1219 if (io_apic_ints[intr].int_vector != 0xff)
1220 return; /* Interrupt handler already assigned */
1222 if (io_apic_ints[intr].int_type != 0 &&
1223 (io_apic_ints[intr].int_type != 3 ||
1224 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1225 io_apic_ints[intr].dst_apic_int == 0)))
1226 return; /* Not INT or ExtInt on != (0, 0) */
1229 while (irq < APIC_INTMAPSIZE &&
1230 int_to_apicintpin[irq].ioapic != -1)
1233 if (irq >= APIC_INTMAPSIZE)
1234 return; /* No free interrupt handlers */
1236 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1237 intpin = io_apic_ints[intr].dst_apic_int;
1239 assign_apic_irq(apic, intpin, irq);
1240 io_apic_setup_intpin(apic, intpin);
1245 swap_apic_id(int apic, int oldid, int newid)
1252 return; /* Nothing to do */
1254 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1255 apic, oldid, newid);
1257 /* Swap physical APIC IDs in interrupt entries */
1258 for (x = 0; x < nintrs; x++) {
1259 if (io_apic_ints[x].dst_apic_id == oldid)
1260 io_apic_ints[x].dst_apic_id = newid;
1261 else if (io_apic_ints[x].dst_apic_id == newid)
1262 io_apic_ints[x].dst_apic_id = oldid;
1265 /* Swap physical APIC IDs in IO_TO_ID mappings */
1266 for (oapic = 0; oapic < mp_napics; oapic++)
1267 if (IO_TO_ID(oapic) == newid)
1270 if (oapic < mp_napics) {
1271 kprintf("Changing APIC ID for IO APIC #%d from "
1272 "%d to %d in MP table\n",
1273 oapic, newid, oldid);
1274 IO_TO_ID(oapic) = oldid;
1276 IO_TO_ID(apic) = newid;
1281 fix_id_to_io_mapping(void)
1285 for (x = 0; x < NAPICID; x++)
1288 for (x = 0; x <= mp_naps; x++)
1289 if (CPU_TO_ID(x) < NAPICID)
1290 ID_TO_IO(CPU_TO_ID(x)) = x;
1292 for (x = 0; x < mp_napics; x++)
1293 if (IO_TO_ID(x) < NAPICID)
1294 ID_TO_IO(IO_TO_ID(x)) = x;
1299 first_free_apic_id(void)
1303 for (freeid = 0; freeid < NAPICID; freeid++) {
1304 for (x = 0; x <= mp_naps; x++)
1305 if (CPU_TO_ID(x) == freeid)
1309 for (x = 0; x < mp_napics; x++)
1310 if (IO_TO_ID(x) == freeid)
1321 io_apic_id_acceptable(int apic, int id)
1323 int cpu; /* Logical CPU number */
1324 int oapic; /* Logical IO APIC number for other IO APIC */
1327 return 0; /* Out of range */
1329 for (cpu = 0; cpu <= mp_naps; cpu++)
1330 if (CPU_TO_ID(cpu) == id)
1331 return 0; /* Conflict with CPU */
1333 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1334 if (IO_TO_ID(oapic) == id)
1335 return 0; /* Conflict with other APIC */
1337 return 1; /* ID is acceptable for IO APIC */
1342 io_apic_find_int_entry(int apic, int pin)
1346 /* search each of the possible INTerrupt sources */
1347 for (x = 0; x < nintrs; ++x) {
1348 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1349 (pin == io_apic_ints[x].dst_apic_int))
1350 return (&io_apic_ints[x]);
1356 * parse an Intel MP specification table
1363 int apic; /* IO APIC unit number */
1364 int freeid; /* Free physical APIC ID */
1365 int physid; /* Current physical IO APIC ID */
1367 int bus_0 = 0; /* Stop GCC warning */
1368 int bus_pci = 0; /* Stop GCC warning */
1372 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1373 * did it wrong. The MP spec says that when more than 1 PCI bus
1374 * exists the BIOS must begin with bus entries for the PCI bus and use
1375 * actual PCI bus numbering. This implies that when only 1 PCI bus
1376 * exists the BIOS can choose to ignore this ordering, and indeed many
1377 * MP motherboards do ignore it. This causes a problem when the PCI
1378 * sub-system makes requests of the MP sub-system based on PCI bus
1379 * numbers. So here we look for the situation and renumber the
1380 * busses and associated INTs in an effort to "make it right".
1383 /* find bus 0, PCI bus, count the number of PCI busses */
1384 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1385 if (bus_data[x].bus_id == 0) {
1388 if (bus_data[x].bus_type == PCI) {
1394 * bus_0 == slot of bus with ID of 0
1395 * bus_pci == slot of last PCI bus encountered
1398 /* check the 1 PCI bus case for sanity */
1399 /* if it is number 0 all is well */
1400 if (num_pci_bus == 1 &&
1401 bus_data[bus_pci].bus_id != 0) {
1403 /* mis-numbered, swap with whichever bus uses slot 0 */
1405 /* swap the bus entry types */
1406 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1407 bus_data[bus_0].bus_type = PCI;
1409 /* swap each relavant INTerrupt entry */
1410 id = bus_data[bus_pci].bus_id;
1411 for (x = 0; x < nintrs; ++x) {
1412 if (io_apic_ints[x].src_bus_id == id) {
1413 io_apic_ints[x].src_bus_id = 0;
1415 else if (io_apic_ints[x].src_bus_id == 0) {
1416 io_apic_ints[x].src_bus_id = id;
1421 /* Assign IO APIC IDs.
1423 * First try the existing ID. If a conflict is detected, try
1424 * the ID in the MP table. If a conflict is still detected, find
1427 * We cannot use the ID_TO_IO table before all conflicts has been
1428 * resolved and the table has been corrected.
1430 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1432 /* First try to use the value set by the BIOS */
1433 physid = io_apic_get_id(apic);
1434 if (io_apic_id_acceptable(apic, physid)) {
1435 if (IO_TO_ID(apic) != physid)
1436 swap_apic_id(apic, IO_TO_ID(apic), physid);
1440 /* Then check if the value in the MP table is acceptable */
1441 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1444 /* Last resort, find a free APIC ID and use it */
1445 freeid = first_free_apic_id();
1446 if (freeid >= NAPICID)
1447 panic("No free physical APIC IDs found");
1449 if (io_apic_id_acceptable(apic, freeid)) {
1450 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1453 panic("Free physical APIC ID not usable");
1455 fix_id_to_io_mapping();
1457 /* detect and fix broken Compaq MP table */
1458 if (apic_int_type(0, 0) == -1) {
1459 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1460 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1461 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1462 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1463 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1464 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1466 } else if (apic_int_type(0, 0) == 0) {
1467 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1468 for (x = 0; x < nintrs; ++x)
1469 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1470 (0 == io_apic_ints[x].dst_apic_int)) {
1471 io_apic_ints[x].int_type = 3;
1472 io_apic_ints[x].int_vector = 0xff;
1478 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1479 * controllers universally come in pairs. If IRQ 14 is specified
1480 * as an ISA interrupt, then IRQ 15 had better be too.
1482 * [ Shuttle XPC / AMD Athlon X2 ]
1483 * The MPTable is missing an entry for IRQ 15. Note that the
1484 * ACPI table has an entry for both 14 and 15.
1486 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1487 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1488 io14 = io_apic_find_int_entry(0, 14);
1489 io_apic_ints[nintrs] = *io14;
1490 io_apic_ints[nintrs].src_bus_irq = 15;
1491 io_apic_ints[nintrs].dst_apic_int = 15;
1496 /* Assign low level interrupt handlers */
1498 setup_apic_irq_mapping(void)
1504 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1505 int_to_apicintpin[x].ioapic = -1;
1506 int_to_apicintpin[x].int_pin = 0;
1507 int_to_apicintpin[x].apic_address = NULL;
1508 int_to_apicintpin[x].redirindex = 0;
1510 /* Default to masked */
1511 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1514 /* First assign ISA/EISA interrupts */
1515 for (x = 0; x < nintrs; x++) {
1516 int_vector = io_apic_ints[x].src_bus_irq;
1517 if (int_vector < APIC_INTMAPSIZE &&
1518 io_apic_ints[x].int_vector == 0xff &&
1519 int_to_apicintpin[int_vector].ioapic == -1 &&
1520 (apic_int_is_bus_type(x, ISA) ||
1521 apic_int_is_bus_type(x, EISA)) &&
1522 io_apic_ints[x].int_type == 0) {
1523 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1524 io_apic_ints[x].dst_apic_int,
1529 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1530 for (x = 0; x < nintrs; x++) {
1531 if (io_apic_ints[x].dst_apic_int == 0 &&
1532 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1533 io_apic_ints[x].int_vector == 0xff &&
1534 int_to_apicintpin[0].ioapic == -1 &&
1535 io_apic_ints[x].int_type == 3) {
1536 assign_apic_irq(0, 0, 0);
1540 /* PCI interrupt assignment is deferred */
1544 mp_set_cpuids(int cpu_id, int apic_id)
1546 CPU_TO_ID(cpu_id) = apic_id;
1547 ID_TO_CPU(apic_id) = cpu_id;
1551 processor_entry(const struct PROCENTRY *entry, int cpu)
1555 /* check for usability */
1556 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1559 /* check for BSP flag */
1560 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1561 mp_set_cpuids(0, entry->apic_id);
1562 return 0; /* its already been counted */
1565 /* add another AP to list, if less than max number of CPUs */
1566 else if (cpu < MAXCPU) {
1567 mp_set_cpuids(cpu, entry->apic_id);
1575 bus_entry(const struct BUSENTRY *entry, int bus)
1580 /* encode the name into an index */
1581 for (x = 0; x < 6; ++x) {
1582 if ((c = entry->bus_type[x]) == ' ')
1588 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1589 panic("unknown bus type: '%s'", name);
1591 bus_data[bus].bus_id = entry->bus_id;
1592 bus_data[bus].bus_type = x;
1598 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1600 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1603 IO_TO_ID(apic) = entry->apic_id;
1604 ID_TO_IO(entry->apic_id) = apic;
1610 lookup_bus_type(char *name)
1614 for (x = 0; x < MAX_BUSTYPE; ++x)
1615 if (strcmp(bus_type_table[x].name, name) == 0)
1616 return bus_type_table[x].type;
1618 return UNKNOWN_BUSTYPE;
1622 int_entry(const struct INTENTRY *entry, int intr)
1626 io_apic_ints[intr].int_type = entry->int_type;
1627 io_apic_ints[intr].int_flags = entry->int_flags;
1628 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1629 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1630 if (entry->dst_apic_id == 255) {
1631 /* This signal goes to all IO APICS. Select an IO APIC
1632 with sufficient number of interrupt pins */
1633 for (apic = 0; apic < mp_napics; apic++)
1634 if (((io_apic_read(apic, IOAPIC_VER) &
1635 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1636 entry->dst_apic_int)
1638 if (apic < mp_napics)
1639 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1641 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1643 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1644 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1650 apic_int_is_bus_type(int intr, int bus_type)
1654 for (bus = 0; bus < mp_nbusses; ++bus)
1655 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1656 && ((int) bus_data[bus].bus_type == bus_type))
1663 * Given a traditional ISA INT mask, return an APIC mask.
1666 isa_apic_mask(u_int isa_mask)
1671 #if defined(SKIP_IRQ15_REDIRECT)
1672 if (isa_mask == (1 << 15)) {
1673 kprintf("skipping ISA IRQ15 redirect\n");
1676 #endif /* SKIP_IRQ15_REDIRECT */
1678 isa_irq = ffs(isa_mask); /* find its bit position */
1679 if (isa_irq == 0) /* doesn't exist */
1681 --isa_irq; /* make it zero based */
1683 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1687 return (1 << apic_pin); /* convert pin# to a mask */
1691 * Determine which APIC pin an ISA/EISA INT is attached to.
1693 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1694 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1695 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1696 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1698 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1700 isa_apic_irq(int isa_irq)
1704 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1705 if (INTTYPE(intr) == 0) { /* standard INT */
1706 if (SRCBUSIRQ(intr) == isa_irq) {
1707 if (apic_int_is_bus_type(intr, ISA) ||
1708 apic_int_is_bus_type(intr, EISA)) {
1709 if (INTIRQ(intr) == 0xff)
1710 return -1; /* unassigned */
1711 return INTIRQ(intr); /* found */
1716 return -1; /* NOT found */
1721 * Determine which APIC pin a PCI INT is attached to.
1723 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1724 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1725 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1727 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1731 --pciInt; /* zero based */
1733 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1734 if ((INTTYPE(intr) == 0) /* standard INT */
1735 && (SRCBUSID(intr) == pciBus)
1736 && (SRCBUSDEVICE(intr) == pciDevice)
1737 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1738 if (apic_int_is_bus_type(intr, PCI)) {
1739 if (INTIRQ(intr) == 0xff)
1740 allocate_apic_irq(intr);
1741 if (INTIRQ(intr) == 0xff)
1742 return -1; /* unassigned */
1743 return INTIRQ(intr); /* exact match */
1748 return -1; /* NOT found */
1752 next_apic_irq(int irq)
1759 for (intr = 0; intr < nintrs; intr++) {
1760 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1762 bus = SRCBUSID(intr);
1763 bustype = apic_bus_type(bus);
1764 if (bustype != ISA &&
1770 if (intr >= nintrs) {
1773 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1774 if (INTTYPE(ointr) != 0)
1776 if (bus != SRCBUSID(ointr))
1778 if (bustype == PCI) {
1779 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1781 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1784 if (bustype == ISA || bustype == EISA) {
1785 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1788 if (INTPIN(intr) == INTPIN(ointr))
1792 if (ointr >= nintrs) {
1795 return INTIRQ(ointr);
1808 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1811 * Exactly what this means is unclear at this point. It is a solution
1812 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1813 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1814 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1818 undirect_isa_irq(int rirq)
1822 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1823 /** FIXME: tickle the MB redirector chip */
1827 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1834 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1837 undirect_pci_irq(int rirq)
1841 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1843 /** FIXME: tickle the MB redirector chip */
1847 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1855 * given a bus ID, return:
1856 * the bus type if found
1860 apic_bus_type(int id)
1864 for (x = 0; x < mp_nbusses; ++x)
1865 if (bus_data[x].bus_id == id)
1866 return bus_data[x].bus_type;
1872 * given a LOGICAL APIC# and pin#, return:
1873 * the associated src bus ID if found
1877 apic_src_bus_id(int apic, int pin)
1881 /* search each of the possible INTerrupt sources */
1882 for (x = 0; x < nintrs; ++x)
1883 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1884 (pin == io_apic_ints[x].dst_apic_int))
1885 return (io_apic_ints[x].src_bus_id);
1887 return -1; /* NOT found */
1891 * given a LOGICAL APIC# and pin#, return:
1892 * the associated src bus IRQ if found
1896 apic_src_bus_irq(int apic, int pin)
1900 for (x = 0; x < nintrs; x++)
1901 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1902 (pin == io_apic_ints[x].dst_apic_int))
1903 return (io_apic_ints[x].src_bus_irq);
1905 return -1; /* NOT found */
1910 * given a LOGICAL APIC# and pin#, return:
1911 * the associated INTerrupt type if found
1915 apic_int_type(int apic, int pin)
1919 /* search each of the possible INTerrupt sources */
1920 for (x = 0; x < nintrs; ++x) {
1921 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1922 (pin == io_apic_ints[x].dst_apic_int))
1923 return (io_apic_ints[x].int_type);
1925 return -1; /* NOT found */
1929 * Return the IRQ associated with an APIC pin
1932 apic_irq(int apic, int pin)
1937 for (x = 0; x < nintrs; ++x) {
1938 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1939 (pin == io_apic_ints[x].dst_apic_int)) {
1940 res = io_apic_ints[x].int_vector;
1943 if (apic != int_to_apicintpin[res].ioapic)
1944 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1945 if (pin != int_to_apicintpin[res].int_pin)
1946 panic("apic_irq inconsistent table (2)");
1955 * given a LOGICAL APIC# and pin#, return:
1956 * the associated trigger mode if found
1960 apic_trigger(int apic, int pin)
1964 /* search each of the possible INTerrupt sources */
1965 for (x = 0; x < nintrs; ++x)
1966 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1967 (pin == io_apic_ints[x].dst_apic_int))
1968 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1970 return -1; /* NOT found */
1975 * given a LOGICAL APIC# and pin#, return:
1976 * the associated 'active' level if found
1980 apic_polarity(int apic, int pin)
1984 /* search each of the possible INTerrupt sources */
1985 for (x = 0; x < nintrs; ++x)
1986 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1987 (pin == io_apic_ints[x].dst_apic_int))
1988 return (io_apic_ints[x].int_flags & 0x03);
1990 return -1; /* NOT found */
1994 * set data according to MP defaults
1995 * FIXME: probably not complete yet...
1998 mptable_default(int type)
2004 kprintf(" MP default config type: %d\n", type);
2007 kprintf(" bus: ISA, APIC: 82489DX\n");
2010 kprintf(" bus: EISA, APIC: 82489DX\n");
2013 kprintf(" bus: EISA, APIC: 82489DX\n");
2016 kprintf(" bus: MCA, APIC: 82489DX\n");
2019 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2022 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2025 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2028 kprintf(" future type\n");
2034 /* one and only IO APIC */
2035 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2038 * sanity check, refer to MP spec section 3.6.6, last paragraph
2039 * necessary as some hardware isn't properly setting up the IO APIC
2041 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2042 if (io_apic_id != 2) {
2044 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2045 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2046 io_apic_set_id(0, 2);
2049 IO_TO_ID(0) = io_apic_id;
2050 ID_TO_IO(io_apic_id) = 0;
2052 /* fill out bus entries */
2061 bus_data[0].bus_id = default_data[type - 1][1];
2062 bus_data[0].bus_type = default_data[type - 1][2];
2063 bus_data[1].bus_id = default_data[type - 1][3];
2064 bus_data[1].bus_type = default_data[type - 1][4];
2067 /* case 4: case 7: MCA NOT supported */
2068 default: /* illegal/reserved */
2069 panic("BAD default MP config: %d", type);
2073 /* general cases from MP v1.4, table 5-2 */
2074 for (pin = 0; pin < 16; ++pin) {
2075 io_apic_ints[pin].int_type = 0;
2076 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2077 io_apic_ints[pin].src_bus_id = 0;
2078 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2079 io_apic_ints[pin].dst_apic_id = io_apic_id;
2080 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2083 /* special cases from MP v1.4, table 5-2 */
2085 io_apic_ints[2].int_type = 0xff; /* N/C */
2086 io_apic_ints[13].int_type = 0xff; /* N/C */
2087 #if !defined(APIC_MIXED_MODE)
2089 panic("sorry, can't support type 2 default yet");
2090 #endif /* APIC_MIXED_MODE */
2093 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2096 io_apic_ints[0].int_type = 0xff; /* N/C */
2098 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2102 * Map a physical memory address representing I/O into KVA. The I/O
2103 * block is assumed not to cross a page boundary.
2106 permanent_io_mapping(vm_paddr_t pa)
2112 KKASSERT(pa < 0x100000000LL);
2114 pgeflag = 0; /* not used for SMP yet */
2117 * If the requested physical address has already been incidently
2118 * mapped, just use the existing mapping. Otherwise create a new
2121 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2122 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2123 ((vm_offset_t)pa & PG_FRAME)) {
2127 if (i == SMPpt_alloc_index) {
2128 if (i == NPTEPG - 2) {
2129 panic("permanent_io_mapping: We ran out of space"
2132 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2133 ((vm_offset_t)pa & PG_FRAME));
2134 ++SMPpt_alloc_index;
2136 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2137 ((vm_offset_t)pa & PAGE_MASK);
2138 return ((void *)vaddr);
2142 * start each AP in our list
2145 start_all_aps(u_int boot_addr)
2152 u_char mpbiosreason;
2153 u_long mpbioswarmvec;
2154 struct mdglobaldata *gd;
2155 struct privatespace *ps;
2159 POSTCODE(START_ALL_APS_POST);
2161 /* Initialize BSP's local APIC */
2162 apic_initialize(TRUE);
2164 /* install the AP 1st level boot code */
2165 install_ap_tramp(boot_addr);
2168 /* save the current value of the warm-start vector */
2169 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2170 outb(CMOS_REG, BIOS_RESET);
2171 mpbiosreason = inb(CMOS_DATA);
2173 /* setup a vector to our boot code */
2174 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2175 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2176 outb(CMOS_REG, BIOS_RESET);
2177 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2180 * If we have a TSC we can figure out the SMI interrupt rate.
2181 * The SMI does not necessarily use a constant rate. Spend
2182 * up to 250ms trying to figure it out.
2185 if (cpu_feature & CPUID_TSC) {
2186 set_apic_timer(275000);
2187 smilast = read_apic_timer();
2188 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2189 smicount = smitest();
2190 if (smibest == 0 || smilast - smicount < smibest)
2191 smibest = smilast - smicount;
2194 if (smibest > 250000)
2197 smibest = smibest * (int64_t)1000000 /
2198 get_apic_timer_frequency();
2202 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2203 1000000 / smibest, smibest);
2206 /* set up temporary P==V mapping for AP boot */
2207 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2208 kptbase = (uintptr_t)(void *)KPTphys;
2209 for (x = 0; x < NKPT; x++) {
2210 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2211 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2216 for (x = 1; x <= mp_naps; ++x) {
2218 /* This is a bit verbose, it will go away soon. */
2220 /* first page of AP's private space */
2221 pg = x * i386_btop(sizeof(struct privatespace));
2223 /* allocate new private data page(s) */
2224 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2225 MDGLOBALDATA_BASEALLOC_SIZE);
2226 /* wire it into the private page table page */
2227 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2228 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2229 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2231 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2233 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2234 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2235 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2236 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2238 /* allocate and set up an idle stack data page */
2239 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2240 for (i = 0; i < UPAGES; i++) {
2241 SMPpt[pg + 4 + i] = (pt_entry_t)
2242 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2245 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2246 bzero(gd, sizeof(*gd));
2247 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2249 /* prime data page for it to use */
2250 mi_gdinit(&gd->mi, x);
2252 gd->gd_CMAP1 = &SMPpt[pg + 0];
2253 gd->gd_CMAP2 = &SMPpt[pg + 1];
2254 gd->gd_CMAP3 = &SMPpt[pg + 2];
2255 gd->gd_PMAP1 = &SMPpt[pg + 3];
2256 gd->gd_CADDR1 = ps->CPAGE1;
2257 gd->gd_CADDR2 = ps->CPAGE2;
2258 gd->gd_CADDR3 = ps->CPAGE3;
2259 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2262 * Per-cpu pmap for get_ptbase().
2264 gd->gd_GDADDR1= (unsigned *)
2265 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2266 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2268 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2269 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2272 * Setup the AP boot stack
2274 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2277 /* attempt to start the Application Processor */
2278 CHECK_INIT(99); /* setup checkpoints */
2279 if (!start_ap(gd, boot_addr, smibest)) {
2280 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2281 CHECK_PRINT("trace"); /* show checkpoints */
2282 /* better panic as the AP may be running loose */
2283 kprintf("panic y/n? [y] ");
2284 if (cngetc() != 'n')
2287 CHECK_PRINT("trace"); /* show checkpoints */
2289 /* record its version info */
2290 cpu_apic_versions[x] = cpu_apic_versions[0];
2293 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2296 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2297 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2300 ncpus2_shift = shift;
2301 ncpus2 = 1 << shift;
2302 ncpus2_mask = ncpus2 - 1;
2304 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2305 if ((1 << shift) < ncpus)
2307 ncpus_fit = 1 << shift;
2308 ncpus_fit_mask = ncpus_fit - 1;
2310 /* build our map of 'other' CPUs */
2311 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2312 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2313 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2315 /* fill in our (BSP) APIC version */
2316 cpu_apic_versions[0] = lapic.version;
2318 /* restore the warmstart vector */
2319 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2320 outb(CMOS_REG, BIOS_RESET);
2321 outb(CMOS_DATA, mpbiosreason);
2324 * NOTE! The idlestack for the BSP was setup by locore. Finish
2325 * up, clean out the P==V mapping we did earlier.
2327 for (x = 0; x < NKPT; x++)
2331 /* number of APs actually started */
2336 * load the 1st level AP boot code into base memory.
2339 /* targets for relocation */
2340 extern void bigJump(void);
2341 extern void bootCodeSeg(void);
2342 extern void bootDataSeg(void);
2343 extern void MPentry(void);
2344 extern u_int MP_GDT;
2345 extern u_int mp_gdtbase;
2348 install_ap_tramp(u_int boot_addr)
2351 int size = *(int *) ((u_long) & bootMP_size);
2352 u_char *src = (u_char *) ((u_long) bootMP);
2353 u_char *dst = (u_char *) boot_addr + KERNBASE;
2354 u_int boot_base = (u_int) bootMP;
2359 POSTCODE(INSTALL_AP_TRAMP_POST);
2361 for (x = 0; x < size; ++x)
2365 * modify addresses in code we just moved to basemem. unfortunately we
2366 * need fairly detailed info about mpboot.s for this to work. changes
2367 * to mpboot.s might require changes here.
2370 /* boot code is located in KERNEL space */
2371 dst = (u_char *) boot_addr + KERNBASE;
2373 /* modify the lgdt arg */
2374 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2375 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2377 /* modify the ljmp target for MPentry() */
2378 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2379 *dst32 = ((u_int) MPentry - KERNBASE);
2381 /* modify the target for boot code segment */
2382 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2383 dst8 = (u_int8_t *) (dst16 + 1);
2384 *dst16 = (u_int) boot_addr & 0xffff;
2385 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2387 /* modify the target for boot data segment */
2388 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2389 dst8 = (u_int8_t *) (dst16 + 1);
2390 *dst16 = (u_int) boot_addr & 0xffff;
2391 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2396 * This function starts the AP (application processor) identified
2397 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2398 * to accomplish this. This is necessary because of the nuances
2399 * of the different hardware we might encounter. It ain't pretty,
2400 * but it seems to work.
2402 * NOTE: eventually an AP gets to ap_init(), which is called just
2403 * before the AP goes into the LWKT scheduler's idle loop.
2406 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2410 u_long icr_lo, icr_hi;
2412 POSTCODE(START_AP_POST);
2414 /* get the PHYSICAL APIC ID# */
2415 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2417 /* calculate the vector */
2418 vector = (boot_addr >> 12) & 0xff;
2420 /* We don't want anything interfering */
2423 /* Make sure the target cpu sees everything */
2427 * Try to detect when a SMI has occurred, wait up to 200ms.
2429 * If a SMI occurs during an AP reset but before we issue
2430 * the STARTUP command, the AP may brick. To work around
2431 * this problem we hold off doing the AP startup until
2432 * after we have detected the SMI. Hopefully another SMI
2433 * will not occur before we finish the AP startup.
2435 * Retries don't seem to help. SMIs have a window of opportunity
2436 * and if USB->legacy keyboard emulation is enabled in the BIOS
2437 * the interrupt rate can be quite high.
2439 * NOTE: Don't worry about the L1 cache load, it might bloat
2440 * ldelta a little but ndelta will be so huge when the SMI
2441 * occurs the detection logic will still work fine.
2444 set_apic_timer(200000);
2449 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2450 * and running the target CPU. OR this INIT IPI might be latched (P5
2451 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2454 * see apic/apicreg.h for icr bit definitions.
2456 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2460 * Setup the address for the target AP. We can setup
2461 * icr_hi once and then just trigger operations with
2464 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2465 icr_hi |= (physical_cpu << 24);
2466 icr_lo = lapic.icr_lo & 0xfff00000;
2467 lapic.icr_hi = icr_hi;
2470 * Do an INIT IPI: assert RESET
2472 * Use edge triggered mode to assert INIT
2474 lapic.icr_lo = icr_lo | 0x0000c500;
2475 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2479 * The spec calls for a 10ms delay but we may have to use a
2480 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2481 * interrupt. We have other loops here too and dividing by 2
2482 * doesn't seem to be enough even after subtracting 350us,
2483 * so we divide by 4.
2485 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2486 * interrupt was detected we use the full 10ms.
2490 else if (smibest < 150 * 4 + 350)
2492 else if ((smibest - 350) / 4 < 10000)
2493 u_sleep((smibest - 350) / 4);
2498 * Do an INIT IPI: deassert RESET
2500 * Use level triggered mode to deassert. It is unclear
2501 * why we need to do this.
2503 lapic.icr_lo = icr_lo | 0x00008500;
2504 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2506 u_sleep(150); /* wait 150us */
2509 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2510 * latched, (P5 bug) this 1st STARTUP would then terminate
2511 * immediately, and the previously started INIT IPI would continue. OR
2512 * the previous INIT IPI has already run. and this STARTUP IPI will
2513 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2516 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2517 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2519 u_sleep(200); /* wait ~200uS */
2522 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2523 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2524 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2525 * recognized after hardware RESET or INIT IPI.
2527 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2528 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2531 /* Resume normal operation */
2534 /* wait for it to start, see ap_init() */
2535 set_apic_timer(5000000);/* == 5 seconds */
2536 while (read_apic_timer()) {
2537 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2538 return 1; /* return SUCCESS */
2541 return 0; /* return FAILURE */
2556 while (read_apic_timer()) {
2558 for (count = 0; count < 100; ++count)
2559 ntsc = rdtsc(); /* force loop to occur */
2561 ndelta = ntsc - ltsc;
2562 if (ldelta > ndelta)
2564 if (ndelta > ldelta * 2)
2567 ldelta = ntsc - ltsc;
2570 return(read_apic_timer());
2574 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2576 * If for some reason we were unable to start all cpus we cannot safely
2577 * use broadcast IPIs.
2580 static cpumask_t smp_invltlb_req;
2581 #define SMP_INVLTLB_DEBUG
2587 struct mdglobaldata *md = mdcpu;
2588 #ifdef SMP_INVLTLB_DEBUG
2593 crit_enter_gd(&md->mi);
2594 md->gd_invltlb_ret = 0;
2595 ++md->mi.gd_cnt.v_smpinvltlb;
2596 atomic_set_int(&smp_invltlb_req, md->mi.gd_cpumask);
2597 #ifdef SMP_INVLTLB_DEBUG
2600 if (smp_startup_mask == smp_active_mask) {
2601 all_but_self_ipi(XINVLTLB_OFFSET);
2603 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2604 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2607 #ifdef SMP_INVLTLB_DEBUG
2609 kprintf("smp_invltlb: ipi sent\n");
2611 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2612 (smp_active_mask & ~md->mi.gd_cpumask)) {
2615 #ifdef SMP_INVLTLB_DEBUG
2617 if (++count == 400000000) {
2618 print_backtrace(-1);
2619 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2620 "rflags %016lx retry",
2621 (long)md->gd_invltlb_ret,
2622 (long)smp_invltlb_req,
2623 (long)read_eflags());
2624 __asm __volatile ("sti");
2627 lwkt_process_ipiq();
2629 int bcpu = bsfl(~md->gd_invltlb_ret & ~md->mi.gd_cpumask & smp_active_mask);
2631 kprintf("bcpu %d\n", bcpu);
2632 xgd = globaldata_find(bcpu);
2633 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2642 atomic_clear_int(&smp_invltlb_req, md->mi.gd_cpumask);
2643 crit_exit_gd(&md->mi);
2650 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2651 * bother to bump the critical section count or nested interrupt count
2652 * so only do very low level operations here.
2655 smp_invltlb_intr(void)
2657 struct mdglobaldata *md = mdcpu;
2658 struct mdglobaldata *omd;
2662 mask = smp_invltlb_req;
2667 mask &= ~(1 << cpu);
2668 omd = (struct mdglobaldata *)globaldata_find(cpu);
2669 atomic_set_int(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2676 * When called the executing CPU will send an IPI to all other CPUs
2677 * requesting that they halt execution.
2679 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2681 * - Signals all CPUs in map to stop.
2682 * - Waits for each to stop.
2689 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2690 * from executing at same time.
2693 stop_cpus(u_int map)
2695 map &= smp_active_mask;
2697 /* send the Xcpustop IPI to all CPUs in map */
2698 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2700 while ((stopped_cpus & map) != map)
2708 * Called by a CPU to restart stopped CPUs.
2710 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2712 * - Signals all CPUs in map to restart.
2713 * - Waits for each to restart.
2721 restart_cpus(u_int map)
2723 /* signal other cpus to restart */
2724 started_cpus = map & smp_active_mask;
2726 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2733 * This is called once the mpboot code has gotten us properly relocated
2734 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2735 * and when it returns the scheduler will call the real cpu_idle() main
2736 * loop for the idlethread. Interrupts are disabled on entry and should
2737 * remain disabled at return.
2745 * Adjust smp_startup_mask to signal the BSP that we have started
2746 * up successfully. Note that we do not yet hold the BGL. The BSP
2747 * is waiting for our signal.
2749 * We can't set our bit in smp_active_mask yet because we are holding
2750 * interrupts physically disabled and remote cpus could deadlock
2751 * trying to send us an IPI.
2753 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2757 * Interlock for finalization. Wait until mp_finish is non-zero,
2758 * then get the MP lock.
2760 * Note: We are in a critical section.
2762 * Note: We have to synchronize td_mpcount to our desired MP state
2763 * before calling cpu_try_mplock().
2765 * Note: we are the idle thread, we can only spin.
2767 * Note: The load fence is memory volatile and prevents the compiler
2768 * from improperly caching mp_finish, and the cpu from improperly
2771 while (mp_finish == 0)
2773 ++curthread->td_mpcount;
2774 while (cpu_try_mplock() == 0)
2777 if (cpu_feature & CPUID_TSC) {
2779 * The BSP is constantly updating tsc0_offset, figure out the
2780 * relative difference to synchronize ktrdump.
2782 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2785 /* BSP may have changed PTD while we're waiting for the lock */
2788 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2792 /* Build our map of 'other' CPUs. */
2793 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2795 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2797 /* A quick check from sanity claus */
2798 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2799 if (mycpu->gd_cpuid != apic_id) {
2800 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2801 kprintf("SMP: apic_id = %d\n", apic_id);
2802 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2803 panic("cpuid mismatch! boom!!");
2806 /* Initialize AP's local APIC for irq's */
2807 apic_initialize(FALSE);
2809 /* Set memory range attributes for this CPU to match the BSP */
2810 mem_range_AP_init();
2813 * Once we go active we must process any IPIQ messages that may
2814 * have been queued, because no actual IPI will occur until we
2815 * set our bit in the smp_active_mask. If we don't the IPI
2816 * message interlock could be left set which would also prevent
2819 * The idle loop doesn't expect the BGL to be held and while
2820 * lwkt_switch() normally cleans things up this is a special case
2821 * because we returning almost directly into the idle loop.
2823 * The idle thread is never placed on the runq, make sure
2824 * nothing we've done put it there.
2826 KKASSERT(curthread->td_mpcount == 1);
2827 smp_active_mask |= 1 << mycpu->gd_cpuid;
2830 * Enable interrupts here. idle_restore will also do it, but
2831 * doing it here lets us clean up any strays that got posted to
2832 * the CPU during the AP boot while we are still in a critical
2835 __asm __volatile("sti; pause; pause"::);
2836 mdcpu->gd_fpending = 0;
2838 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2839 lwkt_process_ipiq();
2842 * Releasing the mp lock lets the BSP finish up the SMP init
2845 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2849 * Get SMP fully working before we start initializing devices.
2857 kprintf("Finish MP startup\n");
2858 if (cpu_feature & CPUID_TSC)
2859 tsc0_offset = rdtsc();
2862 while (smp_active_mask != smp_startup_mask) {
2864 if (cpu_feature & CPUID_TSC)
2865 tsc0_offset = rdtsc();
2867 while (try_mplock() == 0)
2870 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2873 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2876 cpu_send_ipiq(int dcpu)
2878 if ((1 << dcpu) & smp_active_mask)
2879 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2882 #if 0 /* single_apic_ipi_passive() not working yet */
2884 * Returns 0 on failure, 1 on success
2887 cpu_send_ipiq_passive(int dcpu)
2890 if ((1 << dcpu) & smp_active_mask) {
2891 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2892 APIC_DELMODE_FIXED);
2898 struct mptable_lapic_cbarg1 {
2901 u_int ht_apicid_mask;
2905 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2907 const struct PROCENTRY *ent;
2908 struct mptable_lapic_cbarg1 *arg = xarg;
2914 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2918 if (ent->apic_id < 32) {
2919 arg->ht_apicid_mask |= 1 << ent->apic_id;
2920 } else if (arg->ht_fixup) {
2921 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2927 struct mptable_lapic_cbarg2 {
2934 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2936 const struct PROCENTRY *ent;
2937 struct mptable_lapic_cbarg2 *arg = xarg;
2943 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2944 KKASSERT(!arg->found_bsp);
2948 if (processor_entry(ent, arg->cpu))
2951 if (arg->logical_cpus) {
2952 struct PROCENTRY proc;
2956 * Create fake mptable processor entries
2957 * and feed them to processor_entry() to
2958 * enumerate the logical CPUs.
2960 bzero(&proc, sizeof(proc));
2962 proc.cpu_flags = PROCENTRY_FLAG_EN;
2963 proc.apic_id = ent->apic_id;
2965 for (i = 1; i < arg->logical_cpus; i++) {
2967 processor_entry(&proc, arg->cpu);
2975 mptable_imcr(struct mptable_pos *mpt)
2977 /* record whether PIC or virtual-wire mode */
2978 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2979 mpt->mp_fps->mpfb2 & 0x80);
2982 struct mptable_lapic_enumerator {
2983 struct lapic_enumerator enumerator;
2984 vm_paddr_t mpfps_paddr;
2988 mptable_lapic_default(void)
2990 int ap_apicid, bsp_apicid;
2992 mp_naps = 1; /* exclude BSP */
2994 /* Map local apic before the id field is accessed */
2995 lapic_map(DEFAULT_APIC_BASE);
2997 bsp_apicid = APIC_ID(lapic.id);
2998 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3001 mp_set_cpuids(0, bsp_apicid);
3002 /* one and only AP */
3003 mp_set_cpuids(1, ap_apicid);
3009 * ID_TO_CPU(N), APIC ID to logical CPU table
3010 * CPU_TO_ID(N), logical CPU to APIC ID table
3013 mptable_lapic_enumerate(struct lapic_enumerator *e)
3015 struct mptable_pos mpt;
3016 struct mptable_lapic_cbarg1 arg1;
3017 struct mptable_lapic_cbarg2 arg2;
3019 int error, logical_cpus = 0;
3020 vm_offset_t lapic_addr;
3021 vm_paddr_t mpfps_paddr;
3023 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
3024 KKASSERT(mpfps_paddr != 0);
3026 error = mptable_map(&mpt, mpfps_paddr);
3028 panic("mptable_lapic_enumerate mptable_map failed\n");
3030 KKASSERT(mpt.mp_fps != NULL);
3033 * Check for use of 'default' configuration
3035 if (mpt.mp_fps->mpfb1 != 0) {
3036 mptable_lapic_default();
3037 mptable_unmap(&mpt);
3042 KKASSERT(cth != NULL);
3044 /* Save local apic address */
3045 lapic_addr = (vm_offset_t)cth->apic_address;
3046 KKASSERT(lapic_addr != 0);
3049 * Find out how many CPUs do we have
3051 bzero(&arg1, sizeof(arg1));
3052 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3054 error = mptable_iterate_entries(cth,
3055 mptable_lapic_pass1_callback, &arg1);
3057 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3058 KKASSERT(arg1.cpu_count != 0);
3060 /* See if we need to fixup HT logical CPUs. */
3061 if (arg1.ht_fixup) {
3062 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3064 if (logical_cpus != 0)
3065 arg1.cpu_count *= logical_cpus;
3067 mp_naps = arg1.cpu_count;
3069 /* Qualify the numbers again, after possible HT fixup */
3070 if (mp_naps > MAXCPU) {
3071 kprintf("Warning: only using %d of %d available CPUs!\n",
3076 --mp_naps; /* subtract the BSP */
3079 * Link logical CPU id to local apic id
3081 bzero(&arg2, sizeof(arg2));
3083 arg2.logical_cpus = logical_cpus;
3085 error = mptable_iterate_entries(cth,
3086 mptable_lapic_pass2_callback, &arg2);
3088 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3089 KKASSERT(arg2.found_bsp);
3091 /* Map local apic */
3092 lapic_map(lapic_addr);
3094 mptable_unmap(&mpt);
3098 mptable_lapic_probe(struct lapic_enumerator *e)
3100 vm_paddr_t mpfps_paddr;
3102 mpfps_paddr = mptable_probe();
3103 if (mpfps_paddr == 0)
3106 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3110 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3112 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3113 .lapic_probe = mptable_lapic_probe,
3114 .lapic_enumerate = mptable_lapic_enumerate
3119 mptable_apic_register(void)
3121 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3123 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);