2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
41 * Routines to handle clock hardware.
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
52 #include "opt_clock.h"
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/eventhandler.h>
58 #include <sys/kernel.h>
63 #include <sys/sysctl.h>
65 #include <sys/systimer.h>
66 #include <sys/globaldata.h>
67 #include <sys/thread2.h>
68 #include <sys/systimer.h>
69 #include <sys/machintr.h>
71 #include <machine/clock.h>
72 #ifdef CLK_CALIBRATION_LOOP
74 #include <machine/cputypes.h>
75 #include <machine/frame.h>
76 #include <machine/ipl.h>
77 #include <machine/limits.h>
78 #include <machine/md_var.h>
79 #include <machine/psl.h>
80 #include <machine/segments.h>
81 #include <machine/smp.h>
82 #include <machine/specialreg.h>
84 #include <machine_base/icu/icu.h>
85 #include <bus/isa/isa.h>
86 #include <bus/isa/rtc.h>
87 #include <machine_base/isa/timerreg.h>
89 #include <machine_base/isa/intr_machdep.h>
91 #ifdef SMP /* APIC-IO */
92 /* The interrupt triggered by the 8254 (timer) chip */
94 static void setup_8254_mixed_mode (void);
96 static void i8254_restore(void);
97 static void resettodr_on_shutdown(void *arg __unused);
100 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
101 * can use a simple formula for leap years.
103 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
104 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
107 #define TIMER_FREQ 1193182
110 static uint8_t i8254_walltimer_sel;
111 static uint16_t i8254_walltimer_cntr;
113 int adjkerntz; /* local offset from GMT in seconds */
114 int disable_rtc_set; /* disable resettodr() if != 0 */
115 int statclock_disable = 1; /* we don't use the statclock right now */
117 int64_t tsc_frequency;
119 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
121 enum tstate { RELEASED, ACQUIRED };
122 enum tstate timer0_state;
123 enum tstate timer1_state;
124 enum tstate timer2_state;
126 static int beeping = 0;
127 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
128 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
129 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
130 static int rtc_loaded;
132 static int i8254_cputimer_div;
134 static int i8254_nointr;
135 static int i8254_intr_disable = 0;
136 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
138 static struct callout sysbeepstop_ch;
140 static sysclock_t i8254_cputimer_count(void);
141 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
142 static void i8254_cputimer_destruct(struct cputimer *cputimer);
144 static struct cputimer i8254_cputimer = {
145 SLIST_ENTRY_INITIALIZER,
149 i8254_cputimer_count,
150 cputimer_default_fromhz,
151 cputimer_default_fromus,
152 i8254_cputimer_construct,
153 i8254_cputimer_destruct,
158 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
159 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
160 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
162 static struct cputimer_intr i8254_cputimer_intr = {
164 .reload = i8254_intr_reload,
165 .enable = cputimer_intr_default_enable,
166 .config = i8254_intr_config,
167 .restart = cputimer_intr_default_restart,
168 .pmfixup = cputimer_intr_default_pmfixup,
169 .initclock = i8254_intr_initclock,
170 .next = SLIST_ENTRY_INITIALIZER,
172 .type = CPUTIMER_INTR_8254,
173 .prio = CPUTIMER_INTR_PRIO_8254,
174 .caps = CPUTIMER_INTR_CAP_PS
178 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
179 * counting as of this interrupt. We use timer1 in free-running mode (not
180 * generating any interrupts) as our main counter. Each cpu has timeouts
183 * This code is INTR_MPSAFE and may be called without the BGL held.
186 clkintr(void *dummy, void *frame_arg)
188 static sysclock_t sysclock_count; /* NOTE! Must be static */
189 struct globaldata *gd = mycpu;
191 struct globaldata *gscan;
196 * SWSTROBE mode is a one-shot, the timer is no longer running
201 * XXX the dispatcher needs work. right now we call systimer_intr()
202 * directly or via IPI for any cpu with systimers queued, which is
203 * usually *ALL* of them. We need to use the LAPIC timer for this.
205 sysclock_count = sys_cputimer->count();
207 for (n = 0; n < ncpus; ++n) {
208 gscan = globaldata_find(n);
209 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
212 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
215 systimer_intr(&sysclock_count, 0, frame_arg);
219 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
220 systimer_intr(&sysclock_count, 0, frame_arg);
229 acquire_timer2(int mode)
231 if (timer2_state != RELEASED)
233 timer2_state = ACQUIRED;
236 * This access to the timer registers is as atomic as possible
237 * because it is a single instruction. We could do better if we
240 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
247 if (timer2_state != ACQUIRED)
249 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
250 timer2_state = RELEASED;
255 * This routine receives statistical clock interrupts from the RTC.
256 * As explained above, these occur at 128 interrupts per second.
257 * When profiling, we receive interrupts at a rate of 1024 Hz.
259 * This does not actually add as much overhead as it sounds, because
260 * when the statistical clock is active, the hardclock driver no longer
261 * needs to keep (inaccurate) statistics on its own. This decouples
262 * statistics gathering from scheduling interrupts.
264 * The RTC chip requires that we read status register C (RTC_INTR)
265 * to acknowledge an interrupt, before it will generate the next one.
266 * Under high interrupt load, rtcintr() can be indefinitely delayed and
267 * the clock can tick immediately after the read from RTC_INTR. In this
268 * case, the mc146818A interrupt signal will not drop for long enough
269 * to register with the 8259 PIC. If an interrupt is missed, the stat
270 * clock will halt, considerably degrading system performance. This is
271 * why we use 'while' rather than a more straightforward 'if' below.
272 * Stat clock ticks can still be lost, causing minor loss of accuracy
273 * in the statistics, but the stat clock will no longer stop.
276 rtcintr(void *dummy, void *frame)
278 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
280 /* statclock(frame); no longer used */
287 DB_SHOW_COMMAND(rtc, rtc)
289 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
290 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
291 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
292 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
297 * Return the current cpu timer count as a 32 bit integer.
301 i8254_cputimer_count(void)
303 static __uint16_t cputimer_last;
308 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
309 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
310 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
311 count = -count; /* -> countup */
312 if (count < cputimer_last) /* rollover */
313 i8254_cputimer.base += 0x00010000;
314 ret = i8254_cputimer.base | count;
315 cputimer_last = count;
321 * This function is called whenever the system timebase changes, allowing
322 * us to calculate what is needed to convert a system timebase tick
323 * into an 8254 tick for the interrupt timer. If we can convert to a
324 * simple shift, multiplication, or division, we do so. Otherwise 64
325 * bit arithmatic is required every time the interrupt timer is reloaded.
328 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
334 * Will a simple divide do the trick?
336 div = (timer->freq + (cti->freq / 2)) / cti->freq;
337 freq = cti->freq * div;
339 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
340 i8254_cputimer_div = div;
342 i8254_cputimer_div = 0;
346 * Reload for the next timeout. It is possible for the reload value
347 * to be 0 or negative, indicating that an immediate timer interrupt
348 * is desired. For now make the minimum 2 ticks.
350 * We may have to convert from the system timebase to the 8254 timebase.
353 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
357 if (i8254_cputimer_div)
358 reload /= i8254_cputimer_div;
360 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
366 if (timer0_running) {
367 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
368 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
369 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
370 if (reload < count) {
371 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
372 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
373 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
378 reload = 0; /* full count */
379 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
380 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
381 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
387 * DELAY(usec) - Spin for the specified number of microseconds.
388 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
389 * but do a thread switch in the loop
391 * Relies on timer 1 counting down from (cputimer_freq / hz)
392 * Note: timer had better have been programmed before this is first used!
395 DODELAY(int n, int doswitch)
397 int delta, prev_tick, tick, ticks_left;
402 static int state = 0;
406 for (n1 = 1; n1 <= 10000000; n1 *= 10)
411 kprintf("DELAY(%d)...", n);
414 * Guard against the timer being uninitialized if we are called
415 * early for console i/o.
417 if (timer0_state == RELEASED)
421 * Read the counter first, so that the rest of the setup overhead is
422 * counted. Then calculate the number of hardware timer ticks
423 * required, rounding up to be sure we delay at least the requested
424 * number of microseconds.
426 prev_tick = sys_cputimer->count();
427 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
433 while (ticks_left > 0) {
434 tick = sys_cputimer->count();
438 delta = tick - prev_tick;
443 if (doswitch && ticks_left > 0)
449 kprintf(" %d calls to getit() at %d usec each\n",
450 getit_calls, (n + 5) / getit_calls);
455 * DELAY() never switches
464 CHECKTIMEOUT(TOTALDELAY *tdd)
469 if (tdd->started == 0) {
470 if (timer0_state == RELEASED)
472 tdd->last_clock = sys_cputimer->count();
476 delta = sys_cputimer->count() - tdd->last_clock;
477 us = (u_int64_t)delta * (u_int64_t)1000000 /
478 (u_int64_t)sys_cputimer->freq;
479 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
482 return (tdd->us < 0);
486 * DRIVERSLEEP() does not switch if called with a spinlock held or
487 * from a hard interrupt.
490 DRIVERSLEEP(int usec)
492 globaldata_t gd = mycpu;
494 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) {
502 sysbeepstop(void *chan)
504 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
510 sysbeep(int pitch, int period)
512 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
515 * Nobody else is using timer2, we do not need the clock lock
517 outb(TIMER_CNTR2, pitch);
518 outb(TIMER_CNTR2, (pitch>>8));
520 /* enable counter2 output to speaker */
521 outb(IO_PPI, inb(IO_PPI) | 3);
523 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
529 * RTC support routines
540 val = inb(IO_RTC + 1);
547 writertc(u_char reg, u_char val)
553 outb(IO_RTC + 1, val);
554 inb(0x84); /* XXX work around wrong order in rtcin() */
561 return(bcd2bin(rtcin(port)));
565 calibrate_clocks(void)
568 u_int count, prev_count, tot_count;
569 int sec, start_sec, timeout;
572 kprintf("Calibrating clock(s) ... ");
573 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
577 /* Read the mc146818A seconds counter. */
579 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
580 sec = rtcin(RTC_SEC);
587 /* Wait for the mC146818A seconds counter to change. */
590 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
591 sec = rtcin(RTC_SEC);
592 if (sec != start_sec)
599 /* Start keeping track of the i8254 counter. */
600 prev_count = sys_cputimer->count();
606 old_tsc = 0; /* shut up gcc */
609 * Wait for the mc146818A seconds counter to change. Read the i8254
610 * counter for each iteration since this is convenient and only
611 * costs a few usec of inaccuracy. The timing of the final reads
612 * of the counters almost matches the timing of the initial reads,
613 * so the main cause of inaccuracy is the varying latency from
614 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
615 * rtcin(RTC_SEC) that returns a changed seconds count. The
616 * maximum inaccuracy from this cause is < 10 usec on 486's.
620 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
621 sec = rtcin(RTC_SEC);
622 count = sys_cputimer->count();
623 tot_count += (int)(count - prev_count);
625 if (sec != start_sec)
632 * Read the cpu cycle counter. The timing considerations are
633 * similar to those for the i8254 clock.
636 tsc_frequency = rdtsc() - old_tsc;
640 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
641 kprintf("i8254 clock: %u Hz\n", tot_count);
645 kprintf("failed, using default i8254 clock of %u Hz\n",
646 i8254_cputimer.freq);
647 return (i8254_cputimer.freq);
653 timer0_state = ACQUIRED;
658 * Timer0 is our fine-grained variable clock interrupt
660 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
661 outb(TIMER_CNTR0, 2); /* lsb */
662 outb(TIMER_CNTR0, 0); /* msb */
666 cputimer_intr_register(&i8254_cputimer_intr);
667 cputimer_intr_select(&i8254_cputimer_intr, 0);
671 * Timer1 or timer2 is our free-running clock, but only if another
672 * has not been selected.
674 cputimer_register(&i8254_cputimer);
675 cputimer_select(&i8254_cputimer, 0);
679 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
684 * Should we use timer 1 or timer 2 ?
687 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
688 if (which != 1 && which != 2)
693 timer->name = "i8254_timer1";
694 timer->type = CPUTIMER_8254_SEL1;
695 i8254_walltimer_sel = TIMER_SEL1;
696 i8254_walltimer_cntr = TIMER_CNTR1;
697 timer1_state = ACQUIRED;
700 timer->name = "i8254_timer2";
701 timer->type = CPUTIMER_8254_SEL2;
702 i8254_walltimer_sel = TIMER_SEL2;
703 i8254_walltimer_cntr = TIMER_CNTR2;
704 timer2_state = ACQUIRED;
708 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
711 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
712 outb(i8254_walltimer_cntr, 0); /* lsb */
713 outb(i8254_walltimer_cntr, 0); /* msb */
714 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
719 i8254_cputimer_destruct(struct cputimer *timer)
721 switch(timer->type) {
722 case CPUTIMER_8254_SEL1:
723 timer1_state = RELEASED;
725 case CPUTIMER_8254_SEL2:
726 timer2_state = RELEASED;
737 /* Restore all of the RTC's "status" (actually, control) registers. */
738 writertc(RTC_STATUSB, RTCSB_24HR);
739 writertc(RTC_STATUSA, rtc_statusa);
740 writertc(RTC_STATUSB, rtc_statusb);
744 * Restore all the timers.
746 * This function is called to resynchronize our core timekeeping after a
747 * long halt, e.g. from apm_default_resume() and friends. It is also
748 * called if after a BIOS call we have detected munging of the 8254.
749 * It is necessary because cputimer_count() counter's delta may have grown
750 * too large for nanouptime() and friends to handle, or (in the case of 8254
751 * munging) might cause the SYSTIMER code to prematurely trigger.
757 i8254_restore(); /* restore timer_freq and hz */
758 rtc_restore(); /* reenable RTC interrupts */
763 * Initialize 8254 timer 0 early so that it can be used in DELAY().
771 * Can we use the TSC?
773 if (cpu_feature & CPUID_TSC)
779 * Initial RTC state, don't do anything unexpected
781 writertc(RTC_STATUSA, rtc_statusa);
782 writertc(RTC_STATUSB, RTCSB_24HR);
785 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
786 * generate an interrupt, which we will ignore for now.
788 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
789 * (so it counts a full 2^16 and repeats). We will use this timer
793 freq = calibrate_clocks();
794 #ifdef CLK_CALIBRATION_LOOP
797 "Press a key on the console to abort clock calibration\n");
798 while (cncheckc() == -1)
804 * Use the calibrated i8254 frequency if it seems reasonable.
805 * Otherwise use the default, and don't use the calibrated i586
808 delta = freq > i8254_cputimer.freq ?
809 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
810 if (delta < i8254_cputimer.freq / 100) {
811 #ifndef CLK_USE_I8254_CALIBRATION
814 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
815 freq = i8254_cputimer.freq;
819 * Interrupt timer's freq must be adjusted
820 * before we change the cuptimer's frequency.
822 i8254_cputimer_intr.freq = freq;
823 cputimer_set_frequency(&i8254_cputimer, freq);
827 "%d Hz differs from default of %d Hz by more than 1%%\n",
828 freq, i8254_cputimer.freq);
832 #ifndef CLK_USE_TSC_CALIBRATION
833 if (tsc_frequency != 0) {
836 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
840 if (tsc_present && tsc_frequency == 0) {
842 * Calibration of the i586 clock relative to the mc146818A
843 * clock failed. Do a less accurate calibration relative
844 * to the i8254 clock.
846 u_int64_t old_tsc = rdtsc();
849 tsc_frequency = rdtsc() - old_tsc;
850 #ifdef CLK_USE_TSC_CALIBRATION
852 kprintf("TSC clock: %llu Hz (Method B)\n",
858 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
862 * We can not use the TSC in SMP mode, until we figure out a
863 * cheap (impossible), reliable and precise (yeah right!) way
864 * to synchronize the TSCs of all the CPUs.
865 * Curse Intel for leaving the counter out of the I/O APIC.
870 * We can not use the TSC if we support APM. Precise timekeeping
871 * on an APM'ed machine is at best a fools pursuit, since
872 * any and all of the time spent in various SMM code can't
873 * be reliably accounted for. Reading the RTC is your only
874 * source of reliable time info. The i8254 looses too of course
875 * but we need to have some kind of time...
876 * We don't know at this point whether APM is going to be used
877 * or not, nor when it might be activated. Play it safe.
880 #endif /* NAPM > 0 */
882 #endif /* !defined(SMP) */
886 * Sync the time of day back to the RTC on shutdown, but only if
887 * we have already loaded it and have not crashed.
890 resettodr_on_shutdown(void *arg __unused)
892 if (rtc_loaded && panicstr == NULL) {
898 * Initialize the time of day register, based on the time base which is, e.g.
902 inittodr(time_t base)
904 unsigned long sec, days;
915 /* Look if we have a RTC present and the time is valid */
916 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
919 /* wait for time update to complete */
920 /* If RTCSA_TUP is zero, we have at least 244us before next update */
922 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
928 #ifdef USE_RTC_CENTURY
929 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
931 year = readrtc(RTC_YEAR) + 1900;
939 month = readrtc(RTC_MONTH);
940 for (m = 1; m < month; m++)
941 days += daysinmonth[m-1];
942 if ((month > 2) && LEAPYEAR(year))
944 days += readrtc(RTC_DAY) - 1;
945 for (y = 1970; y < year; y++)
946 days += DAYSPERYEAR + LEAPYEAR(y);
947 sec = ((( days * 24 +
948 readrtc(RTC_HRS)) * 60 +
949 readrtc(RTC_MIN)) * 60 +
951 /* sec now contains the number of seconds, since Jan 1 1970,
952 in the local time zone */
954 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
956 y = time_second - sec;
957 if (y <= -2 || y >= 2) {
958 /* badly off, adjust it */
968 kprintf("Invalid time in real time clock.\n");
969 kprintf("Check and reset the date immediately!\n");
973 * Write system time back to RTC
990 /* Disable RTC updates and interrupts. */
991 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
993 /* Calculate local time to put in RTC */
995 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
997 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
998 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
999 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
1001 /* We have now the days since 01-01-1970 in tm */
1002 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
1003 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
1005 y++, m = DAYSPERYEAR + LEAPYEAR(y))
1008 /* Now we have the years in y and the day-of-the-year in tm */
1009 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
1010 #ifdef USE_RTC_CENTURY
1011 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
1013 for (m = 0; ; m++) {
1016 ml = daysinmonth[m];
1017 if (m == 1 && LEAPYEAR(y))
1024 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
1025 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
1027 /* Reenable RTC updates and interrupts. */
1028 writertc(RTC_STATUSB, rtc_statusb);
1034 * Start both clocks running. DragonFly note: the stat clock is no longer
1035 * used. Instead, 8254 based systimers are used for all major clock
1036 * interrupts. statclock_disable is set by default.
1039 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1042 #ifdef SMP /* APIC-IO */
1043 int apic_8254_trial;
1047 callout_init(&sysbeepstop_ch);
1049 if (!selected && i8254_intr_disable) {
1050 i8254_nointr = 1; /* don't try to register again */
1051 cputimer_intr_deregister(cti);
1055 if (statclock_disable) {
1057 * The stat interrupt mask is different without the
1058 * statistics clock. Also, don't set the interrupt
1059 * flag which would normally cause the RTC to generate
1062 rtc_statusb = RTCSB_24HR;
1064 /* Setting stathz to nonzero early helps avoid races. */
1065 stathz = RTC_NOPROFRATE;
1066 profhz = RTC_PROFRATE;
1069 /* Finish initializing 8253 timer 0. */
1070 #ifdef SMP /* APIC-IO */
1071 if (apic_io_enable) {
1072 apic_8254_intr = isa_apic_irq(0);
1073 apic_8254_trial = 0;
1074 if (apic_8254_intr >= 0 ) {
1075 if (apic_int_type(0, 0) == 3)
1076 apic_8254_trial = 1;
1078 /* look for ExtInt on pin 0 */
1079 if (apic_int_type(0, 0) == 3) {
1080 apic_8254_intr = apic_irq(0, 0);
1081 setup_8254_mixed_mode();
1083 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1086 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1088 INTR_EXCL | INTR_CLOCK |
1089 INTR_NOPOLL | INTR_MPSAFE |
1091 machintr_intren(apic_8254_intr);
1094 register_int(0, clkintr, NULL, "clk", NULL,
1095 INTR_EXCL | INTR_CLOCK |
1096 INTR_NOPOLL | INTR_MPSAFE |
1098 machintr_intren(ICU_IRQ0);
1099 #ifdef SMP /* APIC-IO */
1103 /* Initialize RTC. */
1104 writertc(RTC_STATUSA, rtc_statusa);
1105 writertc(RTC_STATUSB, RTCSB_24HR);
1107 if (statclock_disable == 0) {
1108 diag = rtcin(RTC_DIAG);
1110 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1112 #ifdef SMP /* APIC-IO */
1113 if (apic_io_enable) {
1114 if (isa_apic_irq(8) != 8)
1115 panic("APIC RTC != 8");
1119 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL,
1120 INTR_EXCL | INTR_CLOCK | INTR_NOPOLL |
1124 writertc(RTC_STATUSB, rtc_statusb);
1127 #ifdef SMP /* APIC-IO */
1128 if (apic_io_enable) {
1129 if (apic_8254_trial) {
1134 * Following code assumes the 8254 is the cpu timer,
1135 * so make sure it is.
1137 KKASSERT(sys_cputimer == &i8254_cputimer);
1138 KKASSERT(cti == &i8254_cputimer_intr);
1140 lastcnt = get_interrupt_counter(apic_8254_intr);
1143 * Force an 8254 Timer0 interrupt and wait 1/100s for
1144 * it to happen, then see if we got it.
1146 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1147 i8254_intr_reload(cti, 2);
1148 base = sys_cputimer->count();
1149 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1151 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
1153 * The MP table is broken.
1154 * The 8254 was not connected to the specified pin
1156 * Workaround: Limited variant of mixed mode.
1158 machintr_intrdis(apic_8254_intr);
1159 unregister_int(clkdesc);
1160 kprintf("APIC_IO: Broken MP table detected: "
1161 "8254 is not connected to "
1162 "IOAPIC #%d intpin %d\n",
1163 int_to_apicintpin[apic_8254_intr].ioapic,
1164 int_to_apicintpin[apic_8254_intr].int_pin);
1166 * Revoke current ISA IRQ 0 assignment and
1167 * configure a fallback interrupt routing from
1168 * the 8254 Timer via the 8259 PIC to the
1169 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1170 * We reuse the low level interrupt handler number.
1172 if (apic_irq(0, 0) < 0) {
1173 revoke_apic_irq(apic_8254_intr);
1174 assign_apic_irq(0, 0, apic_8254_intr);
1176 apic_8254_intr = apic_irq(0, 0);
1177 setup_8254_mixed_mode();
1178 register_int(apic_8254_intr, clkintr, NULL, "clk",
1180 INTR_EXCL | INTR_CLOCK |
1181 INTR_NOPOLL | INTR_MPSAFE |
1183 machintr_intren(apic_8254_intr);
1186 if (apic_int_type(0, 0) != 3 ||
1187 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1188 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1189 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1190 int_to_apicintpin[apic_8254_intr].ioapic,
1191 int_to_apicintpin[apic_8254_intr].int_pin);
1194 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1200 #ifdef SMP /* APIC-IO */
1203 setup_8254_mixed_mode(void)
1206 * Allow 8254 timer to INTerrupt 8259:
1207 * re-initialize master 8259:
1208 * reset; prog 4 bytes, single ICU, edge triggered
1210 outb(IO_ICU1, 0x13);
1211 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1212 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1213 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1214 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1216 /* program IO APIC for type 3 INT on INT0 */
1217 if (ext_int_setup(0, 0) < 0)
1218 panic("8254 redirect via APIC pin0 impossible!");
1223 setstatclockrate(int newhz)
1225 if (newhz == RTC_PROFRATE)
1226 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1228 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1229 writertc(RTC_STATUSA, rtc_statusa);
1234 tsc_get_timecount(struct timecounter *tc)
1240 #ifdef KERN_TIMESTAMP
1241 #define KERN_TIMESTAMP_SIZE 16384
1242 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1243 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1244 sizeof(tsc), "LU", "Kernel timestamps");
1250 tsc[i] = (u_int32_t)rdtsc();
1253 if (i >= KERN_TIMESTAMP_SIZE)
1255 tsc[i] = 0; /* mark last entry */
1257 #endif /* KERN_TIMESTAMP */
1264 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1271 if (sys_cputimer == &i8254_cputimer)
1272 count = sys_cputimer->count();
1280 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1281 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1284 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1285 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1287 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1288 0, 0, hw_i8254_timestamp, "A", "");
1290 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1291 &tsc_present, 0, "TSC Available");
1292 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1293 &tsc_frequency, 0, "TSC Frequency");