2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
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9 * modification, are permitted provided that the following conditions
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13 * 2. Redistributions in binary form must reproduce the above copyright
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17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
37 * $FreeBSD: src/sys/i386/isa/isa_dma.c,v 1.4.2.1 2000/08/08 19:49:53 peter Exp $
38 * $DragonFly: src/sys/bus/isa/amd64/isa_dma.c,v 1.1 2008/08/02 05:22:17 dillon Exp $
42 * code to manage AT bus
44 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com):
45 * Fixed uninitialized variable problem and added code to deal
46 * with DMA page boundaries in isa_dmarangecheck(). Fixed word
47 * mode DMA count compution and reorganized DMA setup code in
51 #include <sys/param.h>
52 #include <sys/systm.h>
54 #include <sys/kernel.h>
55 #include <sys/malloc.h>
58 #include <vm/vm_param.h>
61 #include <machine_base/isa/ic/i8237.h>
62 #include <machine/pmap.h>
63 #include <bus/isa/isavar.h>
66 ** Register definitions for DMA controller 1 (channels 0..3):
68 #define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
69 #define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
70 #define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
71 #define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
74 ** Register definitions for DMA controller 2 (channels 4..7):
76 #define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
77 #define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
78 #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
79 #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
81 static int isa_dmarangecheck (caddr_t va, u_int length, int chan);
83 static caddr_t dma_bouncebuf[8];
84 static u_int dma_bouncebufsize[8];
85 static u_int8_t dma_bounced = 0;
86 static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */
87 static u_int8_t dma_inuse = 0; /* User for acquire/release */
88 static u_int8_t dma_auto_mode = 0;
90 #define VALID_DMA_MASK (7)
92 /* high byte of address is stored in this port for i-th dma channel */
93 static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
96 * Setup a DMA channel's bounce buffer.
99 isa_dmainit(int chan, u_int bouncebufsize)
104 if (chan & ~VALID_DMA_MASK)
105 panic("isa_dmainit: channel out of range");
107 if (dma_bouncebuf[chan] != NULL)
108 panic("isa_dmainit: impossible request");
111 dma_bouncebufsize[chan] = bouncebufsize;
113 /* Try malloc() first. It works better if it works. */
114 buf = kmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT);
116 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) {
117 dma_bouncebuf[chan] = buf;
120 kfree(buf, M_DEVBUF);
122 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful,
123 1ul, chan & 4 ? 0x20000ul : 0x10000ul);
125 kprintf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize);
127 dma_bouncebuf[chan] = buf;
131 * Register a DMA channel's usage. Usually called from a device driver
132 * in open() or during its initialization.
135 isa_dma_acquire(int chan)
138 if (chan & ~VALID_DMA_MASK)
139 panic("isa_dma_acquire: channel out of range");
142 if (dma_inuse & (1 << chan)) {
143 kprintf("isa_dma_acquire: channel %d already in use\n", chan);
146 dma_inuse |= (1 << chan);
147 dma_auto_mode &= ~(1 << chan);
153 * Unregister a DMA channel's usage. Usually called from a device driver
154 * during close() or during its shutdown.
157 isa_dma_release(int chan)
160 if (chan & ~VALID_DMA_MASK)
161 panic("isa_dma_release: channel out of range");
163 if ((dma_inuse & (1 << chan)) == 0)
164 kprintf("isa_dma_release: channel %d not in use\n", chan);
167 if (dma_busy & (1 << chan)) {
168 dma_busy &= ~(1 << chan);
170 * XXX We should also do "dma_bounced &= (1 << chan);"
171 * because we are acting on behalf of isa_dmadone() which
172 * was not called to end the last DMA operation. This does
173 * not matter now, but it may in the future.
177 dma_inuse &= ~(1 << chan);
178 dma_auto_mode &= ~(1 << chan);
182 * isa_dmacascade(): program 8237 DMA controller channel to accept
183 * external dma control by a board.
186 isa_dmacascade(int chan)
189 if (chan & ~VALID_DMA_MASK)
190 panic("isa_dmacascade: channel out of range");
193 /* set dma channel mode, and set dma channel mode */
194 if ((chan & 4) == 0) {
195 outb(DMA1_MODE, DMA37MD_CASCADE | chan);
196 outb(DMA1_SMSK, chan);
198 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
199 outb(DMA2_SMSK, chan & 3);
204 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
205 * problems by using a bounce buffer.
208 isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan)
215 if (chan & ~VALID_DMA_MASK)
216 panic("isa_dmastart: channel out of range");
218 if ((chan < 4 && nbytes > (1<<16))
219 || (chan >= 4 && (nbytes > (1<<17) || (u_int)(uintptr_t)addr & 1)))
220 panic("isa_dmastart: impossible request");
222 if ((dma_inuse & (1 << chan)) == 0)
223 kprintf("isa_dmastart: channel %d not acquired\n", chan);
228 * XXX This should be checked, but drivers like ad1848 only call
229 * isa_dmastart() once because they use Auto DMA mode. If we
230 * leave this in, drivers that do this will print this continuously.
232 if (dma_busy & (1 << chan))
233 kprintf("isa_dmastart: channel %d busy\n", chan);
236 dma_busy |= (1 << chan);
238 if (isa_dmarangecheck(addr, nbytes, chan)) {
239 if (dma_bouncebuf[chan] == NULL
240 || dma_bouncebufsize[chan] < nbytes)
241 panic("isa_dmastart: bad bounce buffer");
242 dma_bounced |= (1 << chan);
243 newaddr = dma_bouncebuf[chan];
245 /* copy bounce buffer on write */
246 if (flags & ISADMA_WRITE)
247 bcopy(addr, newaddr, nbytes);
251 /* translate to physical */
252 phys = pmap_extract(&kernel_pmap, (vm_offset_t)addr);
254 if (flags & ISADMA_RAW) {
255 dma_auto_mode |= (1 << chan);
257 dma_auto_mode &= ~(1 << chan);
260 if ((chan & 4) == 0) {
262 * Program one of DMA channels 0..3. These are
263 * byte mode channels.
265 /* set dma channel mode, and reset address ff */
267 /* If ISADMA_RAW flag is set, then use autoinitialise mode */
268 if (flags & ISADMA_RAW) {
269 if (flags & ISADMA_READ)
270 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan);
272 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan);
275 if (flags & ISADMA_READ)
276 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
278 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
281 /* send start address */
282 waport = DMA1_CHN(chan);
284 outb(waport, phys>>8);
285 outb(dmapageport[chan], phys>>16);
288 outb(waport + 1, --nbytes);
289 outb(waport + 1, nbytes>>8);
292 outb(DMA1_SMSK, chan);
295 * Program one of DMA channels 4..7. These are
296 * word mode channels.
298 /* set dma channel mode, and reset address ff */
300 /* If ISADMA_RAW flag is set, then use autoinitialise mode */
301 if (flags & ISADMA_RAW) {
302 if (flags & ISADMA_READ)
303 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3));
305 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3));
308 if (flags & ISADMA_READ)
309 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
311 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
314 /* send start address */
315 waport = DMA2_CHN(chan - 4);
316 outb(waport, phys>>1);
317 outb(waport, phys>>9);
318 outb(dmapageport[chan], phys>>16);
322 outb(waport + 2, --nbytes);
323 outb(waport + 2, nbytes>>8);
326 outb(DMA2_SMSK, chan & 3);
331 isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
334 if (chan & ~VALID_DMA_MASK)
335 panic("isa_dmadone: channel out of range");
337 if ((dma_inuse & (1 << chan)) == 0)
338 kprintf("isa_dmadone: channel %d not acquired\n", chan);
341 if (((dma_busy & (1 << chan)) == 0) &&
342 (dma_auto_mode & (1 << chan)) == 0 )
343 kprintf("isa_dmadone: channel %d not busy\n", chan);
345 if ((dma_auto_mode & (1 << chan)) == 0)
346 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4);
348 if (dma_bounced & (1 << chan)) {
349 /* copy bounce buffer on read */
350 if (flags & ISADMA_READ)
351 bcopy(dma_bouncebuf[chan], addr, nbytes);
353 dma_bounced &= ~(1 << chan);
355 dma_busy &= ~(1 << chan);
359 * Check for problems with the address range of a DMA transfer
360 * (non-contiguous physical pages, outside of bus address space,
361 * crossing DMA page boundaries).
362 * Return true if special handling needed.
366 isa_dmarangecheck(caddr_t va, u_int length, int chan)
368 vm_paddr_t phys, priorpage = 0;
370 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
372 endva = (vm_offset_t)round_page((vm_offset_t)va + length);
373 for (; va < (caddr_t) endva ; va += PAGE_SIZE) {
374 phys = trunc_page(pmap_extract(&kernel_pmap, (vm_offset_t)va));
375 #define ISARAM_END RAM_END
377 panic("isa_dmacheck: no physical page present");
378 if (phys >= ISARAM_END)
381 if (priorpage + PAGE_SIZE != phys)
383 /* check if crossing a DMA page boundary */
384 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
393 * Query the progress of a transfer on a DMA channel.
395 * To avoid having to interrupt a transfer in progress, we sample
396 * each of the high and low databytes twice, and apply the following
397 * logic to determine the correct count.
399 * Reads are performed with interrupts disabled, thus it is to be
400 * expected that the time between reads is very small. At most
401 * one rollover in the low count byte can be expected within the
402 * four reads that are performed.
404 * There are three gaps in which a rollover can occur :
414 * If a rollover occurs in gap1 or gap2, the low2 value will be
415 * greater than the low1 value. In this case, low2 and high2 are a
416 * corresponding pair.
418 * In any other case, low1 and high1 can be considered to be correct.
420 * The function returns the number of bytes remaining in the transfer,
421 * or -1 if the channel requested is not active.
425 isa_dmastatus(int chan)
429 u_long low1, high1, low2, high2;
431 /* channel active? */
432 if ((dma_inuse & (1 << chan)) == 0) {
433 kprintf("isa_dmastatus: channel %d not active\n", chan);
438 if (((dma_busy & (1 << chan)) == 0) &&
439 (dma_auto_mode & (1 << chan)) == 0 ) {
440 kprintf("chan %d not busy\n", chan);
443 if (chan < 4) { /* low DMA controller */
445 waport = DMA1_CHN(chan) + 1;
446 } else { /* high DMA controller */
448 waport = DMA2_CHN(chan - 4) + 2;
451 cpu_disable_intr(); /* YYY *//* no interrupts Mr Jones! */
452 outb(ffport, 0); /* clear register LSB flipflop */
455 outb(ffport, 0); /* clear again */
458 cpu_enable_intr(); /* enable interrupts again */
461 * Now decide if a wrap has tried to skew our results.
462 * Note that after TC, the count will read 0xffff, while we want
463 * to return zero, so we add and then mask to compensate.
466 cnt = (low1 + (high1 << 8) + 1) & 0xffff;
468 cnt = (low2 + (high2 << 8) + 1) & 0xffff;
471 if (chan >= 4) /* high channels move words */
477 * Stop a DMA transfer currently in progress.
480 isa_dmastop(int chan)
482 if ((dma_inuse & (1 << chan)) == 0)
483 kprintf("isa_dmastop: channel %d not acquired\n", chan);
485 if (((dma_busy & (1 << chan)) == 0) &&
486 ((dma_auto_mode & (1 << chan)) == 0)) {
487 kprintf("chan %d not busy\n", chan);
491 if ((chan & 4) == 0) {
492 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */);
494 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */);
496 return(isa_dmastatus(chan));
500 isa_dmabp(struct buf *bp)
504 KKASSERT(bp->b_cmd != BUF_CMD_DONE);
505 if (bp->b_flags & B_RAW)
507 if (bp->b_cmd == BUF_CMD_READ) {
508 flags |= ISADMA_READ;
510 /* BUF_CMD_WRITE, BUF_CMD_FORMAT */
511 flags |= ISADMA_WRITE;