3 * ===================================
4 * HARP | Host ATM Research Platform
5 * ===================================
8 * This Host ATM Research Platform ("HARP") file (the "Software") is
9 * made available by Network Computing Services, Inc. ("NetworkCS")
10 * "AS IS". NetworkCS does not provide maintenance, improvements or
11 * support of any kind.
13 * NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
14 * INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
15 * AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
16 * SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
17 * In no event shall NetworkCS be responsible for any damages, including
18 * but not limited to consequential damages, arising from or relating to
19 * any use of the Software or related support.
21 * Copyright 1994-1998 Network Computing Services, Inc.
23 * Copies of this Software may be made, however, the above copyright
24 * notice must be reproduced on all copies.
26 * @(#) $FreeBSD: src/sys/dev/hea/eni_suni.h,v 1.2 1999/08/28 00:41:46 peter Exp $
27 * @(#) $DragonFly: src/sys/dev/atm/hea/eni_suni.h,v 1.2 2003/06/17 04:28:26 dillon Exp $
32 * Efficient ENI Adapter Support
33 * -----------------------------
35 * Defines for SUNI chip
39 #ifndef _ENI_ENI_SUNI_H
40 #define _ENI_ENI_SUNI_H
43 * Interrupt bits in SUNI Master Interrupt Status Reg
45 #define SUNI_RSOPI 0x01
46 #define SUNI_RLOPI 0x02
47 #define SUNI_RPOPI 0x04
48 #define SUNI_RACPI 0x08
49 #define SUNI_TACPI 0x10
50 #define SUNI_RDOOLI 0x20
51 #define SUNI_LCDI 0x40
52 #define SUNI_TROOLI 0x80
55 * SUNI Register numbers
57 #define SUNI_MASTER_REG 0x00 /* Master reset and ID */
58 #define SUNI_IS_REG 0x02 /* Master Interrupt Status */
59 #define SUNI_CLOCK_REG 0x06 /* Clock synth/control/status */
60 #define SUNI_RSOP_REG 0x10 /* RSOP control/Interrupt Status */
61 #define SUNI_SECT_BIP_REG 0x12
62 #define SUNI_RLOP_REG 0x18 /* RLOP control/Interrupt Status */
63 #define SUNI_LINE_BIP_REG 0x1A
64 #define SUNI_LINE_FEBE_REG 0x1D
65 #define SUNI_RPOP_IS_REG 0x31 /* RPOP Interrupt Status */
66 #define SUNI_PATH_BIP_REG 0x38
67 #define SUNI_PATH_FEBE_REG 0x3A
68 #define SUNI_RACP_REG 0x50 /* RACP control/status */
69 #define SUNI_HECS_REG 0x54
70 #define SUNI_UHECS_REG 0x55
71 #define SUNI_TACP_REG 0x60 /* TACP control/status */
74 * Delay timer to allow SUNI statistic registers to load
78 #endif /* _ENI_ENI_SUNI_H */