2 * Copyright (c) 2004, Joerg Sonnenberger <joerg@bec.de>
4 * Copyright (c) 1994,1995 Stefan Esser. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $DragonFly: src/sys/bus/pci/pci_pcib.c,v 1.5 2005/10/30 04:41:10 dillon Exp $
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
38 #include <sys/systm.h>
40 #include <machine/resource.h>
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
45 #include "pcib_private.h"
47 static devclass_t pcib_devclass;
50 * Attach a pci bus device to a motherboard or pci-to-pci bridge bus.
51 * Due to probe recursion it is possible for pci-to-pci bridges (such as
52 * on the DELL2550) to attach before all the motherboard bridges have
53 * attached. We must call device_add_child() with the secondary id
54 * rather then -1 in order to ensure that we do not accidently use
55 * a motherboard PCI id, otherwise the device probe will believe that
56 * the later motherboard bridge bus has already been probed and refuse
57 * to probe it. The result: disappearing busses!
59 * Bridges will cause recursions or duplicate attach attempts. If
60 * we have already attached this bus we don't do it again!
62 * NOTE THE DEVICE TOPOLOGY!
64 * [pcibX]->[pciX]->[pciX.Y]
67 * When attaching a new bus device note that the PCI methods are
68 * based in the parent device, but the device ivars for those methods
69 * are based in our sub-device. The PCI accessor functions all assume
70 * you are passing-in the sub-device.
73 pcib_attach_common(device_t dev)
75 struct pcib_softc *sc;
78 sc = device_get_softc(dev);
82 * Get current bridge configuration.
84 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
85 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
86 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
87 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
88 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
89 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
92 * Determine current I/O decode.
94 if (sc->command & PCIM_CMD_PORTEN) {
95 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
96 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
97 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
98 pci_read_config(dev, PCIR_IOBASEL_1, 1));
100 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
103 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
104 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
105 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
106 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
108 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
113 * Determine current memory decode.
115 if (sc->command & PCIM_CMD_MEMEN) {
116 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
117 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
118 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
119 pci_read_config(dev, PCIR_PMBASEL_1, 2));
120 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
121 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
127 switch (pci_get_devid(dev)) {
128 case 0x12258086: /* Intel 82454KX/GX (Orion) */
132 supbus = pci_read_config(dev, 0x41, 1);
133 if (supbus != 0xff) {
134 sc->secbus = supbus + 1;
135 sc->subbus = supbus + 1;
141 * The i82380FB mobile docking controller is a PCI-PCI bridge,
142 * and it is a subtractive bridge. However, the ProgIf is wrong
143 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
144 * happen. There's also a Toshiba bridge that behaves this
147 case 0x124b8086: /* Intel 82380FB Mobile */
148 case 0x060513d7: /* Toshiba ???? */
149 sc->flags |= PCIB_SUBTRACTIVE;
154 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
155 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
156 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
157 * This means they act as if they were subtractively decoding
158 * bridges and pass all transactions. Mark them and real ProgIf 1
159 * parts as subtractive.
161 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
162 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
163 sc->flags |= PCIB_SUBTRACTIVE;
166 device_printf(dev, " secondary bus %d\n", sc->secbus);
167 device_printf(dev, " subordinate bus %d\n", sc->subbus);
168 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
169 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
170 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
171 if (sc->flags & PCIB_SUBTRACTIVE)
172 device_printf(dev, " Subtractively decoded bridge.\n");
176 * XXX If the secondary bus number is zero, we should assign a bus number
177 * since the BIOS hasn't, then initialise the bridge.
181 * XXX If the subordinate bus number is less than the secondary bus number,
182 * we should pick a better value. One sensible alternative would be to
183 * pick 255; the only tradeoff here is that configuration transactions
184 * would be more widely routed than absolutely necessary.
189 * Called with the bridge candidate, which is under a PCI slot device.
190 * Note that the ivars are stored in the candidate.
193 pci_match_bridge(device_t dev)
195 switch (pci_get_devid(dev)) {
196 /* Intel -- vendor 0x8086 */
198 return ("Intel 82443LX (440 LX) PCI-PCI (AGP) bridge");
200 return ("Intel 82443BX (440 BX) PCI-PCI (AGP) bridge");
202 return ("Intel 82443GX (440 GX) PCI-PCI (AGP) bridge");
204 return ("Intel 82454NX PCI Expander Bridge");
206 return ("Intel 82801BA/BAM (ICH2) PCI-PCI (AGP) bridge");
208 return ("Intel 82380FB mobile PCI to PCI bridge");
210 return ("Intel 82801AA (ICH) Hub to PCI bridge");
212 return ("Intel 82801AB (ICH0) Hub to PCI bridge");
214 return ("Intel 82801BA/CA/DB/EB/FB (ICH2/3/4/5/6) Hub to PCI bridge");
216 return ("Intel 82845 PCI-PCI (AGP) bridge");
218 /* VLSI -- vendor 0x1004 */
220 return ("VLSI 82C534 Eagle II PCI Bus bridge");
222 return ("VLSI 82C538 Eagle II PCI Docking bridge");
224 /* VIA Technologies -- vendor 0x1106 */
226 return ("VIA 8363 (Apollo KT133) PCI-PCI (AGP) bridge");
228 return ("VIA 82C598MVP (Apollo MVP3) PCI-PCI (AGP) bridge");
229 /* Exclude the ACPI function of VT82Cxxx series */
235 /* AcerLabs -- vendor 0x10b9 */
236 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
237 /* id is '10b9" but the register always shows "10b9". -Foxfair */
239 return ("AcerLabs M5247 PCI-PCI(AGP Supported) bridge");
240 case 0x524310b9:/* 5243 seems like 5247, need more info to divide*/
241 return ("AcerLabs M5243 PCI-PCI bridge");
243 /* AMD -- vendor 0x1022 */
245 return ("AMD-751 PCI-PCI (1x/2x AGP) bridge");
247 return ("AMD-761 PCI-PCI (4x AGP) bridge");
249 /* DEC -- vendor 0x1011 */
251 return ("DEC 21050 PCI-PCI bridge");
253 return ("DEC 21052 PCI-PCI bridge");
255 return ("DEC 21150 PCI-PCI bridge");
257 return ("DEC 21152 PCI-PCI bridge");
259 return ("DEC 21153 PCI-PCI bridge");
261 return ("DEC 21154 PCI-PCI bridge");
263 /* NVIDIA -- vendor 0x10de */
266 return ("NVIDIA nForce2 PCI-PCI bridge");
270 return ("IBM 82351 PCI-PCI bridge");
271 /* UMC United Microelectronics 0x1060 */
273 return ("UMC UM8881 HB4 486 PCI Chipset");
276 if (pci_get_class(dev) == PCIC_BRIDGE
277 && pci_get_subclass(dev) == PCIS_BRIDGE_PCI) {
278 return pci_bridge_type(dev);
285 * bus/pci/i386/pcibus.c added "pcib" devices under "pci" (slot) devices,
286 * causing us to probe and attach here.
288 * Note that the parent "pci" device has stored ivars in our device. We
289 * are both a "pci" device and potentially a "pcib" device.
292 pcib_probe(device_t dev)
296 desc = pci_match_bridge(dev);
298 device_set_desc_copy(dev, desc);
306 * Note that the "pci" device ivars are stored in the ivar data field
307 * for our device. The "pcib" device ivars are stored in the softc
311 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
313 struct pcib_softc *sc = device_get_softc(dev);
317 *result = sc->secbus;
324 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
326 struct pcib_softc *sc = device_get_softc(dev);
337 pcib_attach(device_t dev)
339 struct pcib_softc *sc;
341 pcib_attach_common(dev);
342 sc = device_get_softc(dev);
343 /*chipset_attach(dev, device_get_unit(dev));*/
346 * The pcib unit is not really under our control because
347 * we have are not (XXX) using the identify interface to
348 * assign the bridge driver, instead letting subr_bus do
349 * it via the probe mechanism. However, we *do* directly
350 * create the "pci" children and we can control the unit
351 * number we assign for those. We assign the secondary bus
352 * id as the unit number.
354 if (sc->secbus != 0) {
355 if (devclass_find_unit("pci", sc->secbus)) {
356 device_printf(dev, "Duplicate secondary bus %d, "
357 "cannot attach bridge\n",
361 device_add_child(dev, "pci", sc->secbus);
362 bus_generic_attach(dev);
369 * Is the prefetch window open (eg, can we allocate memory in it?)
372 pcib_is_prefetch_open(struct pcib_softc *sc)
374 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
378 * Is the nonprefetch window open (eg, can we allocate memory in it?)
381 pcib_is_nonprefetch_open(struct pcib_softc *sc)
383 return (sc->membase > 0 && sc->membase < sc->memlimit);
387 * Is the io window open (eg, can we allocate ports in it?)
390 pcib_is_io_open(struct pcib_softc *sc)
392 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
396 * We have to trap resource allocation requests and ensure that the bridge
397 * is set up to, or capable of handling them.
400 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
401 u_long start, u_long end, u_long count, u_int flags)
403 struct pcib_softc *sc = device_get_softc(dev);
407 * Fail the allocation for this range if it's not supported.
412 if (!pcib_is_io_open(sc))
414 ok = (start >= sc->iobase && end <= sc->iolimit);
415 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
417 if (start < sc->iobase)
419 if (end > sc->iolimit)
425 if (start < sc->iobase && end > sc->iolimit) {
432 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", end, start);
438 device_printf(dev, "device %s requested unsupported I/O "
439 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
440 device_get_nameunit(child), start, end,
441 sc->iobase, sc->iolimit);
445 device_printf(dev, "device %s requested decoded I/O range 0x%lx-0x%lx\n",
446 device_get_nameunit(child), start, end);
451 if (pcib_is_nonprefetch_open(sc))
452 ok = ok || (start >= sc->membase && end <= sc->memlimit);
453 if (pcib_is_prefetch_open(sc))
454 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
455 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
458 if (flags & RF_PREFETCHABLE) {
459 if (pcib_is_prefetch_open(sc)) {
460 if (start < sc->pmembase)
461 start = sc->pmembase;
462 if (end > sc->pmemlimit)
467 } else { /* non-prefetchable */
468 if (pcib_is_nonprefetch_open(sc)) {
469 if (start < sc->membase)
471 if (end > sc->memlimit)
479 ok = 1; /* subtractive bridge: always ok */
481 if (pcib_is_nonprefetch_open(sc)) {
482 if (start < sc->membase && end > sc->memlimit) {
487 if (pcib_is_prefetch_open(sc)) {
488 if (start < sc->pmembase && end > sc->pmemlimit) {
489 start = sc->pmembase;
496 device_printf(dev, "memory: end (%lx) < start (%lx)\n", end, start);
501 if (!ok && bootverbose)
503 "device %s requested unsupported memory range "
504 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
505 device_get_nameunit(child), start, end,
506 sc->membase, sc->memlimit, sc->pmembase,
511 device_printf(dev,"device %s requested decoded memory range 0x%lx-0x%lx\n",
512 device_get_nameunit(child), start, end);
519 * Bridge is OK decoding this resource, so pass it up.
521 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
525 pcib_maxslots(device_t dev)
531 pcib_read_config(device_t dev, int b, int s, int f,
535 * Pass through to the next ppb up the chain (i.e. our
538 * [pcibX]->[pciX]->[pciX.Y]
541 * getting back to this point.
543 return PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)),
544 b, s, f, reg, width);
548 pcib_write_config(device_t dev, int b, int s, int f,
549 int reg, uint32_t val, int width)
552 * Pass through to the next ppb up the chain (i.e. our
555 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)),
556 b, s, f, reg, val, width);
560 * Route an interrupt across a PCI bridge.
562 * pcib - is the pci bridge device
563 * dev - is the device
566 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
574 * The PCI standard defines a swizzle of the child-side device/intpin
575 * to the parent-side intpin as follows.
577 * device = device on child bus
578 * child_intpin = intpin on child bus slot (0-3)
579 * parent_intpin = intpin on parent bus slot (0-3)
581 * parent_intpin = (device + child_intpin) % 4
583 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
586 * Our parent is a PCI bus. Its parent must export the pci interface
587 * which includes the ability to route interrupts.
589 bus = device_get_parent(pcib);
590 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib,
592 device_printf(pcib, "routed slot %d INT%c to irq %d\n",
593 pci_get_slot(dev), 'A' + pin - 1, intnum);
598 * Try to read the bus number of a host-PCI bridge using appropriate config
602 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
607 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
608 if (id == 0xffffffff)
614 /* XXX This is a guess */
615 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
619 /* Intel 82454KX/GX (Orion) */
620 *busnum = read_config(bus, slot, func, 0x4a, 1);
624 * For the 450nx chipset, there is a whole bundle of
625 * things pretending to be host bridges. The MIOC will
626 * be seen first and isn't really a pci bridge (the
627 * actual busses are attached to the PXB's). We need to
628 * read the registers of the MIOC to figure out the
629 * bus numbers for the PXB channels.
631 * Since the MIOC doesn't have a pci bus attached, we
632 * pretend it wasn't there.
638 /* Intel 82454NX PXB#0, Bus#A */
639 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
642 /* Intel 82454NX PXB#0, Bus#B */
643 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
646 /* Intel 82454NX PXB#1, Bus#A */
647 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
650 /* Intel 82454NX PXB#1, Bus#B */
651 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
656 /* ServerWorks -- vendor 0x1166 */
668 *busnum = read_config(bus, slot, func, 0x44, 1);
671 /* Don't know how to read bus number. */
678 static device_method_t pcib_methods[] = {
679 /* Device interface */
680 DEVMETHOD(device_probe, pcib_probe),
681 DEVMETHOD(device_attach, pcib_attach),
682 DEVMETHOD(device_shutdown, bus_generic_shutdown),
683 DEVMETHOD(device_suspend, bus_generic_suspend),
684 DEVMETHOD(device_resume, bus_generic_resume),
687 DEVMETHOD(bus_print_child, bus_generic_print_child),
688 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
689 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
690 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
691 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
692 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
693 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
694 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
695 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
698 DEVMETHOD(pcib_maxslots, pcib_maxslots),
699 DEVMETHOD(pcib_read_config, pcib_read_config),
700 DEVMETHOD(pcib_write_config, pcib_write_config),
701 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
706 static driver_t pcib_driver = {
709 sizeof(struct pcib_softc)
712 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);