3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.5 2008/10/03 05:09:18 sephe Exp $
39 struct re_chain_data {
42 caddr_t re_rx_buf_ptr;
43 bus_dmamap_t re_rx_dmamap;
45 struct mbuf *re_tx_chain[RE_TX_LIST_CNT];
46 bus_dmamap_t re_tx_dmamap[RE_TX_LIST_CNT];
51 #define RE_INC(x) (x = (x + 1) % RE_TX_LIST_CNT)
52 #define RE_CUR_TXADDR(x) ((x->re_cdata.cur_tx * 4) + RE_TXADDR0)
53 #define RE_CUR_TXSTAT(x) ((x->re_cdata.cur_tx * 4) + RE_TXSTAT0)
54 #define RE_CUR_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.cur_tx])
55 #define RE_CUR_DMAMAP(x) (x->re_cdata.re_tx_dmamap[x->re_cdata.cur_tx])
56 #define RE_LAST_TXADDR(x) ((x->re_cdata.last_tx * 4) + RE_TXADDR0)
57 #define RE_LAST_TXSTAT(x) ((x->re_cdata.last_tx * 4) + RE_TXSTAT0)
58 #define RE_LAST_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.last_tx])
59 #define RE_LAST_DMAMAP(x) (x->re_cdata.re_tx_dmamap[x->re_cdata.last_tx])
70 int re_type; /* RE_{8139CPLUS,8169} */
71 uint32_t re_flags; /* see RE_F_ */
75 #define RE_8139CPLUS 3
82 struct re_dmaload_arg {
84 bus_dma_segment_t *re_segs;
88 struct mbuf *re_tx_mbuf[RE_TX_DESC_CNT];
89 struct mbuf *re_rx_mbuf[RE_RX_DESC_CNT];
90 bus_addr_t re_rx_paddr[RE_RX_DESC_CNT];
95 bus_dmamap_t re_tx_dmamap[RE_TX_DESC_CNT];
96 bus_dmamap_t re_rx_dmamap[RE_RX_DESC_CNT];
97 bus_dmamap_t re_rx_spare;
98 bus_dma_tag_t re_mtag; /* mbuf mapping tag */
99 bus_dma_tag_t re_stag; /* stats mapping tag */
100 bus_dmamap_t re_smap; /* stats map */
101 struct re_stats *re_stats;
102 bus_addr_t re_stats_addr;
103 bus_dma_tag_t re_rx_list_tag;
104 bus_dmamap_t re_rx_list_map;
105 struct re_desc *re_rx_list;
106 bus_addr_t re_rx_list_addr;
107 bus_dma_tag_t re_tx_list_tag;
108 bus_dmamap_t re_tx_list_map;
109 struct re_desc *re_tx_list;
110 bus_addr_t re_tx_list_addr;
114 struct arpcom arpcom; /* interface info */
118 bus_space_handle_t re_bhandle; /* bus space handle */
119 bus_space_tag_t re_btag; /* bus space tag */
120 struct resource *re_res;
121 struct resource *re_irq;
124 bus_dma_tag_t re_parent_tag;
125 bus_dma_tag_t re_tag;
128 uint8_t re_stats_no_timeout;
130 struct re_chain_data re_cdata;
131 struct re_list_data re_ldata;
132 struct callout re_timer;
133 struct mbuf *re_head;
134 struct mbuf *re_tail;
135 uint32_t re_flags; /* see RE_F_ */
136 uint32_t re_rxlenmask;
139 int suspended; /* 0 = normal 1 = suspended */
142 #ifdef DEVICE_POLLING
146 struct sysctl_ctx_list re_sysctl_ctx;
147 struct sysctl_oid *re_sysctl_tree;
152 uint32_t saved_maps[5]; /* pci data */
153 uint32_t saved_biosaddr;
154 uint8_t saved_intline;
155 uint8_t saved_cachelnsz;
156 uint8_t saved_lattimer;
160 #define RE_F_HASMPC 0x1
161 #define RE_F_PCIE 0x2
163 #define RE_TX_MODERATION_IS_ENABLED(sc) \
164 ((sc)->re_tx_ack == RE_ISR_TIMEOUT_EXPIRED)
166 #define RE_DISABLE_TX_MODERATION(sc) do { \
167 (sc)->re_tx_ack = RE_ISR_TX_OK; \
168 (sc)->re_intrs = RE_INTRS | RE_ISR_TX_OK; \
171 #define RE_ENABLE_TX_MODERATION(sc) do { \
172 (sc)->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; \
173 (sc)->re_intrs = RE_INTRS; \
177 * register space access macros
179 #define CSR_WRITE_STREAM_4(sc, reg, val) \
180 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)
181 #define CSR_WRITE_4(sc, reg, val) \
182 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)
183 #define CSR_WRITE_2(sc, reg, val) \
184 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)
185 #define CSR_WRITE_1(sc, reg, val) \
186 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)
188 #define CSR_READ_4(sc, reg) \
189 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)
190 #define CSR_READ_2(sc, reg) \
191 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)
192 #define CSR_READ_1(sc, reg) \
193 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)
195 #define CSR_SETBIT_1(sc, reg, val) \
196 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))
197 #define CSR_CLRBIT_1(sc, reg, val) \
198 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))
200 #define RE_TXDESC_SPARE 4