2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.8 2007/11/30 15:11:42 ariff Exp $
28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.14 2007/12/01 08:32:11 hasso Exp $
32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
33 * that this driver still in its early stage, and possible of rewrite are
34 * pretty much guaranteed. There are supposedly several distinct parent/child
35 * busses to make this "perfect", but as for now and for the sake of
36 * simplicity, everything is gobble up within single source.
39 * 1) HDA Controller support
40 * 2) HDA Codecs support, which may include
44 * 3) Widget parser - the real magic of why this driver works on so
45 * many hardwares with minimal vendor specific quirk. The original
46 * parser was written using Ruby and can be found at
47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
48 * ruby parser take the verbose dmesg dump as its input. Refer to
49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
50 * interesting documents, especially UAA (Universal Audio Architecture).
51 * 4) Possible vendor specific support.
52 * (snd_hda_intel, snd_hda_ati, etc..)
54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
55 * Compaq V3000 with Conexant HDA.
57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
59 * * This driver is a collaborative effort made by: *
61 * * Stephane E. Potvin <sepotvin@videotron.ca> *
62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
63 * * Wesley Morgan <morganw@chemikals.org> *
64 * * Daniel Eischen <deischen@FreeBSD.org> *
65 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
66 * * Ariff Abdullah <ariff@FreeBSD.org> *
68 * * ....and various people from freebsd-multimedia@FreeBSD.org *
70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
73 #include <dev/sound/pcm/sound.h>
74 #include <bus/pci/pcireg.h>
75 #include <bus/pci/pcivar.h>
77 #include <sys/ctype.h>
78 #include <sys/taskqueue.h>
80 #include <dev/sound/pci/hda/hdac_private.h>
81 #include <dev/sound/pci/hda/hdac_reg.h>
82 #include <dev/sound/pci/hda/hda_reg.h>
83 #include <dev/sound/pci/hda/hdac.h>
87 #define HDA_DRV_TEST_REV "20071129_0050"
88 #define HDA_WIDGET_PARSER_REV 1
90 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.14 2007/12/01 08:32:11 hasso Exp $");
97 #define HDA_BOOTVERBOSE(stmt) do { \
98 if (hda_debug && bootverbose != 0) { \
104 #undef HDAC_INTR_EXTRA
105 #define HDAC_INTR_EXTRA 1
108 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
109 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
110 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
111 #define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */
113 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
114 #include <machine/specialreg.h>
115 #define HDAC_DMA_ATTR(sc, v, s, attr) do { \
116 vm_offset_t va = (vm_offset_t)(v); \
117 vm_size_t sz = (vm_size_t)(s); \
118 if ((sc) != NULL && ((sc)->flags & HDAC_F_DMA_NOCACHE) && \
119 va != 0 && sz != 0) \
120 (void)pmap_change_attr(va, sz, (attr)); \
123 #define HDAC_DMA_ATTR(...)
126 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
127 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
128 (fl) == 0xffffffff || \
129 (((fl) & 0xffff0000) == 0xffff0000 && \
130 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
131 (((fl) & 0x0000ffff) == 0x0000ffff && \
132 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
133 #define HDA_MATCH_ALL 0xffffffff
134 #define HDAC_INVALID 0xffffffff
136 /* Default controller / jack sense poll: 250ms */
137 #define HDAC_POLL_INTERVAL max(hz >> 2, 1)
140 * Make room for possible 4096 playback/record channels, in 100 years to come.
142 #define HDAC_TRIGGER_NONE 0x00000000
143 #define HDAC_TRIGGER_PLAY 0x00000fff
144 #define HDAC_TRIGGER_REC 0x00fff000
145 #define HDAC_TRIGGER_UNSOL 0x80000000
147 #define HDA_MODEL_CONSTRUCT(vendor, model) \
148 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
150 /* Controller models */
153 #define INTEL_VENDORID 0x8086
154 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
155 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
156 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
157 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
158 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e)
159 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
162 #define NVIDIA_VENDORID 0x10de
163 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
164 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
165 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
166 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
167 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
168 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
169 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c)
170 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d)
171 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
174 #define ATI_VENDORID 0x1002
175 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
176 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
177 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
180 #define VIA_VENDORID 0x1106
181 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
182 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
185 #define SIS_VENDORID 0x1039
186 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
187 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
192 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
195 #define HP_VENDORID 0x103c
196 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
197 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
198 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
199 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
200 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
201 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
202 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
203 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802)
204 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
205 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
206 #define HP_NX6325_SUBVENDORX 0x103c30b0
209 #define DELL_VENDORID 0x1028
210 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
211 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
212 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
213 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
214 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
217 #define CLEVO_VENDORID 0x1558
218 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
219 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
222 #define ACER_VENDORID 0x1025
223 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
224 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127)
225 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
226 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
229 #define ASUS_VENDORID 0x1043
230 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
231 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
232 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
233 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
234 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
235 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
236 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
237 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
238 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
239 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
240 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
241 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
242 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
243 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
244 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
247 #define IBM_VENDORID 0x1014
248 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
249 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
252 #define LENOVO_VENDORID 0x17aa
253 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
254 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)
255 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
258 #define SAMSUNG_VENDORID 0x144d
259 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
260 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
263 #define MEDION_VENDORID 0x161f
264 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
265 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
267 /* Apple Computer Inc. */
268 #define APPLE_VENDORID 0x106b
269 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1)
272 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
273 * instead of their own, which is beyond my comprehension
274 * (see HDA_CODEC_STAC9221 below).
276 #define APPLE_INTEL_MAC 0x76808384
279 #define LG_VENDORID 0x1854
280 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
281 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
283 /* Fujitsu Siemens */
284 #define FS_VENDORID 0x1734
285 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
286 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd)
287 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
289 /* Fujitsu Limited */
290 #define FL_VENDORID 0x10cf
291 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326)
292 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff)
295 #define TOSHIBA_VENDORID 0x1179
296 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
297 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01)
298 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
300 /* Micro-Star International (MSI) */
301 #define MSI_VENDORID 0x1462
302 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
303 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a)
304 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
306 /* Giga-Byte Technology */
307 #define GB_VENDORID 0x1458
308 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022)
309 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff)
312 #define UNIWILL_VENDORID 0x1584
313 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
314 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
317 /* Misc constants.. */
318 #define HDA_AMP_MUTE_DEFAULT (0xffffffff)
319 #define HDA_AMP_MUTE_NONE (0)
320 #define HDA_AMP_MUTE_LEFT (1 << 0)
321 #define HDA_AMP_MUTE_RIGHT (1 << 1)
322 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
324 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
325 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
327 #define HDA_DAC_PATH (1 << 0)
328 #define HDA_ADC_PATH (1 << 1)
329 #define HDA_ADC_RECSEL (1 << 2)
331 #define HDA_DAC_LOCKED (1 << 3)
332 #define HDA_ADC_LOCKED (1 << 4)
334 #define HDA_CTL_OUT (1 << 0)
335 #define HDA_CTL_IN (1 << 1)
336 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT)
338 #define HDA_GPIO_MAX 8
339 /* 0 - 7 = GPIO , 8 = Flush */
340 #define HDA_QUIRK_GPIO0 (1 << 0)
341 #define HDA_QUIRK_GPIO1 (1 << 1)
342 #define HDA_QUIRK_GPIO2 (1 << 2)
343 #define HDA_QUIRK_GPIO3 (1 << 3)
344 #define HDA_QUIRK_GPIO4 (1 << 4)
345 #define HDA_QUIRK_GPIO5 (1 << 5)
346 #define HDA_QUIRK_GPIO6 (1 << 6)
347 #define HDA_QUIRK_GPIO7 (1 << 7)
348 #define HDA_QUIRK_GPIOFLUSH (1 << 8)
350 /* 9 - 25 = anything else */
351 #define HDA_QUIRK_SOFTPCMVOL (1 << 9)
352 #define HDA_QUIRK_FIXEDRATE (1 << 10)
353 #define HDA_QUIRK_FORCESTEREO (1 << 11)
354 #define HDA_QUIRK_EAPDINV (1 << 12)
355 #define HDA_QUIRK_DMAPOS (1 << 13)
357 /* 26 - 31 = vrefs */
358 #define HDA_QUIRK_IVREF50 (1 << 26)
359 #define HDA_QUIRK_IVREF80 (1 << 27)
360 #define HDA_QUIRK_IVREF100 (1 << 28)
361 #define HDA_QUIRK_OVREF50 (1 << 29)
362 #define HDA_QUIRK_OVREF80 (1 << 30)
363 #define HDA_QUIRK_OVREF100 (1 << 31)
365 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
367 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
369 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
371 #define SOUND_MASK_SKIP (1 << 30)
372 #define SOUND_MASK_DISABLE (1 << 31)
374 static const struct {
377 } hdac_quirks_tab[] = {
378 { "gpio0", HDA_QUIRK_GPIO0 },
379 { "gpio1", HDA_QUIRK_GPIO1 },
380 { "gpio2", HDA_QUIRK_GPIO2 },
381 { "gpio3", HDA_QUIRK_GPIO3 },
382 { "gpio4", HDA_QUIRK_GPIO4 },
383 { "gpio5", HDA_QUIRK_GPIO5 },
384 { "gpio6", HDA_QUIRK_GPIO6 },
385 { "gpio7", HDA_QUIRK_GPIO7 },
386 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
387 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
388 { "fixedrate", HDA_QUIRK_FIXEDRATE },
389 { "forcestereo", HDA_QUIRK_FORCESTEREO },
390 { "eapdinv", HDA_QUIRK_EAPDINV },
391 { "dmapos", HDA_QUIRK_DMAPOS },
392 { "ivref50", HDA_QUIRK_IVREF50 },
393 { "ivref80", HDA_QUIRK_IVREF80 },
394 { "ivref100", HDA_QUIRK_IVREF100 },
395 { "ovref50", HDA_QUIRK_OVREF50 },
396 { "ovref80", HDA_QUIRK_OVREF80 },
397 { "ovref100", HDA_QUIRK_OVREF100 },
398 { "ivref", HDA_QUIRK_IVREF },
399 { "ovref", HDA_QUIRK_OVREF },
400 { "vref", HDA_QUIRK_VREF },
402 #define HDAC_QUIRKS_TAB_LEN \
403 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
405 #define HDA_BDL_MIN 2
406 #define HDA_BDL_MAX 256
407 #define HDA_BDL_DEFAULT HDA_BDL_MIN
409 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
410 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
412 #define HDA_BUFSZ_MIN 4096
413 #define HDA_BUFSZ_MAX 65536
414 #define HDA_BUFSZ_DEFAULT 16384
416 #define HDA_PARSE_MAXDEPTH 10
418 #define HDAC_UNSOLTAG_EVENT_HP 0x00
419 #define HDAC_UNSOLTAG_EVENT_TEST 0x01
421 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
429 static uint32_t hdac_fmt[] = {
430 AFMT_STEREO | AFMT_S16_LE,
434 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
436 static const struct {
440 { HDA_INTEL_82801F, "Intel 82801F" },
441 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
442 { HDA_INTEL_82801G, "Intel 82801G" },
443 { HDA_INTEL_82801H, "Intel 82801H" },
444 { HDA_INTEL_82801I, "Intel 82801I" },
445 { HDA_NVIDIA_MCP51, "NVidia MCP51" },
446 { HDA_NVIDIA_MCP55, "NVidia MCP55" },
447 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" },
448 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" },
449 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" },
450 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" },
451 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" },
452 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" },
453 { HDA_ATI_SB450, "ATI SB450" },
454 { HDA_ATI_SB600, "ATI SB600" },
455 { HDA_VIA_VT82XX, "VIA VT8251/8237A" },
456 { HDA_SIS_966, "SiS 966" },
458 { HDA_INTEL_ALL, "Intel (Unknown)" },
459 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
460 { HDA_ATI_ALL, "ATI (Unknown)" },
461 { HDA_VIA_ALL, "VIA (Unknown)" },
462 { HDA_SIS_ALL, "SiS (Unknown)" },
464 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
466 static const struct {
471 } hdac_pcie_snoop[] = {
472 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
473 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
474 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
476 #define HDAC_PCIESNOOP_LEN \
477 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
479 static const struct {
486 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
487 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
488 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
489 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
490 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
491 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
492 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
493 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
494 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
495 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
496 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
497 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
498 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
499 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
500 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
501 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
502 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
503 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
504 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
505 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
506 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
507 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
508 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
509 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
510 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
511 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
512 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
513 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
514 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
515 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
516 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
517 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
518 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
519 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
520 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
522 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
524 /* All codecs you can eat... */
525 #define HDA_CODEC_CONSTRUCT(vendor, id) \
526 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
529 #define REALTEK_VENDORID 0x10ec
530 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
531 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
532 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)
533 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
534 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
535 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
536 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
537 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
538 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
539 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
540 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
541 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
544 #define ANALOGDEVICES_VENDORID 0x11d4
545 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
546 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
547 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984)
548 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
549 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
550 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
551 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
554 #define CMEDIA_VENDORID 0x434d
555 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
556 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
559 #define SIGMATEL_VENDORID 0x8384
560 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
561 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
562 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
563 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
564 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
565 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
566 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
571 * Ok, the truth is, I don't have any idea at all whether
572 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
573 * place that tell me it is "Venice" is from its Windows driver INF.
576 * Waikiki - CX20551-22
578 #define CONEXANT_VENDORID 0x14f1
579 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
580 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
581 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
584 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
585 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
586 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
587 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
588 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
589 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
590 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
591 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
592 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
593 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
594 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
595 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
596 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
600 static const struct {
604 { HDA_CODEC_ALC260, "Realtek ALC260" },
605 { HDA_CODEC_ALC262, "Realtek ALC262" },
606 { HDA_CODEC_ALC268, "Realtek ALC268" },
607 { HDA_CODEC_ALC660, "Realtek ALC660" },
608 { HDA_CODEC_ALC861, "Realtek ALC861" },
609 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
610 { HDA_CODEC_ALC880, "Realtek ALC880" },
611 { HDA_CODEC_ALC882, "Realtek ALC882" },
612 { HDA_CODEC_ALC883, "Realtek ALC883" },
613 { HDA_CODEC_ALC885, "Realtek ALC885" },
614 { HDA_CODEC_ALC888, "Realtek ALC888" },
615 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
616 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
617 { HDA_CODEC_AD1984, "Analog Devices AD1984" },
618 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
619 { HDA_CODEC_AD1988, "Analog Devices AD1988" },
620 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
621 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
622 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
623 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
624 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
625 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
626 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" },
627 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
628 { HDA_CODEC_CXVENICE, "Conexant Venice" },
629 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
630 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
631 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
632 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
633 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
634 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
635 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
636 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
637 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
638 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
639 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
640 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
641 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
643 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
644 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
645 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
646 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
647 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
648 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
650 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
658 static const struct {
668 } hdac_hp_switch[] = {
669 /* Specific OEM models */
670 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
671 0, 0, -1, 17, { 16, -1 }, 16 },
672 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
673 0, 0, -1, 21, { 16, 17, -1 }, -1 } */
674 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG,
675 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */
676 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
677 0, 0, -1, 6, { 5, -1 }, 5 },
678 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
679 0, 0, -1, 6, { 5, -1 }, 5 },
680 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
681 0, 0, -1, 6, { 5, -1 }, 5 },
682 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL,
683 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */
684 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
685 0, 0, -1, 6, { 5, -1 }, -1 },
686 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL,
687 0, 0, -1, 27, { 20, -1 }, -1 },
688 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
689 0, 0, -1, 13, { 14, -1 }, -1 },
690 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
691 0, 0, -1, 13, { 14, -1 }, -1 },
692 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL,
693 0, 0, -1, 6, { 5, 7, -1 }, -1 },
694 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL,
695 0, 0, -1, 21, { 20, 22, -1 }, -1 },
696 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL,
697 0, 0, -1, 10, { 13, -1 }, -1 },
698 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
699 1, 0, -1, 26, { 27, -1 }, -1 },
700 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
701 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */
702 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL,
703 0, 0, -1, 27, { 20, -1 }, -1 },
704 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
705 0, 0, -1, 20, { 21, -1 }, -1 },
706 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
707 0, 0, -1, 20, { 21, -1 }, -1 },
708 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL,
709 0, 0, -1, 20, { 21, -1 }, -1 },
710 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
711 0, 0, -1, 20, { 21, -1 }, -1 },
712 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
713 0, 0, -1, 20, { 27, -1 }, -1 },
714 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
715 0, 0, -1, 20, { 27, -1 }, -1 },
716 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
717 0, 0, -1, 20, { 21, -1 }, -1 },
718 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
719 0, 0, -1, 20, { 16, -1 }, -1 },
721 * All models that at least come from the same vendor with
724 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
725 0, 0, -1, 17, { 16, -1 }, 16 },
726 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
727 0, 0, -1, 6, { 5, -1 }, 5 },
728 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
729 0, 0, -1, 6, { 5, -1 }, -1 },
730 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
731 0, 0, -1, 13, { 14, -1 }, -1 },
733 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
734 1, 0, -1, 26, { 27, -1 }, -1 },
735 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
736 0, 0, -1, 20, { 21, -1 }, -1 },
739 #define HDAC_HP_SWITCH_LEN \
740 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0]))
742 static const struct {
747 } hdac_eapd_switch[] = {
748 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
749 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
750 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
752 #define HDAC_EAPD_SWITCH_LEN \
753 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0]))
755 /****************************************************************************
756 * Function prototypes
757 ****************************************************************************/
758 static void hdac_intr_handler(void *);
759 static int hdac_reset(struct hdac_softc *);
760 static int hdac_get_capabilities(struct hdac_softc *);
761 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
762 static int hdac_dma_alloc(struct hdac_softc *,
763 struct hdac_dma *, bus_size_t);
764 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
765 static int hdac_mem_alloc(struct hdac_softc *);
766 static void hdac_mem_free(struct hdac_softc *);
767 static int hdac_irq_alloc(struct hdac_softc *);
768 static void hdac_irq_free(struct hdac_softc *);
769 static void hdac_corb_init(struct hdac_softc *);
770 static void hdac_rirb_init(struct hdac_softc *);
771 static void hdac_corb_start(struct hdac_softc *);
772 static void hdac_rirb_start(struct hdac_softc *);
773 static void hdac_scan_codecs(struct hdac_softc *, int);
774 static int hdac_probe_codec(struct hdac_codec *);
775 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
776 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
778 static void hdac_attach2(void *);
780 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
782 static void hdac_command_send_internal(struct hdac_softc *,
783 struct hdac_command_list *, int);
785 static int hdac_probe(device_t);
786 static int hdac_attach(device_t);
787 static int hdac_detach(device_t);
788 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
789 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
791 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
793 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
794 nid_t, nid_t, int, int, int, int, int, int);
795 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
796 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
798 static int hdac_rirb_flush(struct hdac_softc *sc);
799 static int hdac_unsolq_flush(struct hdac_softc *sc);
801 #define hdac_command(a1, a2, a3) \
802 hdac_command_sendone_internal(a1, a2, a3)
804 #define hdac_codec_id(d) \
805 ((uint32_t)((d == NULL) ? 0x00000000 : \
806 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \
807 ((uint32_t)(d)->device_id & 0x0000ffff))))
810 hdac_codec_name(struct hdac_devinfo *devinfo)
815 id = hdac_codec_id(devinfo);
817 for (i = 0; i < HDAC_CODECS_LEN; i++) {
818 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
819 return (hdac_codecs[i].name);
822 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
826 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
828 static char *ossname[] = SOUND_DEVICE_NAMES;
829 static char *unknown = "???";
832 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
833 if (devmask & (1 << i))
840 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
842 static char *ossname[] = SOUND_DEVICE_NAMES;
846 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
847 if (mask & (1 << i)) {
849 strlcat(buf, ", ", len);
850 strlcat(buf, ossname[i], len);
856 static struct hdac_audio_ctl *
857 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
859 if (devinfo == NULL ||
860 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
861 index == NULL || devinfo->function.audio.ctl == NULL ||
862 devinfo->function.audio.ctlcnt < 1 ||
863 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
865 return (&devinfo->function.audio.ctl[(*index)++]);
868 static struct hdac_audio_ctl *
869 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
872 struct hdac_audio_ctl *ctl, *retctl = NULL;
873 int i, at, atindex, found = 0;
875 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
888 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
889 if (ctl->enable == 0 || ctl->widget == NULL)
891 if (!(ctl->widget->nid == nid && (atindex == -1 ||
892 ctl->index == atindex)))
900 return ((at == -1) ? retctl : NULL);
904 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
906 struct hdac_softc *sc;
907 struct hdac_widget *w;
908 struct hdac_audio_ctl *ctl;
909 uint32_t val, id, res;
910 int i = 0, j, timeout, forcemute;
913 if (devinfo == NULL || devinfo->codec == NULL ||
914 devinfo->codec->sc == NULL)
917 sc = devinfo->codec->sc;
918 cad = devinfo->codec->cad;
919 id = hdac_codec_id(devinfo);
920 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
921 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
922 sc->pci_subvendor) &&
923 hdac_hp_switch[i].id == id)
927 if (i >= HDAC_HP_SWITCH_LEN)
931 if (hdac_hp_switch[i].eapdnid != -1) {
932 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
933 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
934 forcemute = (w->param.eapdbtl &
935 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
938 if (hdac_hp_switch[i].execsense != -1)
940 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
941 hdac_hp_switch[i].execsense), cad);
945 res = hdac_command(sc,
946 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid),
948 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff)
951 } while (--timeout != 0);
954 device_printf(sc->dev,
955 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n",
956 hdac_hp_switch[i].hpnid, timeout, res);
959 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
960 res ^= hdac_hp_switch[i].inverted;
962 switch (hdac_hp_switch[i].type) {
963 case HDAC_HP_SWITCH_CTL:
964 ctl = hdac_audio_ctl_amp_get(devinfo,
965 hdac_hp_switch[i].hpnid, 0, 1);
967 val = (res != 0 && forcemute == 0) ?
968 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
969 if (val != ctl->muted) {
971 hdac_audio_ctl_amp_set(ctl,
972 HDA_AMP_MUTE_DEFAULT, ctl->left,
976 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
977 ctl = hdac_audio_ctl_amp_get(devinfo,
978 hdac_hp_switch[i].spkrnid[j], 0, 1);
981 val = (res != 0 || forcemute == 1) ?
982 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
983 if (val == ctl->muted)
986 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
987 ctl->left, ctl->right);
990 case HDAC_HP_SWITCH_CTRL:
993 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
994 if (w != NULL && w->type ==
995 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
997 val = w->wclass.pin.ctrl |
998 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1000 val = w->wclass.pin.ctrl &
1001 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1002 if (val != w->wclass.pin.ctrl) {
1003 w->wclass.pin.ctrl = val;
1005 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1006 w->nid, w->wclass.pin.ctrl), cad);
1009 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1010 w = hdac_widget_get(devinfo,
1011 hdac_hp_switch[i].spkrnid[j]);
1012 if (w == NULL || w->type !=
1013 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1015 val = w->wclass.pin.ctrl &
1016 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1017 if (val == w->wclass.pin.ctrl)
1019 w->wclass.pin.ctrl = val;
1020 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
1021 cad, w->nid, w->wclass.pin.ctrl), cad);
1025 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
1026 if (w != NULL && w->type ==
1027 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1028 val = w->wclass.pin.ctrl &
1029 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1030 if (val != w->wclass.pin.ctrl) {
1031 w->wclass.pin.ctrl = val;
1033 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1034 w->nid, w->wclass.pin.ctrl), cad);
1037 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1038 w = hdac_widget_get(devinfo,
1039 hdac_hp_switch[i].spkrnid[j]);
1040 if (w == NULL || w->type !=
1041 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1044 val = w->wclass.pin.ctrl |
1045 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1047 val = w->wclass.pin.ctrl &
1048 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1049 if (val == w->wclass.pin.ctrl)
1051 w->wclass.pin.ctrl = val;
1052 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
1053 cad, w->nid, w->wclass.pin.ctrl), cad);
1057 case HDAC_HP_SWITCH_DEBUG:
1058 if (hdac_hp_switch[i].execsense != -1)
1060 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
1061 hdac_hp_switch[i].execsense), cad);
1062 res = hdac_command(sc,
1063 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
1064 device_printf(sc->dev,
1065 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1066 hdac_hp_switch[i].hpnid, res);
1067 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1068 w = hdac_widget_get(devinfo,
1069 hdac_hp_switch[i].spkrnid[j]);
1070 if (w == NULL || w->type !=
1071 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1073 if (hdac_hp_switch[i].execsense != -1)
1075 HDA_CMD_SET_PIN_SENSE(cad, w->nid,
1076 hdac_hp_switch[i].execsense), cad);
1077 res = hdac_command(sc,
1078 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
1079 device_printf(sc->dev,
1080 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1081 j + 1, w->nid, res);
1090 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1092 struct hdac_softc *sc;
1093 struct hdac_devinfo *devinfo = NULL;
1094 device_t *devlist = NULL;
1097 if (codec == NULL || codec->sc == NULL)
1103 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
1106 device_get_children(sc->dev, &devlist, &devcount);
1107 for (i = 0; devlist != NULL && i < devcount; i++) {
1108 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
1109 if (devinfo != NULL && devinfo->node_type ==
1110 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
1111 devinfo->codec != NULL &&
1112 devinfo->codec->cad == codec->cad) {
1117 if (devlist != NULL)
1118 kfree(devlist, M_TEMP);
1120 if (devinfo == NULL)
1124 case HDAC_UNSOLTAG_EVENT_HP:
1125 hdac_hp_switch_handler(devinfo);
1127 case HDAC_UNSOLTAG_EVENT_TEST:
1128 device_printf(sc->dev, "Unsol Test!\n");
1136 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1138 /* XXX to be removed */
1139 #ifdef HDAC_INTR_EXTRA
1143 if (!(ch->flags & HDAC_CHN_RUNNING))
1146 /* XXX to be removed */
1147 #ifdef HDAC_INTR_EXTRA
1148 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1151 /* XXX to be removed */
1152 #ifdef HDAC_INTR_EXTRA
1154 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1155 device_printf(sc->dev,
1156 "PCMDIR_%s intr triggered beyond stream boundary:"
1158 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1162 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1163 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1165 /* XXX to be removed */
1166 #ifdef HDAC_INTR_EXTRA
1167 if (res & HDAC_SDSTS_BCIS) {
1170 /* XXX to be removed */
1171 #ifdef HDAC_INTR_EXTRA
1178 /****************************************************************************
1179 * void hdac_intr_handler(void *)
1181 * Interrupt handler. Processes interrupts received from the hdac.
1182 ****************************************************************************/
1184 hdac_intr_handler(void *context)
1186 struct hdac_softc *sc;
1189 struct hdac_rirb *rirb_base;
1192 sc = (struct hdac_softc *)context;
1195 if (sc->polling != 0) {
1200 /* Do we have anything to do? */
1201 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1202 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1209 /* Was this a controller interrupt? */
1210 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1211 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1212 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1213 /* Get as many responses that we can */
1214 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1215 HDAC_WRITE_1(&sc->mem,
1216 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1217 if (hdac_rirb_flush(sc) != 0)
1218 trigger |= HDAC_TRIGGER_UNSOL;
1219 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1221 /* XXX to be removed */
1222 /* Clear interrupt and exit */
1223 #ifdef HDAC_INTR_EXTRA
1224 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1228 if (intsts & HDAC_INTSTS_SIS_MASK) {
1229 if ((intsts & (1 << sc->num_iss)) &&
1230 hdac_stream_intr(sc, &sc->play) != 0)
1231 trigger |= HDAC_TRIGGER_PLAY;
1232 if ((intsts & (1 << 0)) &&
1233 hdac_stream_intr(sc, &sc->rec) != 0)
1234 trigger |= HDAC_TRIGGER_REC;
1235 /* XXX to be removed */
1236 #ifdef HDAC_INTR_EXTRA
1237 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1238 HDAC_INTSTS_SIS_MASK);
1244 if (trigger & HDAC_TRIGGER_PLAY)
1245 chn_intr(sc->play.c);
1246 if (trigger & HDAC_TRIGGER_REC)
1247 chn_intr(sc->rec.c);
1248 if (trigger & HDAC_TRIGGER_UNSOL)
1249 taskqueue_enqueue(taskqueue_swi, &sc->unsolq_task);
1252 /****************************************************************************
1253 * int hdac_reset(hdac_softc *)
1255 * Reset the hdac to a quiescent and known state.
1256 ****************************************************************************/
1258 hdac_reset(struct hdac_softc *sc)
1264 * Stop all Streams DMA engine
1266 for (i = 0; i < sc->num_iss; i++)
1267 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1268 for (i = 0; i < sc->num_oss; i++)
1269 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1270 for (i = 0; i < sc->num_bss; i++)
1271 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1274 * Stop Control DMA engines.
1276 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1277 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1280 * Reset DMA position buffer.
1282 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1283 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1286 * Reset the controller. The reset must remain asserted for
1287 * a minimum of 100us.
1289 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1290 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1293 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1294 if (!(gctl & HDAC_GCTL_CRST))
1298 if (gctl & HDAC_GCTL_CRST) {
1299 device_printf(sc->dev, "Unable to put hdac in reset\n");
1303 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1304 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1307 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1308 if (gctl & HDAC_GCTL_CRST)
1312 if (!(gctl & HDAC_GCTL_CRST)) {
1313 device_printf(sc->dev, "Device stuck in reset\n");
1318 * Wait for codecs to finish their own reset sequence. The delay here
1319 * should be of 250us but for some reasons, on it's not enough on my
1320 * computer. Let's use twice as much as necessary to make sure that
1321 * it's reset properly.
1329 /****************************************************************************
1330 * int hdac_get_capabilities(struct hdac_softc *);
1332 * Retreive the general capabilities of the hdac;
1333 * Number of Input Streams
1334 * Number of Output Streams
1335 * Number of bidirectional Streams
1337 * CORB and RIRB sizes
1338 ****************************************************************************/
1340 hdac_get_capabilities(struct hdac_softc *sc)
1343 uint8_t corbsize, rirbsize;
1345 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1346 sc->num_iss = HDAC_GCAP_ISS(gcap);
1347 sc->num_oss = HDAC_GCAP_OSS(gcap);
1348 sc->num_bss = HDAC_GCAP_BSS(gcap);
1350 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1352 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1353 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1354 HDAC_CORBSIZE_CORBSZCAP_256)
1355 sc->corb_size = 256;
1356 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1357 HDAC_CORBSIZE_CORBSZCAP_16)
1359 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1360 HDAC_CORBSIZE_CORBSZCAP_2)
1363 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1364 __func__, corbsize);
1368 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1369 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1370 HDAC_RIRBSIZE_RIRBSZCAP_256)
1371 sc->rirb_size = 256;
1372 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1373 HDAC_RIRBSIZE_RIRBSZCAP_16)
1375 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1376 HDAC_RIRBSIZE_RIRBSZCAP_2)
1379 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1380 __func__, rirbsize);
1388 /****************************************************************************
1391 * This function is called by bus_dmamap_load when the mapping has been
1392 * established. We just record the physical address of the mapping into
1393 * the struct hdac_dma passed in.
1394 ****************************************************************************/
1396 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1398 struct hdac_dma *dma;
1401 dma = (struct hdac_dma *)callback_arg;
1402 dma->dma_paddr = segs[0].ds_addr;
1407 /****************************************************************************
1408 * int hdac_dma_alloc
1410 * This function allocate and setup a dma region (struct hdac_dma).
1411 * It must be freed by a corresponding hdac_dma_free.
1412 ****************************************************************************/
1414 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1420 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1421 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1422 BUS_SPACE_MAXADDR_32BIT;
1423 bzero(dma, sizeof(*dma));
1428 result = bus_dma_tag_create(NULL, /* parent */
1429 HDAC_DMA_ALIGNMENT, /* alignment */
1431 lowaddr, /* lowaddr */
1432 BUS_SPACE_MAXADDR, /* highaddr */
1433 NULL, /* filtfunc */
1434 NULL, /* fistfuncarg */
1435 roundsz, /* maxsize */
1437 roundsz, /* maxsegsz */
1439 &dma->dma_tag); /* dmat */
1441 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1443 goto hdac_dma_alloc_fail;
1447 * Allocate DMA memory
1449 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1450 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1451 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1452 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1455 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1456 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map);
1459 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1461 goto hdac_dma_alloc_fail;
1464 dma->dma_size = roundsz;
1469 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1470 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1471 if (result != 0 || dma->dma_paddr == 0) {
1474 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1476 goto hdac_dma_alloc_fail;
1480 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1481 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1486 hdac_dma_alloc_fail:
1487 hdac_dma_free(sc, dma);
1493 /****************************************************************************
1494 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1496 * Free a struct dhac_dma that has been previously allocated via the
1497 * hdac_dma_alloc function.
1498 ****************************************************************************/
1500 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1502 if (dma->dma_map != NULL) {
1505 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1506 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1508 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1510 if (dma->dma_vaddr != NULL) {
1511 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1512 dma->dma_vaddr = NULL;
1514 dma->dma_map = NULL;
1515 if (dma->dma_tag != NULL) {
1516 bus_dma_tag_destroy(dma->dma_tag);
1517 dma->dma_tag = NULL;
1522 /****************************************************************************
1523 * int hdac_mem_alloc(struct hdac_softc *)
1525 * Allocate all the bus resources necessary to speak with the physical
1527 ****************************************************************************/
1529 hdac_mem_alloc(struct hdac_softc *sc)
1531 struct hdac_mem *mem;
1534 mem->mem_rid = PCIR_BAR(0);
1535 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1536 &mem->mem_rid, RF_ACTIVE);
1537 if (mem->mem_res == NULL) {
1538 device_printf(sc->dev,
1539 "%s: Unable to allocate memory resource\n", __func__);
1542 mem->mem_tag = rman_get_bustag(mem->mem_res);
1543 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1548 /****************************************************************************
1549 * void hdac_mem_free(struct hdac_softc *)
1551 * Free up resources previously allocated by hdac_mem_alloc.
1552 ****************************************************************************/
1554 hdac_mem_free(struct hdac_softc *sc)
1556 struct hdac_mem *mem;
1559 if (mem->mem_res != NULL)
1560 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1562 mem->mem_res = NULL;
1565 /****************************************************************************
1566 * int hdac_irq_alloc(struct hdac_softc *)
1568 * Allocate and setup the resources necessary for interrupt handling.
1569 ****************************************************************************/
1571 hdac_irq_alloc(struct hdac_softc *sc)
1573 struct hdac_irq *irq;
1579 #if 0 /* TODO: No MSI support in DragonFly yet. */
1580 if ((sc->flags & HDAC_F_MSI) &&
1581 (result = pci_msi_count(sc->dev)) == 1 &&
1582 pci_alloc_msi(sc->dev, &result) == 0)
1586 sc->flags &= ~HDAC_F_MSI;
1588 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1589 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1590 if (irq->irq_res == NULL) {
1591 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1593 goto hdac_irq_alloc_fail;
1595 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
1596 hdac_intr_handler, sc, &irq->irq_handle);
1598 device_printf(sc->dev,
1599 "%s: Unable to setup interrupt handler (%x)\n",
1601 goto hdac_irq_alloc_fail;
1606 hdac_irq_alloc_fail:
1612 /****************************************************************************
1613 * void hdac_irq_free(struct hdac_softc *)
1615 * Free up resources previously allocated by hdac_irq_alloc.
1616 ****************************************************************************/
1618 hdac_irq_free(struct hdac_softc *sc)
1620 struct hdac_irq *irq;
1623 if (irq->irq_res != NULL && irq->irq_handle != NULL)
1624 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1625 if (irq->irq_res != NULL)
1626 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1628 #if 0 /* TODO: No MSI support in DragonFly yet. */
1629 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1)
1630 pci_release_msi(sc->dev);
1632 irq->irq_handle = NULL;
1633 irq->irq_res = NULL;
1637 /****************************************************************************
1638 * void hdac_corb_init(struct hdac_softc *)
1640 * Initialize the corb registers for operations but do not start it up yet.
1641 * The CORB engine must not be running when this function is called.
1642 ****************************************************************************/
1644 hdac_corb_init(struct hdac_softc *sc)
1649 /* Setup the CORB size. */
1650 switch (sc->corb_size) {
1652 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1655 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1658 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1661 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1663 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1665 /* Setup the CORB Address in the hdac */
1666 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1667 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1668 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1670 /* Set the WP and RP */
1672 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1673 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1675 * The HDA specification indicates that the CORBRPRST bit will always
1676 * read as zero. Unfortunately, it seems that at least the 82801G
1677 * doesn't reset the bit to zero, which stalls the corb engine.
1678 * manually reset the bit to zero before continuing.
1680 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1682 /* Enable CORB error reporting */
1684 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1688 /****************************************************************************
1689 * void hdac_rirb_init(struct hdac_softc *)
1691 * Initialize the rirb registers for operations but do not start it up yet.
1692 * The RIRB engine must not be running when this function is called.
1693 ****************************************************************************/
1695 hdac_rirb_init(struct hdac_softc *sc)
1700 /* Setup the RIRB size. */
1701 switch (sc->rirb_size) {
1703 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1706 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1709 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1712 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1714 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1716 /* Setup the RIRB Address in the hdac */
1717 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1718 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1719 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1721 /* Setup the WP and RP */
1723 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1725 if (sc->polling == 0) {
1726 /* Setup the interrupt threshold */
1727 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1729 /* Enable Overrun and response received reporting */
1731 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1732 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1734 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1740 * Make sure that the Host CPU cache doesn't contain any dirty
1741 * cache lines that falls in the rirb. If I understood correctly, it
1742 * should be sufficient to do this only once as the rirb is purely
1743 * read-only from now on.
1745 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1746 BUS_DMASYNC_PREREAD);
1750 /****************************************************************************
1751 * void hdac_corb_start(hdac_softc *)
1753 * Startup the corb DMA engine
1754 ****************************************************************************/
1756 hdac_corb_start(struct hdac_softc *sc)
1760 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1761 corbctl |= HDAC_CORBCTL_CORBRUN;
1762 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1765 /****************************************************************************
1766 * void hdac_rirb_start(hdac_softc *)
1768 * Startup the rirb DMA engine
1769 ****************************************************************************/
1771 hdac_rirb_start(struct hdac_softc *sc)
1775 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1776 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1777 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1781 /****************************************************************************
1782 * void hdac_scan_codecs(struct hdac_softc *, int)
1784 * Scan the bus for available codecs, starting with num.
1785 ****************************************************************************/
1787 hdac_scan_codecs(struct hdac_softc *sc, int num)
1789 struct hdac_codec *codec;
1795 if (num >= HDAC_CODEC_MAX)
1796 num = HDAC_CODEC_MAX - 1;
1798 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1799 for (i = num; i < HDAC_CODEC_MAX; i++) {
1800 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1801 /* We have found a codec. */
1802 codec = (struct hdac_codec *)kmalloc(sizeof(*codec),
1803 M_HDAC, M_ZERO | M_NOWAIT);
1804 if (codec == NULL) {
1805 device_printf(sc->dev,
1806 "Unable to allocate memory for codec\n");
1809 codec->commands = NULL;
1810 codec->responses_received = 0;
1811 codec->verbs_sent = 0;
1814 sc->codecs[i] = codec;
1815 if (hdac_probe_codec(codec) != 0)
1819 /* All codecs have been probed, now try to attach drivers to them */
1820 /* bus_generic_attach(sc->dev); */
1823 /****************************************************************************
1824 * void hdac_probe_codec(struct hdac_softc *, int)
1826 * Probe a the given codec_id for available function groups.
1827 ****************************************************************************/
1829 hdac_probe_codec(struct hdac_codec *codec)
1831 struct hdac_softc *sc = codec->sc;
1832 struct hdac_devinfo *devinfo;
1833 uint32_t vendorid, revisionid, subnode;
1837 nid_t cad = codec->cad;
1840 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1842 vendorid = hdac_command(sc,
1843 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1845 revisionid = hdac_command(sc,
1846 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1848 subnode = hdac_command(sc,
1849 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1851 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1852 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1855 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1856 startnode, endnode);
1858 for (i = startnode; i < endnode; i++) {
1859 devinfo = hdac_probe_function(codec, i);
1860 if (devinfo != NULL) {
1861 /* XXX Ignore other FG. */
1862 devinfo->vendor_id =
1863 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1864 devinfo->device_id =
1865 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1866 devinfo->revision_id =
1867 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1868 devinfo->stepping_id =
1869 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1871 device_printf(sc->dev,
1872 "HDA_DEBUG: \tFound AFG nid=%d "
1873 "[startnode=%d endnode=%d]\n",
1874 devinfo->nid, startnode, endnode);
1881 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1886 static struct hdac_devinfo *
1887 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1889 struct hdac_softc *sc = codec->sc;
1890 struct hdac_devinfo *devinfo;
1891 uint32_t fctgrptype;
1892 nid_t cad = codec->cad;
1894 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1895 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1897 /* XXX For now, ignore other FG. */
1898 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1901 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC,
1903 if (devinfo == NULL) {
1904 device_printf(sc->dev, "%s: Unable to allocate ivar\n",
1910 devinfo->node_type = fctgrptype;
1911 devinfo->codec = codec;
1913 hdac_add_child(sc, devinfo);
1919 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1921 devinfo->dev = device_add_child(sc->dev, NULL, -1);
1922 device_set_ivars(devinfo->dev, (void *)devinfo);
1923 /* XXX - Print more information when booting verbose??? */
1927 hdac_widget_connection_parse(struct hdac_widget *w)
1929 struct hdac_softc *sc = w->devinfo->codec->sc;
1931 int i, j, max, ents, entnum;
1932 nid_t cad = w->devinfo->codec->cad;
1934 nid_t cnid, addcnid, prevcnid;
1938 res = hdac_command(sc,
1939 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1941 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
1946 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
1947 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
1950 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
1951 #define CONN_NMASK(e) (CONN_RMASK(e) - 1)
1952 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
1953 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
1954 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
1956 for (i = 0; i < ents; i += entnum) {
1957 res = hdac_command(sc,
1958 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1959 for (j = 0; j < entnum; j++) {
1960 cnid = CONN_CNID(res, entnum, j);
1962 if (w->nconns < ents)
1963 device_printf(sc->dev,
1964 "%s: nid=%d WARNING: zero cnid "
1965 "entnum=%d j=%d index=%d "
1966 "entries=%d found=%d res=0x%08x\n",
1967 __func__, nid, entnum, j, i,
1968 ents, w->nconns, res);
1972 if (cnid < w->devinfo->startnode ||
1973 cnid >= w->devinfo->endnode) {
1975 device_printf(sc->dev,
1976 "%s: GHOST: nid=%d j=%d "
1977 "entnum=%d index=%d res=0x%08x\n",
1978 __func__, nid, j, entnum, i, res);
1981 if (CONN_RANGE(res, entnum, j) == 0)
1983 else if (prevcnid == 0 || prevcnid >= cnid) {
1984 device_printf(sc->dev,
1985 "%s: WARNING: Invalid child range "
1986 "nid=%d index=%d j=%d entnum=%d "
1987 "prevcnid=%d cnid=%d res=0x%08x\n",
1988 __func__, nid, i, j, entnum, prevcnid,
1992 addcnid = prevcnid + 1;
1993 while (addcnid <= cnid) {
1994 if (w->nconns > max) {
1995 device_printf(sc->dev,
1996 "%s: nid=%d: Adding %d: "
1997 "Max connection reached! max=%d\n",
1998 __func__, nid, addcnid, max + 1);
2001 w->conns[w->nconns++] = addcnid++;
2009 device_printf(sc->dev,
2010 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n",
2011 __func__, nid, ents, w->nconns);
2017 hdac_widget_pin_getconfig(struct hdac_widget *w)
2019 struct hdac_softc *sc;
2020 uint32_t config, orig, id;
2023 sc = w->devinfo->codec->sc;
2024 cad = w->devinfo->codec->cad;
2026 id = hdac_codec_id(w->devinfo);
2028 config = hdac_command(sc,
2029 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
2034 * XXX REWRITE!!!! Don't argue!
2036 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
2039 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2040 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2043 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2044 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
2049 } else if (id == HDA_CODEC_ALC880 &&
2050 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
2051 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
2065 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2066 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2068 case 25: /* XXX MIC2 */
2069 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2070 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2072 case 26: /* LINE1 */
2073 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2074 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2076 case 27: /* XXX LINE2 */
2077 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2078 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2081 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2082 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
2091 } else if (id == HDA_CODEC_ALC883 &&
2092 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR ||
2093 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) {
2096 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2097 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2098 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2099 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2102 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2103 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2104 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2105 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2110 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor ==
2111 HP_V3000_SUBVENDOR) {
2114 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2115 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2118 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2119 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2120 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2121 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2124 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2125 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2126 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2127 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2132 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor ==
2133 HP_DV5000_SUBVENDOR) {
2137 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2138 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2143 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2144 ASUS_W6F_SUBVENDOR) {
2147 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2148 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2149 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2150 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2153 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2154 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2155 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2156 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2161 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2162 UNIWILL_9075_SUBVENDOR) {
2165 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2166 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2167 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2168 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2173 } else if (id == HDA_CODEC_AD1986A &&
2174 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
2175 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) {
2178 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2179 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2182 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2183 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2192 device_printf(sc->dev,
2193 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n",
2201 hdac_widget_pin_getcaps(struct hdac_widget *w)
2203 struct hdac_softc *sc;
2204 uint32_t caps, orig, id;
2207 sc = w->devinfo->codec->sc;
2208 cad = w->devinfo->codec->cad;
2210 id = hdac_codec_id(w->devinfo);
2212 caps = hdac_command(sc,
2213 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2218 device_printf(sc->dev,
2219 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n",
2227 hdac_widget_pin_parse(struct hdac_widget *w)
2229 struct hdac_softc *sc = w->devinfo->codec->sc;
2230 uint32_t config, pincap;
2231 char *devstr, *connstr;
2232 nid_t cad = w->devinfo->codec->cad;
2235 config = hdac_widget_pin_getconfig(w);
2236 w->wclass.pin.config = config;
2238 pincap = hdac_widget_pin_getcaps(w);
2239 w->wclass.pin.cap = pincap;
2241 w->wclass.pin.ctrl = hdac_command(sc,
2242 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
2243 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
2244 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
2245 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
2246 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
2248 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
2249 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
2250 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
2251 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
2252 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
2253 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
2254 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2255 w->param.eapdbtl = hdac_command(sc,
2256 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2257 w->param.eapdbtl &= 0x7;
2258 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2260 w->param.eapdbtl = HDAC_INVALID;
2262 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
2263 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
2264 devstr = "line out";
2266 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
2269 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
2270 devstr = "headphones out";
2272 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
2275 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
2276 devstr = "SPDIF out";
2278 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
2279 devstr = "digital (other) out";
2281 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
2282 devstr = "modem, line side";
2284 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
2285 devstr = "modem, handset side";
2287 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
2290 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
2293 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
2296 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
2297 devstr = "telephony";
2299 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
2300 devstr = "SPDIF in";
2302 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
2303 devstr = "digital (other) in";
2305 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
2313 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
2314 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
2317 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
2320 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
2323 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
2324 connstr = "jack / fixed";
2327 connstr = "unknown";
2331 strlcat(w->name, ": ", sizeof(w->name));
2332 strlcat(w->name, devstr, sizeof(w->name));
2333 strlcat(w->name, " (", sizeof(w->name));
2334 strlcat(w->name, connstr, sizeof(w->name));
2335 strlcat(w->name, ")", sizeof(w->name));
2339 hdac_widget_parse(struct hdac_widget *w)
2341 struct hdac_softc *sc = w->devinfo->codec->sc;
2344 nid_t cad = w->devinfo->codec->cad;
2347 wcap = hdac_command(sc,
2348 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2350 w->param.widget_cap = wcap;
2351 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2354 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2355 typestr = "audio output";
2357 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2358 typestr = "audio input";
2360 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2361 typestr = "audio mixer";
2363 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2364 typestr = "audio selector";
2366 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2369 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2370 typestr = "power widget";
2372 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2373 typestr = "volume widget";
2375 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2376 typestr = "beep widget";
2378 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2379 typestr = "vendor widget";
2382 typestr = "unknown type";
2386 strlcpy(w->name, typestr, sizeof(w->name));
2388 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
2390 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
2395 hdac_widget_connection_parse(w);
2397 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2398 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2399 w->param.outamp_cap =
2401 HDA_CMD_GET_PARAMETER(cad, nid,
2402 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2404 w->param.outamp_cap =
2405 w->devinfo->function.audio.outamp_cap;
2407 w->param.outamp_cap = 0;
2409 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2410 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2411 w->param.inamp_cap =
2413 HDA_CMD_GET_PARAMETER(cad, nid,
2414 HDA_PARAM_INPUT_AMP_CAP), cad);
2416 w->param.inamp_cap =
2417 w->devinfo->function.audio.inamp_cap;
2419 w->param.inamp_cap = 0;
2421 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2422 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2423 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2424 cap = hdac_command(sc,
2425 HDA_CMD_GET_PARAMETER(cad, nid,
2426 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2427 w->param.supp_stream_formats = (cap != 0) ? cap :
2428 w->devinfo->function.audio.supp_stream_formats;
2429 cap = hdac_command(sc,
2430 HDA_CMD_GET_PARAMETER(cad, nid,
2431 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2432 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2433 w->devinfo->function.audio.supp_pcm_size_rate;
2435 w->param.supp_stream_formats =
2436 w->devinfo->function.audio.supp_stream_formats;
2437 w->param.supp_pcm_size_rate =
2438 w->devinfo->function.audio.supp_pcm_size_rate;
2441 w->param.supp_stream_formats = 0;
2442 w->param.supp_pcm_size_rate = 0;
2445 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2446 hdac_widget_pin_parse(w);
2449 static struct hdac_widget *
2450 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2452 if (devinfo == NULL || devinfo->widget == NULL ||
2453 nid < devinfo->startnode || nid >= devinfo->endnode)
2455 return (&devinfo->widget[nid - devinfo->startnode]);
2459 hda_poll_channel(struct hdac_chan *ch)
2462 volatile uint32_t ptr;
2464 if (!(ch->flags & HDAC_CHN_RUNNING))
2467 sz = ch->blksz * ch->blkcnt;
2468 if (ch->dmapos != NULL)
2469 ptr = *(ch->dmapos);
2471 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2472 ch->off + HDAC_SDLPIB);
2475 ptr &= ~(ch->blksz - 1);
2476 delta = (sz + ptr - ch->prevptr) % sz;
2478 if (delta < ch->blksz)
2486 #define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \
2490 hda_poll_callback(void *arg)
2492 struct hdac_softc *sc = arg;
2499 if (sc->polling == 0 || hda_chan_active(sc) == 0) {
2505 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0;
2506 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0;
2509 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/,
2510 hda_poll_callback, sc);
2514 if (trigger & HDAC_TRIGGER_PLAY)
2515 chn_intr(sc->play.c);
2516 if (trigger & HDAC_TRIGGER_REC)
2517 chn_intr(sc->rec.c);
2521 hdac_rirb_flush(struct hdac_softc *sc)
2523 struct hdac_rirb *rirb_base, *rirb;
2524 struct hdac_codec *codec;
2525 struct hdac_command_list *commands;
2531 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2532 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2534 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2535 BUS_DMASYNC_POSTREAD);
2539 while (sc->rirb_rp != rirbwp) {
2541 sc->rirb_rp %= sc->rirb_size;
2542 rirb = &rirb_base[sc->rirb_rp];
2543 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2544 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2545 sc->codecs[cad] == NULL)
2547 resp = rirb->response;
2548 codec = sc->codecs[cad];
2549 commands = codec->commands;
2550 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2551 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2552 ((resp >> 26) & 0xffff);
2553 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2554 } else if (commands != NULL && commands->num_commands > 0 &&
2555 codec->responses_received < commands->num_commands)
2556 commands->responses[codec->responses_received++] =
2565 hdac_unsolq_flush(struct hdac_softc *sc)
2571 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2572 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2573 while (sc->unsolq_rp != sc->unsolq_wp) {
2574 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2575 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2576 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2577 hdac_unsolicited_handler(sc->codecs[cad], tag);
2580 sc->unsolq_st = HDAC_UNSOLQ_READY;
2587 hdac_poll_callback(void *arg)
2589 struct hdac_softc *sc = arg;
2594 if (sc->polling == 0 || sc->poll_ival == 0) {
2598 if (hdac_rirb_flush(sc) != 0)
2599 hdac_unsolq_flush(sc);
2600 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2605 hdac_stream_stop(struct hdac_chan *ch)
2607 struct hdac_softc *sc = ch->devinfo->codec->sc;
2610 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2611 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2613 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2615 ch->flags &= ~HDAC_CHN_RUNNING;
2617 if (sc->polling != 0) {
2620 if (hda_chan_active(sc) == 0) {
2621 callout_stop(&sc->poll_hda);
2624 if (sc->play.flags & HDAC_CHN_RUNNING)
2628 pollticks = ((uint64_t)hz * ch->blksz) /
2629 ((uint64_t)sndbuf_getbps(ch->b) *
2630 sndbuf_getspd(ch->b));
2634 if (pollticks < 1) {
2636 device_printf(sc->dev,
2637 "%s: pollticks=%d < 1 !\n",
2638 __func__, pollticks);
2642 if (pollticks > sc->poll_ticks) {
2644 device_printf(sc->dev,
2645 "%s: pollticks %d -> %d\n",
2646 __func__, sc->poll_ticks,
2649 sc->poll_ticks = pollticks;
2650 callout_reset(&sc->poll_hda, 1,
2651 hda_poll_callback, sc);
2655 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2656 ctl &= ~(1 << (ch->off >> 5));
2657 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2662 hdac_stream_start(struct hdac_chan *ch)
2664 struct hdac_softc *sc = ch->devinfo->codec->sc;
2667 if (sc->polling != 0) {
2670 pollticks = ((uint64_t)hz * ch->blksz) /
2671 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b));
2675 if (pollticks < 1) {
2677 device_printf(sc->dev,
2678 "%s: pollticks=%d < 1 !\n",
2679 __func__, pollticks);
2683 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) {
2685 if (hda_chan_active(sc) == 0) {
2686 device_printf(sc->dev,
2687 "%s: pollticks=%d\n",
2688 __func__, pollticks);
2690 device_printf(sc->dev,
2691 "%s: pollticks %d -> %d\n",
2692 __func__, sc->poll_ticks,
2696 sc->poll_ticks = pollticks;
2697 callout_reset(&sc->poll_hda, 1, hda_poll_callback,
2700 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2701 ctl |= HDAC_SDCTL_RUN;
2703 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2704 ctl |= 1 << (ch->off >> 5);
2705 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2706 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2707 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2710 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2712 ch->flags |= HDAC_CHN_RUNNING;
2716 hdac_stream_reset(struct hdac_chan *ch)
2718 struct hdac_softc *sc = ch->devinfo->codec->sc;
2723 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2724 ctl |= HDAC_SDCTL_SRST;
2725 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2727 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2728 if (ctl & HDAC_SDCTL_SRST)
2732 if (!(ctl & HDAC_SDCTL_SRST)) {
2733 device_printf(sc->dev, "timeout in reset\n");
2735 ctl &= ~HDAC_SDCTL_SRST;
2736 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2739 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2740 if (!(ctl & HDAC_SDCTL_SRST))
2744 if (ctl & HDAC_SDCTL_SRST)
2745 device_printf(sc->dev, "can't reset!\n");
2749 hdac_stream_setid(struct hdac_chan *ch)
2751 struct hdac_softc *sc = ch->devinfo->codec->sc;
2754 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
2755 ctl &= ~HDAC_SDCTL2_STRM_MASK;
2756 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
2757 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
2761 hdac_bdl_setup(struct hdac_chan *ch)
2763 struct hdac_softc *sc = ch->devinfo->codec->sc;
2764 struct hdac_bdle *bdle;
2766 uint32_t blksz, blkcnt;
2769 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
2770 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
2772 if (sc->polling != 0) {
2773 blksz = ch->blksz * ch->blkcnt;
2777 blkcnt = ch->blkcnt;
2780 for (i = 0; i < blkcnt; i++, bdle++) {
2781 bdle->addrl = (uint32_t)addr;
2782 bdle->addrh = (uint32_t)(addr >> 32);
2784 bdle->ioc = 1 ^ sc->polling;
2788 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
2789 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
2790 addr = ch->bdl_dma.dma_paddr;
2791 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2792 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2793 if (ch->dmapos != NULL &&
2794 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
2795 addr = sc->pos_dma.dma_paddr;
2796 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
2797 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
2798 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
2803 hdac_bdl_alloc(struct hdac_chan *ch)
2805 struct hdac_softc *sc = ch->devinfo->codec->sc;
2808 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2809 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2811 device_printf(sc->dev, "can't alloc bdl\n");
2819 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2820 int index, int lmute, int rmute,
2821 int left, int right, int dir)
2828 if (left != right || lmute != rmute) {
2829 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2830 (lmute << 7) | left;
2832 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2833 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2834 (rmute << 7) | right;
2836 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2837 (lmute << 7) | left;
2840 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2844 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2845 int left, int right)
2847 struct hdac_softc *sc;
2851 if (ctl == NULL || ctl->widget == NULL ||
2852 ctl->widget->devinfo == NULL ||
2853 ctl->widget->devinfo->codec == NULL ||
2854 ctl->widget->devinfo->codec->sc == NULL)
2857 sc = ctl->widget->devinfo->codec->sc;
2858 cad = ctl->widget->devinfo->codec->cad;
2859 nid = ctl->widget->nid;
2861 if (mute == HDA_AMP_MUTE_DEFAULT) {
2862 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2863 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2865 lmute = HDA_AMP_LEFT_MUTED(mute);
2866 rmute = HDA_AMP_RIGHT_MUTED(mute);
2869 if (ctl->dir & HDA_CTL_OUT)
2870 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2871 lmute, rmute, left, right, 0);
2872 if (ctl->dir & HDA_CTL_IN)
2873 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2874 lmute, rmute, left, right, 1);
2880 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2882 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2884 hdac_command(w->devinfo->codec->sc,
2885 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2886 w->nid, index), w->devinfo->codec->cad);
2891 /****************************************************************************
2892 * uint32_t hdac_command_sendone_internal
2894 * Wrapper function that sends only one command to a given codec
2895 ****************************************************************************/
2897 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2899 struct hdac_command_list cl;
2900 uint32_t response = HDAC_INVALID;
2902 if (!hdac_lockowned(sc))
2903 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2904 cl.num_commands = 1;
2906 cl.responses = &response;
2908 hdac_command_send_internal(sc, &cl, cad);
2913 /****************************************************************************
2914 * hdac_command_send_internal
2916 * Send a command list to the codec via the corb. We queue as much verbs as
2917 * we can and msleep on the codec. When the interrupt get the responses
2918 * back from the rirb, it will wake us up so we can queue the remaining verbs
2920 ****************************************************************************/
2922 hdac_command_send_internal(struct hdac_softc *sc,
2923 struct hdac_command_list *commands, nid_t cad)
2925 struct hdac_codec *codec;
2930 struct hdac_rirb *rirb_base;
2932 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
2933 commands->num_commands < 1)
2936 codec = sc->codecs[cad];
2937 codec->commands = commands;
2938 codec->responses_received = 0;
2939 codec->verbs_sent = 0;
2940 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2941 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2944 if (codec->verbs_sent != commands->num_commands) {
2945 /* Queue as many verbs as possible */
2946 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
2948 bus_dmamap_sync(sc->corb_dma.dma_tag,
2949 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
2951 while (codec->verbs_sent != commands->num_commands &&
2952 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2954 sc->corb_wp %= sc->corb_size;
2956 commands->verbs[codec->verbs_sent++];
2959 /* Send the verbs to the codecs */
2961 bus_dmamap_sync(sc->corb_dma.dma_tag,
2962 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
2964 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2968 while (hdac_rirb_flush(sc) == 0 && --timeout)
2970 } while ((codec->verbs_sent != commands->num_commands ||
2971 codec->responses_received != commands->num_commands) && --retry);
2974 device_printf(sc->dev,
2975 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2976 __func__, commands->num_commands, codec->verbs_sent,
2977 codec->responses_received);
2979 codec->commands = NULL;
2980 codec->responses_received = 0;
2981 codec->verbs_sent = 0;
2983 hdac_unsolq_flush(sc);
2987 /****************************************************************************
2989 ****************************************************************************/
2991 /****************************************************************************
2992 * int hdac_probe(device_t)
2994 * Probe for the presence of an hdac. If none is found, check for a generic
2995 * match using the subclass of the device.
2996 ****************************************************************************/
2998 hdac_probe(device_t dev)
3002 uint16_t class, subclass;
3005 model = (uint32_t)pci_get_device(dev) << 16;
3006 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
3007 class = pci_get_class(dev);
3008 subclass = pci_get_subclass(dev);
3010 bzero(desc, sizeof(desc));
3012 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
3013 if (hdac_devices[i].model == model) {
3014 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3015 result = BUS_PROBE_DEFAULT;
3018 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
3019 class == PCIC_MULTIMEDIA &&
3020 subclass == PCIS_MULTIMEDIA_HDA) {
3021 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3022 result = BUS_PROBE_GENERIC;
3026 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
3027 subclass == PCIS_MULTIMEDIA_HDA) {
3028 strlcpy(desc, "Generic", sizeof(desc));
3029 result = BUS_PROBE_GENERIC;
3031 if (result != ENXIO) {
3032 strlcat(desc, " High Definition Audio Controller",
3034 device_set_desc_copy(dev, desc);
3041 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
3042 struct pcm_channel *c, int dir)
3044 struct hdac_devinfo *devinfo = data;
3045 struct hdac_softc *sc = devinfo->codec->sc;
3046 struct hdac_chan *ch;
3049 if (dir == PCMDIR_PLAY) {
3051 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
3052 devinfo->function.audio.playcnt++;
3055 ch->off = devinfo->function.audio.reccnt << 5;
3056 devinfo->function.audio.reccnt++;
3058 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
3059 ch->caps.minspeed = ch->caps.maxspeed = 48000;
3060 ch->pcmrates[0] = 48000;
3061 ch->pcmrates[1] = 0;
3063 if (sc->pos_dma.dma_vaddr != NULL)
3064 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
3065 (sc->streamcnt * 8));
3068 ch->sid = ++sc->streamcnt;
3072 ch->devinfo = devinfo;
3073 ch->blksz = sc->chan_size / sc->chan_blkcnt;
3074 ch->blkcnt = sc->chan_blkcnt;
3077 if (hdac_bdl_alloc(ch) != 0) {
3082 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0)
3085 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b),
3092 hdac_channel_free(kobj_t obj, void *data)
3094 struct hdac_softc *sc;
3095 struct hdac_chan *ch;
3097 ch = (struct hdac_chan *)data;
3098 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ?
3099 ch->devinfo->codec->sc : NULL;
3100 if (ch != NULL && sc != NULL) {
3101 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b),
3102 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK);
3109 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3111 struct hdac_chan *ch = data;
3114 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3115 if (format == ch->caps.fmtlist[i]) {
3125 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3127 struct hdac_chan *ch = data;
3128 uint32_t spd = 0, threshold;
3131 for (i = 0; ch->pcmrates[i] != 0; i++) {
3132 spd = ch->pcmrates[i];
3133 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3134 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3135 if (speed < threshold)
3139 if (spd == 0) /* impossible */
3148 hdac_stream_setup(struct hdac_chan *ch)
3150 struct hdac_softc *sc = ch->devinfo->codec->sc;
3151 struct hdac_widget *w;
3152 int i, chn, totalchn;
3153 nid_t cad = ch->devinfo->codec->cad;
3157 if (ch->fmt & AFMT_S16_LE)
3158 fmt |= ch->bit16 << 4;
3159 else if (ch->fmt & AFMT_S32_LE)
3160 fmt |= ch->bit32 << 4;
3164 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3165 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3166 fmt |= hda_rate_tab[i].base;
3167 fmt |= hda_rate_tab[i].mul;
3168 fmt |= hda_rate_tab[i].div;
3173 if (ch->fmt & AFMT_STEREO) {
3179 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3182 for (i = 0; ch->io[i] != -1; i++) {
3183 w = hdac_widget_get(ch->devinfo, ch->io[i]);
3187 device_printf(sc->dev,
3188 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
3190 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3194 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3195 if (ch->dir == PCMDIR_REC)
3197 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3198 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0),
3202 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3203 ch->sid << 4), cad);
3205 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ?
3211 hdac_channel_setfragments(kobj_t obj, void *data,
3212 uint32_t blksz, uint32_t blkcnt)
3214 struct hdac_chan *ch = data;
3215 struct hdac_softc *sc = ch->devinfo->codec->sc;
3217 blksz &= HDA_BLK_ALIGN;
3219 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3220 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3221 if (blksz < HDA_BLK_MIN)
3222 blksz = HDA_BLK_MIN;
3223 if (blkcnt > HDA_BDL_MAX)
3224 blkcnt = HDA_BDL_MAX;
3225 if (blkcnt < HDA_BDL_MIN)
3226 blkcnt = HDA_BDL_MIN;
3228 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3229 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3231 else if ((blksz >> 1) >= HDA_BLK_MIN)
3237 if ((sndbuf_getblksz(ch->b) != blksz ||
3238 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3239 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3240 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3241 __func__, blksz, blkcnt);
3243 ch->blksz = sndbuf_getblksz(ch->b);
3244 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3250 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3252 struct hdac_chan *ch = data;
3253 struct hdac_softc *sc = ch->devinfo->codec->sc;
3255 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt);
3261 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3263 struct hdac_devinfo *devinfo = ch->devinfo;
3264 nid_t cad = devinfo->codec->cad;
3267 hdac_stream_stop(ch);
3269 for (i = 0; ch->io[i] != -1; i++) {
3271 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3277 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3281 hdac_stream_stop(ch);
3282 hdac_stream_reset(ch);
3284 hdac_stream_setid(ch);
3285 hdac_stream_setup(ch);
3286 hdac_stream_start(ch);
3290 hdac_channel_trigger(kobj_t obj, void *data, int go)
3292 struct hdac_chan *ch = data;
3293 struct hdac_softc *sc = ch->devinfo->codec->sc;
3295 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT))
3301 hdac_channel_start(sc, ch);
3305 hdac_channel_stop(sc, ch);
3316 hdac_channel_getptr(kobj_t obj, void *data)
3318 struct hdac_chan *ch = data;
3319 struct hdac_softc *sc = ch->devinfo->codec->sc;
3323 if (sc->polling != 0)
3325 else if (ch->dmapos != NULL)
3326 ptr = *(ch->dmapos);
3328 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3332 * Round to available space and force 128 bytes aligment.
3334 ptr %= ch->blksz * ch->blkcnt;
3335 ptr &= HDA_BLK_ALIGN;
3340 static struct pcmchan_caps *
3341 hdac_channel_getcaps(kobj_t obj, void *data)
3343 return (&((struct hdac_chan *)data)->caps);
3346 static kobj_method_t hdac_channel_methods[] = {
3347 KOBJMETHOD(channel_init, hdac_channel_init),
3348 KOBJMETHOD(channel_free, hdac_channel_free),
3349 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3350 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3351 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3352 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3353 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3354 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3357 CHANNEL_DECLARE(hdac_channel);
3360 hdac_jack_poll_callback(void *arg)
3362 struct hdac_devinfo *devinfo = arg;
3363 struct hdac_softc *sc;
3365 if (devinfo == NULL || devinfo->codec == NULL ||
3366 devinfo->codec->sc == NULL)
3368 sc = devinfo->codec->sc;
3370 if (sc->poll_ival == 0) {
3374 hdac_hp_switch_handler(devinfo);
3375 callout_reset(&sc->poll_jack, sc->poll_ival,
3376 hdac_jack_poll_callback, devinfo);
3381 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3383 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3384 struct hdac_softc *sc = devinfo->codec->sc;
3385 struct hdac_widget *w, *cw;
3386 struct hdac_audio_ctl *ctl;
3387 uint32_t mask, recmask, id;
3388 int i, j, softpcmvol;
3396 id = hdac_codec_id(devinfo);
3397 cad = devinfo->codec->cad;
3398 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
3399 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
3400 sc->pci_subvendor) && hdac_hp_switch[i].id == id))
3402 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
3403 if (w == NULL || w->enable == 0 || w->type !=
3404 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3406 if (hdac_hp_switch[i].polling != 0)
3407 callout_reset(&sc->poll_jack, 1,
3408 hdac_jack_poll_callback, devinfo);
3409 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
3411 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
3412 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
3413 HDAC_UNSOLTAG_EVENT_HP), cad);
3416 hdac_hp_switch_handler(devinfo);
3418 device_printf(sc->dev,
3419 "HDA_DEBUG: Enabling headphone/speaker "
3420 "audio routing switching:\n");
3421 device_printf(sc->dev,
3422 "HDA_DEBUG: \tindex=%d nid=%d "
3423 "pci_subvendor=0x%08x "
3424 "codec=0x%08x [%s]\n",
3425 i, w->nid, sc->pci_subvendor, id,
3426 (hdac_hp_switch[i].polling != 0) ? "POLL" :
3431 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3432 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3433 sc->pci_subvendor) &&
3434 hdac_eapd_switch[i].id == id))
3436 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3437 if (w == NULL || w->enable == 0)
3439 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3440 w->param.eapdbtl == HDAC_INVALID)
3442 mask |= SOUND_MASK_OGAIN;
3446 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3447 w = hdac_widget_get(devinfo, i);
3448 if (w == NULL || w->enable == 0)
3450 mask |= w->ctlflags;
3451 if (!(w->pflags & HDA_ADC_RECSEL))
3453 for (j = 0; j < w->nconns; j++) {
3454 cw = hdac_widget_get(devinfo, w->conns[j]);
3455 if (cw == NULL || cw->enable == 0)
3457 recmask |= cw->ctlflags;
3461 if (!(mask & SOUND_MASK_PCM)) {
3463 mask |= SOUND_MASK_PCM;
3465 softpcmvol = (devinfo->function.audio.quirks &
3466 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
3470 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3471 if (ctl->widget == NULL || ctl->enable == 0)
3473 if (!(ctl->ossmask & SOUND_MASK_PCM))
3479 if (softpcmvol == 1 || ctl == NULL) {
3480 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
3482 device_printf(sc->dev,
3483 "HDA_DEBUG: %s Soft PCM volume\n",
3485 "Forcing" : "Enabling");
3489 * XXX Temporary quirk for STAC9220, until the parser
3492 if (id == HDA_CODEC_STAC9220) {
3493 mask |= SOUND_MASK_VOLUME;
3494 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3496 if (ctl->widget == NULL || ctl->enable == 0)
3498 if (ctl->widget->nid == 11 && ctl->index == 0) {
3499 ctl->ossmask = SOUND_MASK_VOLUME;
3500 ctl->ossval = 100 | (100 << 8);
3502 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3504 } else if (id == HDA_CODEC_STAC9221) {
3505 mask |= SOUND_MASK_VOLUME;
3506 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3508 if (ctl->widget == NULL)
3510 if (ctl->widget->type ==
3511 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3512 ctl->index == 0 && (ctl->widget->nid == 2 ||
3513 ctl->widget->enable != 0)) {
3515 ctl->ossmask = SOUND_MASK_VOLUME;
3516 ctl->ossval = 100 | (100 << 8);
3517 } else if (ctl->enable == 0)
3520 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3523 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3525 if (!(mask & SOUND_MASK_VOLUME))
3526 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3528 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3530 if (ctl->widget == NULL || ctl->enable == 0)
3532 if (!HDA_FLAG_MATCH(ctl->ossmask,
3533 SOUND_MASK_VOLUME | SOUND_MASK_PCM))
3535 if (!(ctl->mute == 1 && ctl->step == 0))
3541 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER |
3542 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN |
3544 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3545 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3547 mix_setrecdevs(m, recmask);
3548 mix_setdevs(m, mask);
3556 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3557 unsigned left, unsigned right)
3559 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3560 struct hdac_softc *sc = devinfo->codec->sc;
3561 struct hdac_widget *w;
3562 struct hdac_audio_ctl *ctl;
3564 int lvol, rvol, mlvol, mrvol;
3568 if (dev == SOUND_MIXER_OGAIN) {
3570 /*if (left != right || !(left == 0 || left == 1)) {
3574 id = hdac_codec_id(devinfo);
3575 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3576 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3577 sc->pci_subvendor) &&
3578 hdac_eapd_switch[i].id == id)
3581 if (i >= HDAC_EAPD_SWITCH_LEN) {
3585 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3587 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3588 w->param.eapdbtl == HDAC_INVALID) {
3592 orig = w->param.eapdbtl;
3594 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3596 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3597 if (orig != w->param.eapdbtl) {
3600 if (hdac_eapd_switch[i].hp_switch != 0)
3601 hdac_hp_switch_handler(devinfo);
3602 val = w->param.eapdbtl;
3603 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3604 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3606 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3607 w->nid, val), devinfo->codec->cad);
3610 return (left | (left << 8));
3612 if (dev == SOUND_MIXER_VOLUME)
3613 devinfo->function.audio.mvol = left | (right << 8);
3615 mlvol = devinfo->function.audio.mvol & 0x7f;
3616 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
3621 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3622 if (ctl->widget == NULL || ctl->enable == 0 ||
3623 !(ctl->ossmask & (1 << dev)))
3626 case SOUND_MIXER_VOLUME:
3627 lvol = ((ctl->ossval & 0x7f) * left) / 100;
3628 lvol = (lvol * ctl->step) / 100;
3629 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
3630 rvol = (rvol * ctl->step) / 100;
3633 if (ctl->ossmask & SOUND_MASK_VOLUME) {
3634 lvol = (left * mlvol) / 100;
3635 lvol = (lvol * ctl->step) / 100;
3636 rvol = (right * mrvol) / 100;
3637 rvol = (rvol * ctl->step) / 100;
3639 lvol = (left * ctl->step) / 100;
3640 rvol = (right * ctl->step) / 100;
3642 ctl->ossval = left | (right << 8);
3646 if (ctl->step < 1) {
3647 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
3648 (ctl->muted & HDA_AMP_MUTE_LEFT);
3649 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
3650 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3652 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
3653 (ctl->muted & HDA_AMP_MUTE_LEFT);
3654 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
3655 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3657 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3661 return (left | (right << 8));
3665 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3667 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3668 struct hdac_widget *w, *cw;
3669 struct hdac_softc *sc = devinfo->codec->sc;
3670 uint32_t ret = src, target;
3674 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3675 if (src & (1 << i)) {
3683 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3684 w = hdac_widget_get(devinfo, i);
3685 if (w == NULL || w->enable == 0)
3687 if (!(w->pflags & HDA_ADC_RECSEL))
3689 for (j = 0; j < w->nconns; j++) {
3690 cw = hdac_widget_get(devinfo, w->conns[j]);
3691 if (cw == NULL || cw->enable == 0)
3693 if ((target == SOUND_MASK_VOLUME &&
3695 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
3696 (target != SOUND_MASK_VOLUME &&
3698 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
3700 if (cw->ctlflags & target) {
3701 if (!(w->pflags & HDA_ADC_LOCKED))
3702 hdac_widget_connection_select(w, j);
3714 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3715 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
3716 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
3717 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
3720 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3723 hdac_unsolq_task(void *context, int pending)
3725 struct hdac_softc *sc;
3727 sc = (struct hdac_softc *)context;
3730 hdac_unsolq_flush(sc);
3734 /****************************************************************************
3735 * int hdac_attach(device_t)
3737 * Attach the device into the kernel. Interrupts usually won't be enabled
3738 * when this function is called. Setup everything that doesn't require
3739 * interrupts and defer probing of codecs until interrupts are enabled.
3740 ****************************************************************************/
3742 hdac_attach(device_t dev)
3744 struct hdac_softc *sc;
3750 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
3751 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
3753 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
3754 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
3755 vendor = pci_get_vendor(dev);
3757 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
3758 /* Screw nx6325 - subdevice/subvendor swapped */
3759 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
3762 callout_init(&sc->poll_hda);
3763 callout_init(&sc->poll_hdac);
3764 callout_init(&sc->poll_jack);
3766 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
3769 sc->poll_ival = HDAC_POLL_INTERVAL;
3770 if (resource_int_value(device_get_name(dev),
3771 device_get_unit(dev), "polling", &i) == 0 && i != 0)
3776 sc->chan_size = pcm_getbuffersize(dev,
3777 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
3779 if (resource_int_value(device_get_name(dev),
3780 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
3782 if (i < HDA_BLK_MIN)
3784 sc->chan_blkcnt = sc->chan_size / i;
3786 while (sc->chan_blkcnt >> i)
3788 sc->chan_blkcnt = 1 << (i - 1);
3789 if (sc->chan_blkcnt < HDA_BDL_MIN)
3790 sc->chan_blkcnt = HDA_BDL_MIN;
3791 else if (sc->chan_blkcnt > HDA_BDL_MAX)
3792 sc->chan_blkcnt = HDA_BDL_MAX;
3794 sc->chan_blkcnt = HDA_BDL_DEFAULT;
3796 result = bus_dma_tag_create(NULL, /* parent */
3797 HDAC_DMA_ALIGNMENT, /* alignment */
3799 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3800 BUS_SPACE_MAXADDR, /* highaddr */
3801 NULL, /* filtfunc */
3802 NULL, /* fistfuncarg */
3803 sc->chan_size, /* maxsize */
3805 sc->chan_size, /* maxsegsz */
3807 &sc->chan_dmat); /* dmat */
3809 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
3811 snd_mtxfree(sc->lock);
3812 kfree(sc, M_DEVBUF);
3818 for (i = 0; i < HDAC_CODEC_MAX; i++)
3819 sc->codecs[i] = NULL;
3821 pci_enable_busmaster(dev);
3823 if (vendor == INTEL_VENDORID) {
3825 v = pci_read_config(dev, 0x44, 1);
3826 pci_write_config(dev, 0x44, v & 0xf8, 1);
3828 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
3829 pci_read_config(dev, 0x44, 1));
3832 #if 0 /* TODO: No MSI support yet in DragonFly. */
3833 if (resource_int_value(device_get_name(dev),
3834 device_get_unit(dev), "msi", &i) == 0 && i != 0 &&
3835 pci_msi_count(dev) == 1)
3836 sc->flags |= HDAC_F_MSI;
3839 sc->flags &= ~HDAC_F_MSI;
3841 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3842 sc->flags |= HDAC_F_DMA_NOCACHE;
3844 if (resource_int_value(device_get_name(dev),
3845 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
3847 sc->flags &= ~HDAC_F_DMA_NOCACHE;
3850 * Try to enable PCIe snoop to avoid messing around with
3851 * uncacheable DMA attribute. Since PCIe snoop register
3852 * config is pretty much vendor specific, there are no
3853 * general solutions on how to enable it, forcing us (even
3854 * Microsoft) to enable uncacheable or write combined DMA
3857 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
3859 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
3860 if (hdac_pcie_snoop[i].vendor != vendor)
3862 sc->flags &= ~HDAC_F_DMA_NOCACHE;
3863 if (hdac_pcie_snoop[i].reg == 0x00)
3865 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3866 if ((v & hdac_pcie_snoop[i].enable) ==
3867 hdac_pcie_snoop[i].enable)
3869 v &= hdac_pcie_snoop[i].mask;
3870 v |= hdac_pcie_snoop[i].enable;
3871 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
3872 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3873 if ((v & hdac_pcie_snoop[i].enable) !=
3874 hdac_pcie_snoop[i].enable) {
3877 "WARNING: Failed to enable PCIe "
3880 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3881 sc->flags |= HDAC_F_DMA_NOCACHE;
3886 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3891 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
3892 (sc->flags & HDAC_F_DMA_NOCACHE) ?
3893 "Uncacheable" : "PCIe snoop", vendor);
3896 /* Allocate resources */
3897 result = hdac_mem_alloc(sc);
3899 goto hdac_attach_fail;
3900 result = hdac_irq_alloc(sc);
3902 goto hdac_attach_fail;
3904 /* Get Capabilities */
3905 result = hdac_get_capabilities(sc);
3907 goto hdac_attach_fail;
3909 /* Allocate CORB and RIRB dma memory */
3910 result = hdac_dma_alloc(sc, &sc->corb_dma,
3911 sc->corb_size * sizeof(uint32_t));
3913 goto hdac_attach_fail;
3914 result = hdac_dma_alloc(sc, &sc->rirb_dma,
3915 sc->rirb_size * sizeof(struct hdac_rirb));
3917 goto hdac_attach_fail;
3919 /* Quiesce everything */
3922 /* Initialize the CORB and RIRB */
3926 /* Defer remaining of initialization until interrupts are enabled */
3927 sc->intrhook.ich_func = hdac_attach2;
3928 sc->intrhook.ich_arg = (void *)sc;
3929 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
3930 sc->intrhook.ich_func = NULL;
3931 hdac_attach2((void *)sc);
3938 hdac_dma_free(sc, &sc->rirb_dma);
3939 hdac_dma_free(sc, &sc->corb_dma);
3941 snd_mtxfree(sc->lock);
3942 kfree(sc, M_DEVBUF);
3948 hdac_audio_parse(struct hdac_devinfo *devinfo)
3950 struct hdac_softc *sc = devinfo->codec->sc;
3951 struct hdac_widget *w;
3956 cad = devinfo->codec->cad;
3960 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad);
3964 res = hdac_command(sc,
3965 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
3967 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
3968 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
3969 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
3971 res = hdac_command(sc,
3972 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
3973 devinfo->function.audio.gpio = res;
3976 device_printf(sc->dev, " Vendor: 0x%08x\n",
3977 devinfo->vendor_id);
3978 device_printf(sc->dev, " Device: 0x%08x\n",
3979 devinfo->device_id);
3980 device_printf(sc->dev, " Revision: 0x%08x\n",
3981 devinfo->revision_id);
3982 device_printf(sc->dev, " Stepping: 0x%08x\n",
3983 devinfo->stepping_id);
3984 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
3986 device_printf(sc->dev, " Nodes: start=%d "
3987 "endnode=%d total=%d\n",
3988 devinfo->startnode, devinfo->endnode, devinfo->nodecnt);
3989 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size);
3990 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size);
3991 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n",
3992 sc->num_iss, sc->num_oss, sc->num_bss);
3993 device_printf(sc->dev, " GPIO: 0x%08x\n",
3994 devinfo->function.audio.gpio);
3995 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d "
3996 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
3997 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
3998 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
3999 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
4000 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
4001 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
4004 res = hdac_command(sc,
4005 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
4007 devinfo->function.audio.supp_stream_formats = res;
4009 res = hdac_command(sc,
4010 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
4012 devinfo->function.audio.supp_pcm_size_rate = res;
4014 res = hdac_command(sc,
4015 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
4017 devinfo->function.audio.outamp_cap = res;
4019 res = hdac_command(sc,
4020 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
4022 devinfo->function.audio.inamp_cap = res;
4024 if (devinfo->nodecnt > 0)
4025 devinfo->widget = (struct hdac_widget *)kmalloc(
4026 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
4029 devinfo->widget = NULL;
4031 if (devinfo->widget == NULL) {
4032 device_printf(sc->dev, "unable to allocate widgets!\n");
4033 devinfo->endnode = devinfo->startnode;
4034 devinfo->nodecnt = 0;
4038 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4039 w = hdac_widget_get(devinfo, i);
4041 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
4043 w->devinfo = devinfo;
4049 w->param.eapdbtl = HDAC_INVALID;
4050 hdac_widget_parse(w);
4056 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
4058 struct hdac_softc *sc = devinfo->codec->sc;
4059 struct hdac_audio_ctl *ctls;
4060 struct hdac_widget *w, *cw;
4061 int i, j, cnt, max, ocap, icap;
4062 int mute, offset, step, size;
4064 /* XXX This is redundant */
4066 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4067 w = hdac_widget_get(devinfo, i);
4068 if (w == NULL || w->enable == 0)
4070 if (w->param.outamp_cap != 0)
4072 if (w->param.inamp_cap != 0) {
4074 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4075 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4076 for (j = 0; j < w->nconns; j++) {
4077 cw = hdac_widget_get(devinfo,
4079 if (cw == NULL || cw->enable == 0)
4091 devinfo->function.audio.ctlcnt = max;
4096 ctls = (struct hdac_audio_ctl *)kmalloc(
4097 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
4101 device_printf(sc->dev, "unable to allocate ctls!\n");
4102 devinfo->function.audio.ctlcnt = 0;
4107 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
4109 device_printf(sc->dev, "%s: Ctl overflow!\n",
4113 w = hdac_widget_get(devinfo, i);
4114 if (w == NULL || w->enable == 0)
4116 ocap = w->param.outamp_cap;
4117 icap = w->param.inamp_cap;
4119 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
4120 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
4121 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
4122 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
4123 /*if (offset > step) {
4125 device_printf(sc->dev,
4126 "HDA_DEBUG: BUGGY outamp: nid=%d "
4127 "[offset=%d > step=%d]\n",
4128 w->nid, offset, step);
4132 ctls[cnt].enable = 1;
4133 ctls[cnt].widget = w;
4134 ctls[cnt].mute = mute;
4135 ctls[cnt].step = step;
4136 ctls[cnt].size = size;
4137 ctls[cnt].offset = offset;
4138 ctls[cnt].left = offset;
4139 ctls[cnt].right = offset;
4140 ctls[cnt++].dir = HDA_CTL_OUT;
4144 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
4145 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
4146 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
4147 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
4148 /*if (offset > step) {
4150 device_printf(sc->dev,
4151 "HDA_DEBUG: BUGGY inamp: nid=%d "
4152 "[offset=%d > step=%d]\n",
4153 w->nid, offset, step);
4158 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4159 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4160 for (j = 0; j < w->nconns; j++) {
4162 device_printf(sc->dev,
4163 "%s: Ctl overflow!\n",
4167 cw = hdac_widget_get(devinfo,
4169 if (cw == NULL || cw->enable == 0)
4171 ctls[cnt].enable = 1;
4172 ctls[cnt].widget = w;
4173 ctls[cnt].childwidget = cw;
4174 ctls[cnt].index = j;
4175 ctls[cnt].mute = mute;
4176 ctls[cnt].step = step;
4177 ctls[cnt].size = size;
4178 ctls[cnt].offset = offset;
4179 ctls[cnt].left = offset;
4180 ctls[cnt].right = offset;
4181 ctls[cnt++].dir = HDA_CTL_IN;
4186 device_printf(sc->dev,
4187 "%s: Ctl overflow!\n",
4191 ctls[cnt].enable = 1;
4192 ctls[cnt].widget = w;
4193 ctls[cnt].mute = mute;
4194 ctls[cnt].step = step;
4195 ctls[cnt].size = size;
4196 ctls[cnt].offset = offset;
4197 ctls[cnt].left = offset;
4198 ctls[cnt].right = offset;
4199 ctls[cnt++].dir = HDA_CTL_IN;
4205 devinfo->function.audio.ctl = ctls;
4208 static const struct {
4211 uint32_t set, unset;
4214 * XXX Force stereo quirk. Monoural recording / playback
4215 * on few codecs (especially ALC880) seems broken or
4216 * perhaps unsupported.
4218 { HDA_MATCH_ALL, HDA_MATCH_ALL,
4219 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4220 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4221 HDA_QUIRK_GPIO0, 0 },
4222 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4223 HDA_QUIRK_GPIO0, 0 },
4224 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4225 HDA_QUIRK_GPIO0, 0 },
4226 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4227 HDA_QUIRK_GPIO0, 0 },
4228 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4229 HDA_QUIRK_GPIO0, 0 },
4230 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4231 HDA_QUIRK_EAPDINV, 0 },
4232 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A,
4233 HDA_QUIRK_EAPDINV, 0 },
4234 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4235 HDA_QUIRK_OVREF, 0 },
4236 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861,
4237 HDA_QUIRK_OVREF, 0 },
4238 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4239 HDA_QUIRK_OVREF, 0 },
4240 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4241 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4242 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4243 HDA_QUIRK_GPIO1, 0 },
4244 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4245 HDA_QUIRK_EAPDINV, 0 },
4246 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4247 HDA_QUIRK_EAPDINV, 0 },
4248 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885,
4249 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0},
4250 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4251 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4252 { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4253 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4254 { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4255 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4256 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE,
4257 0, HDA_QUIRK_FORCESTEREO },
4258 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX,
4259 HDA_QUIRK_SOFTPCMVOL, 0 }
4261 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4264 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4266 struct hdac_widget *w;
4267 struct hdac_audio_ctl *ctl;
4268 uint32_t id, subvendor;
4271 id = hdac_codec_id(devinfo);
4272 subvendor = devinfo->codec->sc->pci_subvendor;
4277 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4278 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4279 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4281 if (hdac_quirks[i].set != 0)
4282 devinfo->function.audio.quirks |=
4284 if (hdac_quirks[i].unset != 0)
4285 devinfo->function.audio.quirks &=
4286 ~(hdac_quirks[i].unset);
4290 case HDA_CODEC_ALC260:
4291 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4292 w = hdac_widget_get(devinfo, i);
4293 if (w == NULL || w->enable == 0)
4296 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4301 if (subvendor == HP_XW4300_SUBVENDOR) {
4302 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4303 if (ctl != NULL && ctl->widget != NULL) {
4304 ctl->ossmask = SOUND_MASK_SPEAKER;
4305 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4307 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4308 if (ctl != NULL && ctl->widget != NULL) {
4309 ctl->ossmask = SOUND_MASK_SPEAKER;
4310 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4312 } else if (subvendor == HP_3010_SUBVENDOR) {
4313 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4314 if (ctl != NULL && ctl->widget != NULL) {
4315 ctl->ossmask = SOUND_MASK_SPEAKER;
4316 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4318 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1);
4319 if (ctl != NULL && ctl->widget != NULL) {
4320 ctl->ossmask = SOUND_MASK_SPEAKER;
4321 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4325 case HDA_CODEC_ALC268:
4326 if (HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, subvendor)) {
4327 w = hdac_widget_get(devinfo, 29);
4331 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET;
4332 w->param.widget_cap &=
4333 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
4334 w->param.widget_cap |=
4335 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
4336 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
4337 strlcpy(w->name, "beep widget", sizeof(w->name));
4341 case HDA_CODEC_ALC262:
4342 if (subvendor == HP_DC7700_SUBVENDOR) {
4343 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1);
4344 if (ctl != NULL && ctl->widget != NULL) {
4345 ctl->ossmask = SOUND_MASK_SPEAKER;
4346 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4348 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1);
4349 if (ctl != NULL && ctl->widget != NULL) {
4350 ctl->ossmask = SOUND_MASK_SPEAKER;
4351 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4355 case HDA_CODEC_ALC861:
4356 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1);
4358 ctl->muted = HDA_AMP_MUTE_ALL;
4360 case HDA_CODEC_ALC880:
4361 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4362 w = hdac_widget_get(devinfo, i);
4363 if (w == NULL || w->enable == 0)
4366 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4367 w->nid != 9 && w->nid != 29) {
4369 } else if (w->type !=
4370 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET &&
4373 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET;
4374 w->param.widget_cap &=
4375 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
4376 w->param.widget_cap |=
4377 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
4378 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
4379 strlcpy(w->name, "beep widget", sizeof(w->name));
4383 case HDA_CODEC_ALC883:
4385 * nid: 24/25 = External (jack) or Internal (fixed) Mic.
4386 * Clear vref cap for jack connectivity.
4388 w = hdac_widget_get(devinfo, 24);
4389 if (w != NULL && w->enable != 0 && w->type ==
4390 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4391 (w->wclass.pin.config &
4392 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4393 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4394 w->wclass.pin.cap &= ~(
4395 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4396 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4397 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4398 w = hdac_widget_get(devinfo, 25);
4399 if (w != NULL && w->enable != 0 && w->type ==
4400 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4401 (w->wclass.pin.config &
4402 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4403 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4404 w->wclass.pin.cap &= ~(
4405 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4406 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4407 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4409 * nid: 26 = Line-in, leave it alone.
4412 case HDA_CODEC_AD1981HD:
4413 w = hdac_widget_get(devinfo, 11);
4414 if (w != NULL && w->enable != 0 && w->nconns > 3)
4416 if (subvendor == IBM_M52_SUBVENDOR) {
4417 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1);
4419 ctl->ossmask = SOUND_MASK_SPEAKER;
4422 case HDA_CODEC_AD1986A:
4423 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4424 w = hdac_widget_get(devinfo, i);
4425 if (w == NULL || w->enable == 0)
4428 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4433 if (subvendor == ASUS_M2NPVMX_SUBVENDOR ||
4434 subvendor == ASUS_A8NVMCSM_SUBVENDOR) {
4435 /* nid 28 is mic, nid 29 is line-in */
4436 w = hdac_widget_get(devinfo, 15);
4439 w = hdac_widget_get(devinfo, 16);
4444 case HDA_CODEC_AD1988:
4445 case HDA_CODEC_AD1988B:
4446 /*w = hdac_widget_get(devinfo, 12);
4449 w->pflags |= HDA_ADC_LOCKED;
4451 w = hdac_widget_get(devinfo, 13);
4454 w->pflags |= HDA_ADC_LOCKED;
4456 w = hdac_widget_get(devinfo, 14);
4459 w->pflags |= HDA_ADC_LOCKED;
4461 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1);
4463 ctl->ossmask = SOUND_MASK_IGAIN;
4464 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4466 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1);
4468 ctl->ossmask = SOUND_MASK_IGAIN;
4469 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4471 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1);
4473 ctl->ossmask = SOUND_MASK_IGAIN;
4474 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4476 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1);
4478 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4479 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4481 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1);
4483 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4484 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4486 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1);
4488 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4489 ctl->widget->ctlflags |= SOUND_MASK_LINE;
4491 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1);
4493 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME;
4494 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4497 case HDA_CODEC_STAC9221:
4499 * Dell XPS M1210 need all DACs for each output jacks
4501 if (subvendor == DELL_XPSM1210_SUBVENDOR)
4503 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4504 w = hdac_widget_get(devinfo, i);
4505 if (w == NULL || w->enable == 0)
4508 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4514 case HDA_CODEC_STAC9221D:
4515 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4516 w = hdac_widget_get(devinfo, i);
4517 if (w == NULL || w->enable == 0)
4520 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4526 case HDA_CODEC_STAC9227:
4527 w = hdac_widget_get(devinfo, 8);
4530 w = hdac_widget_get(devinfo, 9);
4534 case HDA_CODEC_CXWAIKIKI:
4535 if (subvendor == HP_DV5000_SUBVENDOR) {
4536 w = hdac_widget_get(devinfo, 27);
4540 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4542 ctl->ossmask = SOUND_MASK_SKIP;
4543 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1);
4544 if (ctl != NULL && ctl->childwidget != NULL &&
4545 ctl->childwidget->enable != 0) {
4546 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME;
4547 ctl->childwidget->ctlflags |= SOUND_MASK_PCM;
4549 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1);
4550 if (ctl != NULL && ctl->childwidget != NULL &&
4551 ctl->childwidget->enable != 0) {
4552 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4553 ctl->childwidget->ctlflags |= SOUND_MASK_LINE;
4555 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1);
4556 if (ctl != NULL && ctl->childwidget != NULL &&
4557 ctl->childwidget->enable != 0) {
4558 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4559 ctl->childwidget->ctlflags |= SOUND_MASK_MIC;
4561 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1);
4563 ctl->ossmask = SOUND_MASK_SKIP;
4564 /* XXX mixer \=rec mic broken.. why?!? */
4565 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */
4574 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo)
4576 int *dev = &devinfo->function.audio.ossidx;
4578 while (*dev < SOUND_MIXER_NRDEVICES) {
4580 case SOUND_MIXER_VOLUME:
4581 case SOUND_MIXER_BASS:
4582 case SOUND_MIXER_TREBLE:
4583 case SOUND_MIXER_PCM:
4584 case SOUND_MIXER_SPEAKER:
4585 case SOUND_MIXER_LINE:
4586 case SOUND_MIXER_MIC:
4587 case SOUND_MIXER_CD:
4588 case SOUND_MIXER_RECLEV:
4589 case SOUND_MIXER_IGAIN:
4590 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */
4603 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4605 struct hdac_widget *w;
4608 if (depth > HDA_PARSE_MAXDEPTH)
4610 w = hdac_widget_get(devinfo, nid);
4611 if (w == NULL || w->enable == 0)
4614 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
4615 w->pflags |= HDA_DAC_PATH;
4618 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4619 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4620 for (i = 0; i < w->nconns; i++) {
4621 if (hdac_widget_find_dac_path(devinfo,
4622 w->conns[i], depth + 1) != 0) {
4623 if (w->selconn == -1)
4626 w->pflags |= HDA_DAC_PATH;
4637 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4639 struct hdac_widget *w;
4640 int i, conndev, ret = 0;
4642 if (depth > HDA_PARSE_MAXDEPTH)
4644 w = hdac_widget_get(devinfo, nid);
4645 if (w == NULL || w->enable == 0)
4648 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
4649 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4650 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4651 for (i = 0; i < w->nconns; i++) {
4652 if (hdac_widget_find_adc_path(devinfo, w->conns[i],
4654 if (w->selconn == -1)
4656 w->pflags |= HDA_ADC_PATH;
4661 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
4662 conndev = w->wclass.pin.config &
4663 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4664 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4665 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD ||
4666 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN ||
4667 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) {
4668 w->pflags |= HDA_ADC_PATH;
4672 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4673 if (w->pflags & HDA_DAC_PATH) {
4674 w->pflags |= HDA_ADC_PATH;
4685 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo,
4686 nid_t nid, nid_t pnid, int index, int depth)
4688 struct hdac_widget *w, *pw;
4689 struct hdac_audio_ctl *ctl;
4691 int i, ossdev, conndev, strategy;
4693 if (depth > HDA_PARSE_MAXDEPTH)
4696 w = hdac_widget_get(devinfo, nid);
4697 if (w == NULL || w->enable == 0)
4700 pw = hdac_widget_get(devinfo, pnid);
4701 strategy = devinfo->function.audio.parsing_strategy;
4703 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER
4704 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) {
4705 for (i = 0; i < w->nconns; i++) {
4706 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i],
4707 w->nid, i, depth + 1);
4711 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
4712 (w->pflags & HDA_DAC_PATH)) {
4714 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4715 if (ctl->enable == 0 || ctl->widget == NULL)
4717 /* XXX This should be compressed! */
4718 if (((ctl->widget->nid == w->nid) ||
4719 (ctl->widget->nid == pnid && ctl->index == index &&
4720 (ctl->dir & HDA_CTL_IN)) ||
4721 (ctl->widget->nid == pnid && pw != NULL &&
4723 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4724 (pw->nconns < 2 || pw->selconn == index ||
4725 pw->selconn == -1) &&
4726 (ctl->dir & HDA_CTL_OUT)) ||
4727 (strategy == HDA_PARSE_DIRECT &&
4728 ctl->widget->nid == w->nid)) &&
4729 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4730 /*if (pw != NULL && pw->selconn == -1)
4731 pw->selconn = index;
4732 fl |= SOUND_MASK_VOLUME;
4733 fl |= SOUND_MASK_PCM;
4734 ctl->ossmask |= SOUND_MASK_VOLUME;
4735 ctl->ossmask |= SOUND_MASK_PCM;
4736 ctl->ossdev = SOUND_MIXER_PCM;*/
4737 if (!(w->ctlflags & SOUND_MASK_PCM) ||
4739 !(pw->ctlflags & SOUND_MASK_PCM))) {
4740 fl |= SOUND_MASK_VOLUME;
4741 fl |= SOUND_MASK_PCM;
4742 ctl->ossmask |= SOUND_MASK_VOLUME;
4743 ctl->ossmask |= SOUND_MASK_PCM;
4744 ctl->ossdev = SOUND_MIXER_PCM;
4745 w->ctlflags |= SOUND_MASK_VOLUME;
4746 w->ctlflags |= SOUND_MASK_PCM;
4748 if (pw->selconn == -1)
4749 pw->selconn = index;
4760 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4761 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4762 (w->pflags & HDA_ADC_PATH)) {
4763 conndev = w->wclass.pin.config &
4764 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4766 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4767 if (ctl->enable == 0 || ctl->widget == NULL)
4769 /* XXX This should be compressed! */
4770 if (((ctl->widget->nid == pnid && ctl->index == index &&
4771 (ctl->dir & HDA_CTL_IN)) ||
4772 (ctl->widget->nid == pnid && pw != NULL &&
4774 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4775 (pw->nconns < 2 || pw->selconn == index ||
4776 pw->selconn == -1) &&
4777 (ctl->dir & HDA_CTL_OUT)) ||
4778 (strategy == HDA_PARSE_DIRECT &&
4779 ctl->widget->nid == w->nid)) &&
4780 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4781 if (pw != NULL && pw->selconn == -1)
4782 pw->selconn = index;
4785 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
4786 ossdev = SOUND_MIXER_MIC;
4788 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
4789 ossdev = SOUND_MIXER_LINE;
4791 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
4792 ossdev = SOUND_MIXER_CD;
4796 hdac_audio_ctl_ossmixer_getnextdev(
4802 if (strategy == HDA_PARSE_MIXER) {
4803 fl |= SOUND_MASK_VOLUME;
4804 ctl->ossmask |= SOUND_MASK_VOLUME;
4807 ctl->ossmask |= 1 << ossdev;
4808 ctl->ossdev = ossdev;
4813 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4815 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4816 if (ctl->enable == 0 || ctl->widget == NULL)
4818 /* XXX This should be compressed! */
4819 if (((ctl->widget->nid == pnid && ctl->index == index &&
4820 (ctl->dir & HDA_CTL_IN)) ||
4821 (ctl->widget->nid == pnid && pw != NULL &&
4823 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4824 (pw->nconns < 2 || pw->selconn == index ||
4825 pw->selconn == -1) &&
4826 (ctl->dir & HDA_CTL_OUT)) ||
4827 (strategy == HDA_PARSE_DIRECT &&
4828 ctl->widget->nid == w->nid)) &&
4829 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4830 if (pw != NULL && pw->selconn == -1)
4831 pw->selconn = index;
4832 fl |= SOUND_MASK_VOLUME;
4833 fl |= SOUND_MASK_SPEAKER;
4834 ctl->ossmask |= SOUND_MASK_VOLUME;
4835 ctl->ossmask |= SOUND_MASK_SPEAKER;
4836 ctl->ossdev = SOUND_MIXER_SPEAKER;
4846 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4848 struct hdac_widget *w, *cw;
4849 struct hdac_audio_ctl *ctl;
4853 if (depth > HDA_PARSE_MAXDEPTH)
4856 w = hdac_widget_get(devinfo, nid);
4857 if (w == NULL || w->enable == 0)
4859 /*if (!(w->pflags & HDA_ADC_PATH))
4861 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4862 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4865 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4866 if (ctl->enable == 0 || ctl->widget == NULL)
4868 if (ctl->widget->nid == nid) {
4869 ctl->ossmask |= SOUND_MASK_RECLEV;
4870 w->ctlflags |= SOUND_MASK_RECLEV;
4871 return (SOUND_MASK_RECLEV);
4874 for (i = 0; i < w->nconns; i++) {
4875 cw = hdac_widget_get(devinfo, w->conns[i]);
4876 if (cw == NULL || cw->enable == 0)
4878 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4880 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1);
4891 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4893 struct hdac_widget *w, *cw;
4896 if (depth > HDA_PARSE_MAXDEPTH)
4899 w = hdac_widget_get(devinfo, nid);
4900 if (w == NULL || w->enable == 0)
4902 /*if (!(w->pflags & HDA_ADC_PATH))
4904 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4905 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4908 for (i = 0; i < w->nconns; i++) {
4909 cw = hdac_widget_get(devinfo, w->conns[i]);
4913 w->pflags |= HDA_ADC_RECSEL;
4917 for (i = 0; i < w->nconns; i++) {
4918 if (hdac_audio_ctl_recsel_build(devinfo,
4919 w->conns[i], depth + 1) != 0)
4926 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo)
4928 struct hdac_widget *w, *cw;
4929 int i, j, conndev, found_dac = 0;
4932 strategy = devinfo->function.audio.parsing_strategy;
4934 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4935 w = hdac_widget_get(devinfo, i);
4936 if (w == NULL || w->enable == 0)
4938 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4940 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap))
4942 conndev = w->wclass.pin.config &
4943 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4944 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4945 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4946 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT))
4948 for (j = 0; j < w->nconns; j++) {
4949 cw = hdac_widget_get(devinfo, w->conns[j]);
4950 if (cw == NULL || cw->enable == 0)
4952 if (strategy == HDA_PARSE_MIXER && !(cw->type ==
4953 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4955 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4957 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0)
4959 if (w->selconn == -1)
4961 w->pflags |= HDA_DAC_PATH;
4971 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
4973 struct hdac_widget *w;
4974 struct hdac_audio_ctl *ctl;
4975 int i, j, dacs, strategy;
4977 /* Construct DAC path */
4978 strategy = HDA_PARSE_MIXER;
4979 devinfo->function.audio.parsing_strategy = strategy;
4981 device_printf(devinfo->codec->sc->dev,
4982 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n",
4983 HDA_WIDGET_PARSER_REV);
4985 dacs = hdac_audio_build_tree_strategy(devinfo);
4988 device_printf(devinfo->codec->sc->dev,
4989 "HDA_DEBUG: HWiP: 0 DAC path found! "
4991 "using HDA_PARSE_DIRECT strategy.\n");
4993 strategy = HDA_PARSE_DIRECT;
4994 devinfo->function.audio.parsing_strategy = strategy;
4995 dacs = hdac_audio_build_tree_strategy(devinfo);
4999 device_printf(devinfo->codec->sc->dev,
5000 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s "
5002 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT");
5005 /* Construct ADC path */
5006 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5007 w = hdac_widget_get(devinfo, i);
5008 if (w == NULL || w->enable == 0)
5010 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
5012 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0);
5016 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5017 w = hdac_widget_get(devinfo, i);
5018 if (w == NULL || w->enable == 0)
5020 if ((strategy == HDA_PARSE_MIXER &&
5021 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
5022 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
5023 && (w->pflags & HDA_DAC_PATH)) ||
5024 (strategy == HDA_PARSE_DIRECT && (w->pflags &
5025 (HDA_DAC_PATH | HDA_ADC_PATH)))) {
5026 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo,
5027 w->nid, devinfo->startnode - 1, 0, 0);
5028 } else if (w->type ==
5029 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
5031 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) !=
5033 if (ctl->enable == 0 || ctl->widget == NULL)
5035 if (ctl->widget->nid != w->nid)
5037 ctl->ossmask |= SOUND_MASK_VOLUME;
5038 ctl->ossmask |= SOUND_MASK_SPEAKER;
5039 ctl->ossdev = SOUND_MIXER_SPEAKER;
5040 w->ctlflags |= SOUND_MASK_VOLUME;
5041 w->ctlflags |= SOUND_MASK_SPEAKER;
5046 /* Input mixers (rec) */
5047 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5048 w = hdac_widget_get(devinfo, i);
5049 if (w == NULL || w->enable == 0)
5051 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
5052 w->pflags & HDA_ADC_PATH))
5054 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0);
5055 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0);
5059 #define HDA_COMMIT_CONN (1 << 0)
5060 #define HDA_COMMIT_CTRL (1 << 1)
5061 #define HDA_COMMIT_EAPD (1 << 2)
5062 #define HDA_COMMIT_GPIO (1 << 3)
5063 #define HDA_COMMIT_MISC (1 << 4)
5064 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \
5065 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC)
5068 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl)
5070 struct hdac_softc *sc = devinfo->codec->sc;
5071 struct hdac_widget *w;
5075 if (!(cfl & HDA_COMMIT_ALL))
5078 cad = devinfo->codec->cad;
5080 if ((cfl & HDA_COMMIT_MISC)) {
5081 if (sc->pci_subvendor == APPLE_INTEL_MAC)
5082 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
5086 if (cfl & HDA_COMMIT_GPIO) {
5087 uint32_t gdata, gmask, gdir;
5088 int commitgpio, numgpio;
5095 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
5096 devinfo->function.audio.gpio);
5098 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
5099 commitgpio = (numgpio > 0) ? 1 : 0;
5101 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
5102 if (!(devinfo->function.audio.quirks &
5105 if (commitgpio == 0) {
5108 gdata = hdac_command(sc,
5109 HDA_CMD_GET_GPIO_DATA(cad,
5110 devinfo->nid), cad);
5111 gmask = hdac_command(sc,
5112 HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
5113 devinfo->nid), cad);
5114 gdir = hdac_command(sc,
5115 HDA_CMD_GET_GPIO_DIRECTION(cad,
5116 devinfo->nid), cad);
5117 device_printf(sc->dev,
5118 "GPIO init: data=0x%08x "
5119 "mask=0x%08x dir=0x%08x\n",
5120 gdata, gmask, gdir);
5132 if (commitgpio != 0) {
5134 device_printf(sc->dev,
5135 "GPIO commit: data=0x%08x mask=0x%08x "
5137 gdata, gmask, gdir);
5140 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
5143 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
5146 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
5151 for (i = 0; i < devinfo->nodecnt; i++) {
5152 w = &devinfo->widget[i];
5153 if (w == NULL || w->enable == 0)
5155 if (cfl & HDA_COMMIT_CONN) {
5156 if (w->selconn == -1)
5159 hdac_widget_connection_select(w, w->selconn);
5161 if ((cfl & HDA_COMMIT_CTRL) &&
5162 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5165 pincap = w->wclass.pin.cap;
5167 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) ==
5168 (HDA_DAC_PATH | HDA_ADC_PATH))
5169 device_printf(sc->dev, "WARNING: node %d "
5170 "participate both for DAC/ADC!\n", w->nid);
5171 if (w->pflags & HDA_DAC_PATH) {
5172 w->wclass.pin.ctrl &=
5173 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
5174 if ((w->wclass.pin.config &
5175 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) !=
5176 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
5177 w->wclass.pin.ctrl &=
5178 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
5179 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
5180 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5181 w->wclass.pin.ctrl |=
5182 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5183 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5184 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
5185 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5186 w->wclass.pin.ctrl |=
5187 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5188 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5189 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
5190 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5191 w->wclass.pin.ctrl |=
5192 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5193 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5194 } else if (w->pflags & HDA_ADC_PATH) {
5195 w->wclass.pin.ctrl &=
5196 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5197 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE);
5198 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
5199 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5200 w->wclass.pin.ctrl |=
5201 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5202 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5203 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
5204 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5205 w->wclass.pin.ctrl |=
5206 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5207 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5208 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
5209 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5210 w->wclass.pin.ctrl |=
5211 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5212 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5214 w->wclass.pin.ctrl &= ~(
5215 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
5216 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5217 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
5218 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
5220 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
5221 w->wclass.pin.ctrl), cad);
5223 if ((cfl & HDA_COMMIT_EAPD) &&
5224 w->param.eapdbtl != HDAC_INVALID) {
5227 val = w->param.eapdbtl;
5228 if (devinfo->function.audio.quirks &
5230 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
5232 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
5241 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
5243 struct hdac_softc *sc = devinfo->codec->sc;
5244 struct hdac_audio_ctl *ctl;
5247 devinfo->function.audio.mvol = 100 | (100 << 8);
5249 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5250 if (ctl->enable == 0 || ctl->widget == NULL) {
5252 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5253 i, (ctl->widget != NULL) ?
5254 ctl->widget->nid : -1);
5255 if (ctl->childwidget != NULL)
5256 kprintf(" childnid=%d",
5257 ctl->childwidget->nid);
5258 if (ctl->widget == NULL)
5259 kprintf(" NULL WIDGET!");
5260 kprintf(" DISABLED\n");
5265 if (ctl->ossmask == 0) {
5266 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5267 i, ctl->widget->nid);
5268 if (ctl->childwidget != NULL)
5269 kprintf(" childnid=%d",
5270 ctl->childwidget->nid);
5271 kprintf(" Bind to NONE\n");
5274 if (ctl->step > 0) {
5275 ctl->ossval = (ctl->left * 100) / ctl->step;
5276 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8;
5279 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
5280 ctl->left, ctl->right);
5285 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir)
5287 struct hdac_chan *ch;
5288 struct hdac_widget *w;
5289 uint32_t cap, fmtcap, pcmcap, path;
5290 int i, type, ret, max;
5292 if (dir == PCMDIR_PLAY) {
5293 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT;
5294 ch = &devinfo->codec->sc->play;
5295 path = HDA_DAC_PATH;
5297 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT;
5298 ch = &devinfo->codec->sc->rec;
5299 path = HDA_ADC_PATH;
5302 ch->caps = hdac_caps;
5303 ch->caps.fmtlist = ch->fmtlist;
5306 ch->pcmrates[0] = 48000;
5307 ch->pcmrates[1] = 0;
5310 fmtcap = devinfo->function.audio.supp_stream_formats;
5311 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
5312 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1;
5314 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) {
5315 w = hdac_widget_get(devinfo, i);
5316 if (w == NULL || w->enable == 0 || w->type != type ||
5317 !(w->pflags & path))
5319 cap = w->param.widget_cap;
5320 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap))
5322 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap))
5324 cap = w->param.supp_stream_formats;
5325 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) {
5327 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) {
5329 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5332 fmtcap = w->param.supp_stream_formats;
5333 pcmcap = w->param.supp_pcm_size_rate;
5335 fmtcap &= w->param.supp_stream_formats;
5336 pcmcap &= w->param.supp_pcm_size_rate;
5342 ch->supp_stream_formats = fmtcap;
5343 ch->supp_pcm_size_rate = pcmcap;
5354 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5356 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5358 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5360 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5362 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5365 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO))
5366 ch->fmtlist[i++] = AFMT_S16_LE;
5367 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO;
5368 if (ch->bit32 > 0) {
5369 if (!(devinfo->function.audio.quirks &
5370 HDA_QUIRK_FORCESTEREO))
5371 ch->fmtlist[i++] = AFMT_S32_LE;
5372 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO;
5376 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5377 ch->pcmrates[i++] = 8000;
5378 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5379 ch->pcmrates[i++] = 11025;
5380 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5381 ch->pcmrates[i++] = 16000;
5382 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5383 ch->pcmrates[i++] = 22050;
5384 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5385 ch->pcmrates[i++] = 32000;
5386 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5387 ch->pcmrates[i++] = 44100;
5388 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */
5389 ch->pcmrates[i++] = 48000;
5390 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5391 ch->pcmrates[i++] = 88200;
5392 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5393 ch->pcmrates[i++] = 96000;
5394 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5395 ch->pcmrates[i++] = 176400;
5396 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5397 ch->pcmrates[i++] = 192000;
5398 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */
5399 ch->pcmrates[i] = 0;
5401 ch->caps.minspeed = ch->pcmrates[0];
5402 ch->caps.maxspeed = ch->pcmrates[i - 1];
5410 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag)
5412 struct hdac_audio_ctl *ctl;
5413 struct hdac_softc *sc = devinfo->codec->sc;
5419 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM |
5420 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
5421 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN;
5425 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5426 if (ctl->enable == 0 || ctl->widget == NULL ||
5427 ctl->widget->enable == 0 || (ctl->ossmask &
5428 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)))
5430 if ((flag == 0 && (ctl->ossmask & ~fl)) ||
5431 (flag != 0 && (ctl->ossmask & flag))) {
5432 if (banner != NULL) {
5433 device_printf(sc->dev, "\n");
5434 device_printf(sc->dev, "%s\n", banner);
5436 goto hdac_ctl_dump_it_all;
5442 hdac_ctl_dump_it_all:
5444 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5445 if (ctl->enable == 0 || ctl->widget == NULL ||
5446 ctl->widget->enable == 0)
5448 if (!((flag == 0 && (ctl->ossmask & ~fl)) ||
5449 (flag != 0 && (ctl->ossmask & flag))))
5452 device_printf(sc->dev, "\n");
5453 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n",
5454 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask));
5456 device_printf(sc->dev, " |\n");
5457 device_printf(sc->dev, " +- nid: %2d index: %2d ",
5458 ctl->widget->nid, ctl->index);
5459 if (ctl->childwidget != NULL)
5460 kprintf("(nid: %2d) ", ctl->childwidget->nid);
5463 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n",
5464 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir,
5470 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap)
5476 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap);
5477 device_printf(sc->dev, " Format:");
5478 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
5480 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
5481 kprintf(" FLOAT32");
5482 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5488 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap);
5489 device_printf(sc->dev, " PCM size:");
5490 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5492 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5494 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5496 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5498 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5501 device_printf(sc->dev, " PCM rate:");
5502 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5504 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5506 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5508 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5510 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5512 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5515 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5517 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5519 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5521 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5528 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
5530 uint32_t pincap, wcap;
5532 pincap = w->wclass.pin.cap;
5533 wcap = w->param.widget_cap;
5535 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
5536 device_printf(sc->dev, " ");
5537 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
5539 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
5541 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
5543 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
5545 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
5547 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
5549 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
5551 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
5553 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5555 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5557 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5559 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
5561 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
5565 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
5567 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap))
5568 kprintf(" : UNSOL");
5570 device_printf(sc->dev, " Pin config: 0x%08x\n",
5571 w->wclass.pin.config);
5572 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
5573 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
5575 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
5577 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
5583 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
5585 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
5586 device_printf(sc->dev, " "
5587 "mute=%d step=%d size=%d offset=%d\n",
5588 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
5589 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
5590 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
5591 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
5595 hdac_dump_nodes(struct hdac_devinfo *devinfo)
5597 struct hdac_softc *sc = devinfo->codec->sc;
5598 struct hdac_widget *w, *cw;
5601 device_printf(sc->dev, "\n");
5602 device_printf(sc->dev, "Default Parameter\n");
5603 device_printf(sc->dev, "-----------------\n");
5604 hdac_dump_audio_formats(sc,
5605 devinfo->function.audio.supp_stream_formats,
5606 devinfo->function.audio.supp_pcm_size_rate);
5607 device_printf(sc->dev, " IN amp: 0x%08x\n",
5608 devinfo->function.audio.inamp_cap);
5609 device_printf(sc->dev, " OUT amp: 0x%08x\n",
5610 devinfo->function.audio.outamp_cap);
5611 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5612 w = hdac_widget_get(devinfo, i);
5614 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
5617 device_printf(sc->dev, "\n");
5618 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid,
5619 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ?
5620 "DIGITAL" : "ANALOG",
5621 (w->enable == 0) ? " [DISABLED]" : "");
5622 device_printf(sc->dev, " name: %s\n", w->name);
5623 device_printf(sc->dev, " widget_cap: 0x%08x\n",
5624 w->param.widget_cap);
5625 device_printf(sc->dev, " Parse flags: 0x%08x\n",
5627 device_printf(sc->dev, " Ctl flags: 0x%08x\n",
5629 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
5630 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
5631 hdac_dump_audio_formats(sc,
5632 w->param.supp_stream_formats,
5633 w->param.supp_pcm_size_rate);
5634 } else if (w->type ==
5635 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5636 hdac_dump_pin(sc, w);
5637 if (w->param.eapdbtl != HDAC_INVALID)
5638 device_printf(sc->dev, " EAPD: 0x%08x\n",
5640 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
5641 w->param.outamp_cap != 0)
5642 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
5643 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
5644 w->param.inamp_cap != 0)
5645 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
5646 device_printf(sc->dev, " connections: %d\n", w->nconns);
5647 for (j = 0; j < w->nconns; j++) {
5648 cw = hdac_widget_get(devinfo, w->conns[j]);
5649 device_printf(sc->dev, " |\n");
5650 device_printf(sc->dev, " + <- nid=%d [%s]",
5651 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
5653 kprintf(" [UNKNOWN]");
5654 else if (cw->enable == 0)
5655 kprintf(" [DISABLED]");
5656 if (w->nconns > 1 && w->selconn == j && w->type !=
5657 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5658 kprintf(" (selected)");
5666 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5668 struct hdac_widget *w, *cw;
5669 struct hdac_softc *sc = devinfo->codec->sc;
5672 if (depth > HDA_PARSE_MAXDEPTH)
5675 w = hdac_widget_get(devinfo, nid);
5676 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH))
5679 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5680 device_printf(sc->dev, "\n");
5681 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5682 device_printf(sc->dev, " ^\n");
5683 device_printf(sc->dev, " |\n");
5684 device_printf(sc->dev, " +-----<------+\n");
5686 device_printf(sc->dev, " ^\n");
5687 device_printf(sc->dev, " |\n");
5688 device_printf(sc->dev, " ");
5689 kprintf(" nid=%d [%s]\n", w->nid, w->name);
5692 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) {
5694 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
5695 for (i = 0; i < w->nconns; i++) {
5696 cw = hdac_widget_get(devinfo, w->conns[i]);
5697 if (cw == NULL || cw->enable == 0 || cw->type ==
5698 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5700 if (hdac_dump_dac_internal(devinfo, cw->nid,
5704 } else if ((w->type ==
5705 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR ||
5706 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5707 w->selconn > -1 && w->selconn < w->nconns) {
5708 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn],
5717 hdac_dump_dac(struct hdac_devinfo *devinfo)
5719 struct hdac_widget *w;
5720 struct hdac_softc *sc = devinfo->codec->sc;
5723 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5724 w = hdac_widget_get(devinfo, i);
5725 if (w == NULL || w->enable == 0)
5727 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
5728 !(w->pflags & HDA_DAC_PATH))
5732 device_printf(sc->dev, "\n");
5733 device_printf(sc->dev, "Playback path:\n");
5735 hdac_dump_dac_internal(devinfo, w->nid, 0);
5740 hdac_dump_adc(struct hdac_devinfo *devinfo)
5742 struct hdac_widget *w, *cw;
5743 struct hdac_softc *sc = devinfo->codec->sc;
5748 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5749 w = hdac_widget_get(devinfo, i);
5750 if (w == NULL || w->enable == 0)
5752 if (!(w->pflags & HDA_ADC_RECSEL))
5756 device_printf(sc->dev, "\n");
5757 device_printf(sc->dev, "Recording sources:\n");
5759 device_printf(sc->dev, "\n");
5760 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5761 for (j = 0; j < w->nconns; j++) {
5762 cw = hdac_widget_get(devinfo, w->conns[j]);
5763 if (cw == NULL || cw->enable == 0)
5765 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags,
5766 ossdevs, sizeof(ossdevs));
5767 device_printf(sc->dev, " |\n");
5768 device_printf(sc->dev, " + <- nid=%d [%s]",
5770 if (strlen(ossdevs) > 0) {
5771 kprintf(" [recsrc: %s]", ossdevs);
5779 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt)
5784 device_printf(sc->dev, "\n");
5785 device_printf(sc->dev, " PCM Playback: %d\n", pcnt);
5786 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5787 sc->play.supp_pcm_size_rate);
5788 device_printf(sc->dev, " DAC:");
5789 for (nids = sc->play.io; *nids != -1; nids++)
5790 kprintf(" %d", *nids);
5795 device_printf(sc->dev, "\n");
5796 device_printf(sc->dev, " PCM Record: %d\n", rcnt);
5797 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5798 sc->rec.supp_pcm_size_rate);
5799 device_printf(sc->dev, " ADC:");
5800 for (nids = sc->rec.io; *nids != -1; nids++)
5801 kprintf(" %d", *nids);
5807 hdac_release_resources(struct hdac_softc *sc)
5809 struct hdac_devinfo *devinfo = NULL;
5810 device_t *devlist = NULL;
5819 callout_stop(&sc->poll_hda);
5820 callout_stop(&sc->poll_hdac);
5821 callout_stop(&sc->poll_jack);
5827 /* give pending interrupts stuck on the lock a chance to clear */
5829 tsleep(&sc->irq, 0, "hdaslp", hz / 10);
5831 device_get_children(sc->dev, &devlist, &devcount);
5832 for (i = 0; devlist != NULL && i < devcount; i++) {
5833 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
5834 if (devinfo == NULL)
5836 if (devinfo->widget != NULL)
5837 kfree(devinfo->widget, M_HDAC);
5838 if (devinfo->node_type ==
5839 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
5840 devinfo->function.audio.ctl != NULL)
5841 kfree(devinfo->function.audio.ctl, M_HDAC);
5842 kfree(devinfo, M_HDAC);
5843 device_delete_child(sc->dev, devlist[i]);
5845 if (devlist != NULL)
5846 kfree(devlist, M_TEMP);
5848 for (i = 0; i < HDAC_CODEC_MAX; i++) {
5849 if (sc->codecs[i] != NULL)
5850 kfree(sc->codecs[i], M_HDAC);
5851 sc->codecs[i] = NULL;
5854 hdac_dma_free(sc, &sc->pos_dma);
5855 hdac_dma_free(sc, &sc->rirb_dma);
5856 hdac_dma_free(sc, &sc->corb_dma);
5857 if (sc->play.blkcnt > 0)
5858 hdac_dma_free(sc, &sc->play.bdl_dma);
5859 if (sc->rec.blkcnt > 0)
5860 hdac_dma_free(sc, &sc->rec.bdl_dma);
5861 if (sc->chan_dmat != NULL) {
5862 bus_dma_tag_destroy(sc->chan_dmat);
5863 sc->chan_dmat = NULL;
5866 snd_mtxfree(sc->lock);
5867 kfree(sc, M_DEVBUF);
5870 /* This function surely going to make its way into upper level someday. */
5872 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
5875 int i = 0, j, k, len, inv;
5883 if (resource_string_value(device_get_name(sc->dev),
5884 device_get_unit(sc->dev), "config", &res) != 0)
5886 if (!(res != NULL && strlen(res) > 0))
5889 device_printf(sc->dev, "HDA_DEBUG: HDA Config:");
5892 while (res[i] != '\0' &&
5893 (res[i] == ',' || isspace(res[i]) != 0))
5895 if (res[i] == '\0') {
5902 while (res[j] != '\0' &&
5903 !(res[j] == ',' || isspace(res[j]) != 0))
5906 if (len > 2 && strncmp(res + i, "no", 2) == 0)
5910 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
5911 if (strncmp(res + i + inv,
5912 hdac_quirks_tab[k].key, len - inv) != 0)
5914 if (len - inv != strlen(hdac_quirks_tab[k].key))
5917 kprintf(" %s%s", (inv != 0) ? "no" : "",
5918 hdac_quirks_tab[k].key);
5920 if (inv == 0 && on != NULL)
5921 *on |= hdac_quirks_tab[k].value;
5922 else if (inv != 0 && off != NULL)
5923 *off |= hdac_quirks_tab[k].value;
5930 #ifdef SND_DYNSYSCTL
5932 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
5934 struct hdac_softc *sc;
5935 struct hdac_devinfo *devinfo;
5940 dev = oidp->oid_arg1;
5941 devinfo = pcm_getdevinfo(dev);
5942 if (devinfo == NULL || devinfo->codec == NULL ||
5943 devinfo->codec->sc == NULL)
5945 sc = devinfo->codec->sc;
5949 err = sysctl_handle_int(oidp, &val, 0, req);
5951 if (err != 0 || req->newptr == NULL)
5953 if (val < 0 || val > 1)
5957 if (val != sc->polling) {
5958 if (hda_chan_active(sc) != 0)
5960 else if (val == 0) {
5961 callout_stop(&sc->poll_hdac);
5964 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT,
5966 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5967 ctl |= HDAC_RIRBCTL_RINTCTL;
5968 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5969 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
5970 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
5974 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0);
5975 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0);
5976 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5977 ctl &= ~HDAC_RIRBCTL_RINTCTL;
5978 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5979 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback,
5991 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS)
5993 struct hdac_softc *sc;
5994 struct hdac_devinfo *devinfo;
5998 dev = oidp->oid_arg1;
5999 devinfo = pcm_getdevinfo(dev);
6000 if (devinfo == NULL || devinfo->codec == NULL ||
6001 devinfo->codec->sc == NULL)
6003 sc = devinfo->codec->sc;
6005 val = ((uint64_t)sc->poll_ival * 1000) / hz;
6007 err = sysctl_handle_int(oidp, &val, 0, req);
6009 if (err != 0 || req->newptr == NULL)
6016 val = ((uint64_t)val * hz) / 1000;
6023 sc->poll_ival = val;
6031 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
6033 struct hdac_softc *sc;
6034 struct hdac_devinfo *devinfo;
6035 struct hdac_widget *w;
6037 uint32_t res, pincap, execres;
6041 dev = oidp->oid_arg1;
6042 devinfo = pcm_getdevinfo(dev);
6043 if (devinfo == NULL || devinfo->codec == NULL ||
6044 devinfo->codec->sc == NULL)
6047 err = sysctl_handle_int(oidp, &val, 0, req);
6048 if (err != 0 || req->newptr == NULL || val == 0)
6050 sc = devinfo->codec->sc;
6051 cad = devinfo->codec->cad;
6053 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid);
6054 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6055 w = hdac_widget_get(devinfo, i);
6056 if (w == NULL || w->type !=
6057 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6059 pincap = w->wclass.pin.cap;
6060 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) ||
6061 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) &&
6062 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) {
6065 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad);
6067 res = hdac_command(sc,
6068 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
6069 if (res != 0x7fffffff)
6072 } while (--timeout != 0);
6075 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad,
6079 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n",
6080 w->nid, timeout, res,
6081 (w->enable == 0) ? "DISABLED" : "ENABLED");
6084 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
6085 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
6086 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
6087 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
6088 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
6089 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
6090 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) {
6091 device_printf(dev, " GPI:");
6092 res = hdac_command(sc,
6093 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad);
6094 kprintf(" data=0x%08x", res);
6095 res = hdac_command(sc,
6096 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid),
6098 kprintf(" wake=0x%08x", res);
6099 res = hdac_command(sc,
6100 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
6102 kprintf(" unsol=0x%08x", res);
6103 res = hdac_command(sc,
6104 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad);
6105 kprintf(" sticky=0x%08x\n", res);
6107 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) {
6108 device_printf(dev, " GPO:");
6109 res = hdac_command(sc,
6110 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad);
6111 kprintf(" data=0x%08x\n", res);
6113 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) {
6114 device_printf(dev, "GPI0:");
6115 res = hdac_command(sc,
6116 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad);
6117 kprintf(" data=0x%08x", res);
6118 res = hdac_command(sc,
6119 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad);
6120 kprintf(" enable=0x%08x", res);
6121 res = hdac_command(sc,
6122 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad);
6123 kprintf(" direction=0x%08x\n", res);
6124 res = hdac_command(sc,
6125 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad);
6126 device_printf(dev, " wake=0x%08x", res);
6127 res = hdac_command(sc,
6128 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
6130 kprintf(" unsol=0x%08x", res);
6131 res = hdac_command(sc,
6132 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad);
6133 kprintf(" sticky=0x%08x\n", res);
6142 hdac_attach2(void *arg)
6144 struct hdac_softc *sc;
6145 struct hdac_widget *w;
6146 struct hdac_audio_ctl *ctl;
6147 uint32_t quirks_on, quirks_off;
6148 int pcnt, rcnt, codec_index;
6150 char status[SND_STATUSLEN];
6151 device_t *devlist = NULL;
6153 struct hdac_devinfo *devinfo = NULL;
6155 sc = (struct hdac_softc *)arg;
6157 hdac_config_fetch(sc, &quirks_on, &quirks_off);
6160 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n",
6161 quirks_on, quirks_off);
6164 if (resource_int_value(device_get_name(sc->dev),
6165 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) {
6166 switch (sc->pci_subvendor) {
6167 case GB_G33S2H_SUBVENDOR:
6178 /* Remove ourselves from the config hooks */
6179 if (sc->intrhook.ich_func != NULL) {
6180 config_intrhook_disestablish(&sc->intrhook);
6181 sc->intrhook.ich_func = NULL;
6184 /* Start the corb and rirb engines */
6186 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n");
6188 hdac_corb_start(sc);
6190 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n");
6192 hdac_rirb_start(sc);
6195 device_printf(sc->dev,
6196 "HDA_DEBUG: Enabling controller interrupt...\n");
6198 if (sc->polling == 0)
6199 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
6200 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
6201 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
6207 device_printf(sc->dev,
6208 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n",
6211 hdac_scan_codecs(sc, codec_index);
6213 device_get_children(sc->dev, &devlist, &devcount);
6214 for (i = 0; devlist != NULL && i < devcount; i++) {
6215 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
6216 if (devinfo != NULL && devinfo->node_type ==
6217 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
6222 if (devlist != NULL)
6223 kfree(devlist, M_TEMP);
6225 if (devinfo == NULL) {
6227 device_printf(sc->dev, "Audio Function Group not found!\n");
6228 hdac_release_resources(sc);
6233 device_printf(sc->dev,
6234 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n",
6235 devinfo->nid, devinfo->codec->cad);
6237 hdac_audio_parse(devinfo);
6239 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n");
6241 hdac_audio_ctl_parse(devinfo);
6243 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n");
6245 hdac_vendor_patch_parse(devinfo);
6247 devinfo->function.audio.quirks |= quirks_on;
6248 if (quirks_off != 0)
6249 devinfo->function.audio.quirks &= ~quirks_off;
6251 /* XXX Disable all DIGITAL path. */
6252 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6253 w = hdac_widget_get(devinfo, i);
6256 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
6260 /* XXX Disable useless pin ? */
6261 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6262 (w->wclass.pin.config &
6263 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
6264 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
6268 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6269 if (ctl->widget == NULL)
6271 if (ctl->ossmask & SOUND_MASK_DISABLE)
6274 if (w->enable == 0 ||
6275 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6277 w = ctl->childwidget;
6280 if (w->enable == 0 ||
6281 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6286 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n");
6288 hdac_audio_build_tree(devinfo);
6291 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6292 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))
6296 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n");
6298 hdac_audio_commit(devinfo, HDA_COMMIT_ALL);
6300 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n");
6302 hdac_audio_ctl_commit(devinfo);
6305 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n");
6307 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY);
6309 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n");
6311 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC);
6315 device_printf(sc->dev,
6316 "HDA_DEBUG: OSS mixer initialization...\n");
6320 * There is no point of return after this. If the driver failed,
6321 * so be it. Let the detach procedure do all the cleanup.
6323 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0)
6324 device_printf(sc->dev, "Can't register mixer\n");
6332 device_printf(sc->dev,
6333 "HDA_DEBUG: Registering PCM channels...\n");
6335 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0)
6336 device_printf(sc->dev, "Can't register PCM\n");
6340 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) &&
6341 hdac_dma_alloc(sc, &sc->pos_dma,
6342 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) {
6344 device_printf(sc->dev,
6345 "Failed to allocate DMA pos buffer (non-fatal)\n");
6349 for (i = 0; i < pcnt; i++)
6350 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo);
6351 for (i = 0; i < rcnt; i++)
6352 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo);
6354 #ifdef SND_DYNSYSCTL
6355 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6356 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6357 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6358 sysctl_hdac_polling, "I", "Enable polling mode");
6359 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6360 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6361 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
6362 sizeof(sc->dev), sysctl_hdac_polling_interval, "I",
6363 "Controller/Jack Sense polling interval (1-1000 ms)");
6365 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6366 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6367 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6368 sysctl_hdac_pindump, "I", "Dump pin states/data");
6372 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]",
6373 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res),
6374 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV);
6375 pcm_setstatus(sc->dev, status);
6376 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo));
6378 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n",
6379 hdac_codec_id(devinfo));
6381 device_printf(sc->dev, "<HDA Driver Revision: %s>\n",
6385 if (devinfo->function.audio.quirks != 0) {
6386 device_printf(sc->dev, "\n");
6387 device_printf(sc->dev, "HDA config/quirks:");
6388 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
6389 if ((devinfo->function.audio.quirks &
6390 hdac_quirks_tab[i].value) ==
6391 hdac_quirks_tab[i].value)
6392 kprintf(" %s", hdac_quirks_tab[i].key);
6396 device_printf(sc->dev, "\n");
6397 device_printf(sc->dev, "+-------------------+\n");
6398 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
6399 device_printf(sc->dev, "+-------------------+\n");
6400 hdac_dump_nodes(devinfo);
6401 device_printf(sc->dev, "\n");
6402 device_printf(sc->dev, "+------------------------+\n");
6403 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
6404 device_printf(sc->dev, "+------------------------+\n");
6405 device_printf(sc->dev, "\n");
6407 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6408 device_printf(sc->dev, "%3d: nid=%d", i,
6409 (ctl->widget != NULL) ? ctl->widget->nid : -1);
6410 if (ctl->childwidget != NULL)
6411 kprintf(" cnid=%d", ctl->childwidget->nid);
6412 kprintf(" dir=0x%x index=%d "
6413 "ossmask=0x%08x ossdev=%d%s\n",
6414 ctl->dir, ctl->index,
6415 ctl->ossmask, ctl->ossdev,
6416 (ctl->enable == 0) ? " [DISABLED]" : "");
6418 device_printf(sc->dev, "\n");
6419 device_printf(sc->dev, "+-----------------------------------+\n");
6420 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n");
6421 device_printf(sc->dev, "+-----------------------------------+\n");
6422 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME);
6423 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM);
6424 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD);
6425 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC);
6426 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE);
6427 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV);
6428 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER);
6429 hdac_dump_ctls(devinfo, NULL, 0);
6430 hdac_dump_dac(devinfo);
6431 hdac_dump_adc(devinfo);
6432 device_printf(sc->dev, "\n");
6433 device_printf(sc->dev, "+--------------------------------------+\n");
6434 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n");
6435 device_printf(sc->dev, "+--------------------------------------+\n");
6436 hdac_dump_pcmchannels(sc, pcnt, rcnt);
6439 if (sc->polling != 0) {
6441 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
6446 /****************************************************************************
6447 * int hdac_detach(device_t)
6449 * Detach and free up resources utilized by the hdac device.
6450 ****************************************************************************/
6452 hdac_detach(device_t dev)
6454 struct hdac_softc *sc = NULL;
6455 struct hdac_devinfo *devinfo = NULL;
6458 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev);
6459 if (devinfo != NULL && devinfo->codec != NULL)
6460 sc = devinfo->codec->sc;
6464 if (sc->registered > 0) {
6465 err = pcm_unregister(dev);
6470 hdac_release_resources(sc);
6475 static device_method_t hdac_methods[] = {
6476 /* device interface */
6477 DEVMETHOD(device_probe, hdac_probe),
6478 DEVMETHOD(device_attach, hdac_attach),
6479 DEVMETHOD(device_detach, hdac_detach),
6483 static driver_t hdac_driver = {
6489 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0);
6490 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
6491 MODULE_VERSION(snd_hda, 1);