2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.18 2005/03/08 18:40:28 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <machine/clock.h>
47 #include <machine/md_var.h>
50 #include <bus/pci/pcivar.h>
51 #include <bus/pci/pcireg.h>
54 /* device structures */
55 struct ata_pci_controller {
56 struct resource *bmio;
63 #define IOMASK 0xfffffffc
64 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
65 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
66 (pci_get_progif(dev) & 0x05) != 0x05)
69 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
74 if (device_get_children(device_get_parent(dev), &children, &nchildren))
77 for (i = 0; i < nchildren; i++) {
78 if (pci_get_devid(children[i]) == devid &&
79 pci_get_revid(children[i]) >= revid) {
80 free(children, M_TEMP);
84 free(children, M_TEMP);
89 ata_via_southbridge_fixup(device_t dev)
94 if (device_get_children(device_get_parent(dev), &children, &nchildren))
97 for (i = 0; i < nchildren; i++) {
98 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
99 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
100 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
101 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
102 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
104 if ((reg76 & 0xf0) != 0xd0) {
106 "Correcting VIA config for southbridge data corruption bug\n");
107 pci_write_config(children[i], 0x75, 0x80, 1);
108 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
113 free(children, M_TEMP);
117 ata_pci_match(device_t dev)
119 if (pci_get_class(dev) != PCIC_STORAGE)
122 switch (pci_get_devid(dev)) {
123 /* supported chipsets */
125 return "Intel PIIX ATA controller";
128 return "Intel PIIX3 ATA controller";
133 return "Intel PIIX4 ATA33 controller";
136 return "Intel ICH0 ATA33 controller";
140 return "Intel ICH ATA66 controller";
144 return "Intel ICH2 ATA100 controller";
148 return "Intel ICH3 ATA100 controller";
152 return "Intel ICH4 ATA100 controller";
155 return "Intel ICH5 SATA150 controller";
158 return "Intel ICH5 ATA100 controller";
161 return "Intel ICH6/W SATA150 controller";
164 return "Intel ICH6R/RW SATA150 controller";
167 return "Intel ICH6R/RW ATA100 controller";
170 if (pci_get_revid(dev) >= 0xc4)
171 return "AcerLabs Aladdin ATA100 controller";
172 else if (pci_get_revid(dev) >= 0xc2)
173 return "AcerLabs Aladdin ATA66 controller";
174 else if (pci_get_revid(dev) >= 0x20)
175 return "AcerLabs Aladdin ATA33 controller";
177 return "AcerLabs Aladdin ATA controller";
180 if (ata_find_dev(dev, 0x05861106, 0x02))
181 return "VIA 82C586 ATA33 controller";
182 if (ata_find_dev(dev, 0x05861106, 0))
183 return "VIA 82C586 ATA controller";
184 if (ata_find_dev(dev, 0x05961106, 0x12))
185 return "VIA 82C596 ATA66 controller";
186 if (ata_find_dev(dev, 0x05961106, 0))
187 return "VIA 82C596 ATA33 controller";
188 if (ata_find_dev(dev, 0x06861106, 0x40))
189 return "VIA 82C686 ATA100 controller";
190 if (ata_find_dev(dev, 0x06861106, 0x10))
191 return "VIA 82C686 ATA66 controller";
192 if (ata_find_dev(dev, 0x06861106, 0))
193 return "VIA 82C686 ATA33 controller";
194 if (ata_find_dev(dev, 0x82311106, 0))
195 return "VIA 8231 ATA100 controller";
196 if (ata_find_dev(dev, 0x30741106, 0) ||
197 ata_find_dev(dev, 0x31091106, 0))
198 return "VIA 8233 ATA100 controller";
199 if (ata_find_dev(dev, 0x31471106, 0))
200 return "VIA 8233 ATA133 controller";
201 if (ata_find_dev(dev, 0x31771106, 0))
202 return "VIA 8235 ATA133 controller";
203 if (ata_find_dev(dev, 0x31491106, 0))
204 return "VIA 8237 ATA133 controller";
205 return "VIA Apollo ATA controller";
208 return "VIA 8237 SATA 150 controller";
211 if (ata_find_dev(dev, 0x07461039, 0))
212 return "SiS 5591 ATA133 controller";
213 if (ata_find_dev(dev, 0x06301039, 0x30) ||
214 ata_find_dev(dev, 0x06331039, 0) ||
215 ata_find_dev(dev, 0x06351039, 0) ||
216 ata_find_dev(dev, 0x06401039, 0) ||
217 ata_find_dev(dev, 0x06451039, 0) ||
218 ata_find_dev(dev, 0x06461039, 0) ||
219 ata_find_dev(dev, 0x06481039, 0) ||
220 ata_find_dev(dev, 0x06501039, 0) ||
221 ata_find_dev(dev, 0x07301039, 0) ||
222 ata_find_dev(dev, 0x07331039, 0) ||
223 ata_find_dev(dev, 0x07351039, 0) ||
224 ata_find_dev(dev, 0x07401039, 0) ||
225 ata_find_dev(dev, 0x07451039, 0) ||
226 ata_find_dev(dev, 0x07501039, 0))
227 return "SiS 5591 ATA100 controller";
228 else if (ata_find_dev(dev, 0x05301039, 0) ||
229 ata_find_dev(dev, 0x05401039, 0) ||
230 ata_find_dev(dev, 0x06201039, 0) ||
231 ata_find_dev(dev, 0x06301039, 0))
232 return "SiS 5591 ATA66 controller";
234 return "SiS 5591 ATA33 controller";
237 return "SiI 3512 SATA controller";
240 return "SiI 3112 SATA controller";
243 return "SiI 3114 SATA controller";
246 return "SiI 3124 SATA controller";
249 return "SiI 0680 ATA133 controller";
252 return "CMD 649 ATA100 controller";
255 return "CMD 648 ATA66 controller";
258 return "CMD 646 ATA controller";
261 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
262 return "Cypress 82C693 ATA controller";
266 return "Cyrix 5530 ATA33 controller";
269 return "AMD 756 ATA66 controller";
272 return "AMD 766 ATA100 controller";
275 return "AMD 768 ATA100 controller";
278 return "AMD 8111 UltraATA/133 controller";
281 return "nVIDIA nForce1 ATA100 controller";
284 return "nVIDIA nForce2 ATA133 controller";
287 return "nVIDIA nForce3 ATA133 controller";
290 return "ServerWorks ROSB4 ATA33 controller";
293 if (pci_get_revid(dev) >= 0x92)
294 return "ServerWorks CSB5 ATA100 controller";
296 return "ServerWorks CSB5 ATA66 controller";
299 return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
302 return "ServerWorks CSB6 ATA66 controller (channel 2)";
305 return "Promise ATA33 controller";
309 return "Promise ATA66 controller";
313 return "Promise ATA100 controller";
317 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
318 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
319 static long start = 0, end = 0;
321 /* we belive we are on a TX4, now do our (simple) magic */
322 if (pci_get_slot(dev) == 1) {
323 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
324 return "Promise TX4 ATA100 controller (channel 0+1)";
326 else if (pci_get_slot(dev) == 2 && start && end) {
327 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
329 return "Promise TX4 ATA100 controller (channel 2+3)";
334 return "Promise TX2 ATA100 controller";
340 return "Promise TX2 ATA133 controller";
343 switch (pci_get_revid(dev)) {
346 return "HighPoint HPT366 ATA66 controller";
348 return "HighPoint HPT368 ATA66 controller";
351 return "HighPoint HPT370 ATA100 controller";
353 return "HighPoint HPT372 ATA133 controller";
358 switch (pci_get_revid(dev)) {
361 return "HighPoint HPT372 ATA133 controller";
366 switch (pci_get_revid(dev)) {
368 return "HighPoint HPT374 ATA133 controller";
373 return "Cenatek Rocket Drive controller";
375 /* unsupported but known chipsets, generic DMA only */
378 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
381 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
383 /* unknown chipsets, try generic DMA if it seems possible */
385 if (pci_get_class(dev) == PCIC_STORAGE &&
386 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
387 return "Generic PCI ATA controller";
393 ata_pci_probe(device_t dev)
395 const char *desc = ata_pci_match(dev);
398 device_set_desc(dev, desc);
406 ata_pci_add_child(device_t dev, int unit)
410 /* check if this is located at one of the std addresses */
411 if (ATA_MASTERDEV(dev)) {
412 if (!(child = device_add_child(dev, "ata", unit)))
416 if (!(child = device_add_child(dev, "ata", 2)))
423 ata_pci_attach(device_t dev)
425 struct ata_pci_controller *controller = device_get_softc(dev);
426 u_int8_t class, subclass;
431 /* set up vendor-specific stuff */
432 type = pci_get_devid(dev);
433 class = pci_get_class(dev);
434 subclass = pci_get_subclass(dev);
435 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
437 if (!(cmd & PCIM_CMD_PORTEN)) {
438 device_printf(dev, "ATA channel disabled by BIOS\n");
442 /* is busmastering supported ? */
443 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
444 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
446 /* is there a valid port range to connect to ? */
448 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
449 0, ~0, 1, RF_ACTIVE);
450 if (!controller->bmio)
451 device_printf(dev, "Busmastering DMA not configured\n");
454 device_printf(dev, "Busmastering DMA not supported\n");
456 /* do extra chipset specific setups */
460 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
461 pci_write_config(dev, 0x53,
462 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
465 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
468 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
471 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
472 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
475 case 0x00041103: /* HighPoint HPT366/368/370/372 */
476 if (pci_get_revid(dev) < 2) { /* HPT 366 */
477 /* turn off interrupt prediction */
478 pci_write_config(dev, 0x51,
479 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
482 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
483 /* turn off interrupt prediction */
484 pci_write_config(dev, 0x51,
485 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
486 pci_write_config(dev, 0x55,
487 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
489 /* turn on interrupts */
490 pci_write_config(dev, 0x5a,
491 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
494 pci_write_config(dev, 0x5b, 0x22, 1);
499 case 0x00051103: /* HighPoint HPT372 */
500 case 0x00081103: /* HighPoint HPT374 */
501 /* turn off interrupt prediction */
502 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
503 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
505 /* turn on interrupts */
506 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
509 pci_write_config(dev, 0x5b,
510 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
513 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
514 /* prepare for ATA-66 on the 82C686a and 82C596b */
515 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
516 !ata_find_dev(dev, 0x06861106, 0x40)) ||
517 ata_find_dev(dev, 0x05961106, 0x12))
518 pci_write_config(dev, 0x50, 0x030b030b, 4);
520 /* the southbridge might need the data corruption fix */
521 if (ata_find_dev(dev, 0x06861106, 0x40) ||
522 ata_find_dev(dev, 0x82311106, 0x10))
523 ata_via_southbridge_fixup(dev);
525 /* set fifo configuration half'n'half */
526 pci_write_config(dev, 0x43,
527 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
529 /* set status register read retry */
530 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
532 /* set DMA read & end-of-sector fifo flush */
533 pci_write_config(dev, 0x46,
534 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
536 /* set sector size */
537 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
538 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
540 case 0x74111022: /* AMD 766 default setup */
541 flags = 1; /* bugged */
543 case 0x74091022: /* AMD 756 default setup */
544 case 0x74411022: /* AMD 768 default setup */
545 case 0x746d1022: /* AMD 8111 default setup */
547 pci_write_config(dev, 0x41,
548 pci_read_config(dev, 0x41, 1) & 0x0f, 1);
550 pci_write_config(dev, 0x41,
551 pci_read_config(dev, 0x41, 1) | 0xf0, 1);
554 case 0x01bc10de: /* NVIDIA nForce1 default setup */
555 case 0x006510de: /* NVIDIA nForce2 default setup */
558 case 0x00d510de: /* NVIDIA nForce3 default setup */
560 pci_write_config(dev, 0x51,
561 pci_read_config(dev, 0x51, 1) & 0x0f, 1);
563 pci_write_config(dev, 0x51,
564 pci_read_config(dev, 0x51, 1) | 0xf0, 1);
568 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
569 pci_write_config(dev, 0x64,
570 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
574 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
575 pci_write_config(dev, 0x5a,
576 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
577 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
580 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
581 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
582 pci_write_config(dev, 0x8a,
583 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
584 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
585 device_printf(dev, "SiI 0680 could not set clock\n");
590 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
591 pci_write_config(dev, 0x71, 0x01, 1);
594 case 0x10001042: /* RZ 100? known bad, no DMA */
596 case 0x06401095: /* CMD 640 known bad, no DMA */
597 controller->bmio = NULL;
598 device_printf(dev, "Busmastering DMA disabled\n");
601 if (controller->bmio) {
602 controller->bmaddr = rman_get_start(controller->bmio);
603 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
604 SYS_RES_IOPORT, rid, controller->bmio);
605 controller->bmio = NULL;
609 * the Cypress chip is a mess, it contains two ATA functions, but
610 * both channels are visible on the first one.
611 * simply ignore the second function for now, as the right
612 * solution (ignoring the second channel on the first function)
613 * doesn't work with the crappy ATA interrupt setup on the alpha.
615 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
618 ata_pci_add_child(dev, 0);
620 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
621 ata_pci_add_child(dev, 1);
623 return bus_generic_attach(dev);
627 ata_pci_intr(struct ata_channel *ch)
632 * since we might share the IRQ with another device, and in some
633 * cases with our twin channel, we only want to process interrupts
634 * that we know this channel generated.
636 switch (ch->chiptype) {
637 case 0x00041103: /* HighPoint HPT366/368/370/372 */
638 case 0x00051103: /* HighPoint HPT372 */
639 case 0x00081103: /* HighPoint HPT374 */
640 if (((dmastat = ata_dmastatus(ch)) &
641 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
643 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
647 case 0x06481095: /* CMD 648 */
648 case 0x06491095: /* CMD 649 */
649 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
650 (ch->unit ? 0x08 : 0x04)))
652 #if !defined(NO_ATANG)
653 pci_write_config(device_get_parent(ch->dev), 0x71,
654 pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
655 ~(ch->unit ? 0x04 : 0x08), 1);
659 case 0x06801095: /* SiI 680 */
660 if (!(pci_read_config(device_get_parent(ch->dev),
661 (ch->unit ? 0xb1 : 0xa1), 1) & 0x08))
665 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
666 case 0x0d38105a: /* Promise Fasttrak 66 */
667 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
668 case 0x0d30105a: /* Promise OEM ATA100 */
669 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
670 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
671 (ch->unit ? 0x00004000 : 0x00000400)))
675 case 0x4d68105a: /* Promise TX2 ATA100 */
676 case 0x6268105a: /* Promise TX2 ATA100 */
677 case 0x4d69105a: /* Promise TX2 ATA133 */
678 case 0x5275105a: /* Promise TX2 ATA133 */
679 case 0x6269105a: /* Promise TX2 ATA133 */
680 case 0x7275105a: /* Promise TX2 ATA133 */
681 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
682 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
686 case 0x24d18086: /* Intel ICH5 SATA150 */
687 case 0x24db8086: /* Intel ICH5 ATA100 */
688 case 0x26518086: /* Intel ICH6 SATA150 */
689 case 0x26528086: /* Intel ICH6R SATA150 */
690 dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
691 if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
692 ATA_BMSTAT_INTERRUPT)
694 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat &
695 ~(ATA_BMSTAT_DMA_SIMPLEX | ATA_BMSTAT_ERROR));
701 if (ch->flags & ATA_DMA_ACTIVE) {
702 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
704 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
711 ata_pci_print_child(device_t dev, device_t child)
713 struct ata_channel *ch = device_get_softc(child);
716 retval += bus_print_child_header(dev, child);
717 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
719 if (ATA_MASTERDEV(dev))
720 retval += printf(" irq %d", 14 + ch->unit);
722 retval += bus_print_child_footer(dev, child);
727 static struct resource *
728 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
729 u_long start, u_long end, u_long count, u_int flags)
731 struct ata_pci_controller *controller = device_get_softc(dev);
732 struct resource *res = NULL;
733 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
736 if (type == SYS_RES_IOPORT) {
739 if (ATA_MASTERDEV(dev)) {
741 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
742 end = start + ATA_IOSIZE - 1;
744 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
745 SYS_RES_IOPORT, &myrid,
746 start, end, count, flags);
749 myrid = 0x10 + 8 * unit;
750 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
751 SYS_RES_IOPORT, &myrid,
752 start, end, count, flags);
756 case ATA_ALTADDR_RID:
757 if (ATA_MASTERDEV(dev)) {
759 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
760 end = start + ATA_ALTIOSIZE - 1;
761 count = ATA_ALTIOSIZE;
762 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
763 SYS_RES_IOPORT, &myrid,
764 start, end, count, flags);
767 myrid = 0x14 + 8 * unit;
768 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
769 SYS_RES_IOPORT, &myrid,
770 start, end, count, flags);
772 start = rman_get_start(res) + 2;
773 end = start + ATA_ALTIOSIZE - 1;
774 count = ATA_ALTIOSIZE;
775 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
776 SYS_RES_IOPORT, myrid, res);
777 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
778 SYS_RES_IOPORT, &myrid,
779 start, end, count, flags);
785 if (controller->bmaddr) {
788 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
789 end = start + ATA_BMIOSIZE - 1;
790 count = ATA_BMIOSIZE;
791 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
792 SYS_RES_IOPORT, &myrid,
793 start, end, count, flags);
799 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
800 if (ATA_MASTERDEV(dev)) {
802 return alpha_platform_alloc_ide_intr(unit);
804 int irq = (unit == 0 ? 14 : 15);
806 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
807 SYS_RES_IRQ, rid, irq, irq, 1, flags);
811 /* primary and secondary channels share interrupt, keep track */
812 if (!controller->irq)
813 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
815 rid, 0, ~0, 1, flags);
816 controller->irqcnt++;
817 return controller->irq;
824 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
827 struct ata_pci_controller *controller = device_get_softc(dev);
828 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
830 if (type == SYS_RES_IOPORT) {
833 if (ATA_MASTERDEV(dev))
834 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
835 SYS_RES_IOPORT, 0x0, r);
837 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
838 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
841 case ATA_ALTADDR_RID:
842 if (ATA_MASTERDEV(dev))
843 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
844 SYS_RES_IOPORT, 0x0, r);
846 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
847 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
851 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
852 SYS_RES_IOPORT, 0x20, r);
857 if (type == SYS_RES_IRQ) {
858 if (rid != ATA_IRQ_RID)
861 if (ATA_MASTERDEV(dev)) {
863 return alpha_platform_release_ide_intr(unit, r);
865 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
866 SYS_RES_IRQ, rid, r);
870 /* primary and secondary channels share interrupt, keep track */
871 if (--controller->irqcnt)
873 controller->irq = NULL;
874 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
875 SYS_RES_IRQ, rid, r);
882 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
883 int flags, driver_intr_t *intr, void *arg,
886 if (ATA_MASTERDEV(dev)) {
888 return alpha_platform_setup_ide_intr(irq, intr, arg, cookiep);
890 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
891 flags, intr, arg, cookiep);
895 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
896 flags, intr, arg, cookiep);
900 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
903 if (ATA_MASTERDEV(dev)) {
905 return alpha_platform_teardown_ide_intr(irq, cookie);
907 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
911 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
914 static device_method_t ata_pci_methods[] = {
915 /* device interface */
916 DEVMETHOD(device_probe, ata_pci_probe),
917 DEVMETHOD(device_attach, ata_pci_attach),
918 DEVMETHOD(device_shutdown, bus_generic_shutdown),
919 DEVMETHOD(device_suspend, bus_generic_suspend),
920 DEVMETHOD(device_resume, bus_generic_resume),
923 DEVMETHOD(bus_print_child, ata_pci_print_child),
924 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
925 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
926 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
927 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
928 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
929 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
933 static driver_t ata_pci_driver = {
936 sizeof(struct ata_pci_controller),
939 static devclass_t ata_pci_devclass;
941 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
944 ata_pcisub_probe(device_t dev)
946 struct ata_channel *ch = device_get_softc(dev);
950 /* find channel number on this controller */
951 device_get_children(device_get_parent(dev), &children, &count);
952 for (i = 0; i < count; i++) {
953 if (children[i] == dev)
956 free(children, M_TEMP);
957 ch->chiptype = pci_get_devid(device_get_parent(dev));
958 ch->intr_func = ata_pci_intr;
959 return ata_probe(dev);
962 static device_method_t ata_pcisub_methods[] = {
963 /* device interface */
964 DEVMETHOD(device_probe, ata_pcisub_probe),
965 DEVMETHOD(device_attach, ata_attach),
966 DEVMETHOD(device_detach, ata_detach),
967 DEVMETHOD(device_resume, ata_resume),
971 static driver_t ata_pcisub_driver = {
974 sizeof(struct ata_channel),
977 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);