3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.40 2008/04/27 14:18:16 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
118 #include <sys/endian.h>
119 #include <sys/kernel.h>
120 #include <sys/malloc.h>
121 #include <sys/mbuf.h>
122 /* #include <sys/module.h> */
123 #include <sys/rman.h>
124 #include <sys/serialize.h>
125 #include <sys/socket.h>
126 #include <sys/sockio.h>
127 #include <sys/sysctl.h>
130 #include <net/ethernet.h>
132 #include <net/ifq_var.h>
133 #include <net/if_arp.h>
134 #include <net/if_dl.h>
135 #include <net/if_media.h>
136 #include <net/if_types.h>
137 #include <net/vlan/if_vlan_var.h>
138 #include <net/vlan/if_vlan_ether.h>
140 #include <dev/netif/mii_layer/mii.h>
141 #include <dev/netif/mii_layer/miivar.h>
143 #include <bus/pci/pcidevs.h>
144 #include <bus/pci/pcireg.h>
145 #include <bus/pci/pcivar.h>
147 /* "device miibus" required. See GENERIC if you get errors here. */
148 #include "miibus_if.h"
150 #include <dev/netif/re/if_rereg.h>
151 #include <dev/netif/re/if_revar.h>
153 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
155 #define RE_DISABLE_HWCSUM
159 * Various supported device vendors/types and their names.
161 static const struct re_type re_devs[] = {
162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
163 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
164 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
165 "RealTek 8139C+ 10/100BaseTX" },
166 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E,
167 "RealTek 8101E PCIe 10/100baseTX" },
168 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1,
169 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
170 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2,
171 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
172 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN3,
173 "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
175 "RealTek 8169 Gigabit Ethernet" },
176 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
177 "RealTek 8169S Single-chip Gigabit Ethernet" },
178 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB,
179 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC,
181 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
182 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC,
183 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
184 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
185 "RealTek 8110S Single-chip Gigabit Ethernet" },
186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S,
187 "Corega CG-LAPCIGT Gigabit Ethernet" },
188 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S,
189 "Linksys EG1032 Gigabit Ethernet" },
190 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S,
191 "US Robotics 997902 Gigabit Ethernet" },
195 static const struct re_hwrev re_hwrevs[] = {
196 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" },
197 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" },
198 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" },
199 { RE_HWREV_8168_SPIN3, RE_8169, RE_F_PCIE, "8168" },
200 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" },
201 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" },
202 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" },
203 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" },
204 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" },
205 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" },
206 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" },
210 static int re_probe(device_t);
211 static int re_attach(device_t);
212 static int re_detach(device_t);
214 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
216 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
217 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
219 static int re_allocmem(device_t, struct re_softc *);
220 static int re_newbuf(struct re_softc *, int, struct mbuf *);
221 static int re_rx_list_init(struct re_softc *);
222 static int re_tx_list_init(struct re_softc *);
223 static void re_rxeof(struct re_softc *);
224 static void re_txeof(struct re_softc *);
225 static void re_intr(void *);
226 static void re_tick(void *);
227 static void re_tick_serialized(void *);
228 static void re_start(struct ifnet *);
229 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
230 static void re_init(void *);
231 static void re_stop(struct re_softc *);
232 static void re_watchdog(struct ifnet *);
233 static int re_suspend(device_t);
234 static int re_resume(device_t);
235 static void re_shutdown(device_t);
236 static int re_ifmedia_upd(struct ifnet *);
237 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
239 static void re_eeprom_putbyte(struct re_softc *, int);
240 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
241 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
242 static int re_gmii_readreg(device_t, int, int);
243 static int re_gmii_writereg(device_t, int, int, int);
245 static int re_miibus_readreg(device_t, int, int);
246 static int re_miibus_writereg(device_t, int, int, int);
247 static void re_miibus_statchg(device_t);
249 static void re_setmulti(struct re_softc *);
250 static void re_reset(struct re_softc *);
253 static int re_diag(struct re_softc *);
256 #ifdef DEVICE_POLLING
257 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
260 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS);
262 static device_method_t re_methods[] = {
263 /* Device interface */
264 DEVMETHOD(device_probe, re_probe),
265 DEVMETHOD(device_attach, re_attach),
266 DEVMETHOD(device_detach, re_detach),
267 DEVMETHOD(device_suspend, re_suspend),
268 DEVMETHOD(device_resume, re_resume),
269 DEVMETHOD(device_shutdown, re_shutdown),
272 DEVMETHOD(bus_print_child, bus_generic_print_child),
273 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
276 DEVMETHOD(miibus_readreg, re_miibus_readreg),
277 DEVMETHOD(miibus_writereg, re_miibus_writereg),
278 DEVMETHOD(miibus_statchg, re_miibus_statchg),
283 static driver_t re_driver = {
286 sizeof(struct re_softc)
289 static devclass_t re_devclass;
291 DECLARE_DUMMY_MODULE(if_re);
292 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
293 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
294 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
297 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
300 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
303 * Send a read command and address to the EEPROM, check for ACK.
306 re_eeprom_putbyte(struct re_softc *sc, int addr)
310 d = addr | (RE_9346_READ << sc->re_eewidth);
313 * Feed in each bit and strobe the clock.
315 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
317 EE_SET(RE_EE_DATAIN);
319 EE_CLR(RE_EE_DATAIN);
329 * Read a word of data stored in the EEPROM at address 'addr.'
332 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
338 * Send address of word we want to read.
340 re_eeprom_putbyte(sc, addr);
343 * Start reading bits from EEPROM.
345 for (i = 0x8000; i != 0; i >>= 1) {
348 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
358 * Read a sequence of words from the EEPROM.
361 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
364 uint16_t word = 0, *ptr;
366 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
369 for (i = 0; i < cnt; i++) {
370 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
371 re_eeprom_getword(sc, off + i, &word);
372 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
373 ptr = (uint16_t *)(dest + (i * 2));
377 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
381 re_gmii_readreg(device_t dev, int phy, int reg)
383 struct re_softc *sc = device_get_softc(dev);
390 /* Let the rgephy driver read the GMEDIASTAT register */
392 if (reg == RE_GMEDIASTAT)
393 return(CSR_READ_1(sc, RE_GMEDIASTAT));
395 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
398 for (i = 0; i < RE_TIMEOUT; i++) {
399 rval = CSR_READ_4(sc, RE_PHYAR);
400 if (rval & RE_PHYAR_BUSY)
405 if (i == RE_TIMEOUT) {
406 device_printf(dev, "PHY read failed\n");
410 return(rval & RE_PHYAR_PHYDATA);
414 re_gmii_writereg(device_t dev, int phy, int reg, int data)
416 struct re_softc *sc = device_get_softc(dev);
420 CSR_WRITE_4(sc, RE_PHYAR,
421 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
424 for (i = 0; i < RE_TIMEOUT; i++) {
425 rval = CSR_READ_4(sc, RE_PHYAR);
426 if ((rval & RE_PHYAR_BUSY) == 0)
432 device_printf(dev, "PHY write failed\n");
438 re_miibus_readreg(device_t dev, int phy, int reg)
440 struct re_softc *sc = device_get_softc(dev);
442 uint16_t re8139_reg = 0;
444 if (sc->re_type == RE_8169) {
445 rval = re_gmii_readreg(dev, phy, reg);
449 /* Pretend the internal PHY is only at address 0 */
455 re8139_reg = RE_BMCR;
458 re8139_reg = RE_BMSR;
461 re8139_reg = RE_ANAR;
464 re8139_reg = RE_ANER;
467 re8139_reg = RE_LPAR;
473 * Allow the rlphy driver to read the media status
474 * register. If we have a link partner which does not
475 * support NWAY, this is the register which will tell
476 * us the results of parallel detection.
479 return(CSR_READ_1(sc, RE_MEDIASTAT));
481 device_printf(dev, "bad phy register\n");
484 rval = CSR_READ_2(sc, re8139_reg);
485 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) {
486 /* 8139C+ has different bit layout. */
487 rval &= ~(BMCR_LOOP | BMCR_ISO);
493 re_miibus_writereg(device_t dev, int phy, int reg, int data)
495 struct re_softc *sc= device_get_softc(dev);
496 u_int16_t re8139_reg = 0;
498 if (sc->re_type == RE_8169)
499 return(re_gmii_writereg(dev, phy, reg, data));
501 /* Pretend the internal PHY is only at address 0 */
507 re8139_reg = RE_BMCR;
508 if (sc->re_type == RE_8139CPLUS) {
509 /* 8139C+ has different bit layout. */
510 data &= ~(BMCR_LOOP | BMCR_ISO);
514 re8139_reg = RE_BMSR;
517 re8139_reg = RE_ANAR;
520 re8139_reg = RE_ANER;
523 re8139_reg = RE_LPAR;
529 device_printf(dev, "bad phy register\n");
532 CSR_WRITE_2(sc, re8139_reg, data);
537 re_miibus_statchg(device_t dev)
542 * Program the 64-bit multicast hash filter.
545 re_setmulti(struct re_softc *sc)
547 struct ifnet *ifp = &sc->arpcom.ac_if;
549 uint32_t hashes[2] = { 0, 0 };
550 struct ifmultiaddr *ifma;
554 rxfilt = CSR_READ_4(sc, RE_RXCFG);
556 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
557 rxfilt |= RE_RXCFG_RX_MULTI;
558 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
559 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
560 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
564 /* first, zot all the existing hash bits */
565 CSR_WRITE_4(sc, RE_MAR0, 0);
566 CSR_WRITE_4(sc, RE_MAR4, 0);
568 /* now program new ones */
569 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
570 if (ifma->ifma_addr->sa_family != AF_LINK)
572 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
573 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
575 hashes[0] |= (1 << h);
577 hashes[1] |= (1 << (h - 32));
582 rxfilt |= RE_RXCFG_RX_MULTI;
584 rxfilt &= ~RE_RXCFG_RX_MULTI;
586 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
589 * For some unfathomable reason, RealTek decided to reverse
590 * the order of the multicast hash registers in the PCI Express
591 * parts. This means we have to write the hash pattern in reverse
592 * order for those devices.
594 if (sc->re_flags & RE_F_PCIE) {
595 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0]));
596 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1]));
598 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
599 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
604 re_reset(struct re_softc *sc)
608 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
610 for (i = 0; i < RE_TIMEOUT; i++) {
612 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
616 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
618 CSR_WRITE_1(sc, 0x82, 1);
623 * The following routine is designed to test for a defect on some
624 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
625 * lines connected to the bus, however for a 32-bit only card, they
626 * should be pulled high. The result of this defect is that the
627 * NIC will not work right if you plug it into a 64-bit slot: DMA
628 * operations will be done with 64-bit transfers, which will fail
629 * because the 64-bit data lines aren't connected.
631 * There's no way to work around this (short of talking a soldering
632 * iron to the board), however we can detect it. The method we use
633 * here is to put the NIC into digital loopback mode, set the receiver
634 * to promiscuous mode, and then try to send a frame. We then compare
635 * the frame data we sent to what was received. If the data matches,
636 * then the NIC is working correctly, otherwise we know the user has
637 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
638 * slot. In the latter case, there's no way the NIC can work correctly,
639 * so we print out a message on the console and abort the device attach.
643 re_diag(struct re_softc *sc)
645 struct ifnet *ifp = &sc->arpcom.ac_if;
647 struct ether_header *eh;
648 struct re_desc *cur_rx;
651 int total_len, i, error = 0, phyaddr;
652 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
653 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
655 /* Allocate a single mbuf */
657 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
662 * Initialize the NIC in test mode. This sets the chip up
663 * so that it can send and receive frames, but performs the
664 * following special functions:
665 * - Puts receiver in promiscuous mode
666 * - Enables digital loopback mode
667 * - Leaves interrupts turned off
670 ifp->if_flags |= IFF_PROMISC;
675 if (sc->re_type == RE_8169)
680 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
681 for (i = 0; i < RE_TIMEOUT; i++) {
682 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
683 if (!(status & BMCR_RESET))
687 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
688 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
692 /* Put some data in the mbuf */
694 eh = mtod(m0, struct ether_header *);
695 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
696 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
697 eh->ether_type = htons(ETHERTYPE_IP);
698 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
701 * Queue the packet, start transmission.
702 * Note: ifq_handoff() ultimately calls re_start() for us.
705 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
706 error = ifq_handoff(ifp, m0, NULL);
713 /* Wait for it to propagate through the chip */
716 for (i = 0; i < RE_TIMEOUT; i++) {
717 status = CSR_READ_2(sc, RE_ISR);
718 CSR_WRITE_2(sc, RE_ISR, status);
719 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
720 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
725 if (i == RE_TIMEOUT) {
726 if_printf(ifp, "diagnostic failed to receive packet "
727 "in loopback mode\n");
733 * The packet should have been dumped into the first
734 * entry in the RX DMA ring. Grab it from there.
737 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
738 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
739 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
740 BUS_DMASYNC_POSTWRITE);
741 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
743 m0 = sc->re_ldata.re_rx_mbuf[0];
744 sc->re_ldata.re_rx_mbuf[0] = NULL;
745 eh = mtod(m0, struct ether_header *);
747 cur_rx = &sc->re_ldata.re_rx_list[0];
748 total_len = RE_RXBYTES(cur_rx);
749 rxstat = le32toh(cur_rx->re_cmdstat);
751 if (total_len != ETHER_MIN_LEN) {
752 if_printf(ifp, "diagnostic failed, received short packet\n");
757 /* Test that the received packet data matches what we sent. */
759 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
760 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
761 be16toh(eh->ether_type) != ETHERTYPE_IP) {
762 if_printf(ifp, "WARNING, DMA FAILURE!\n");
763 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
764 dst, ":", src, ":", ETHERTYPE_IP);
765 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
766 eh->ether_dhost, ":", eh->ether_shost, ":",
767 ntohs(eh->ether_type));
768 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
769 "into a 64-bit PCI slot.\n");
770 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
771 "for proper operation.\n");
772 if_printf(ifp, "Read the re(4) man page for more details.\n");
777 /* Turn interface off, release resources */
781 ifp->if_flags &= ~IFF_PROMISC;
791 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
792 * IDs against our list and return a device name if we find a match.
795 re_probe(device_t dev)
797 const struct re_type *t;
801 uint16_t vendor, product;
805 vendor = pci_get_vendor(dev);
806 product = pci_get_device(dev);
809 * Only attach to rev.3 of the Linksys EG1032 adapter.
810 * Rev.2 is supported by sk(4).
812 if (vendor == PCI_VENDOR_LINKSYS &&
813 product == PCI_PRODUCT_LINKSYS_EG1032 &&
814 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
817 for (t = re_devs; t->re_name != NULL; t++) {
818 if (product == t->re_did && vendor == t->re_vid)
823 * Check if we found a RealTek device.
825 if (t->re_name == NULL)
829 * Temporarily map the I/O space so we can read the chip ID register.
831 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
833 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
835 if (sc->re_res == NULL) {
836 device_printf(dev, "couldn't map ports/memory\n");
841 sc->re_btag = rman_get_bustag(sc->re_res);
842 sc->re_bhandle = rman_get_bushandle(sc->re_res);
844 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
845 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
849 * and continue matching for the specific chip...
851 for (; t->re_name != NULL; t++) {
852 if (product == t->re_did && vendor == t->re_vid &&
853 t->re_basetype == hwrev) {
854 device_set_desc(dev, t->re_name);
860 kprintf("re: unknown hwrev %#x\n", hwrev);
865 * This routine takes the segment list provided as the result of
866 * a bus_dma_map_load() operation and assigns the addresses/lengths
867 * to RealTek DMA descriptors. This can be called either by the RX
868 * code or the TX code. In the RX case, we'll probably wind up mapping
869 * at most one segment. For the TX case, there could be any number of
870 * segments since TX packets may span multiple mbufs. In either case,
871 * if the number of segments is larger than the re_maxsegs limit
872 * specified by the caller, we abort the mapping operation. Sadly,
873 * whoever designed the buffer mapping API did not provide a way to
874 * return an error from here, so we have to fake it a bit.
878 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
879 bus_size_t mapsize, int error)
881 struct re_dmaload_arg *ctx;
882 struct re_desc *d = NULL;
891 /* Signal error to caller if there's too many segments */
892 if (nseg > ctx->re_maxsegs) {
898 * Map the segment array into descriptors. Note that we set the
899 * start-of-frame and end-of-frame markers for either TX or RX, but
900 * they really only have meaning in the TX case. (In the RX case,
901 * it's the chip that tells us where packets begin and end.)
902 * We also keep track of the end of the ring and set the
903 * end-of-ring bits as needed, and we set the ownership bits
904 * in all except the very first descriptor. (The caller will
905 * set this descriptor later when it start transmission or
910 d = &ctx->re_ring[idx];
911 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
915 cmdstat = segs[i].ds_len;
916 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
917 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
919 cmdstat |= RE_TDESC_CMD_SOF;
921 cmdstat |= RE_TDESC_CMD_OWN;
922 if (idx == (RE_RX_DESC_CNT - 1))
923 cmdstat |= RE_TDESC_CMD_EOR;
924 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
931 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
932 ctx->re_maxsegs = nseg;
937 * Map a single buffer address.
941 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
948 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
950 *addr = segs->ds_addr;
954 re_allocmem(device_t dev, struct re_softc *sc)
959 * Allocate map for RX mbufs.
962 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
963 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
964 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
965 &sc->re_ldata.re_mtag);
967 device_printf(dev, "could not allocate dma tag\n");
972 * Allocate map for TX descriptor list.
974 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
975 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
976 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
977 &sc->re_ldata.re_tx_list_tag);
979 device_printf(dev, "could not allocate dma tag\n");
983 /* Allocate DMA'able memory for the TX ring */
985 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
986 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
987 &sc->re_ldata.re_tx_list_map);
989 device_printf(dev, "could not allocate TX ring\n");
993 /* Load the map for the TX ring. */
995 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
996 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
997 RE_TX_LIST_SZ, re_dma_map_addr,
998 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
1000 device_printf(dev, "could not get address of TX ring\n");
1004 /* Create DMA maps for TX buffers */
1006 for (i = 0; i < RE_TX_DESC_CNT; i++) {
1007 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1008 &sc->re_ldata.re_tx_dmamap[i]);
1010 device_printf(dev, "can't create DMA map for TX\n");
1016 * Allocate map for RX descriptor list.
1018 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
1019 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1020 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1021 &sc->re_ldata.re_rx_list_tag);
1023 device_printf(dev, "could not allocate dma tag\n");
1027 /* Allocate DMA'able memory for the RX ring */
1029 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1030 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1031 &sc->re_ldata.re_rx_list_map);
1033 device_printf(dev, "could not allocate RX ring\n");
1037 /* Load the map for the RX ring. */
1039 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1040 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
1041 RE_RX_LIST_SZ, re_dma_map_addr,
1042 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
1044 device_printf(dev, "could not get address of RX ring\n");
1048 /* Create DMA maps for RX buffers */
1050 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1051 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1052 &sc->re_ldata.re_rx_dmamap[i]);
1054 device_printf(dev, "can't create DMA map for RX\n");
1063 * Attach the interface. Allocate softc structures, do ifmedia
1064 * setup and ethernet/BPF attach.
1067 re_attach(device_t dev)
1069 struct re_softc *sc = device_get_softc(dev);
1071 const struct re_hwrev *hw_rev;
1072 uint8_t eaddr[ETHER_ADDR_LEN];
1073 uint16_t as[ETHER_ADDR_LEN / 2];
1074 uint16_t re_did = 0;
1076 int error = 0, rid, i;
1078 callout_init(&sc->re_timer);
1083 RE_ENABLE_TX_MODERATION(sc);
1085 sysctl_ctx_init(&sc->re_sysctl_ctx);
1086 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1087 SYSCTL_STATIC_CHILDREN(_hw),
1089 device_get_nameunit(dev),
1091 if (sc->re_sysctl_tree == NULL) {
1092 device_printf(dev, "can't add sysctl node\n");
1096 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1097 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1098 OID_AUTO, "tx_moderation",
1099 CTLTYPE_INT | CTLFLAG_RW,
1100 sc, 0, re_sysctl_tx_moderation, "I",
1101 "Enable/Disable TX moderation");
1103 #ifndef BURN_BRIDGES
1105 * Handle power management nonsense.
1108 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1109 uint32_t membase, irq;
1111 /* Save important PCI config data. */
1112 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1113 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1115 /* Reset the power state. */
1116 device_printf(dev, "chip is in D%d power mode "
1117 "-- setting to D0\n", pci_get_powerstate(dev));
1119 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1121 /* Restore PCI config data. */
1122 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1123 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1127 * Map control/status registers.
1129 pci_enable_busmaster(dev);
1132 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1135 if (sc->re_res == NULL) {
1136 device_printf(dev, "couldn't map ports\n");
1141 sc->re_btag = rman_get_bustag(sc->re_res);
1142 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1144 /* Allocate interrupt */
1146 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1147 RF_SHAREABLE | RF_ACTIVE);
1149 if (sc->re_irq == NULL) {
1150 device_printf(dev, "couldn't map interrupt\n");
1155 /* Reset the adapter. */
1158 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1159 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1160 if (hw_rev->re_rev == hwrev) {
1161 sc->re_type = hw_rev->re_type;
1162 sc->re_flags = hw_rev->re_flags;
1168 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1169 if (re_did != 0x8129)
1173 * Get station address from the EEPROM.
1175 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
1176 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1177 as[i] = le16toh(as[i]);
1178 bcopy(as, eaddr, sizeof(eaddr));
1180 if (sc->re_type == RE_8169) {
1181 /* Set RX length mask */
1182 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1183 sc->re_txstart = RE_GTXSTART;
1185 /* Set RX length mask */
1186 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1187 sc->re_txstart = RE_TXSTART;
1191 * Allocate the parent bus DMA tag appropriate for PCI.
1193 #define RE_NSEG_NEW 32
1194 error = bus_dma_tag_create(NULL, /* parent */
1195 1, 0, /* alignment, boundary */
1196 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1197 BUS_SPACE_MAXADDR, /* highaddr */
1198 NULL, NULL, /* filter, filterarg */
1199 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1200 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1201 BUS_DMA_ALLOCNOW, /* flags */
1202 &sc->re_parent_tag);
1206 error = re_allocmem(dev, sc);
1212 if (mii_phy_probe(dev, &sc->re_miibus,
1213 re_ifmedia_upd, re_ifmedia_sts)) {
1214 device_printf(dev, "MII without any phy!\n");
1219 ifp = &sc->arpcom.ac_if;
1221 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1222 ifp->if_mtu = ETHERMTU;
1223 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1224 ifp->if_ioctl = re_ioctl;
1225 ifp->if_capabilities = IFCAP_VLAN_MTU;
1226 ifp->if_start = re_start;
1227 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1228 #ifdef DEVICE_POLLING
1229 ifp->if_poll = re_poll;
1231 ifp->if_watchdog = re_watchdog;
1232 ifp->if_init = re_init;
1233 if (sc->re_type == RE_8169)
1234 ifp->if_baudrate = 1000000000;
1236 ifp->if_baudrate = 100000000;
1237 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1238 ifq_set_ready(&ifp->if_snd);
1240 #ifdef RE_DISABLE_HWCSUM
1241 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1242 ifp->if_hwassist = 0;
1244 ifp->if_capenable = ifp->if_capabilities;
1245 ifp->if_hwassist = RE_CSUM_FEATURES;
1246 #endif /* RE_DISABLE_HWCSUM */
1249 * Call MI attach routine.
1251 ether_ifattach(ifp, eaddr, NULL);
1255 * Perform hardware diagnostic on the original RTL8169.
1256 * Some 32-bit cards were incorrectly wired and would
1257 * malfunction if plugged into a 64-bit slot.
1259 if (hwrev == RE_HWREV_8169) {
1260 lwkt_serialize_enter(ifp->if_serializer);
1261 error = re_diag(sc);
1262 lwkt_serialize_exit(ifp->if_serializer);
1265 device_printf(dev, "hardware diagnostic failure\n");
1266 ether_ifdetach(ifp);
1270 #endif /* RE_DIAG */
1272 /* Hook interrupt last to avoid having to lock softc */
1273 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc,
1274 &sc->re_intrhand, ifp->if_serializer);
1277 device_printf(dev, "couldn't set up irq\n");
1278 ether_ifdetach(ifp);
1290 * Shutdown hardware and free up resources. This can be called any
1291 * time after the mutex has been initialized. It is called in both
1292 * the error case in attach and the normal detach case so it needs
1293 * to be careful about only freeing resources that have actually been
1297 re_detach(device_t dev)
1299 struct re_softc *sc = device_get_softc(dev);
1300 struct ifnet *ifp = &sc->arpcom.ac_if;
1303 /* These should only be active if attach succeeded */
1304 if (device_is_attached(dev)) {
1305 lwkt_serialize_enter(ifp->if_serializer);
1307 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1308 lwkt_serialize_exit(ifp->if_serializer);
1310 ether_ifdetach(ifp);
1313 device_delete_child(dev, sc->re_miibus);
1314 bus_generic_detach(dev);
1317 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1319 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1323 /* Unload and free the RX DMA ring memory and map */
1325 if (sc->re_ldata.re_rx_list_tag) {
1326 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1327 sc->re_ldata.re_rx_list_map);
1328 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1329 sc->re_ldata.re_rx_list,
1330 sc->re_ldata.re_rx_list_map);
1331 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1334 /* Unload and free the TX DMA ring memory and map */
1336 if (sc->re_ldata.re_tx_list_tag) {
1337 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1338 sc->re_ldata.re_tx_list_map);
1339 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1340 sc->re_ldata.re_tx_list,
1341 sc->re_ldata.re_tx_list_map);
1342 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1345 /* Destroy all the RX and TX buffer maps */
1347 if (sc->re_ldata.re_mtag) {
1348 for (i = 0; i < RE_TX_DESC_CNT; i++)
1349 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1350 sc->re_ldata.re_tx_dmamap[i]);
1351 for (i = 0; i < RE_RX_DESC_CNT; i++)
1352 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1353 sc->re_ldata.re_rx_dmamap[i]);
1354 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1357 /* Unload and free the stats buffer and map */
1359 if (sc->re_ldata.re_stag) {
1360 bus_dmamap_unload(sc->re_ldata.re_stag,
1361 sc->re_ldata.re_rx_list_map);
1362 bus_dmamem_free(sc->re_ldata.re_stag,
1363 sc->re_ldata.re_stats,
1364 sc->re_ldata.re_smap);
1365 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1368 if (sc->re_parent_tag)
1369 bus_dma_tag_destroy(sc->re_parent_tag);
1375 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1377 struct re_dmaload_arg arg;
1378 struct mbuf *n = NULL;
1382 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1387 m->m_data = m->m_ext.ext_buf;
1389 m->m_len = m->m_pkthdr.len = MCLBYTES;
1393 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1394 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1401 arg.re_ring = sc->re_ldata.re_rx_list;
1403 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1404 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1405 &arg, BUS_DMA_NOWAIT);
1406 if (error || arg.re_maxsegs != 1) {
1412 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1413 sc->re_ldata.re_rx_mbuf[idx] = m;
1415 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1416 BUS_DMASYNC_PREREAD);
1422 re_tx_list_init(struct re_softc *sc)
1424 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1425 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1427 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1428 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1429 sc->re_ldata.re_tx_prodidx = 0;
1430 sc->re_ldata.re_tx_considx = 0;
1431 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1437 re_rx_list_init(struct re_softc *sc)
1441 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1442 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1444 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1445 error = re_newbuf(sc, i, NULL);
1450 /* Flush the RX descriptors */
1452 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1453 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1455 sc->re_ldata.re_rx_prodidx = 0;
1456 sc->re_head = sc->re_tail = NULL;
1462 * RX handler for C+ and 8169. For the gigE chips, we support
1463 * the reception of jumbo frames that have been fragmented
1464 * across multiple 2K mbuf cluster buffers.
1467 re_rxeof(struct re_softc *sc)
1469 struct ifnet *ifp = &sc->arpcom.ac_if;
1471 struct re_desc *cur_rx;
1472 uint32_t rxstat, rxvlan;
1475 /* Invalidate the descriptor memory */
1477 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1478 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1480 for (i = sc->re_ldata.re_rx_prodidx;
1481 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1482 cur_rx = &sc->re_ldata.re_rx_list[i];
1483 m = sc->re_ldata.re_rx_mbuf[i];
1484 total_len = RE_RXBYTES(cur_rx);
1485 rxstat = le32toh(cur_rx->re_cmdstat);
1486 rxvlan = le32toh(cur_rx->re_vlanctl);
1488 /* Invalidate the RX mbuf and unload its map */
1490 bus_dmamap_sync(sc->re_ldata.re_mtag,
1491 sc->re_ldata.re_rx_dmamap[i],
1492 BUS_DMASYNC_POSTWRITE);
1493 bus_dmamap_unload(sc->re_ldata.re_mtag,
1494 sc->re_ldata.re_rx_dmamap[i]);
1496 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1497 m->m_len = MCLBYTES - ETHER_ALIGN;
1498 if (sc->re_head == NULL) {
1499 sc->re_head = sc->re_tail = m;
1501 sc->re_tail->m_next = m;
1504 re_newbuf(sc, i, NULL);
1509 * NOTE: for the 8139C+, the frame length field
1510 * is always 12 bits in size, but for the gigE chips,
1511 * it is 13 bits (since the max RX frame length is 16K).
1512 * Unfortunately, all 32 bits in the status word
1513 * were already used, so to make room for the extra
1514 * length bit, RealTek took out the 'frame alignment
1515 * error' bit and shifted the other status bits
1516 * over one slot. The OWN, EOR, FS and LS bits are
1517 * still in the same places. We have already extracted
1518 * the frame length and checked the OWN bit, so rather
1519 * than using an alternate bit mapping, we shift the
1520 * status bits one space to the right so we can evaluate
1521 * them using the 8169 status as though it was in the
1522 * same format as that of the 8139C+.
1524 if (sc->re_type == RE_8169)
1527 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1530 * If this is part of a multi-fragment packet,
1531 * discard all the pieces.
1533 if (sc->re_head != NULL) {
1534 m_freem(sc->re_head);
1535 sc->re_head = sc->re_tail = NULL;
1537 re_newbuf(sc, i, m);
1542 * If allocating a replacement mbuf fails,
1543 * reload the current one.
1546 if (re_newbuf(sc, i, NULL)) {
1548 if (sc->re_head != NULL) {
1549 m_freem(sc->re_head);
1550 sc->re_head = sc->re_tail = NULL;
1552 re_newbuf(sc, i, m);
1556 if (sc->re_head != NULL) {
1557 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1559 * Special case: if there's 4 bytes or less
1560 * in this buffer, the mbuf can be discarded:
1561 * the last 4 bytes is the CRC, which we don't
1562 * care about anyway.
1564 if (m->m_len <= ETHER_CRC_LEN) {
1565 sc->re_tail->m_len -=
1566 (ETHER_CRC_LEN - m->m_len);
1569 m->m_len -= ETHER_CRC_LEN;
1570 sc->re_tail->m_next = m;
1573 sc->re_head = sc->re_tail = NULL;
1574 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1576 m->m_pkthdr.len = m->m_len =
1577 (total_len - ETHER_CRC_LEN);
1580 m->m_pkthdr.rcvif = ifp;
1582 /* Do RX checksumming if enabled */
1584 if (ifp->if_capenable & IFCAP_RXCSUM) {
1586 /* Check IP header checksum */
1587 if (rxstat & RE_RDESC_STAT_PROTOID)
1588 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1589 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1590 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1592 /* Check TCP/UDP checksum */
1593 if ((RE_TCPPKT(rxstat) &&
1594 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1595 (RE_UDPPKT(rxstat) &&
1596 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1597 m->m_pkthdr.csum_flags |=
1598 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1599 CSUM_FRAG_NOT_CHECKED;
1600 m->m_pkthdr.csum_data = 0xffff;
1604 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1606 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1608 ifp->if_input(ifp, m);
1612 /* Flush the RX DMA ring */
1614 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1615 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1617 sc->re_ldata.re_rx_prodidx = i;
1621 re_txeof(struct re_softc *sc)
1623 struct ifnet *ifp = &sc->arpcom.ac_if;
1627 /* Invalidate the TX descriptor list */
1629 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1630 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
1632 for (idx = sc->re_ldata.re_tx_considx;
1633 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) {
1634 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1635 if (txstat & RE_TDESC_CMD_OWN)
1638 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
1641 * We only stash mbufs in the last descriptor
1642 * in a fragment chain, which also happens to
1643 * be the only place where the TX status bits
1646 if (txstat & RE_TDESC_CMD_EOF) {
1647 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1648 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1649 bus_dmamap_unload(sc->re_ldata.re_mtag,
1650 sc->re_ldata.re_tx_dmamap[idx]);
1651 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1652 RE_TDESC_STAT_COLCNT))
1653 ifp->if_collisions++;
1654 if (txstat & RE_TDESC_STAT_TXERRSUM)
1659 sc->re_ldata.re_tx_free++;
1662 /* No changes made to the TX ring, so no flush needed */
1663 if (sc->re_ldata.re_tx_free) {
1664 sc->re_ldata.re_tx_considx = idx;
1665 ifp->if_flags &= ~IFF_OACTIVE;
1670 * Some chips will ignore a second TX request issued while an
1671 * existing transmission is in progress. If the transmitter goes
1672 * idle but there are still packets waiting to be sent, we need
1673 * to restart the channel here to flush them out. This only seems
1674 * to be required with the PCIe devices.
1676 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1677 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
1680 * If not all descriptors have been released reaped yet,
1681 * reload the timer so that we will eventually get another
1682 * interrupt that will cause us to re-enter this routine.
1683 * This is done in case the transmitter has gone idle.
1685 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
1686 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1687 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1693 struct re_softc *sc = xsc;
1695 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1696 re_tick_serialized(xsc);
1697 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1701 re_tick_serialized(void *xsc)
1703 struct re_softc *sc = xsc;
1704 struct ifnet *ifp = &sc->arpcom.ac_if;
1705 struct mii_data *mii;
1707 mii = device_get_softc(sc->re_miibus);
1710 if (!(mii->mii_media_status & IFM_ACTIVE))
1713 if (mii->mii_media_status & IFM_ACTIVE &&
1714 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1716 if (!ifq_is_empty(&ifp->if_snd))
1721 callout_reset(&sc->re_timer, hz, re_tick, sc);
1724 #ifdef DEVICE_POLLING
1727 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1729 struct re_softc *sc = ifp->if_softc;
1733 /* disable interrupts */
1734 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1736 case POLL_DEREGISTER:
1737 /* enable interrupts */
1738 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1741 sc->rxcycles = count;
1745 if (!ifq_is_empty(&ifp->if_snd))
1746 (*ifp->if_start)(ifp);
1748 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1751 status = CSR_READ_2(sc, RE_ISR);
1752 if (status == 0xffff)
1755 CSR_WRITE_2(sc, RE_ISR, status);
1758 * XXX check behaviour on receiver stalls.
1761 if (status & RE_ISR_SYSTEM_ERR) {
1769 #endif /* DEVICE_POLLING */
1774 struct re_softc *sc = arg;
1775 struct ifnet *ifp = &sc->arpcom.ac_if;
1778 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1782 status = CSR_READ_2(sc, RE_ISR);
1783 /* If the card has gone away the read returns 0xffff. */
1784 if (status == 0xffff)
1787 CSR_WRITE_2(sc, RE_ISR, status);
1789 if ((status & sc->re_intrs) == 0)
1792 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW))
1795 if ((status & sc->re_tx_ack) ||
1796 (status & RE_ISR_TX_ERR) ||
1797 (status & RE_ISR_TX_DESC_UNAVAIL))
1800 if (status & RE_ISR_SYSTEM_ERR) {
1805 if (status & RE_ISR_LINKCHG) {
1806 callout_stop(&sc->re_timer);
1807 re_tick_serialized(sc);
1811 if (!ifq_is_empty(&ifp->if_snd))
1812 (*ifp->if_start)(ifp);
1816 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1818 struct ifnet *ifp = &sc->arpcom.ac_if;
1819 struct mbuf *m, *m_new = NULL;
1820 struct re_dmaload_arg arg;
1825 if (sc->re_ldata.re_tx_free <= 4)
1831 * Set up checksum offload. Note: checksum offload bits must
1832 * appear in all descriptors of a multi-descriptor transmit
1833 * attempt. (This is according to testing done with an 8169
1834 * chip. I'm not sure if this is a requirement or a bug.)
1839 if (m->m_pkthdr.csum_flags & CSUM_IP)
1840 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1841 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1842 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1843 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1844 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1848 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1849 if (arg.re_maxsegs > 4)
1850 arg.re_maxsegs -= 4;
1851 arg.re_ring = sc->re_ldata.re_tx_list;
1853 map = sc->re_ldata.re_tx_dmamap[*idx];
1856 * With some of the RealTek chips, using the checksum offload
1857 * support in conjunction with the autopadding feature results
1858 * in the transmission of corrupt frames. For example, if we
1859 * need to send a really small IP fragment that's less than 60
1860 * bytes in size, and IP header checksumming is enabled, the
1861 * resulting ethernet frame that appears on the wire will
1862 * have garbled payload. To work around this, if TX checksum
1863 * offload is enabled, we always manually pad short frames out
1864 * to the minimum ethernet frame size. We do this by pretending
1865 * the mbuf chain has too many fragments so the coalescing code
1866 * below can assemble the packet into a single buffer that's
1867 * padded out to the mininum frame size.
1869 * Note: this appears unnecessary for TCP, and doing it for TCP
1870 * with PCIe adapters seems to result in bad checksums.
1872 if (arg.re_flags && !(arg.re_flags & RE_TDESC_CMD_TCPCSUM) &&
1873 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
1876 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1877 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1880 if (error && error != EFBIG) {
1881 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1885 /* Too many segments to map, coalesce into a single mbuf */
1887 if (error || arg.re_maxsegs == 0) {
1888 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1889 if (m_new == NULL) {
1897 * Manually pad short frames, and zero the pad space
1898 * to avoid leaking data.
1900 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) {
1901 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
1902 RE_MIN_FRAMELEN - m_new->m_pkthdr.len);
1903 m_new->m_pkthdr.len += RE_MIN_FRAMELEN -
1904 m_new->m_pkthdr.len;
1905 m_new->m_len = m_new->m_pkthdr.len;
1911 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1912 arg.re_ring = sc->re_ldata.re_tx_list;
1914 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1915 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1918 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1924 * Insure that the map for this transmission
1925 * is placed at the array index of the last descriptor
1928 sc->re_ldata.re_tx_dmamap[*idx] =
1929 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1930 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1932 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1933 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1936 * Set up hardware VLAN tagging. Note: vlan tag info must
1937 * appear in the first descriptor of a multi-descriptor
1938 * transmission attempt.
1941 if (m->m_flags & M_VLANTAG) {
1942 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1943 htole32(htobe16(m->m_pkthdr.ether_vlantag) |
1944 RE_TDESC_VLANCTL_TAG);
1947 /* Transfer ownership of packet to the chip. */
1949 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1950 htole32(RE_TDESC_CMD_OWN);
1951 if (*idx != arg.re_idx)
1952 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1953 htole32(RE_TDESC_CMD_OWN);
1955 RE_DESC_INC(arg.re_idx);
1962 * Main transmit routine for C+ and gigE NICs.
1966 re_start(struct ifnet *ifp)
1968 struct re_softc *sc = ifp->if_softc;
1969 struct mbuf *m_head;
1970 struct mbuf *m_head2;
1971 int called_defrag, idx, need_trans;
1973 if (!sc->re_link || (ifp->if_flags & IFF_OACTIVE))
1976 idx = sc->re_ldata.re_tx_prodidx;
1979 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1980 m_head = ifq_poll(&ifp->if_snd);
1984 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
1986 * If we could not encapsulate the defragged packet,
1987 * the returned m_head2 is garbage and we must dequeue
1988 * and throw away the original packet.
1990 if (called_defrag) {
1991 ifq_dequeue(&ifp->if_snd, m_head);
1994 ifp->if_flags |= IFF_OACTIVE;
1999 * Clean out the packet we encapsulated. If we defragged
2000 * the packet the m_head2 is the one that got encapsulated
2001 * and the original must be thrown away. Otherwise m_head2
2002 * *IS* the original.
2004 ifq_dequeue(&ifp->if_snd, m_head);
2010 * If there's a BPF listener, bounce a copy of this frame
2013 ETHER_BPF_MTAP(ifp, m_head2);
2017 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
2018 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
2019 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2023 /* Flush the TX descriptors */
2024 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2025 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2027 sc->re_ldata.re_tx_prodidx = idx;
2030 * RealTek put the TX poll request register in a different
2031 * location on the 8169 gigE chip. I don't know why.
2033 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2035 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2037 * Use the countdown timer for interrupt moderation.
2038 * 'TX done' interrupts are disabled. Instead, we reset the
2039 * countdown timer, which will begin counting until it hits
2040 * the value in the TIMERINT register, and then trigger an
2041 * interrupt. Each time we write to the TIMERCNT register,
2042 * the timer count is reset to 0.
2044 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2048 * Set a timeout in case the chip goes out to lunch.
2056 struct re_softc *sc = xsc;
2057 struct ifnet *ifp = &sc->arpcom.ac_if;
2058 struct mii_data *mii;
2061 mii = device_get_softc(sc->re_miibus);
2064 * Cancel pending I/O and free all RX/TX buffers.
2069 * Enable C+ RX and TX mode, as well as VLAN stripping and
2070 * RX checksum offload. We must configure the C+ register
2071 * before all others.
2073 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2074 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
2075 (ifp->if_capenable & IFCAP_RXCSUM ?
2076 RE_CPLUSCMD_RXCSUM_ENB : 0));
2079 * Init our MAC address. Even though the chipset
2080 * documentation doesn't mention it, we need to enter "Config
2081 * register write enable" mode to modify the ID registers.
2083 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2084 CSR_WRITE_4(sc, RE_IDR0,
2085 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2086 CSR_WRITE_2(sc, RE_IDR4,
2087 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2088 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2091 * For C+ mode, initialize the RX descriptors and mbufs.
2093 re_rx_list_init(sc);
2094 re_tx_list_init(sc);
2097 * Load the addresses of the RX and TX lists into the chip.
2099 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2100 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2101 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2102 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2104 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2105 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2106 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2107 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2110 * Enable transmit and receive.
2112 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2115 * Set the initial TX and RX configuration.
2117 if (sc->re_testmode) {
2118 if (sc->re_type == RE_8169)
2119 CSR_WRITE_4(sc, RE_TXCFG,
2120 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2122 CSR_WRITE_4(sc, RE_TXCFG,
2123 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2125 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2127 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2129 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2131 /* Set the individual bit to receive frames for this host only. */
2132 rxcfg = CSR_READ_4(sc, RE_RXCFG);
2133 rxcfg |= RE_RXCFG_RX_INDIV;
2135 /* If we want promiscuous mode, set the allframes bit. */
2136 if (ifp->if_flags & IFF_PROMISC) {
2137 rxcfg |= RE_RXCFG_RX_ALLPHYS;
2138 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2140 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
2141 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2145 * Set capture broadcast bit to capture broadcast frames.
2147 if (ifp->if_flags & IFF_BROADCAST) {
2148 rxcfg |= RE_RXCFG_RX_BROAD;
2149 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2151 rxcfg &= ~RE_RXCFG_RX_BROAD;
2152 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2156 * Program the multicast filter, if necessary.
2160 #ifdef DEVICE_POLLING
2162 * Disable interrupts if we are polling.
2164 if (ifp->if_flags & IFF_POLLING)
2165 CSR_WRITE_2(sc, RE_IMR, 0);
2166 else /* otherwise ... */
2167 #endif /* DEVICE_POLLING */
2169 * Enable interrupts.
2171 if (sc->re_testmode)
2172 CSR_WRITE_2(sc, RE_IMR, 0);
2174 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2175 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2177 /* Set initial TX threshold */
2178 sc->re_txthresh = RE_TX_THRESH_INIT;
2180 /* Start RX/TX process. */
2181 if (sc->re_flags & RE_F_HASMPC)
2182 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2184 /* Enable receiver and transmitter. */
2185 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2188 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2190 * Initialize the timer interrupt register so that
2191 * a timer interrupt will be generated once the timer
2192 * reaches a certain number of ticks. The timer is
2193 * reloaded on each transmit. This gives us TX interrupt
2194 * moderation, which dramatically improves TX frame rate.
2196 if (sc->re_type == RE_8169)
2197 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2199 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2203 * For 8169 gigE NICs, set the max allowed RX packet
2204 * size so we can receive jumbo frames.
2206 if (sc->re_type == RE_8169)
2207 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2209 if (sc->re_testmode) {
2215 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2217 ifp->if_flags |= IFF_RUNNING;
2218 ifp->if_flags &= ~IFF_OACTIVE;
2221 callout_reset(&sc->re_timer, hz, re_tick, sc);
2225 * Set media options.
2228 re_ifmedia_upd(struct ifnet *ifp)
2230 struct re_softc *sc = ifp->if_softc;
2231 struct mii_data *mii;
2233 mii = device_get_softc(sc->re_miibus);
2240 * Report current media status.
2243 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2245 struct re_softc *sc = ifp->if_softc;
2246 struct mii_data *mii;
2248 mii = device_get_softc(sc->re_miibus);
2251 ifmr->ifm_active = mii->mii_media_active;
2252 ifmr->ifm_status = mii->mii_media_status;
2256 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2258 struct re_softc *sc = ifp->if_softc;
2259 struct ifreq *ifr = (struct ifreq *) data;
2260 struct mii_data *mii;
2265 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2267 ifp->if_mtu = ifr->ifr_mtu;
2270 if (ifp->if_flags & IFF_UP)
2272 else if (ifp->if_flags & IFF_RUNNING)
2282 mii = device_get_softc(sc->re_miibus);
2283 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2286 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2287 ifp->if_capenable |=
2288 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2289 if (ifp->if_capenable & IFCAP_TXCSUM)
2290 ifp->if_hwassist = RE_CSUM_FEATURES;
2292 ifp->if_hwassist = 0;
2293 if (ifp->if_flags & IFF_RUNNING)
2297 error = ether_ioctl(ifp, command, data);
2304 re_watchdog(struct ifnet *ifp)
2306 struct re_softc *sc = ifp->if_softc;
2308 if_printf(ifp, "watchdog timeout\n");
2317 if (!ifq_is_empty(&ifp->if_snd))
2322 * Stop the adapter and free any mbufs allocated to the
2326 re_stop(struct re_softc *sc)
2328 struct ifnet *ifp = &sc->arpcom.ac_if;
2332 callout_stop(&sc->re_timer);
2334 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2336 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2337 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2338 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2340 if (sc->re_head != NULL) {
2341 m_freem(sc->re_head);
2342 sc->re_head = sc->re_tail = NULL;
2345 /* Free the TX list buffers. */
2346 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2347 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2348 bus_dmamap_unload(sc->re_ldata.re_mtag,
2349 sc->re_ldata.re_tx_dmamap[i]);
2350 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2351 sc->re_ldata.re_tx_mbuf[i] = NULL;
2355 /* Free the RX list buffers. */
2356 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2357 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2358 bus_dmamap_unload(sc->re_ldata.re_mtag,
2359 sc->re_ldata.re_rx_dmamap[i]);
2360 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2361 sc->re_ldata.re_rx_mbuf[i] = NULL;
2367 * Device suspend routine. Stop the interface and save some PCI
2368 * settings in case the BIOS doesn't restore them properly on
2372 re_suspend(device_t dev)
2374 #ifndef BURN_BRIDGES
2377 struct re_softc *sc = device_get_softc(dev);
2381 #ifndef BURN_BRIDGES
2382 for (i = 0; i < 5; i++)
2383 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2384 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2385 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2386 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2387 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2396 * Device resume routine. Restore some PCI settings in case the BIOS
2397 * doesn't, re-enable busmastering, and restart the interface if
2401 re_resume(device_t dev)
2403 struct re_softc *sc = device_get_softc(dev);
2404 struct ifnet *ifp = &sc->arpcom.ac_if;
2405 #ifndef BURN_BRIDGES
2409 #ifndef BURN_BRIDGES
2410 /* better way to do this? */
2411 for (i = 0; i < 5; i++)
2412 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2413 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2414 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2415 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2416 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2418 /* reenable busmastering */
2419 pci_enable_busmaster(dev);
2420 pci_enable_io(dev, SYS_RES_IOPORT);
2423 /* reinitialize interface if necessary */
2424 if (ifp->if_flags & IFF_UP)
2433 * Stop all chip I/O so that the kernel's probe routines don't
2434 * get confused by errant DMAs when rebooting.
2437 re_shutdown(device_t dev)
2439 struct re_softc *sc = device_get_softc(dev);
2440 struct ifnet *ifp = &sc->arpcom.ac_if;
2442 lwkt_serialize_enter(ifp->if_serializer);
2444 lwkt_serialize_exit(ifp->if_serializer);
2448 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS)
2450 struct re_softc *sc = arg1;
2451 struct ifnet *ifp = &sc->arpcom.ac_if;
2452 int error = 0, mod, mod_old;
2454 lwkt_serialize_enter(ifp->if_serializer);
2456 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc);
2458 error = sysctl_handle_int(oidp, &mod, 0, req);
2459 if (error || req->newptr == NULL || mod == mod_old)
2461 if (mod != 0 && mod != 1) {
2467 RE_ENABLE_TX_MODERATION(sc);
2469 RE_DISABLE_TX_MODERATION(sc);
2471 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP))
2474 lwkt_serialize_exit(ifp->if_serializer);