2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * from: @(#)fdreg.h 7.1 (Berkeley) 5/9/91
34 * $FreeBSD: src/sys/isa/fdreg.h,v 1.13 2000/01/06 07:13:54 imp Exp $
35 * $DragonFly: src/sys/dev/disk/fd/fdreg.h,v 1.3 2003/08/07 21:16:52 dillon Exp $
39 * AT floppy controller registers and bitfields
42 /* uses NEC765 controller */
46 #define FDOUT 2 /* Digital Output Register (W) */
47 #define FDO_FDSEL 0x03 /* floppy device select */
48 #define FDO_FRST 0x04 /* floppy controller reset */
49 #define FDO_FDMAEN 0x08 /* enable floppy DMA and Interrupt */
50 #define FDO_MOEN0 0x10 /* motor enable drive 0 */
51 #define FDO_MOEN1 0x20 /* motor enable drive 1 */
52 #define FDO_MOEN2 0x40 /* motor enable drive 2 */
53 #define FDO_MOEN3 0x80 /* motor enable drive 3 */
55 #define FDSTS 4 /* NEC 765 Main Status Register (R) */
56 #define FDDATA 5 /* NEC 765 Data Register (R/W) */
57 #define FDCTL 7 /* Control Register (W) */
60 # define FDC_500KBPS 0x00 /* 500KBPS MFM drive transfer rate */
61 # define FDC_300KBPS 0x01 /* 300KBPS MFM drive transfer rate */
62 # define FDC_250KBPS 0x02 /* 250KBPS MFM drive transfer rate */
63 # define FDC_125KBPS 0x03 /* 125KBPS FM drive transfer rate */
64 /* for some controllers 1MPBS instead */
65 #endif /* FDC_500KBPS */
68 * this is the secret PIO data port (offset from base)
70 #define FDC_YE_DATAPORT 6
72 #define FDIN 7 /* Digital Input Register (R) */
73 #define FDI_DCHG 0x80 /* diskette has been changed */
74 /* requires drive and motor being selected */
75 /* is cleared by any step pulse to drive */