2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/ata/ata-all.h,v 1.118 2006/06/28 09:59:09 sos Exp $
27 * $DragonFly: src/sys/dev/disk/nata/ata-all.h,v 1.2 2006/12/04 15:15:54 tgen Exp $
30 #include <sys/param.h>
33 #include <sys/callout.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
37 #include <sys/objcache.h>
38 #include <sys/queue.h>
40 #include <sys/spinlock.h>
41 #include <sys/systm.h>
42 #include <sys/taskqueue.h>
44 #include <machine/bus_dma.h>
46 /* ATA register defines */
47 #define ATA_DATA 0 /* (RW) data */
49 #define ATA_FEATURE 1 /* (W) feature */
50 #define ATA_F_DMA 0x01 /* enable DMA */
51 #define ATA_F_OVL 0x02 /* enable overlap */
53 #define ATA_COUNT 2 /* (W) sector count */
55 #define ATA_SECTOR 3 /* (RW) sector # */
56 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
57 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
58 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
59 #define ATA_D_LBA 0x40 /* use LBA addressing */
60 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
62 #define ATA_COMMAND 7 /* (W) command */
64 #define ATA_ERROR 8 /* (R) error */
65 #define ATA_E_ILI 0x01 /* illegal length */
66 #define ATA_E_NM 0x02 /* no media */
67 #define ATA_E_ABORT 0x04 /* command aborted */
68 #define ATA_E_MCR 0x08 /* media change request */
69 #define ATA_E_IDNF 0x10 /* ID not found */
70 #define ATA_E_MC 0x20 /* media changed */
71 #define ATA_E_UNC 0x40 /* uncorrectable data */
72 #define ATA_E_ICRC 0x80 /* UDMA crc error */
73 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
75 #define ATA_IREASON 9 /* (R) interrupt reason */
76 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
77 #define ATA_I_IN 0x02 /* read (1) | write (0) */
78 #define ATA_I_RELEASE 0x04 /* released bus (1) */
79 #define ATA_I_TAGMASK 0xf8 /* tag mask */
81 #define ATA_STATUS 10 /* (R) status */
82 #define ATA_ALTSTAT 11 /* (R) alternate status */
83 #define ATA_S_ERROR 0x01 /* error */
84 #define ATA_S_INDEX 0x02 /* index */
85 #define ATA_S_CORR 0x04 /* data corrected */
86 #define ATA_S_DRQ 0x08 /* data request */
87 #define ATA_S_DSC 0x10 /* drive seek completed */
88 #define ATA_S_SERVICE 0x10 /* drive needs service */
89 #define ATA_S_DWF 0x20 /* drive write fault */
90 #define ATA_S_DMA 0x20 /* DMA ready */
91 #define ATA_S_READY 0x40 /* drive ready */
92 #define ATA_S_BUSY 0x80 /* busy */
94 #define ATA_CONTROL 12 /* (W) control */
96 #define ATA_CTLOFFSET 0x206 /* control register offset */
97 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */
98 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */
99 #define ATA_A_IDS 0x02 /* disable interrupts */
100 #define ATA_A_RESET 0x04 /* RESET controller */
101 #define ATA_A_4BIT 0x08 /* 4 head bits */
102 #define ATA_A_HOB 0x80 /* High Order Byte enable */
104 /* SATA register defines */
105 #define ATA_SSTATUS 13
106 #define ATA_SS_DET_MASK 0x0000000f
107 #define ATA_SS_DET_NO_DEVICE 0x00000000
108 #define ATA_SS_DET_DEV_PRESENT 0x00000001
109 #define ATA_SS_DET_PHY_ONLINE 0x00000003
110 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
112 #define ATA_SS_SPD_MASK 0x000000f0
113 #define ATA_SS_SPD_NO_SPEED 0x00000000
114 #define ATA_SS_SPD_GEN1 0x00000010
115 #define ATA_SS_SPD_GEN2 0x00000020
117 #define ATA_SS_IPM_MASK 0x00000f00
118 #define ATA_SS_IPM_NO_DEVICE 0x00000000
119 #define ATA_SS_IPM_ACTIVE 0x00000100
120 #define ATA_SS_IPM_PARTIAL 0x00000200
121 #define ATA_SS_IPM_SLUMBER 0x00000600
123 #define ATA_SS_CONWELL_MASK \
124 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK)
125 #define ATA_SS_CONWELL_GEN1 \
126 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE)
127 #define ATA_SS_CONWELL_GEN2 \
128 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE)
130 #define ATA_SERROR 14
131 #define ATA_SE_DATA_CORRECTED 0x00000001
132 #define ATA_SE_COMM_CORRECTED 0x00000002
133 #define ATA_SE_DATA_ERR 0x00000100
134 #define ATA_SE_COMM_ERR 0x00000200
135 #define ATA_SE_PROT_ERR 0x00000400
136 #define ATA_SE_HOST_ERR 0x00000800
137 #define ATA_SE_PHY_CHANGED 0x00010000
138 #define ATA_SE_PHY_IERROR 0x00020000
139 #define ATA_SE_COMM_WAKE 0x00040000
140 #define ATA_SE_DECODE_ERR 0x00080000
141 #define ATA_SE_PARITY_ERR 0x00100000
142 #define ATA_SE_CRC_ERR 0x00200000
143 #define ATA_SE_HANDSHAKE_ERR 0x00400000
144 #define ATA_SE_LINKSEQ_ERR 0x00800000
145 #define ATA_SE_TRANSPORT_ERR 0x01000000
146 #define ATA_SE_UNKNOWN_FIS 0x02000000
148 #define ATA_SCONTROL 15
149 #define ATA_SC_DET_MASK 0x0000000f
150 #define ATA_SC_DET_IDLE 0x00000000
151 #define ATA_SC_DET_RESET 0x00000001
152 #define ATA_SC_DET_DISABLE 0x00000004
154 #define ATA_SC_SPD_MASK 0x000000f0
155 #define ATA_SC_SPD_NO_SPEED 0x00000000
156 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
157 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
159 #define ATA_SC_IPM_MASK 0x00000f00
160 #define ATA_SC_IPM_NONE 0x00000000
161 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
162 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
164 #define ATA_SACTIVE 16
166 /* SATA AHCI v1.0 register defines */
167 #define ATA_AHCI_CAP 0x00
168 #define ATA_AHCI_NPMASK 0x1f
169 #define ATA_AHCI_CAP_CLO 0x01000000
170 #define ATA_AHCI_CAP_64BIT 0x80000000
172 #define ATA_AHCI_GHC 0x04
173 #define ATA_AHCI_GHC_AE 0x80000000
174 #define ATA_AHCI_GHC_IE 0x00000002
175 #define ATA_AHCI_GHC_HR 0x80000001
177 #define ATA_AHCI_IS 0x08
178 #define ATA_AHCI_PI 0x0c
179 #define ATA_AHCI_VS 0x10
181 #define ATA_AHCI_OFFSET 0x80
183 #define ATA_AHCI_P_CLB 0x100
184 #define ATA_AHCI_P_CLBU 0x104
185 #define ATA_AHCI_P_FB 0x108
186 #define ATA_AHCI_P_FBU 0x10c
187 #define ATA_AHCI_P_IS 0x110
188 #define ATA_AHCI_P_IE 0x114
189 #define ATA_AHCI_P_IX_DHR 0x00000001
190 #define ATA_AHCI_P_IX_PS 0x00000002
191 #define ATA_AHCI_P_IX_DS 0x00000004
192 #define ATA_AHCI_P_IX_SDB 0x00000008
193 #define ATA_AHCI_P_IX_UF 0x00000010
194 #define ATA_AHCI_P_IX_DP 0x00000020
195 #define ATA_AHCI_P_IX_PC 0x00000040
196 #define ATA_AHCI_P_IX_DI 0x00000080
198 #define ATA_AHCI_P_IX_PRC 0x00400000
199 #define ATA_AHCI_P_IX_IPM 0x00800000
200 #define ATA_AHCI_P_IX_OF 0x01000000
201 #define ATA_AHCI_P_IX_INF 0x04000000
202 #define ATA_AHCI_P_IX_IF 0x08000000
203 #define ATA_AHCI_P_IX_HBD 0x10000000
204 #define ATA_AHCI_P_IX_HBF 0x20000000
205 #define ATA_AHCI_P_IX_TFE 0x40000000
206 #define ATA_AHCI_P_IX_CPD 0x80000000
208 #define ATA_AHCI_P_CMD 0x118
209 #define ATA_AHCI_P_CMD_ST 0x00000001
210 #define ATA_AHCI_P_CMD_SUD 0x00000002
211 #define ATA_AHCI_P_CMD_POD 0x00000004
212 #define ATA_AHCI_P_CMD_CLO 0x00000008
213 #define ATA_AHCI_P_CMD_FRE 0x00000010
214 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
215 #define ATA_AHCI_P_CMD_ISS 0x00002000
216 #define ATA_AHCI_P_CMD_FR 0x00004000
217 #define ATA_AHCI_P_CMD_CR 0x00008000
218 #define ATA_AHCI_P_CMD_CPS 0x00010000
219 #define ATA_AHCI_P_CMD_PMA 0x00020000
220 #define ATA_AHCI_P_CMD_HPCP 0x00040000
221 #define ATA_AHCI_P_CMD_ISP 0x00080000
222 #define ATA_AHCI_P_CMD_CPD 0x00100000
223 #define ATA_AHCI_P_CMD_ATAPI 0x01000000
224 #define ATA_AHCI_P_CMD_DLAE 0x02000000
225 #define ATA_AHCI_P_CMD_ALPE 0x04000000
226 #define ATA_AHCI_P_CMD_ASP 0x08000000
227 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
228 #define ATA_AHCI_P_CMD_NOOP 0x00000000
229 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000
230 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000
231 #define ATA_AHCI_P_CMD_SLUMPER 0x60000000
233 #define ATA_AHCI_P_TFD 0x120
234 #define ATA_AHCI_P_SIG 0x124
235 #define ATA_AHCI_P_SSTS 0x128
236 #define ATA_AHCI_P_SCTL 0x12c
237 #define ATA_AHCI_P_SERR 0x130
238 #define ATA_AHCI_P_SACT 0x134
239 #define ATA_AHCI_P_CI 0x138
241 #define ATA_AHCI_CL_SIZE 32
242 #define ATA_AHCI_CL_OFFSET 0
243 #define ATA_AHCI_FB_OFFSET 1024
244 #define ATA_AHCI_CT_OFFSET 1024+256
245 #define ATA_AHCI_CT_SG_OFFSET 128
246 #define ATA_AHCI_CT_SIZE 256
248 /* DMA register defines */
249 #define ATA_DMA_ENTRIES 256
250 #define ATA_DMA_EOT 0x80000000
252 #define ATA_BMCMD_PORT 17
253 #define ATA_BMCMD_START_STOP 0x01
254 #define ATA_BMCMD_WRITE_READ 0x08
256 #define ATA_BMDEVSPEC_0 18
257 #define ATA_BMSTAT_PORT 19
258 #define ATA_BMSTAT_ACTIVE 0x01
259 #define ATA_BMSTAT_ERROR 0x02
260 #define ATA_BMSTAT_INTERRUPT 0x04
261 #define ATA_BMSTAT_MASK 0x07
262 #define ATA_BMSTAT_DMA_MASTER 0x20
263 #define ATA_BMSTAT_DMA_SLAVE 0x40
264 #define ATA_BMSTAT_DMA_SIMPLEX 0x80
266 #define ATA_BMDEVSPEC_1 20
267 #define ATA_BMDTP_PORT 21
269 #define ATA_IDX_ADDR 22
270 #define ATA_IDX_DATA 23
271 #define ATA_MAX_RES 24
274 #define ATA_PRIMARY 0x1f0
275 #define ATA_SECONDARY 0x170
276 #define ATA_PC98_BANK 0x432
277 #define ATA_IOSIZE 0x08
278 #define ATA_PC98_IOSIZE 0x10
279 #define ATA_CTLIOSIZE 0x01
280 #define ATA_BMIOSIZE 0x08
281 #define ATA_PC98_BANKIOSIZE 0x01
282 #define ATA_IOADDR_RID 0
283 #define ATA_CTLADDR_RID 1
284 #define ATA_BMADDR_RID 0x20
285 #define ATA_PC98_CTLADDR_RID 8
286 #define ATA_PC98_BANKADDR_RID 9
287 #define ATA_IRQ_RID 0
288 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
289 #define ATA_CFA_MAGIC1 0x844A
290 #define ATA_CFA_MAGIC2 0x848A
291 #define ATAPI_MAGIC_LSB 0x14
292 #define ATAPI_MAGIC_MSB 0xeb
293 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN)
294 #define ATAPI_P_WRITE (ATA_S_DRQ)
295 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD)
296 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
297 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN)
298 #define ATAPI_P_ABORT 0
299 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_NOPOLL)
300 #define ATA_OP_CONTINUES 0
301 #define ATA_OP_FINISHED 1
302 #define ATA_MAX_28BIT_LBA 268435455UL
304 /* structure used for composite atomic operations */
305 #define MAX_COMPOSITES 32 /* u_int32_t bits */
306 struct ata_composite {
307 struct spinlock lock; /* control lock */
308 u_int32_t rd_needed; /* needed read subdisks */
309 u_int32_t rd_done; /* done read subdisks */
310 u_int32_t wr_needed; /* needed write subdisks */
311 u_int32_t wr_depend; /* write depends on subdisks */
312 u_int32_t wr_done; /* done write subdisks */
313 struct ata_request *request[MAX_COMPOSITES];
314 u_int32_t residual; /* bytes still to transfer */
319 /* structure used to queue an ATA/ATAPI request */
321 device_t dev; /* device handle */
322 device_t parent; /* channel handle */
325 u_int8_t command; /* command reg */
326 u_int16_t feature; /* feature reg */
327 u_int16_t count; /* count reg */
328 u_int64_t lba; /* lba reg */
331 u_int8_t ccb[16]; /* ATAPI command block */
332 struct atapi_sense sense; /* ATAPI request sense data */
333 u_int8_t saved_cmd; /* ATAPI saved command */
336 u_int32_t bytecount; /* bytes to transfer */
337 u_int32_t transfersize; /* bytes pr transfer */
338 caddr_t data; /* pointer to data buf */
340 #define ATA_R_CONTROL 0x00000001
341 #define ATA_R_READ 0x00000002
342 #define ATA_R_WRITE 0x00000004
343 #define ATA_R_ATAPI 0x00000008
344 #define ATA_R_DMA 0x00000010
345 #define ATA_R_QUIET 0x00000020
346 #define ATA_R_TIMEOUT 0x00000040
348 #define ATA_R_ORDERED 0x00000100
349 #define ATA_R_AT_HEAD 0x00000200
350 #define ATA_R_REQUEUE 0x00000400
351 #define ATA_R_THREAD 0x00000800
352 #define ATA_R_DIRECT 0x00001000
354 #define ATA_R_DEBUG 0x10000000
355 #define ATA_R_DANGER1 0x20000000
356 #define ATA_R_DANGER2 0x40000000
358 u_int8_t status; /* ATA status */
359 u_int8_t error; /* ATA error */
360 u_int8_t dmastat; /* DMA status */
361 u_int32_t donecount; /* bytes transferred */
362 int result; /* result error code */
363 void (*callback)(struct ata_request *request);
364 struct spinlock done; /* request done sema */
365 int retries; /* retry count */
366 int timeout; /* timeout for this cmd */
367 struct callout callout; /* callout management */
368 struct task task; /* task management */
369 struct bio *bio; /* bio for this request */
370 int this; /* this request ID */
371 struct ata_composite *composite; /* for composite atomic ops */
372 void *driver; /* driver specific */
373 TAILQ_ENTRY(ata_request) chain; /* list management */
376 /* define this for debugging request processing */
378 #define ATA_DEBUG_RQ(request, string) \
380 if (request->flags & ATA_R_DEBUG) \
381 device_printf(request->dev, "req=%p %s " string "\n", \
382 request, ata_cmd2str(request)); \
385 #define ATA_DEBUG_RQ(request, string)
389 /* structure describing an ATA/ATAPI device */
391 device_t dev; /* device handle */
392 int unit; /* physical unit */
393 #define ATA_MASTER 0x00
394 #define ATA_SLAVE 0x10
396 struct ata_params param; /* ata param structure */
397 int mode; /* current transfermode */
398 u_int32_t max_iosize; /* max IO size */
400 #define ATA_D_USE_CHS 0x0001
401 #define ATA_D_MEDIA_CHANGED 0x0002
402 #define ATA_D_ENC_PRESENT 0x0004
403 #define ATA_D_48BIT_ACTIVE 0x0008
406 /* structure for holding DMA Physical Region Descriptors (PRD) entries */
407 struct ata_dma_prdentry {
412 /* structure used by the setprd function */
413 struct ata_dmasetprd_args {
419 /* structure holding DMA related information */
421 bus_dma_tag_t dmatag; /* parent DMA tag */
422 bus_dma_tag_t sg_tag; /* SG list DMA tag */
423 bus_dmamap_t sg_map; /* SG list DMA map */
424 void *sg; /* DMA transfer table */
425 bus_addr_t sg_bus; /* bus address of dmatab */
426 bus_dma_tag_t data_tag; /* data DMA tag */
427 bus_dmamap_t data_map; /* data DMA map */
428 bus_dma_tag_t work_tag; /* workspace DMA tag */
429 bus_dmamap_t work_map; /* workspace DMA map */
430 u_int8_t *work; /* workspace */
431 bus_addr_t work_bus; /* bus address of dmatab */
433 u_int32_t alignment; /* DMA SG list alignment */
434 u_int32_t boundary; /* DMA SG list boundary */
435 u_int32_t segsize; /* DMA SG list segment size */
436 u_int32_t max_iosize; /* DMA data max IO size */
437 u_int32_t cur_iosize; /* DMA data current IO size */
439 #define ATA_DMA_READ 0x01 /* transaction is a read */
440 #define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */
441 #define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */
443 void (*alloc)(device_t dev);
444 void (*free)(device_t dev);
445 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
446 int (*load)(device_t dev, caddr_t data, int32_t count, int dir, void *addr, int *nsegs);
447 int (*unload)(device_t dev);
448 int (*start)(device_t dev);
449 int (*stop)(device_t dev);
450 void (*reset)(device_t dev);
453 /* structure holding lowlevel functions */
454 struct ata_lowlevel {
455 int (*status)(device_t dev);
456 int (*begin_transaction)(struct ata_request *request);
457 int (*end_transaction)(struct ata_request *request);
458 int (*command)(struct ata_request *request);
461 /* structure holding resources for an ATA channel */
462 struct ata_resource {
463 struct resource *res;
467 /* structure describing an ATA channel */
469 device_t dev; /* device handle */
470 int unit; /* physical channel */
471 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
472 struct resource *r_irq; /* interrupt of this channel */
473 void *ih; /* interrupt handle */
474 struct ata_lowlevel hw; /* lowlevel HW functions */
475 struct ata_dma *dma; /* DMA data / functions */
476 int flags; /* channel flags */
477 #define ATA_NO_SLAVE 0x01
478 #define ATA_USE_16BIT 0x02
479 #define ATA_ATAPI_DMA_RO 0x04
480 #define ATA_NO_48BIT_DMA 0x08
481 #define ATA_ALWAYS_DMASTAT 0x10
483 int devices; /* what is present */
484 #define ATA_ATA_MASTER 0x01
485 #define ATA_ATA_SLAVE 0x02
486 #define ATA_ATAPI_MASTER 0x04
487 #define ATA_ATAPI_SLAVE 0x08
489 struct spinlock state_mtx; /* state lock */
490 int state; /* ATA channel state */
491 #define ATA_IDLE 0x0000
492 #define ATA_ACTIVE 0x0001
493 #define ATA_STALL_QUEUE 0x0002
495 struct spinlock queue_mtx; /* queue lock */
496 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */
497 struct ata_request *freezepoint; /* composite freezepoint */
498 struct ata_request *running; /* currently running request */
501 /* disk bay/enclosure related */
502 #define ATA_LED_OFF 0x00
503 #define ATA_LED_RED 0x01
504 #define ATA_LED_GREEN 0x02
505 #define ATA_LED_ORANGE 0x03
506 #define ATA_LED_MASK 0x03
509 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data);
510 extern struct intr_config_hook *ata_delayed_attach;
511 extern devclass_t ata_devclass;
514 /* public prototypes */
516 int ata_probe(device_t dev);
517 int ata_attach(device_t dev);
518 int ata_detach(device_t dev);
519 int ata_reinit(device_t dev);
520 int ata_suspend(device_t dev);
521 int ata_resume(device_t dev);
522 int ata_interrupt(void *data);
523 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data);
524 int ata_identify(device_t dev);
525 void ata_default_registers(device_t dev);
526 void ata_modify_if_48bit(struct ata_request *request);
527 void ata_udelay(int interval);
528 char *ata_mode2str(int mode);
529 int ata_pmode(struct ata_params *ap);
530 int ata_wmode(struct ata_params *ap);
531 int ata_umode(struct ata_params *ap);
532 int ata_limit_mode(device_t dev, int mode, int maxmode);
535 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count);
536 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout);
537 void ata_queue_request(struct ata_request *request);
538 void ata_start(device_t dev);
539 void ata_finish(struct ata_request *request);
540 void ata_timeout(struct ata_request *);
541 void ata_catch_inflight(device_t dev);
542 void ata_fail_requests(device_t dev);
543 char *ata_cmd2str(struct ata_request *request);
545 /* ata-lowlevel.c: */
546 void ata_generic_hw(device_t dev);
547 int ata_begin_transaction(struct ata_request *);
548 int ata_end_transaction(struct ata_request *);
549 void ata_generic_reset(device_t dev);
550 int ata_generic_command(struct ata_request *request);
552 /* macros for alloc/free of struct ata_request */
553 extern struct objcache *ata_request_cache;
554 #define ata_alloc_request() objcache_get(ata_request_cache, M_WAITOK | M_ZERO)
555 #define ata_free_request(request) { \
556 if (!(request->flags & ATA_R_DANGER2)) \
557 objcache_put(ata_request_cache, request); \
559 /* macros for alloc/free of struct ata_composite */
560 extern struct objcache *ata_composite_cache;
561 #define ata_alloc_composite() objcache_get(ata_composite_cache, \
563 #define ata_free_composite(composite) objcache_put(ata_composite_cache, \
566 MALLOC_DECLARE(M_ATA);
568 /* misc newbus defines */
569 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
571 /* macros to hide busspace uglyness */
572 #define ATA_INB(res, offset) \
573 bus_space_read_1(rman_get_bustag((res)), \
574 rman_get_bushandle((res)), (offset))
576 #define ATA_INW(res, offset) \
577 bus_space_read_2(rman_get_bustag((res)), \
578 rman_get_bushandle((res)), (offset))
579 #define ATA_INL(res, offset) \
580 bus_space_read_4(rman_get_bustag((res)), \
581 rman_get_bushandle((res)), (offset))
582 #define ATA_INSW(res, offset, addr, count) \
583 bus_space_read_multi_2(rman_get_bustag((res)), \
584 rman_get_bushandle((res)), \
585 (offset), (addr), (count))
586 #define ATA_INSW_STRM(res, offset, addr, count) \
587 bus_space_read_multi_stream_2(rman_get_bustag((res)), \
588 rman_get_bushandle((res)), \
589 (offset), (addr), (count))
590 #define ATA_INSL(res, offset, addr, count) \
591 bus_space_read_multi_4(rman_get_bustag((res)), \
592 rman_get_bushandle((res)), \
593 (offset), (addr), (count))
594 #define ATA_INSL_STRM(res, offset, addr, count) \
595 bus_space_read_multi_stream_4(rman_get_bustag((res)), \
596 rman_get_bushandle((res)), \
597 (offset), (addr), (count))
598 #define ATA_OUTB(res, offset, value) \
599 bus_space_write_1(rman_get_bustag((res)), \
600 rman_get_bushandle((res)), (offset), (value))
601 #define ATA_OUTW(res, offset, value) \
602 bus_space_write_2(rman_get_bustag((res)), \
603 rman_get_bushandle((res)), (offset), (value))
604 #define ATA_OUTL(res, offset, value) \
605 bus_space_write_4(rman_get_bustag((res)), \
606 rman_get_bushandle((res)), (offset), (value))
607 #define ATA_OUTSW(res, offset, addr, count) \
608 bus_space_write_multi_2(rman_get_bustag((res)), \
609 rman_get_bushandle((res)), \
610 (offset), (addr), (count))
611 #define ATA_OUTSW_STRM(res, offset, addr, count) \
612 bus_space_write_multi_stream_2(rman_get_bustag((res)), \
613 rman_get_bushandle((res)), \
614 (offset), (addr), (count))
615 #define ATA_OUTSL(res, offset, addr, count) \
616 bus_space_write_multi_4(rman_get_bustag((res)), \
617 rman_get_bushandle((res)), \
618 (offset), (addr), (count))
619 #define ATA_OUTSL_STRM(res, offset, addr, count) \
620 bus_space_write_multi_stream_4(rman_get_bustag((res)), \
621 rman_get_bushandle((res)), \
622 (offset), (addr), (count))
624 #define ATA_IDX_INB(ch, idx) \
625 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
627 #define ATA_IDX_INW(ch, idx) \
628 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
630 #define ATA_IDX_INL(ch, idx) \
631 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
633 #define ATA_IDX_INSW(ch, idx, addr, count) \
634 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
636 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
637 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
639 #define ATA_IDX_INSL(ch, idx, addr, count) \
640 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
642 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
643 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
645 #define ATA_IDX_OUTB(ch, idx, value) \
646 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
648 #define ATA_IDX_OUTW(ch, idx, value) \
649 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
651 #define ATA_IDX_OUTL(ch, idx, value) \
652 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
654 #define ATA_IDX_OUTSW(ch, idx, addr, count) \
655 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
657 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
658 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
660 #define ATA_IDX_OUTSL(ch, idx, addr, count) \
661 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
663 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
664 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)