2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.28 2006/12/22 23:26:15 swildner Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
44 #include <machine/stdarg.h>
45 #include <machine/clock.h>
47 #include <bus/pci/pcivar.h>
48 #include <bus/pci/pcireg.h>
51 /* device structures */
52 struct ata_pci_controller {
53 struct resource *bmio;
60 #define IOMASK 0xfffffffc
61 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
62 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
63 (pci_get_progif(dev) & 0x05) != 0x05)
66 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
71 if (device_get_children(device_get_parent(dev), &children, &nchildren))
74 for (i = 0; i < nchildren; i++) {
75 if (pci_get_devid(children[i]) == devid &&
76 pci_get_revid(children[i]) >= revid) {
77 kfree(children, M_TEMP);
81 kfree(children, M_TEMP);
86 ata_via_southbridge_fixup(device_t dev)
91 if (device_get_children(device_get_parent(dev), &children, &nchildren))
94 for (i = 0; i < nchildren; i++) {
95 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
96 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
97 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
98 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
99 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
101 if ((reg76 & 0xf0) != 0xd0) {
103 "Correcting VIA config for southbridge data corruption bug\n");
104 pci_write_config(children[i], 0x75, 0x80, 1);
105 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
110 kfree(children, M_TEMP);
114 ata_pci_match(device_t dev)
116 if (pci_get_class(dev) != PCIC_STORAGE)
119 switch (pci_get_devid(dev)) {
120 /* supported chipsets */
122 return "Intel PIIX ATA controller";
125 return "Intel PIIX3 ATA controller";
130 return "Intel PIIX4 ATA33 controller";
133 return "Intel ICH0 ATA33 controller";
137 return "Intel ICH ATA66 controller";
141 return "Intel ICH2 ATA100 controller";
145 return "Intel ICH3 ATA100 controller";
149 return "Intel ICH4 ATA100 controller";
152 return "Intel ICH5 SATA150 controller";
155 return "Intel ICH5 ATA100 controller";
159 return "Intel ICH6 SATA300 controller";
162 return "Intel ICH6/W SATA150 controller";
165 return "Intel ICH6R/RW SATA150 controller";
168 return "Intel ICH6M SATA150 controller";
171 return "Intel ICH6R/RW ATA100 controller";
174 return "Intel ICH7 ATA controller";
177 return "Intel ICH7M SATA controller";
180 if (pci_get_revid(dev) >= 0xc4)
181 return "AcerLabs Aladdin ATA100 controller";
182 else if (pci_get_revid(dev) >= 0xc2)
183 return "AcerLabs Aladdin ATA66 controller";
184 else if (pci_get_revid(dev) >= 0x20)
185 return "AcerLabs Aladdin ATA33 controller";
187 return "AcerLabs Aladdin ATA controller";
190 if (ata_find_dev(dev, 0x05861106, 0x02))
191 return "VIA 82C586 ATA33 controller";
192 if (ata_find_dev(dev, 0x05861106, 0))
193 return "VIA 82C586 ATA controller";
194 if (ata_find_dev(dev, 0x05961106, 0x12))
195 return "VIA 82C596 ATA66 controller";
196 if (ata_find_dev(dev, 0x05961106, 0))
197 return "VIA 82C596 ATA33 controller";
198 if (ata_find_dev(dev, 0x06861106, 0x40))
199 return "VIA 82C686 ATA100 controller";
200 if (ata_find_dev(dev, 0x06861106, 0x10))
201 return "VIA 82C686 ATA66 controller";
202 if (ata_find_dev(dev, 0x06861106, 0))
203 return "VIA 82C686 ATA33 controller";
204 if (ata_find_dev(dev, 0x82311106, 0))
205 return "VIA 8231 ATA100 controller";
206 if (ata_find_dev(dev, 0x30741106, 0) ||
207 ata_find_dev(dev, 0x31091106, 0))
208 return "VIA 8233 ATA100 controller";
209 if (ata_find_dev(dev, 0x31471106, 0))
210 return "VIA 8233 ATA133 controller";
211 if (ata_find_dev(dev, 0x31771106, 0))
212 return "VIA 8235 ATA133 controller";
213 if (ata_find_dev(dev, 0x31491106, 0))
214 return "VIA 8237 ATA133 controller";
215 return "VIA Apollo ATA controller";
218 return "VIA 8237 SATA 150 controller";
221 if (ata_find_dev(dev, 0x07461039, 0))
222 return "SiS 5591 ATA133 controller";
223 if (ata_find_dev(dev, 0x06301039, 0x30) ||
224 ata_find_dev(dev, 0x06331039, 0) ||
225 ata_find_dev(dev, 0x06351039, 0) ||
226 ata_find_dev(dev, 0x06401039, 0) ||
227 ata_find_dev(dev, 0x06451039, 0) ||
228 ata_find_dev(dev, 0x06461039, 0) ||
229 ata_find_dev(dev, 0x06481039, 0) ||
230 ata_find_dev(dev, 0x06501039, 0) ||
231 ata_find_dev(dev, 0x07301039, 0) ||
232 ata_find_dev(dev, 0x07331039, 0) ||
233 ata_find_dev(dev, 0x07351039, 0) ||
234 ata_find_dev(dev, 0x07401039, 0) ||
235 ata_find_dev(dev, 0x07451039, 0) ||
236 ata_find_dev(dev, 0x07501039, 0))
237 return "SiS 5591 ATA100 controller";
238 else if (ata_find_dev(dev, 0x05301039, 0) ||
239 ata_find_dev(dev, 0x05401039, 0) ||
240 ata_find_dev(dev, 0x06201039, 0) ||
241 ata_find_dev(dev, 0x06301039, 0))
242 return "SiS 5591 ATA66 controller";
244 return "SiS 5591 ATA33 controller";
247 return "SiI 3512 SATA controller";
250 return "SiI 3112 SATA controller";
253 return "SiI 3114 SATA controller";
256 return "SiI 3124 SATA controller";
259 return "SiI 0680 ATA133 controller";
262 return "CMD 649 ATA100 controller";
265 return "CMD 648 ATA66 controller";
268 return "CMD 646 ATA controller";
271 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
272 return "Cypress 82C693 ATA controller";
276 return "Cyrix 5530 ATA33 controller";
279 return "AMD 756 ATA66 controller";
282 return "AMD 766 ATA100 controller";
285 return "AMD 768 ATA100 controller";
288 return "AMD 8111 UltraATA/133 controller";
291 return "nVIDIA nForce1 ATA100 controller";
294 return "nVIDIA nForce2 ATA133 controller";
297 return "nVIDIA nForce3 ATA133 controller";
300 return "nVIDIA nForce3 PRO S1 controller";
303 return "nVIDIA nForce3 PRO controller";
306 return "ServerWorks ROSB4 ATA33 controller";
309 if (pci_get_revid(dev) >= 0x92)
310 return "ServerWorks CSB5 ATA100 controller";
312 return "ServerWorks CSB5 ATA66 controller";
315 return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
318 return "ServerWorks CSB6 ATA66 controller (channel 2)";
321 return "Promise ATA33 controller";
325 return "Promise ATA66 controller";
329 return "Promise ATA100 controller";
333 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
334 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
335 static long start = 0, end = 0;
337 /* we belive we are on a TX4, now do our (simple) magic */
338 if (pci_get_slot(dev) == 1) {
339 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
340 return "Promise TX4 ATA100 controller (channel 0+1)";
342 else if (pci_get_slot(dev) == 2 && start && end) {
343 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
345 return "Promise TX4 ATA100 controller (channel 2+3)";
350 return "Promise TX2 ATA100 controller";
356 return "Promise TX2 ATA133 controller";
359 switch (pci_get_revid(dev)) {
362 return "HighPoint HPT366 ATA66 controller";
364 return "HighPoint HPT368 ATA66 controller";
367 return "HighPoint HPT370 ATA100 controller";
369 return "HighPoint HPT372 ATA133 controller";
374 switch (pci_get_revid(dev)) {
377 return "HighPoint HPT372 ATA133 controller";
382 switch (pci_get_revid(dev)) {
384 return "HighPoint HPT374 ATA133 controller";
389 return "Cenatek Rocket Drive controller";
391 /* unsupported but known chipsets, generic DMA only */
394 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
397 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
399 /* unknown chipsets, try generic DMA if it seems possible */
401 if (pci_get_class(dev) == PCIC_STORAGE &&
402 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
403 return "Generic PCI ATA controller";
409 ata_pci_probe(device_t dev)
411 const char *desc = ata_pci_match(dev);
414 device_set_desc(dev, desc);
422 ata_pci_add_child(device_t dev, int unit)
426 /* check if this is located at one of the std addresses */
427 if (ATA_MASTERDEV(dev)) {
428 if (!(child = device_add_child(dev, "ata", unit)))
432 if (!(child = device_add_child(dev, "ata", 2)))
439 ata_pci_attach(device_t dev)
441 struct ata_pci_controller *controller = device_get_softc(dev);
442 u_int8_t class, subclass;
447 /* set up vendor-specific stuff */
448 type = pci_get_devid(dev);
449 class = pci_get_class(dev);
450 subclass = pci_get_subclass(dev);
451 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
453 if (!(cmd & PCIM_CMD_PORTEN)) {
454 device_printf(dev, "ATA channel disabled by BIOS\n");
458 /* is busmastering supported ? */
459 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
460 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
462 /* is there a valid port range to connect to ? */
464 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
465 0, ~0, 1, RF_ACTIVE);
466 if (!controller->bmio)
467 device_printf(dev, "Busmastering DMA not configured\n");
470 device_printf(dev, "Busmastering DMA not supported\n");
472 /* do extra chipset specific setups */
476 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
477 pci_write_config(dev, 0x53,
478 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
481 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
484 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
487 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
488 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
491 case 0x00041103: /* HighPoint HPT366/368/370/372 */
492 if (pci_get_revid(dev) < 2) { /* HPT 366 */
493 /* turn off interrupt prediction */
494 pci_write_config(dev, 0x51,
495 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
498 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
499 /* turn off interrupt prediction */
500 pci_write_config(dev, 0x51,
501 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
502 pci_write_config(dev, 0x55,
503 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
505 /* turn on interrupts */
506 pci_write_config(dev, 0x5a,
507 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
510 pci_write_config(dev, 0x5b, 0x22, 1);
515 case 0x00051103: /* HighPoint HPT372 */
516 case 0x00081103: /* HighPoint HPT374 */
517 /* turn off interrupt prediction */
518 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
519 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
521 /* turn on interrupts */
522 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
525 pci_write_config(dev, 0x5b,
526 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
529 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
530 /* prepare for ATA-66 on the 82C686a and 82C596b */
531 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
532 !ata_find_dev(dev, 0x06861106, 0x40)) ||
533 ata_find_dev(dev, 0x05961106, 0x12))
534 pci_write_config(dev, 0x50, 0x030b030b, 4);
536 /* the southbridge might need the data corruption fix */
537 if (ata_find_dev(dev, 0x06861106, 0x40) ||
538 ata_find_dev(dev, 0x82311106, 0x10))
539 ata_via_southbridge_fixup(dev);
541 /* set fifo configuration half'n'half */
542 pci_write_config(dev, 0x43,
543 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
545 /* set status register read retry */
546 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
548 /* set DMA read & end-of-sector fifo flush */
549 pci_write_config(dev, 0x46,
550 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
552 /* set sector size */
553 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
554 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
556 case 0x74111022: /* AMD 766 default setup */
557 flags = 1; /* bugged */
559 case 0x74091022: /* AMD 756 default setup */
560 case 0x74411022: /* AMD 768 default setup */
561 case 0x746d1022: /* AMD 8111 default setup */
563 pci_write_config(dev, 0x41,
564 pci_read_config(dev, 0x41, 1) & 0x0f, 1);
566 pci_write_config(dev, 0x41,
567 pci_read_config(dev, 0x41, 1) | 0xf0, 1);
570 case 0x01bc10de: /* NVIDIA nForce1 default setup */
571 case 0x006510de: /* NVIDIA nForce2 default setup */
574 case 0x00d510de: /* NVIDIA nForce3 default setup */
576 pci_write_config(dev, 0x51,
577 pci_read_config(dev, 0x51, 1) & 0x0f, 1);
579 pci_write_config(dev, 0x51,
580 pci_read_config(dev, 0x51, 1) | 0xf0, 1);
584 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
585 pci_write_config(dev, 0x64,
586 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
590 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
591 pci_write_config(dev, 0x5a,
592 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
593 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
596 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
597 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
598 pci_write_config(dev, 0x8a,
599 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
600 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
601 device_printf(dev, "SiI 0680 could not set clock\n");
606 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
607 pci_write_config(dev, 0x71, 0x01, 1);
610 case 0x10001042: /* RZ 100? known bad, no DMA */
612 case 0x06401095: /* CMD 640 known bad, no DMA */
613 controller->bmio = NULL;
614 device_printf(dev, "Busmastering DMA disabled\n");
617 if (controller->bmio) {
618 controller->bmaddr = rman_get_start(controller->bmio);
619 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
620 SYS_RES_IOPORT, rid, controller->bmio);
621 controller->bmio = NULL;
625 * the Cypress chip is a mess, it contains two ATA functions, but
626 * both channels are visible on the first one.
627 * simply ignore the second function for now, as the right
628 * solution (ignoring the second channel on the first function)
629 * doesn't work with the crappy ATA interrupt setup on the alpha.
631 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
634 ata_pci_add_child(dev, 0);
636 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
637 ata_pci_add_child(dev, 1);
639 return bus_generic_attach(dev);
643 ata_pci_intr(struct ata_channel *ch)
648 * since we might share the IRQ with another device, and in some
649 * cases with our twin channel, we only want to process interrupts
650 * that we know this channel generated.
652 switch (ch->chiptype) {
653 case 0x00041103: /* HighPoint HPT366/368/370/372 */
654 case 0x00051103: /* HighPoint HPT372 */
655 case 0x00081103: /* HighPoint HPT374 */
656 if (((dmastat = ata_dmastatus(ch)) &
657 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
659 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
663 case 0x06481095: /* CMD 648 */
664 case 0x06491095: /* CMD 649 */
665 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
666 (ch->unit ? 0x08 : 0x04)))
668 #if !defined(NO_ATANG)
669 pci_write_config(device_get_parent(ch->dev), 0x71,
670 pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
671 ~(ch->unit ? 0x04 : 0x08), 1);
675 case 0x06801095: /* SiI 680 */
676 if (!(pci_read_config(device_get_parent(ch->dev),
677 (ch->unit ? 0xb1 : 0xa1), 1) & 0x08))
681 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
682 case 0x0d38105a: /* Promise Fasttrak 66 */
683 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
684 case 0x0d30105a: /* Promise OEM ATA100 */
685 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
686 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
687 (ch->unit ? 0x00004000 : 0x00000400)))
691 case 0x4d68105a: /* Promise TX2 ATA100 */
692 case 0x6268105a: /* Promise TX2 ATA100 */
693 case 0x4d69105a: /* Promise TX2 ATA133 */
694 case 0x5275105a: /* Promise TX2 ATA133 */
695 case 0x6269105a: /* Promise TX2 ATA133 */
696 case 0x7275105a: /* Promise TX2 ATA133 */
697 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
698 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
702 case 0x24d18086: /* Intel ICH5 SATA150 */
703 case 0x24db8086: /* Intel ICH5 ATA100 */
704 case 0x26518086: /* Intel ICH6 SATA150 */
705 case 0x26528086: /* Intel ICH6R SATA150 */
706 case 0x26808086: /* Intel ICH6R SATA150 */
707 case 0x260e8086: /* Intel ICH6 SATA300 */
708 dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
709 if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
710 ATA_BMSTAT_INTERRUPT)
712 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat &
713 ~(ATA_BMSTAT_DMA_SIMPLEX | ATA_BMSTAT_ERROR));
719 if (ch->flags & ATA_DMA_ACTIVE) {
720 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
722 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
729 ata_pci_print_child(device_t dev, device_t child)
731 struct ata_channel *ch = device_get_softc(child);
734 retval += bus_print_child_header(dev, child);
735 retval += kprintf(": at 0x%lx", rman_get_start(ch->r_io));
737 if (ATA_MASTERDEV(dev))
738 retval += kprintf(" irq %d", 14 + ch->unit);
740 retval += bus_print_child_footer(dev, child);
745 static struct resource *
746 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
747 u_long start, u_long end, u_long count, u_int flags)
749 struct ata_pci_controller *controller = device_get_softc(dev);
750 struct resource *res = NULL;
751 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
754 if (type == SYS_RES_IOPORT) {
757 if (ATA_MASTERDEV(dev)) {
759 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
760 end = start + ATA_IOSIZE - 1;
762 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
763 SYS_RES_IOPORT, &myrid,
764 start, end, count, flags);
767 myrid = 0x10 + 8 * unit;
768 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
769 SYS_RES_IOPORT, &myrid,
770 start, end, count, flags);
774 case ATA_ALTADDR_RID:
775 if (ATA_MASTERDEV(dev)) {
777 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
778 end = start + ATA_ALTIOSIZE - 1;
779 count = ATA_ALTIOSIZE;
780 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
781 SYS_RES_IOPORT, &myrid,
782 start, end, count, flags);
785 myrid = 0x14 + 8 * unit;
786 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
787 SYS_RES_IOPORT, &myrid,
788 start, end, count, flags);
790 start = rman_get_start(res) + 2;
791 end = start + ATA_ALTIOSIZE - 1;
792 count = ATA_ALTIOSIZE;
793 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
794 SYS_RES_IOPORT, myrid, res);
795 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
796 SYS_RES_IOPORT, &myrid,
797 start, end, count, flags);
803 if (controller->bmaddr) {
806 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
807 end = start + ATA_BMIOSIZE - 1;
808 count = ATA_BMIOSIZE;
809 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
810 SYS_RES_IOPORT, &myrid,
811 start, end, count, flags);
817 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
818 if (ATA_MASTERDEV(dev)) {
819 int irq = (unit == 0 ? 14 : 15);
821 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
822 SYS_RES_IRQ, rid, irq, irq, 1, flags);
825 /* primary and secondary channels share interrupt, keep track */
826 if (!controller->irq)
827 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
829 rid, 0, ~0, 1, flags);
830 controller->irqcnt++;
831 return controller->irq;
838 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
841 struct ata_pci_controller *controller = device_get_softc(dev);
842 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
844 if (type == SYS_RES_IOPORT) {
847 if (ATA_MASTERDEV(dev))
848 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
849 SYS_RES_IOPORT, 0x0, r);
851 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
852 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
855 case ATA_ALTADDR_RID:
856 if (ATA_MASTERDEV(dev))
857 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
858 SYS_RES_IOPORT, 0x0, r);
860 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
861 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
865 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
866 SYS_RES_IOPORT, 0x20, r);
871 if (type == SYS_RES_IRQ) {
872 if (rid != ATA_IRQ_RID)
875 if (ATA_MASTERDEV(dev)) {
876 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
877 SYS_RES_IRQ, rid, r);
880 /* primary and secondary channels share interrupt, keep track */
881 if (--controller->irqcnt)
883 controller->irq = NULL;
884 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
885 SYS_RES_IRQ, rid, r);
892 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
893 int flags, driver_intr_t *intr, void *arg,
894 void **cookiep, lwkt_serialize_t serializer)
896 if (ATA_MASTERDEV(dev)) {
897 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
898 flags, intr, arg, cookiep, serializer);
901 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
902 flags, intr, arg, cookiep, serializer);
906 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
909 if (ATA_MASTERDEV(dev)) {
910 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
913 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
916 static device_method_t ata_pci_methods[] = {
917 /* device interface */
918 DEVMETHOD(device_probe, ata_pci_probe),
919 DEVMETHOD(device_attach, ata_pci_attach),
920 DEVMETHOD(device_shutdown, bus_generic_shutdown),
921 DEVMETHOD(device_suspend, bus_generic_suspend),
922 DEVMETHOD(device_resume, bus_generic_resume),
925 DEVMETHOD(bus_print_child, ata_pci_print_child),
926 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
927 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
928 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
929 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
930 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
931 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
935 static driver_t ata_pci_driver = {
938 sizeof(struct ata_pci_controller),
941 static devclass_t ata_pci_devclass;
943 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
946 ata_pcisub_probe(device_t dev)
948 struct ata_channel *ch = device_get_softc(dev);
952 /* find channel number on this controller */
953 device_get_children(device_get_parent(dev), &children, &count);
954 for (i = 0; i < count; i++) {
955 if (children[i] == dev)
958 kfree(children, M_TEMP);
959 ch->chiptype = pci_get_devid(device_get_parent(dev));
960 ch->intr_func = ata_pci_intr;
961 return ata_probe(dev);
964 static device_method_t ata_pcisub_methods[] = {
965 /* device interface */
966 DEVMETHOD(device_probe, ata_pcisub_probe),
967 DEVMETHOD(device_attach, ata_attach),
968 DEVMETHOD(device_detach, ata_detach),
969 DEVMETHOD(device_resume, ata_resume),
970 DEVMETHOD(device_suspend, ata_suspend),
974 static driver_t ata_pcisub_driver = {
977 sizeof(struct ata_channel),
980 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);