2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $
33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.21 2005/06/13 10:20:49 joerg Exp $
37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
38 * Programming manual is available from:
39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Department of Electical Engineering
43 * Columbia University, New York City
47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
48 * controller designed with flexibility and reducing CPU load in mind.
49 * The Starfire offers high and low priority buffer queues, a
50 * producer/consumer index mechanism and several different buffer
51 * queue and completion queue descriptor types. Any one of a number
52 * of different driver designs can be used, depending on system and
53 * OS requirements. This driver makes use of type0 transmit frame
54 * descriptors (since BSD fragments packets across an mbuf chain)
55 * and two RX buffer queues prioritized on size (one queue for small
56 * frames that will fit into a single mbuf, another with full size
57 * mbuf clusters for everything else). The producer/consumer indexes
58 * and completion queues are also used.
60 * One downside to the Starfire has to do with alignment: buffer
61 * queues must be aligned on 256-byte boundaries, and receive buffers
62 * must be aligned on longword boundaries. The receive buffer alignment
63 * causes problems on the Alpha platform, where the packet payload
64 * should be longword aligned. There is no simple way around this.
66 * For receive filtering, the Starfire offers 16 perfect filter slots
67 * and a 512-bit hash table.
69 * The Starfire has no internal transceiver, relying instead on an
70 * external MII-based transceiver. Accessing registers on external
71 * PHYs is done through a special register map rather than with the
72 * usual bitbang MDIO method.
74 * Acesssing the registers on the Starfire is a little tricky. The
75 * Starfire has a 512K internal register space. When programmed for
76 * PCI memory mapped mode, the entire register space can be accessed
77 * directly. However in I/O space mode, only 256 bytes are directly
78 * mapped into PCI I/O space. The other registers can be accessed
79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
80 * registers inside the 256-byte I/O window.
83 #include <sys/param.h>
84 #include <sys/systm.h>
85 #include <sys/sockio.h>
87 #include <sys/malloc.h>
88 #include <sys/kernel.h>
89 #include <sys/socket.h>
90 #include <sys/thread2.h>
93 #include <net/ifq_var.h>
94 #include <net/if_arp.h>
95 #include <net/ethernet.h>
96 #include <net/if_dl.h>
97 #include <net/if_media.h>
101 #include <vm/vm.h> /* for vtophys */
102 #include <vm/pmap.h> /* for vtophys */
103 #include <machine/clock.h> /* for DELAY */
104 #include <machine/bus_pio.h>
105 #include <machine/bus_memio.h>
106 #include <machine/bus.h>
107 #include <machine/resource.h>
109 #include <sys/rman.h>
111 #include "../mii_layer/mii.h"
112 #include "../mii_layer/miivar.h"
114 /* "controller miibus0" required. See GENERIC if you get errors here. */
115 #include "miibus_if.h"
117 #include <bus/pci/pcireg.h>
118 #include <bus/pci/pcivar.h>
120 #define SF_USEIOSPACE
122 #include "if_sfreg.h"
124 static struct sf_type sf_devs[] = {
125 { AD_VENDORID, AD_DEVICEID_STARFIRE,
126 "Adaptec AIC-6915 10/100BaseTX" },
130 static int sf_probe (device_t);
131 static int sf_attach (device_t);
132 static int sf_detach (device_t);
133 static void sf_intr (void *);
134 static void sf_stats_update (void *);
135 static void sf_rxeof (struct sf_softc *);
136 static void sf_txeof (struct sf_softc *);
137 static int sf_encap (struct sf_softc *,
138 struct sf_tx_bufdesc_type0 *,
140 static void sf_start (struct ifnet *);
141 static int sf_ioctl (struct ifnet *, u_long, caddr_t,
143 static void sf_init (void *);
144 static void sf_stop (struct sf_softc *);
145 static void sf_watchdog (struct ifnet *);
146 static void sf_shutdown (device_t);
147 static int sf_ifmedia_upd (struct ifnet *);
148 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *);
149 static void sf_reset (struct sf_softc *);
150 static int sf_init_rx_ring (struct sf_softc *);
151 static void sf_init_tx_ring (struct sf_softc *);
152 static int sf_newbuf (struct sf_softc *,
153 struct sf_rx_bufdesc_type0 *,
155 static void sf_setmulti (struct sf_softc *);
156 static int sf_setperf (struct sf_softc *, int, caddr_t);
157 static int sf_sethash (struct sf_softc *, caddr_t, int);
159 static int sf_setvlan (struct sf_softc *, int, u_int32_t);
162 static u_int8_t sf_read_eeprom (struct sf_softc *, int);
163 static u_int32_t sf_calchash (caddr_t);
165 static int sf_miibus_readreg (device_t, int, int);
166 static int sf_miibus_writereg (device_t, int, int, int);
167 static void sf_miibus_statchg (device_t);
169 static u_int32_t csr_read_4 (struct sf_softc *, int);
170 static void csr_write_4 (struct sf_softc *, int, u_int32_t);
171 static void sf_txthresh_adjust (struct sf_softc *);
174 #define SF_RES SYS_RES_IOPORT
175 #define SF_RID SF_PCI_LOIO
177 #define SF_RES SYS_RES_MEMORY
178 #define SF_RID SF_PCI_LOMEM
181 static device_method_t sf_methods[] = {
182 /* Device interface */
183 DEVMETHOD(device_probe, sf_probe),
184 DEVMETHOD(device_attach, sf_attach),
185 DEVMETHOD(device_detach, sf_detach),
186 DEVMETHOD(device_shutdown, sf_shutdown),
189 DEVMETHOD(bus_print_child, bus_generic_print_child),
190 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
193 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
194 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
195 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
200 static driver_t sf_driver = {
203 sizeof(struct sf_softc),
206 static devclass_t sf_devclass;
208 DECLARE_DUMMY_MODULE(if_sf);
209 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
210 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
212 #define SF_SETBIT(sc, reg, x) \
213 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
215 #define SF_CLRBIT(sc, reg, x) \
216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
218 static u_int32_t csr_read_4(sc, reg)
225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
234 static u_int8_t sf_read_eeprom(sc, reg)
240 val = (csr_read_4(sc, SF_EEADDR_BASE +
241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
246 static void csr_write_4(sc, reg, val)
252 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
253 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
255 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
260 static u_int32_t sf_calchash(addr)
263 u_int32_t crc, carry;
267 /* Compute CRC for the address value. */
268 crc = 0xFFFFFFFF; /* initial value */
270 for (i = 0; i < 6; i++) {
272 for (j = 0; j < 8; j++) {
273 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
277 crc = (crc ^ 0x04c11db6) | carry;
281 /* return the filter bit position */
282 return(crc >> 23 & 0x1FF);
286 * Copy the address 'mac' into the perfect RX filter entry at
287 * offset 'idx.' The perfect filter only has 16 entries so do
290 static int sf_setperf(sc, idx, mac)
297 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
303 p = (u_int16_t *)mac;
305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
306 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
308 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
310 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
316 * Set the bit in the 512-bit hash table that corresponds to the
317 * specified mac address 'mac.' If 'prio' is nonzero, update the
318 * priority hash table instead of the filter hash table.
320 static int sf_sethash(sc, mac, prio)
330 h = sf_calchash(mac);
333 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
334 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
345 * Set a VLAN tag in the receive filter.
347 static int sf_setvlan(sc, idx, vlan)
352 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
355 csr_write_4(sc, SF_RXFILT_HASH_BASE +
356 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
362 static int sf_miibus_readreg(dev, phy, reg)
370 sc = device_get_softc(dev);
372 for (i = 0; i < SF_TIMEOUT; i++) {
373 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
374 if (val & SF_MII_DATAVALID)
381 if ((val & 0x0000FFFF) == 0xFFFF)
384 return(val & 0x0000FFFF);
387 static int sf_miibus_writereg(dev, phy, reg, val)
395 sc = device_get_softc(dev);
397 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
399 for (i = 0; i < SF_TIMEOUT; i++) {
400 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
401 if (!(busy & SF_MII_BUSY))
408 static void sf_miibus_statchg(dev)
412 struct mii_data *mii;
414 sc = device_get_softc(dev);
415 mii = device_get_softc(sc->sf_miibus);
417 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
418 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
419 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
421 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
422 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
428 static void sf_setmulti(sc)
433 struct ifmultiaddr *ifma;
434 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
436 ifp = &sc->arpcom.ac_if;
438 /* First zot all the existing filters. */
439 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
440 sf_setperf(sc, i, (char *)&dummy);
441 for (i = SF_RXFILT_HASH_BASE;
442 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
443 csr_write_4(sc, i, 0);
444 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
446 /* Now program new ones. */
447 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
448 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
451 /* First find the tail of the list. */
452 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
453 ifma = ifma->ifma_link.le_next) {
454 if (ifma->ifma_link.le_next == NULL)
457 /* Now traverse the list backwards. */
458 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
459 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
460 if (ifma->ifma_addr->sa_family != AF_LINK)
463 * Program the first 15 multicast groups
464 * into the perfect filter. For all others,
465 * use the hash table.
467 if (i < SF_RXFILT_PERFECT_CNT) {
469 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
475 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
485 static int sf_ifmedia_upd(ifp)
489 struct mii_data *mii;
492 mii = device_get_softc(sc->sf_miibus);
494 if (mii->mii_instance) {
495 struct mii_softc *miisc;
496 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
497 miisc = LIST_NEXT(miisc, mii_list))
498 mii_phy_reset(miisc);
506 * Report current media status.
508 static void sf_ifmedia_sts(ifp, ifmr)
510 struct ifmediareq *ifmr;
513 struct mii_data *mii;
516 mii = device_get_softc(sc->sf_miibus);
519 ifmr->ifm_active = mii->mii_media_active;
520 ifmr->ifm_status = mii->mii_media_status;
525 static int sf_ioctl(ifp, command, data, cr)
531 struct sf_softc *sc = ifp->if_softc;
532 struct ifreq *ifr = (struct ifreq *) data;
533 struct mii_data *mii;
540 if (ifp->if_flags & IFF_UP) {
541 if (ifp->if_flags & IFF_RUNNING &&
542 ifp->if_flags & IFF_PROMISC &&
543 !(sc->sf_if_flags & IFF_PROMISC)) {
544 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
545 } else if (ifp->if_flags & IFF_RUNNING &&
546 !(ifp->if_flags & IFF_PROMISC) &&
547 sc->sf_if_flags & IFF_PROMISC) {
548 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
549 } else if (!(ifp->if_flags & IFF_RUNNING))
552 if (ifp->if_flags & IFF_RUNNING)
555 sc->sf_if_flags = ifp->if_flags;
565 mii = device_get_softc(sc->sf_miibus);
566 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
569 error = ether_ioctl(ifp, command, data);
578 static void sf_reset(sc)
583 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
584 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
586 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
588 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
590 for (i = 0; i < SF_TIMEOUT; i++) {
592 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
597 printf("sf%d: reset never completed!\n", sc->sf_unit);
599 /* Wait a little while for the chip to get its brains in order. */
605 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
606 * IDs against our list and return a device name if we find a match.
607 * We also check the subsystem ID so that we can identify exactly which
608 * NIC has been found, if possible.
610 static int sf_probe(dev)
617 while(t->sf_name != NULL) {
618 if ((pci_get_vendor(dev) == t->sf_vid) &&
619 (pci_get_device(dev) == t->sf_did)) {
620 switch((pci_read_config(dev,
621 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
622 case AD_SUBSYSID_62011_REV0:
623 case AD_SUBSYSID_62011_REV1:
625 "Adaptec ANA-62011 10/100BaseTX");
628 case AD_SUBSYSID_62022:
630 "Adaptec ANA-62022 10/100BaseTX");
633 case AD_SUBSYSID_62044_REV0:
634 case AD_SUBSYSID_62044_REV1:
636 "Adaptec ANA-62044 10/100BaseTX");
639 case AD_SUBSYSID_62020:
641 "Adaptec ANA-62020 10/100BaseFX");
644 case AD_SUBSYSID_69011:
646 "Adaptec ANA-69011 10/100BaseTX");
650 device_set_desc(dev, t->sf_name);
662 * Attach the interface. Allocate softc structures, do ifmedia
663 * setup and ethernet/BPF attach.
665 static int sf_attach(dev)
672 int unit, rid, error = 0;
674 sc = device_get_softc(dev);
675 unit = device_get_unit(dev);
676 bzero(sc, sizeof(struct sf_softc));
679 * Handle power management nonsense.
681 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
682 if (command == 0x01) {
684 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
685 if (command & SF_PSTATE_MASK) {
686 u_int32_t iobase, membase, irq;
688 /* Save important PCI config data. */
689 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
690 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
691 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
693 /* Reset the power state. */
694 printf("sf%d: chip is in D%d power mode "
695 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
696 command &= 0xFFFFFFFC;
697 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
699 /* Restore PCI config data. */
700 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
701 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
702 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
707 * Map control/status registers.
709 command = pci_read_config(dev, PCIR_COMMAND, 4);
710 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
711 pci_write_config(dev, PCIR_COMMAND, command, 4);
712 command = pci_read_config(dev, PCIR_COMMAND, 4);
715 if (!(command & PCIM_CMD_PORTEN)) {
716 printf("sf%d: failed to enable I/O ports!\n", unit);
721 if (!(command & PCIM_CMD_MEMEN)) {
722 printf("sf%d: failed to enable memory mapping!\n", unit);
729 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE);
731 if (sc->sf_res == NULL) {
732 printf ("sf%d: couldn't map ports\n", unit);
737 sc->sf_btag = rman_get_bustag(sc->sf_res);
738 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
740 /* Allocate interrupt */
742 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
743 RF_SHAREABLE | RF_ACTIVE);
745 if (sc->sf_irq == NULL) {
746 printf("sf%d: couldn't map interrupt\n", unit);
751 callout_init(&sc->sf_stat_timer);
753 /* Reset the adapter. */
757 * Get station address from the EEPROM.
759 for (i = 0; i < ETHER_ADDR_LEN; i++)
760 sc->arpcom.ac_enaddr[i] =
761 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
765 /* Allocate the descriptor queues. */
766 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
767 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
769 if (sc->sf_ldata == NULL) {
770 printf("sf%d: no memory for list buffers!\n", unit);
775 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
778 if (mii_phy_probe(dev, &sc->sf_miibus,
779 sf_ifmedia_upd, sf_ifmedia_sts)) {
780 printf("sf%d: MII without any phy!\n", sc->sf_unit);
785 ifp = &sc->arpcom.ac_if;
787 if_initname(ifp, "sf", unit);
788 ifp->if_mtu = ETHERMTU;
789 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
790 ifp->if_ioctl = sf_ioctl;
791 ifp->if_start = sf_start;
792 ifp->if_watchdog = sf_watchdog;
793 ifp->if_init = sf_init;
794 ifp->if_baudrate = 10000000;
795 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
796 ifq_set_ready(&ifp->if_snd);
799 * Call MI attach routine.
801 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
803 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
804 sf_intr, sc, &sc->sf_intrhand, NULL);
808 device_printf(dev, "couldn't set up irq\n");
819 static int sf_detach(dev)
822 struct sf_softc *sc = device_get_softc(dev);
823 struct ifnet *ifp = &sc->arpcom.ac_if;
827 if (device_is_attached(dev)) {
833 device_delete_child(dev, sc->sf_miibus);
834 bus_generic_detach(dev);
837 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
842 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
844 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
847 contigfree(sc->sf_ldata, sizeof(struct sf_list_data),
854 static int sf_init_rx_ring(sc)
857 struct sf_list_data *ld;
862 bzero((char *)ld->sf_rx_dlist_big,
863 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
864 bzero((char *)ld->sf_rx_clist,
865 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
867 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
868 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
875 static void sf_init_tx_ring(sc)
878 struct sf_list_data *ld;
883 bzero((char *)ld->sf_tx_dlist,
884 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
885 bzero((char *)ld->sf_tx_clist,
886 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
888 for (i = 0; i < SF_TX_DLIST_CNT; i++)
889 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
890 for (i = 0; i < SF_TX_CLIST_CNT; i++)
891 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
893 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
899 static int sf_newbuf(sc, c, m)
901 struct sf_rx_bufdesc_type0 *c;
904 struct mbuf *m_new = NULL;
907 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
911 MCLGET(m_new, MB_DONTWAIT);
912 if (!(m_new->m_flags & M_EXT)) {
916 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
919 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
920 m_new->m_data = m_new->m_ext.ext_buf;
923 m_adj(m_new, sizeof(u_int64_t));
926 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
933 * The starfire is programmed to use 'normal' mode for packet reception,
934 * which means we use the consumer/producer model for both the buffer
935 * descriptor queue and the completion descriptor queue. The only problem
936 * with this is that it involves a lot of register accesses: we have to
937 * read the RX completion consumer and producer indexes and the RX buffer
938 * producer index, plus the RX completion consumer and RX buffer producer
939 * indexes have to be updated. It would have been easier if Adaptec had
940 * put each index in a separate register, especially given that the damn
941 * NIC has a 512K register space.
943 * In spite of all the lovely features that Adaptec crammed into the 6915,
944 * it is marred by one truly stupid design flaw, which is that receive
945 * buffer addresses must be aligned on a longword boundary. This forces
946 * the packet payload to be unaligned, which is suboptimal on the x86 and
947 * completely unuseable on the Alpha. Our only recourse is to copy received
948 * packets into properly aligned buffers before handing them off.
951 static void sf_rxeof(sc)
956 struct sf_rx_bufdesc_type0 *desc;
957 struct sf_rx_cmpdesc_type3 *cur_rx;
958 u_int32_t rxcons, rxprod;
959 int cmpprodidx, cmpconsidx, bufprodidx;
961 ifp = &sc->arpcom.ac_if;
963 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
964 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
965 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
966 cmpconsidx = SF_IDX_LO(rxcons);
967 bufprodidx = SF_IDX_LO(rxprod);
969 while (cmpconsidx != cmpprodidx) {
972 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
973 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
975 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
976 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
978 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
980 sf_newbuf(sc, desc, m);
984 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
985 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
986 sf_newbuf(sc, desc, m);
991 m_adj(m0, ETHER_ALIGN);
996 (*ifp->if_input)(ifp, m);
999 csr_write_4(sc, SF_CQ_CONSIDX,
1000 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
1001 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1002 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1008 * Read the transmit status from the completion queue and release
1009 * mbufs. Note that the buffer descriptor index in the completion
1010 * descriptor is an offset from the start of the transmit buffer
1011 * descriptor list in bytes. This is important because the manual
1012 * gives the impression that it should match the producer/consumer
1013 * index, which is the offset in 8 byte blocks.
1015 static void sf_txeof(sc)
1016 struct sf_softc *sc;
1018 int txcons, cmpprodidx, cmpconsidx;
1019 struct sf_tx_cmpdesc_type1 *cur_cmp;
1020 struct sf_tx_bufdesc_type0 *cur_tx;
1023 ifp = &sc->arpcom.ac_if;
1025 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1026 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1027 cmpconsidx = SF_IDX_HI(txcons);
1029 while (cmpconsidx != cmpprodidx) {
1030 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1031 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1033 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1036 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
1037 sf_txthresh_adjust(sc);
1042 if (cur_tx->sf_mbuf != NULL) {
1043 m_freem(cur_tx->sf_mbuf);
1044 cur_tx->sf_mbuf = NULL;
1047 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1051 ifp->if_flags &= ~IFF_OACTIVE;
1053 csr_write_4(sc, SF_CQ_CONSIDX,
1054 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1055 ((cmpconsidx << 16) & 0xFFFF0000));
1060 static void sf_txthresh_adjust(sc)
1061 struct sf_softc *sc;
1066 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1067 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1068 if (txthresh < 0xFF) {
1070 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1073 printf("sf%d: tx underrun, increasing "
1074 "tx threshold to %d bytes\n",
1075 sc->sf_unit, txthresh * 4);
1077 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1083 static void sf_intr(arg)
1086 struct sf_softc *sc;
1091 ifp = &sc->arpcom.ac_if;
1093 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
1096 /* Disable interrupts. */
1097 csr_write_4(sc, SF_IMR, 0x00000000);
1100 status = csr_read_4(sc, SF_ISR);
1102 csr_write_4(sc, SF_ISR, status);
1104 if (!(status & SF_INTRS))
1107 if (status & SF_ISR_RXDQ1_DMADONE)
1110 if (status & SF_ISR_TX_TXDONE ||
1111 status & SF_ISR_TX_DMADONE ||
1112 status & SF_ISR_TX_QUEUEDONE)
1115 if (status & SF_ISR_TX_LOFIFO)
1116 sf_txthresh_adjust(sc);
1118 if (status & SF_ISR_ABNORMALINTR) {
1119 if (status & SF_ISR_STATSOFLOW) {
1120 callout_stop(&sc->sf_stat_timer);
1121 sf_stats_update(sc);
1127 /* Re-enable interrupts. */
1128 csr_write_4(sc, SF_IMR, SF_INTRS);
1130 if (!ifq_is_empty(&ifp->if_snd))
1136 static void sf_init(xsc)
1139 struct sf_softc *sc = xsc;
1140 struct ifnet *ifp = &sc->arpcom.ac_if;
1148 /* Init all the receive filter registers */
1149 for (i = SF_RXFILT_PERFECT_BASE;
1150 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1151 csr_write_4(sc, i, 0);
1153 /* Empty stats counter registers. */
1154 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1155 csr_write_4(sc, SF_STATS_BASE +
1156 (i + sizeof(u_int32_t)), 0);
1158 /* Init our MAC address */
1159 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1160 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1161 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1163 if (sf_init_rx_ring(sc) == ENOBUFS) {
1164 printf("sf%d: initialization failed: no "
1165 "memory for rx buffers\n", sc->sf_unit);
1170 sf_init_tx_ring(sc);
1172 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1174 /* If we want promiscuous mode, set the allframes bit. */
1175 if (ifp->if_flags & IFF_PROMISC) {
1176 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1178 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1181 if (ifp->if_flags & IFF_BROADCAST) {
1182 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1184 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1188 * Load the multicast filter.
1192 /* Init the completion queue indexes */
1193 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1194 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1196 /* Init the RX completion queue */
1197 csr_write_4(sc, SF_RXCQ_CTL_1,
1198 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1199 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1201 /* Init RX DMA control. */
1202 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1204 /* Init the RX buffer descriptor queue. */
1205 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1206 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1207 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1208 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1210 /* Init the TX completion queue */
1211 csr_write_4(sc, SF_TXCQ_CTL,
1212 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1214 /* Init the TX buffer descriptor queue. */
1215 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1216 vtophys(sc->sf_ldata->sf_tx_dlist));
1217 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1218 csr_write_4(sc, SF_TXDQ_CTL,
1219 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1220 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1222 /* Enable autopadding of short TX frames. */
1223 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1225 /* Enable interrupts. */
1226 csr_write_4(sc, SF_IMR, SF_INTRS);
1227 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1229 /* Enable the RX and TX engines. */
1230 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1231 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1233 /*mii_mediachg(mii);*/
1234 sf_ifmedia_upd(ifp);
1236 ifp->if_flags |= IFF_RUNNING;
1237 ifp->if_flags &= ~IFF_OACTIVE;
1239 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1244 static int sf_encap(sc, c, m_head)
1245 struct sf_softc *sc;
1246 struct sf_tx_bufdesc_type0 *c;
1247 struct mbuf *m_head;
1250 struct sf_frag *f = NULL;
1255 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1256 if (m->m_len != 0) {
1257 if (frag == SF_MAXFRAGS)
1259 f = &c->sf_frags[frag];
1261 f->sf_pktlen = m_head->m_pkthdr.len;
1262 f->sf_fraglen = m->m_len;
1263 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1269 struct mbuf *m_new = NULL;
1271 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1272 if (m_new == NULL) {
1273 printf("sf%d: no memory for tx list", sc->sf_unit);
1277 if (m_head->m_pkthdr.len > MHLEN) {
1278 MCLGET(m_new, MB_DONTWAIT);
1279 if (!(m_new->m_flags & M_EXT)) {
1281 printf("sf%d: no memory for tx list",
1286 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1287 mtod(m_new, caddr_t));
1288 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1291 f = &c->sf_frags[0];
1292 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1293 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1297 c->sf_mbuf = m_head;
1298 c->sf_id = SF_TX_BUFDESC_ID;
1299 c->sf_fragcnt = frag;
1307 static void sf_start(ifp)
1310 struct sf_softc *sc;
1311 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1312 struct mbuf *m_head = NULL;
1320 if (ifp->if_flags & IFF_OACTIVE)
1323 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1324 i = SF_IDX_HI(txprod) >> 4;
1326 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1327 printf("sf%d: TX ring full, resetting\n", sc->sf_unit);
1329 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1330 i = SF_IDX_HI(txprod) >> 4;
1333 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1334 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1335 ifp->if_flags |= IFF_OACTIVE;
1339 m_head = ifq_poll(&ifp->if_snd);
1343 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1344 if (sf_encap(sc, cur_tx, m_head)) {
1345 ifp->if_flags |= IFF_OACTIVE;
1349 ifq_dequeue(&ifp->if_snd);
1350 BPF_MTAP(ifp, cur_tx->sf_mbuf);
1352 SF_INC(i, SF_TX_DLIST_CNT);
1355 * Don't get the TX DMA queue get too full.
1357 if (sc->sf_tx_cnt > 64)
1365 csr_write_4(sc, SF_TXDQ_PRODIDX,
1366 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1367 ((i << 20) & 0xFFFF0000));
1374 static void sf_stop(sc)
1375 struct sf_softc *sc;
1380 ifp = &sc->arpcom.ac_if;
1382 callout_stop(&sc->sf_stat_timer);
1384 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1385 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1386 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1387 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1388 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1389 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1390 csr_write_4(sc, SF_TXCQ_CTL, 0);
1391 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1392 csr_write_4(sc, SF_TXDQ_CTL, 0);
1397 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1398 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1399 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1400 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1404 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1405 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1406 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1407 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1411 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1417 * Note: it is important that this function not be interrupted. We
1418 * use a two-stage register access scheme: if we are interrupted in
1419 * between setting the indirect address register and reading from the
1420 * indirect data register, the contents of the address register could
1421 * be changed out from under us.
1423 static void sf_stats_update(xsc)
1426 struct sf_softc *sc = xsc;
1427 struct ifnet *ifp = &sc->arpcom.ac_if;
1428 struct mii_data *mii = device_get_softc(sc->sf_miibus);
1429 struct sf_stats stats;
1435 ptr = (u_int32_t *)&stats;
1436 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1437 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1438 (i + sizeof(u_int32_t)));
1440 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1441 csr_write_4(sc, SF_STATS_BASE +
1442 (i + sizeof(u_int32_t)), 0);
1444 ifp->if_collisions += stats.sf_tx_single_colls +
1445 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1450 if (mii->mii_media_status & IFM_ACTIVE &&
1451 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1453 if (!ifq_is_empty(&ifp->if_snd))
1457 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1462 static void sf_watchdog(ifp)
1465 struct sf_softc *sc;
1470 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1476 if (!ifq_is_empty(&ifp->if_snd))
1482 static void sf_shutdown(dev)
1485 struct sf_softc *sc;
1487 sc = device_get_softc(dev);