sys/dev/drm/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel D�zer <michel@daenzer.net>
  31  *
  32  * $DragonFly: src/sys/dev/drm/radeon_irq.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  33  */
  34
  35 #include "drmP.h"
  36 #include "drm.h"
  37 #include "radeon_drm.h"
  38 #include "radeon_drv.h"
  39
  40 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,
  41                                               u32 mask)
  42 {
  43         u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
  44         if (irqs)
  45                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
  46         return irqs;
  47 }
  48
  49 /* Interrupts - Used for device synchronization and flushing in the
  50  * following circumstances:
  51  *
  52  * - Exclusive FB access with hw idle:
  53  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
  54  *
  55  * - Frame throttling, NV_fence:
  56  *    - Drop marker irq's into command stream ahead of time.
  57  *    - Wait on irq's with lock *not held*
  58  *    - Check each for termination condition
  59  *
  60  * - Internally in cp_getbuffer, etc:
  61  *    - as above, but wait with lock held???
  62  *
  63  * NOTE: These functions are misleadingly named -- the irq's aren't
  64  * tied to dma at all, this is just a hangover from dri prehistory.
  65  */
  66
  67 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
  68 {
  69         struct drm_device *dev = (struct drm_device *) arg;
  70         drm_radeon_private_t *dev_priv =
  71             (drm_radeon_private_t *) dev->dev_private;
  72         u32 stat;
  73
  74         /* Only consider the bits we're interested in - others could be used
  75          * outside the DRM
  76          */
  77         stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
  78                                                   RADEON_CRTC_VBLANK_STAT |
  79                                                   RADEON_CRTC2_VBLANK_STAT));
  80         if (!stat)
  81                 return IRQ_NONE;
  82
  83         stat &= dev_priv->irq_enable_reg;
  84
  85         /* SW interrupt */
  86         if (stat & RADEON_SW_INT_TEST) {
  87                 DRM_WAKEUP(&dev_priv->swi_queue);
  88         }
  89
  90         /* VBLANK interrupt */
  91         if (stat & (RADEON_CRTC_VBLANK_STAT|RADEON_CRTC2_VBLANK_STAT)) {
  92                 int vblank_crtc = dev_priv->vblank_crtc;
  93
  94                 if ((vblank_crtc &
  95                      (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
  96                     (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
  97                         if (stat & RADEON_CRTC_VBLANK_STAT)
  98                                 atomic_inc(&dev->vbl_received);
  99                         if (stat & RADEON_CRTC2_VBLANK_STAT)
 100                                 atomic_inc(&dev->vbl_received2);
 101                 } else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
 102                            (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
 103                            ((stat & RADEON_CRTC2_VBLANK_STAT) &&
 104                             (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
 105                         atomic_inc(&dev->vbl_received);
 106
 107                 DRM_WAKEUP(&dev->vbl_queue);
 108                 drm_vbl_send_signals(dev);
 109         }
 110
 111         return IRQ_HANDLED;
 112 }
 113
 114 static int radeon_emit_irq(struct drm_device * dev)
 115 {
 116         drm_radeon_private_t *dev_priv = dev->dev_private;
 117         unsigned int ret;
 118         RING_LOCALS;
 119
 120         atomic_inc(&dev_priv->swi_emitted);
 121         ret = atomic_read(&dev_priv->swi_emitted);
 122
 123         BEGIN_RING(4);
 124         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 125         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 126         ADVANCE_RING();
 127         COMMIT_RING();
 128
 129         return ret;
 130 }
 131
 132 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
 133 {
 134         drm_radeon_private_t *dev_priv =
 135             (drm_radeon_private_t *) dev->dev_private;
 136         int ret = 0;
 137
 138         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 139                 return 0;
 140
 141         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 142
 143         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 144                     RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 145
 146         return ret;
 147 }
 148
 149 static int radeon_driver_vblank_do_wait(struct drm_device * dev,
 150                                         unsigned int *sequence, int crtc)
 151 {
 152         drm_radeon_private_t *dev_priv =
 153             (drm_radeon_private_t *) dev->dev_private;
 154         unsigned int cur_vblank;
 155         int ret = 0;
 156         int ack = 0;
 157         atomic_t *counter;
 158         if (!dev_priv) {
 159                 DRM_ERROR("called with no initialization\n");
 160                 return -EINVAL;
 161         }
 162
 163         if (crtc == DRM_RADEON_VBLANK_CRTC1) {
 164                 counter = &dev->vbl_received;
 165                 ack |= RADEON_CRTC_VBLANK_STAT;
 166         } else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
 167                 counter = &dev->vbl_received2;
 168                 ack |= RADEON_CRTC2_VBLANK_STAT;
 169         } else
 170                 return -EINVAL;
 171
 172         radeon_acknowledge_irqs(dev_priv, ack);
 173
 174         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 175
 176         /* Assume that the user has missed the current sequence number
 177          * by about a day rather than she wants to wait for years
 178          * using vertical blanks...
 179          */
 180         DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
 181                     (((cur_vblank = atomic_read(counter))
 182                       - *sequence) <= (1 << 23)));
 183
 184         *sequence = cur_vblank;
 185
 186         return ret;
 187 }
 188
 189 int radeon_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
 190 {
 191         return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1);
 192 }
 193
 194 int radeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
 195 {
 196         return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2);
 197 }
 198
 199 /* Needs the lock as it touches the ring.
 200  */
 201 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
 202 {
 203         drm_radeon_private_t *dev_priv = dev->dev_private;
 204         drm_radeon_irq_emit_t *emit = data;
 205         int result;
 206
 207         LOCK_TEST_WITH_RETURN(dev, file_priv);
 208
 209         if (!dev_priv) {
 210                 DRM_ERROR("called with no initialization\n");
 211                 return -EINVAL;
 212         }
 213
 214         result = radeon_emit_irq(dev);
 215
 216         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 217                 DRM_ERROR("copy_to_user\n");
 218                 return -EFAULT;
 219         }
 220
 221         return 0;
 222 }
 223
 224 /* Doesn't need the hardware lock.
 225  */
 226 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
 227 {
 228         drm_radeon_private_t *dev_priv = dev->dev_private;
 229         drm_radeon_irq_wait_t *irqwait = data;
 230
 231         if (!dev_priv) {
 232                 DRM_ERROR("called with no initialization\n");
 233                 return -EINVAL;
 234         }
 235
 236         return radeon_wait_irq(dev, irqwait->irq_seq);
 237 }
 238
 239 static void radeon_enable_interrupt(struct drm_device *dev)
 240 {
 241         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 242
 243         dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
 244         if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1)
 245                 dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
 246
 247         if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2)
 248                 dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
 249
 250         RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
 251         dev_priv->irq_enabled = 1;
 252 }
 253
 254 /* drm_dma.h hooks
 255 */
 256 void radeon_driver_irq_preinstall(struct drm_device * dev)
 257 {
 258         drm_radeon_private_t *dev_priv =
 259             (drm_radeon_private_t *) dev->dev_private;
 260
 261         /* Disable *all* interrupts */
 262         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 263
 264         /* Clear bits if they're already high */
 265         radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
 266                                            RADEON_CRTC_VBLANK_STAT |
 267                                            RADEON_CRTC2_VBLANK_STAT));
 268 }
 269
 270 void radeon_driver_irq_postinstall(struct drm_device * dev)
 271 {
 272         drm_radeon_private_t *dev_priv =
 273             (drm_radeon_private_t *) dev->dev_private;
 274
 275         atomic_set(&dev_priv->swi_emitted, 0);
 276         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 277
 278         radeon_enable_interrupt(dev);
 279 }
 280
 281 void radeon_driver_irq_uninstall(struct drm_device * dev)
 282 {
 283         drm_radeon_private_t *dev_priv =
 284             (drm_radeon_private_t *) dev->dev_private;
 285         if (!dev_priv)
 286                 return;
 287
 288         dev_priv->irq_enabled = 0;
 289
 290         /* Disable *all* interrupts */
 291         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 292 }
 293
 294
 295 int radeon_vblank_crtc_get(struct drm_device *dev)
 296 {
 297         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 298         u32 flag;
 299         u32 value;
 300
 301         flag = RADEON_READ(RADEON_GEN_INT_CNTL);
 302         value = 0;
 303
 304         if (flag & RADEON_CRTC_VBLANK_MASK)
 305                 value |= DRM_RADEON_VBLANK_CRTC1;
 306
 307         if (flag & RADEON_CRTC2_VBLANK_MASK)
 308                 value |= DRM_RADEON_VBLANK_CRTC2;
 309         return value;
 310 }
 311
 312 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
 313 {
 314         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 315         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 316                 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
 317                 return -EINVAL;
 318         }
 319         dev_priv->vblank_crtc = (unsigned int)value;
 320         radeon_enable_interrupt(dev);
 321         return 0;
 322 }