3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_rereg.h,v 1.3 2004/08/02 13:35:02 joerg Exp $
40 * RealTek 8129/8139 register offsets
42 #define RE_IDR0 0x0000 /* ID register 0 (station addr) */
43 #define RE_IDR1 0x0001 /* Must use 32-bit accesses (?) */
44 #define RE_IDR2 0x0002
45 #define RE_IDR3 0x0003
46 #define RE_IDR4 0x0004
47 #define RE_IDR5 0x0005
48 /* 0006-0007 reserved */
49 #define RE_MAR0 0x0008 /* Multicast hash table */
50 #define RE_MAR1 0x0009
51 #define RE_MAR2 0x000A
52 #define RE_MAR3 0x000B
53 #define RE_MAR4 0x000C
54 #define RE_MAR5 0x000D
55 #define RE_MAR6 0x000E
56 #define RE_MAR7 0x000F
58 #define RE_RXADDR 0x0030 /* RX ring start address */
59 #define RE_RX_EARLY_BYTES 0x0034 /* RX early byte count */
60 #define RE_RX_EARLY_STAT 0x0036 /* RX early status */
61 #define RE_COMMAND 0x0037 /* command register */
62 #define RE_CURRXADDR 0x0038 /* current address of packet read */
63 #define RE_CURRXBUF 0x003A /* current RX buffer address */
64 #define RE_IMR 0x003C /* interrupt mask register */
65 #define RE_ISR 0x003E /* interrupt status register */
66 #define RE_TXCFG 0x0040 /* transmit config */
67 #define RE_RXCFG 0x0044 /* receive config */
68 #define RE_TIMERCNT 0x0048 /* timer count register */
69 #define RE_MISSEDPKT 0x004C /* missed packet counter */
70 #define RE_EECMD 0x0050 /* EEPROM command register */
71 #define RE_CFG0 0x0051 /* config register #0 */
72 #define RE_CFG1 0x0052 /* config register #1 */
73 /* 0053-0057 reserved */
74 #define RE_MEDIASTAT 0x0058 /* media status register (8139) */
75 /* 0059-005A reserved */
76 #define RE_MII 0x005A /* 8129 chip only */
77 #define RE_HALTCLK 0x005B
78 #define RE_MULTIINTR 0x005C /* multiple interrupt */
79 #define RE_PCIREV 0x005E /* PCI revision value */
81 #define RE_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
83 /* Direct PHY access registers only available on 8139 */
84 #define RE_BMCR 0x0062 /* PHY basic mode control */
85 #define RE_BMSR 0x0064 /* PHY basic mode status */
86 #define RE_ANAR 0x0066 /* PHY autoneg advert */
87 #define RE_LPAR 0x0068 /* PHY link partner ability */
88 #define RE_ANER 0x006A /* PHY autoneg expansion */
90 #define RE_DISCCNT 0x006C /* disconnect counter */
91 #define RE_FALSECAR 0x006E /* false carrier counter */
92 #define RE_NWAYTST 0x0070 /* NWAY test register */
93 #define RE_RX_ER 0x0072 /* RX_ER counter */
94 #define RE_CSCFG 0x0074 /* CS configuration register */
97 * When operating in special C+ mode, some of the registers in an
98 * 8139C+ chip have different definitions. These are also used for
101 #define RE_DUMPSTATS_LO 0x0010 /* counter dump command register */
102 #define RE_DUMPSTATS_HI 0x0014 /* counter dump command register */
103 #define RE_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
104 #define RE_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
105 #define RE_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
106 #define RE_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
107 #define RE_CFG2 0x0053
108 #define RE_TIMERINT 0x0054 /* interrupt on timer expire */
109 #define RE_TXSTART 0x00D9 /* 8 bits */
110 #define RE_CPLUS_CMD 0x00E0 /* 16 bits */
111 #define RE_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
112 #define RE_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
113 #define RE_EARLY_TX_THRESH 0x00EC /* 8 bits */
116 * Registers specific to the 8169 gigE chip
118 #define RE_TIMERINT_8169 0x0058 /* different offset than 8139 */
119 #define RE_PHYAR 0x0060
120 #define RE_TBICSR 0x0064
121 #define RE_TBI_ANAR 0x0068
122 #define RE_TBI_LPAR 0x006A
123 #define RE_GMEDIASTAT 0x006C /* 8 bits */
124 #define RE_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
125 #define RE_GTXSTART 0x0038 /* 16 bits */
128 * TX config register bits
130 #define RE_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
131 #define RE_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
132 #define RE_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
133 #define RE_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
134 #define RE_TXCFG_IFG2 0x00080000 /* 8169 only */
135 #define RE_TXCFG_IFG 0x03000000 /* interframe gap */
136 #define RE_TXCFG_HWREV 0x7CC00000
138 #define RE_LOOPTEST_OFF 0x00000000
139 #define RE_LOOPTEST_ON 0x00020000
140 #define RE_LOOPTEST_ON_CPLUS 0x00060000
142 #define RE_HWREV_8169 0x00000000
143 #define RE_HWREV_8169S 0x04000000
144 #define RE_HWREV_8110S 0x00800000
145 #define RE_HWREV_8139CPLUS 0x74800000
147 #define RE_TXDMA_16BYTES 0x00000000
148 #define RE_TXDMA_32BYTES 0x00000100
149 #define RE_TXDMA_64BYTES 0x00000200
150 #define RE_TXDMA_128BYTES 0x00000300
151 #define RE_TXDMA_256BYTES 0x00000400
152 #define RE_TXDMA_512BYTES 0x00000500
153 #define RE_TXDMA_1024BYTES 0x00000600
154 #define RE_TXDMA_2048BYTES 0x00000700
157 * Transmit descriptor status register bits.
159 #define RE_TXSTAT_LENMASK 0x00001FFF
160 #define RE_TXSTAT_OWN 0x00002000
161 #define RE_TXSTAT_TX_UNDERRUN 0x00004000
162 #define RE_TXSTAT_TX_OK 0x00008000
163 #define RE_TXSTAT_EARLY_THRESH 0x003F0000
164 #define RE_TXSTAT_COLLCNT 0x0F000000
165 #define RE_TXSTAT_CARR_HBEAT 0x10000000
166 #define RE_TXSTAT_OUTOFWIN 0x20000000
167 #define RE_TXSTAT_TXABRT 0x40000000
168 #define RE_TXSTAT_CARRLOSS 0x80000000
171 * Interrupt status register bits.
173 #define RE_ISR_RX_OK 0x0001
174 #define RE_ISR_RX_ERR 0x0002
175 #define RE_ISR_TX_OK 0x0004
176 #define RE_ISR_TX_ERR 0x0008
177 #define RE_ISR_RX_OVERRUN 0x0010
178 #define RE_ISR_PKT_UNDERRUN 0x0020
179 #define RE_ISR_LINKCHG 0x0020 /* 8169 only */
180 #define RE_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
181 #define RE_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
182 #define RE_ISR_SWI 0x0100 /* C+ only */
183 #define RE_ISR_CABLE_LEN_CHGD 0x2000
184 #define RE_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
185 #define RE_ISR_TIMEOUT_EXPIRED 0x4000
186 #define RE_ISR_SYSTEM_ERR 0x8000
188 #define RE_INTRS_CPLUS \
189 (RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR| \
190 RE_ISR_RX_OVERRUN|RE_ISR_PKT_UNDERRUN|RE_ISR_FIFO_OFLOW| \
191 RE_ISR_PCS_TIMEOUT|RE_ISR_SYSTEM_ERR|RE_ISR_TIMEOUT_EXPIRED)
194 * Media status register. (8139 only)
196 #define RE_MEDIASTAT_RXPAUSE 0x01
197 #define RE_MEDIASTAT_TXPAUSE 0x02
198 #define RE_MEDIASTAT_LINK 0x04
199 #define RE_MEDIASTAT_SPEED10 0x08
200 #define RE_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
201 #define RE_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
204 * Receive config register.
206 #define RE_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
207 #define RE_RXCFG_RX_INDIV 0x00000002 /* match filter */
208 #define RE_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
209 #define RE_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
210 #define RE_RXCFG_RX_RUNT 0x00000010
211 #define RE_RXCFG_RX_ERRPKT 0x00000020
212 #define RE_RXCFG_WRAP 0x00000080
213 #define RE_RXCFG_MAXDMA 0x00000700
214 #define RE_RXCFG_BUFSZ 0x00001800
215 #define RE_RXCFG_FIFOTHRESH 0x0000E000
216 #define RE_RXCFG_EARLYTHRESH 0x07000000
218 #define RE_RXDMA_16BYTES 0x00000000
219 #define RE_RXDMA_32BYTES 0x00000100
220 #define RE_RXDMA_64BYTES 0x00000200
221 #define RE_RXDMA_128BYTES 0x00000300
222 #define RE_RXDMA_256BYTES 0x00000400
223 #define RE_RXDMA_512BYTES 0x00000500
224 #define RE_RXDMA_1024BYTES 0x00000600
225 #define RE_RXDMA_UNLIMITED 0x00000700
227 #define RE_RXBUF_8 0x00000000
228 #define RE_RXBUF_16 0x00000800
229 #define RE_RXBUF_32 0x00001000
230 #define RE_RXBUF_64 0x00001800
232 #define RE_RXFIFO_16BYTES 0x00000000
233 #define RE_RXFIFO_32BYTES 0x00002000
234 #define RE_RXFIFO_64BYTES 0x00004000
235 #define RE_RXFIFO_128BYTES 0x00006000
236 #define RE_RXFIFO_256BYTES 0x00008000
237 #define RE_RXFIFO_512BYTES 0x0000A000
238 #define RE_RXFIFO_1024BYTES 0x0000C000
239 #define RE_RXFIFO_NOTHRESH 0x0000E000
242 * Bits in RX status header (included with RX'ed packet
245 #define RE_RXSTAT_RXOK 0x00000001
246 #define RE_RXSTAT_ALIGNERR 0x00000002
247 #define RE_RXSTAT_CRCERR 0x00000004
248 #define RE_RXSTAT_GIANT 0x00000008
249 #define RE_RXSTAT_RUNT 0x00000010
250 #define RE_RXSTAT_BADSYM 0x00000020
251 #define RE_RXSTAT_BROAD 0x00002000
252 #define RE_RXSTAT_INDIV 0x00004000
253 #define RE_RXSTAT_MULTI 0x00008000
254 #define RE_RXSTAT_LENMASK 0xFFFF0000
256 #define RE_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
260 #define RE_CMD_EMPTY_RXBUF 0x0001
261 #define RE_CMD_TX_ENB 0x0004
262 #define RE_CMD_RX_ENB 0x0008
263 #define RE_CMD_RESET 0x0010
266 * EEPROM control register
268 #define RE_EE_DATAOUT 0x01 /* Data out */
269 #define RE_EE_DATAIN 0x02 /* Data in */
270 #define RE_EE_CLK 0x04 /* clock */
271 #define RE_EE_SEL 0x08 /* chip select */
272 #define RE_EE_MODE (0x40|0x80)
274 #define RE_EEMODE_OFF 0x00
275 #define RE_EEMODE_AUTOLOAD 0x40
276 #define RE_EEMODE_PROGRAM 0x80
277 #define RE_EEMODE_WRITECFG (0x80|0x40)
279 /* 9346 EEPROM commands */
280 #define RE_EECMD_WRITE 0x140
281 #define RE_EECMD_READ_6BIT 0x180
282 #define RE_EECMD_READ_8BIT 0x600
283 #define RE_EECMD_ERASE 0x1c0
285 #define RE_EE_ID 0x00
286 #define RE_EE_PCI_VID 0x01
287 #define RE_EE_PCI_DID 0x02
288 /* Location of station address inside EEPROM */
289 #define RE_EE_EADDR 0x07
294 #define RE_CFG0_ROM0 0x01
295 #define RE_CFG0_ROM1 0x02
296 #define RE_CFG0_ROM2 0x04
297 #define RE_CFG0_PL0 0x08
298 #define RE_CFG0_PL1 0x10
299 #define RE_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
300 #define RE_CFG0_PCS 0x40
301 #define RE_CFG0_SCR 0x80
306 #define RE_CFG1_PWRDWN 0x01
307 #define RE_CFG1_SLEEP 0x02
308 #define RE_CFG1_IOMAP 0x04
309 #define RE_CFG1_MEMMAP 0x08
310 #define RE_CFG1_RSVD 0x10
311 #define RE_CFG1_DRVLOAD 0x20
312 #define RE_CFG1_LED0 0x40
313 #define RE_CFG1_FULLDUPLEX 0x40 /* 8129 only */
314 #define RE_CFG1_LED1 0x80
317 * 8139C+ register definitions
320 /* RE_DUMPSTATS_LO register */
322 #define RE_DUMPSTATS_START 0x00000008
324 /* Transmit start register */
326 #define RE_TXSTART_SWI 0x01 /* generate TX interrupt */
327 #define RE_TXSTART_START 0x40 /* start normal queue transmit */
328 #define RE_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
331 * Config 2 register, 8139C+/8169/8169S/8110S only
333 #define RE_CFG2_BUSFREQ 0x07
334 #define RE_CFG2_BUSWIDTH 0x08
335 #define RE_CFG2_AUXPWRSTS 0x10
337 #define RE_BUSFREQ_33MHZ 0x00
338 #define RE_BUSFREQ_66MHZ 0x01
340 #define RE_BUSWIDTH_32BITS 0x00
341 #define RE_BUSWIDTH_64BITS 0x08
343 /* C+ mode command register */
345 #define RE_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
346 #define RE_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
347 #define RE_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
348 #define RE_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
349 #define RE_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
350 #define RE_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
352 /* C+ early transmit threshold */
354 #define RE_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
357 * Gigabit PHY access register (8169 only)
360 #define RE_PHYAR_PHYDATA 0x0000FFFF
361 #define RE_PHYAR_PHYREG 0x001F0000
362 #define RE_PHYAR_BUSY 0x80000000
365 * Gigabit media status (8169 only)
367 #define RE_GMEDIASTAT_FDX 0x01 /* full duplex */
368 #define RE_GMEDIASTAT_LINK 0x02 /* link up */
369 #define RE_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
370 #define RE_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
371 #define RE_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
372 #define RE_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
373 #define RE_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
374 #define RE_GMEDIASTAT_TBI 0x80 /* TBI enabled */
377 * The RealTek doesn't use a fragment-based descriptor mechanism.
378 * Instead, there are only four register sets, each or which represents
379 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
380 * packet buffer (32-bit aligned!) and we place the buffer addresses in
381 * the registers so the chip knows where they are.
383 * We can sort of kludge together the same kind of buffer management
384 * used in previous drivers, but we have to do buffer copies almost all
385 * the time, so it doesn't really buy us much.
387 * For reception, there's just one large buffer where the chip stores
388 * all received packets.
391 #define RE_RX_BUF_SZ RE_RXBUF_64
392 #define RE_RXBUFLEN (1 << ((RE_RX_BUF_SZ >> 11) + 13))
393 #define RE_TX_LIST_CNT 4
394 #define RE_MIN_FRAMELEN 60
395 #define RE_TXTHRESH(x) ((x) << 11)
396 #define RE_TX_THRESH_INIT 96
397 #define RE_RX_FIFOTHRESH RE_RXFIFO_NOTHRESH
398 #define RE_RX_MAXDMA RE_RXDMA_UNLIMITED
399 #define RE_TX_MAXDMA RE_TXDMA_2048BYTES
401 #define RE_RXCFG_CONFIG (RE_RX_FIFOTHRESH|RE_RX_MAXDMA|RE_RX_BUF_SZ)
402 #define RE_TXCFG_CONFIG (RE_TXCFG_IFG|RE_TX_MAXDMA)
404 #define RE_ETHER_ALIGN 2
406 struct re_chain_data {
409 caddr_t re_rx_buf_ptr;
410 bus_dmamap_t re_rx_dmamap;
412 struct mbuf *re_tx_chain[RE_TX_LIST_CNT];
413 bus_dmamap_t re_tx_dmamap[RE_TX_LIST_CNT];
418 #define RE_INC(x) (x = (x + 1) % RE_TX_LIST_CNT)
419 #define RE_CUR_TXADDR(x) ((x->re_cdata.cur_tx * 4) + RE_TXADDR0)
420 #define RE_CUR_TXSTAT(x) ((x->re_cdata.cur_tx * 4) + RE_TXSTAT0)
421 #define RE_CUR_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.cur_tx])
422 #define RE_CUR_DMAMAP(x) (x->re_cdata.re_tx_dmamap[x->re_cdata.cur_tx])
423 #define RE_LAST_TXADDR(x) ((x->re_cdata.last_tx * 4) + RE_TXADDR0)
424 #define RE_LAST_TXSTAT(x) ((x->re_cdata.last_tx * 4) + RE_TXSTAT0)
425 #define RE_LAST_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.last_tx])
426 #define RE_LAST_DMAMAP(x) (x->re_cdata.re_tx_dmamap[x->re_cdata.last_tx])
441 struct re_mii_frame {
446 uint8_t mii_turnaround;
453 #define RE_MII_STARTDELIM 0x01
454 #define RE_MII_READOP 0x02
455 #define RE_MII_WRITEOP 0x01
456 #define RE_MII_TURNAROUND 0x02
458 #define RE_8139CPLUS 3
461 #define RE_ISCPLUS(x) ((x)->re_type == RE_8139CPLUS || \
462 (x)->re_type == RE_8169)
465 * The 8139C+ and 8160 gigE chips support descriptor-based TX
466 * and RX. In fact, they even support TCP large send. Descriptors
467 * must be allocated in contiguous blocks that are aligned on a
468 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
472 * RX/TX descriptor definition. When large send mode is enabled, the
473 * lower 11 bits of the TX re_cmd word are used to hold the MSS, and
474 * the checksum offload bits are disabled. The structure layout is
475 * the same for RX and TX descriptors
481 uint32_t re_bufaddr_lo;
482 uint32_t re_bufaddr_hi;
485 #define RE_TDESC_CMD_FRAGLEN 0x0000FFFF
486 #define RE_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
487 #define RE_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
488 #define RE_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
489 #define RE_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
490 #define RE_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
491 #define RE_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
492 #define RE_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
493 #define RE_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
494 #define RE_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
496 #define RE_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
497 #define RE_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
500 * Error bits are valid only on the last descriptor of a frame
501 * (i.e. RE_TDESC_CMD_EOF == 1)
504 #define RE_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
505 #define RE_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
506 #define RE_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
507 #define RE_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
508 #define RE_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
509 #define RE_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
510 #define RE_TDESC_STAT_OWN 0x80000000
513 * RX descriptor cmd/vlan definitions
516 #define RE_RDESC_CMD_EOR 0x40000000
517 #define RE_RDESC_CMD_OWN 0x80000000
518 #define RE_RDESC_CMD_BUFLEN 0x00001FFF
520 #define RE_RDESC_STAT_OWN 0x80000000
521 #define RE_RDESC_STAT_EOR 0x40000000
522 #define RE_RDESC_STAT_SOF 0x20000000
523 #define RE_RDESC_STAT_EOF 0x10000000
524 #define RE_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
525 #define RE_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
526 #define RE_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
527 #define RE_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
528 #define RE_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
529 #define RE_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
530 #define RE_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
531 #define RE_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
532 #define RE_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
533 #define RE_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
534 #define RE_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
535 #define RE_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
536 #define RE_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
537 #define RE_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
538 #define RE_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
539 #define RE_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
541 #define RE_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
542 (re_vlandata valid)*/
543 #define RE_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
545 #define RE_PROTOID_NONIP 0x00000000
546 #define RE_PROTOID_TCPIP 0x00010000
547 #define RE_PROTOID_UDPIP 0x00020000
548 #define RE_PROTOID_IP 0x00030000
549 #define RE_TCPPKT(x) (((x) & RE_RDESC_STAT_PROTOID) == \
551 #define RE_UDPPKT(x) (((x) & RE_RDESC_STAT_PROTOID) == \
555 * Statistics counter structure (8139C+ and 8169 only)
558 uint32_t re_tx_pkts_lo;
559 uint32_t re_tx_pkts_hi;
560 uint32_t re_tx_errs_lo;
561 uint32_t re_tx_errs_hi;
563 uint16_t re_missed_pkts;
564 uint16_t re_rx_framealign_errs;
565 uint32_t re_tx_onecoll;
566 uint32_t re_tx_multicolls;
567 uint32_t re_rx_ucasts_hi;
568 uint32_t re_rx_ucasts_lo;
569 uint32_t re_rx_bcasts_lo;
570 uint32_t re_rx_bcasts_hi;
571 uint32_t re_rx_mcasts;
572 uint16_t re_tx_aborts;
573 uint16_t re_rx_underruns;
576 #define RE_RX_DESC_CNT 64
577 #define RE_TX_DESC_CNT 64
578 #define RE_RX_LIST_SZ (RE_RX_DESC_CNT * sizeof(struct re_desc))
579 #define RE_TX_LIST_SZ (RE_TX_DESC_CNT * sizeof(struct re_desc))
580 #define RE_RING_ALIGN 256
581 #define RE_IFQ_MAXLEN 512
582 #define RE_DESC_INC(x) (x = (x + 1) % RE_TX_DESC_CNT)
583 #define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN)
584 #define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask)
585 #define RE_PKTSZ(x) ((x)/* >> 3*/)
587 #define RE_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF)
588 #define RE_ADDR_HI(y) ((u_int64_t) (y) >> 32)
590 #define RE_JUMBO_FRAMELEN 9018
591 #define RE_JUMBO_MTU (RE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
595 struct re_dmaload_arg {
600 struct re_desc *re_ring;
603 struct re_list_data {
604 struct mbuf *re_tx_mbuf[RE_TX_DESC_CNT];
605 struct mbuf *re_rx_mbuf[RE_TX_DESC_CNT];
610 bus_dmamap_t re_tx_dmamap[RE_TX_DESC_CNT];
611 bus_dmamap_t re_rx_dmamap[RE_RX_DESC_CNT];
612 bus_dma_tag_t re_mtag; /* mbuf mapping tag */
613 bus_dma_tag_t re_stag; /* stats mapping tag */
614 bus_dmamap_t re_smap; /* stats map */
615 struct re_stats *re_stats;
616 bus_addr_t re_stats_addr;
617 bus_dma_tag_t re_rx_list_tag;
618 bus_dmamap_t re_rx_list_map;
619 struct re_desc *re_rx_list;
620 bus_addr_t re_rx_list_addr;
621 bus_dma_tag_t re_tx_list_tag;
622 bus_dmamap_t re_tx_list_map;
623 struct re_desc *re_tx_list;
624 bus_addr_t re_tx_list_addr;
628 struct arpcom arpcom; /* interface info */
629 bus_space_handle_t re_bhandle; /* bus space handle */
630 bus_space_tag_t re_btag; /* bus space tag */
631 struct resource *re_res;
632 struct resource *re_irq;
635 bus_dma_tag_t re_parent_tag;
636 bus_dma_tag_t re_tag;
639 u_int8_t re_stats_no_timeout;
641 struct re_chain_data re_cdata;
642 struct re_list_data re_ldata;
643 struct callout re_timer;
644 struct mbuf *re_head;
645 struct mbuf *re_tail;
647 uint32_t re_rxlenmask;
649 int suspended; /* 0 = normal 1 = suspended */
650 #ifdef DEVICE_POLLING
655 uint32_t saved_maps[5]; /* pci data */
656 uint32_t saved_biosaddr;
657 uint8_t saved_intline;
658 uint8_t saved_cachelnsz;
659 uint8_t saved_lattimer;
664 * register space access macros
666 #define CSR_WRITE_STREAM_4(sc, reg, val) \
667 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)
668 #define CSR_WRITE_4(sc, reg, val) \
669 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)
670 #define CSR_WRITE_2(sc, reg, val) \
671 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)
672 #define CSR_WRITE_1(sc, reg, val) \
673 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)
675 #define CSR_READ_4(sc, reg) \
676 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)
677 #define CSR_READ_2(sc, reg) \
678 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)
679 #define CSR_READ_1(sc, reg) \
680 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)
682 #define RE_TIMEOUT 1000
685 * General constants that are fun to know.
687 * RealTek PCI vendor ID
689 #define RT_VENDORID 0x10EC
692 * RealTek chip device IDs.
694 #define RT_DEVICEID_8129 0x8129
695 #define RT_DEVICEID_8138 0x8138
696 #define RT_DEVICEID_8139 0x8139
697 #define RT_DEVICEID_8169 0x8169
698 #define RT_DEVICEID_8100 0x8100
700 #define RT_REVID_8139CPLUS 0x20
703 * Accton PCI vendor ID
705 #define ACCTON_VENDORID 0x1113
708 * Accton MPX 5030/5038 device ID.
710 #define ACCTON_DEVICEID_5030 0x1211
713 * Nortel PCI vendor ID
715 #define NORTEL_VENDORID 0x126C
718 * Delta Electronics Vendor ID.
720 #define DELTA_VENDORID 0x1500
725 #define DELTA_DEVICEID_8139 0x1360
730 #define ADDTRON_VENDORID 0x4033
733 * Addtron device IDs.
735 #define ADDTRON_DEVICEID_8139 0x1360
740 #define DLINK_VENDORID 0x1186
743 * D-Link DFE-530TX+ device ID
745 #define DLINK_DEVICEID_530TXPLUS 0x1300
748 * D-Link DFE-690TXD device ID
750 #define DLINK_DEVICEID_690TXD 0x1340
753 * Corega K.K vendor ID
755 #define COREGA_VENDORID 0x1259
758 * Corega FEther CB-TXD device ID
760 #define COREGA_DEVICEID_FETHERCBTXD 0xa117
763 * Corega FEtherII CB-TXD device ID
765 #define COREGA_DEVICEID_FETHERIICBTXD 0xa11e
768 * Peppercon vendor ID
770 #define PEPPERCON_VENDORID 0x1743
773 * Peppercon ROL-F device ID
775 #define PEPPERCON_DEVICEID_ROLF 0x8139
778 * Planex Communications, Inc. vendor ID
780 #define PLANEX_VENDORID 0x14ea
783 * Planex FNW-3800-TX device ID
785 #define PLANEX_DEVICEID_FNW3800TX 0xab07
790 #define LEVEL1_VENDORID 0x018A
793 * LevelOne FPC-0106TX devide ID
795 #define LEVEL1_DEVICEID_FPC0106TX 0x0106
800 #define CP_VENDORID 0x021B
805 #define EDIMAX_VENDORID 0x13D1
808 * Edimax EP-4103DL cardbus device ID
810 #define EDIMAX_DEVICEID_EP4103DL 0xAB06
813 * PCI low memory base and low I/O base register, and
814 * other PCI registers.
817 #define RE_PCI_LOMEM 0x14
818 #define RE_PCI_LOIO 0x10