1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.22 2008/06/25 14:39:35 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
59 #include "opt_ethernet.h"
61 #include <sys/param.h>
62 #include <sys/endian.h>
63 #include <sys/kernel.h>
65 #include <sys/interrupt.h>
68 #include <sys/serialize.h>
69 #include <sys/socket.h>
70 #include <sys/sockio.h>
71 #include <sys/sysctl.h>
73 #include <net/ethernet.h>
76 #include <net/if_arp.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/ifq_var.h>
80 #include <net/if_types.h>
81 #include <net/if_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include "miibus_if.h"
94 #include <dev/netif/nfe/if_nfereg.h>
95 #include <dev/netif/nfe/if_nfevar.h>
98 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
100 static int nfe_probe(device_t);
101 static int nfe_attach(device_t);
102 static int nfe_detach(device_t);
103 static void nfe_shutdown(device_t);
104 static int nfe_resume(device_t);
105 static int nfe_suspend(device_t);
107 static int nfe_miibus_readreg(device_t, int, int);
108 static void nfe_miibus_writereg(device_t, int, int, int);
109 static void nfe_miibus_statchg(device_t);
111 #ifdef DEVICE_POLLING
112 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static void nfe_rxeof(struct nfe_softc *);
117 static void nfe_txeof(struct nfe_softc *);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_tick(void *);
143 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
144 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
146 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
148 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
150 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
152 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
155 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
160 static int nfe_debug = 0;
161 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
162 static int nfe_imtime = -1;
164 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
165 TUNABLE_INT("hw.nfe.imtime", &nfe_imtime);
166 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
168 #define DPRINTF(sc, fmt, ...) do { \
169 if ((sc)->sc_debug) { \
170 if_printf(&(sc)->arpcom.ac_if, \
175 #define DPRINTFN(sc, lv, fmt, ...) do { \
176 if ((sc)->sc_debug >= (lv)) { \
177 if_printf(&(sc)->arpcom.ac_if, \
182 #else /* !NFE_DEBUG */
184 #define DPRINTF(sc, fmt, ...)
185 #define DPRINTFN(sc, lv, fmt, ...)
187 #endif /* NFE_DEBUG */
191 bus_dma_segment_t *segs;
194 static const struct nfe_dev {
199 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
200 "NVIDIA nForce Fast Ethernet" },
202 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
203 "NVIDIA nForce2 Fast Ethernet" },
205 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
206 "NVIDIA nForce3 Gigabit Ethernet" },
208 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
209 chipset, and possibly also the 400R; it might be both nForce2- and
210 nForce3-based boards can use the same MCPs (= southbridges) */
211 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
212 "NVIDIA nForce3 Gigabit Ethernet" },
214 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
215 "NVIDIA nForce3 Gigabit Ethernet" },
217 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
218 "NVIDIA nForce3 Gigabit Ethernet" },
220 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
221 "NVIDIA nForce3 Gigabit Ethernet" },
223 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
224 "NVIDIA CK804 Gigabit Ethernet" },
226 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
227 "NVIDIA CK804 Gigabit Ethernet" },
229 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
230 "NVIDIA MCP04 Gigabit Ethernet" },
232 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
233 "NVIDIA MCP04 Gigabit Ethernet" },
235 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
236 "NVIDIA MCP51 Gigabit Ethernet" },
238 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
239 "NVIDIA MCP51 Gigabit Ethernet" },
241 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
242 "NVIDIA MCP55 Gigabit Ethernet" },
244 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
245 "NVIDIA MCP55 Gigabit Ethernet" },
247 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
248 "NVIDIA MCP61 Gigabit Ethernet" },
250 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
251 "NVIDIA MCP61 Gigabit Ethernet" },
253 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
254 "NVIDIA MCP61 Gigabit Ethernet" },
256 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
257 "NVIDIA MCP61 Gigabit Ethernet" },
259 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
260 "NVIDIA MCP65 Gigabit Ethernet" },
262 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
263 "NVIDIA MCP65 Gigabit Ethernet" },
265 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
266 "NVIDIA MCP65 Gigabit Ethernet" },
268 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
269 "NVIDIA MCP65 Gigabit Ethernet" },
271 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
272 "NVIDIA MCP67 Gigabit Ethernet" },
274 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
275 "NVIDIA MCP67 Gigabit Ethernet" },
277 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
278 "NVIDIA MCP67 Gigabit Ethernet" },
280 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
281 "NVIDIA MCP67 Gigabit Ethernet" }
284 static device_method_t nfe_methods[] = {
285 /* Device interface */
286 DEVMETHOD(device_probe, nfe_probe),
287 DEVMETHOD(device_attach, nfe_attach),
288 DEVMETHOD(device_detach, nfe_detach),
289 DEVMETHOD(device_suspend, nfe_suspend),
290 DEVMETHOD(device_resume, nfe_resume),
291 DEVMETHOD(device_shutdown, nfe_shutdown),
294 DEVMETHOD(bus_print_child, bus_generic_print_child),
295 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
298 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
299 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
300 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
305 static driver_t nfe_driver = {
308 sizeof(struct nfe_softc)
311 static devclass_t nfe_devclass;
313 DECLARE_DUMMY_MODULE(if_nfe);
314 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
315 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
316 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
319 nfe_probe(device_t dev)
321 const struct nfe_dev *n;
324 vid = pci_get_vendor(dev);
325 did = pci_get_device(dev);
326 for (n = nfe_devices; n->desc != NULL; ++n) {
327 if (vid == n->vid && did == n->did) {
328 struct nfe_softc *sc = device_get_softc(dev);
331 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
332 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
333 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
334 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
335 sc->sc_flags = NFE_JUMBO_SUP |
338 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
339 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
340 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
341 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
342 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
343 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
344 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
345 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
346 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
347 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
348 sc->sc_flags = NFE_40BIT_ADDR;
350 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
351 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
352 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
353 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
354 sc->sc_flags = NFE_JUMBO_SUP |
358 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
359 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
360 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
361 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
362 sc->sc_flags = NFE_JUMBO_SUP |
365 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
366 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
367 sc->sc_flags = NFE_JUMBO_SUP |
374 device_set_desc(dev, n->desc);
375 device_set_async_attach(dev, TRUE);
383 nfe_attach(device_t dev)
385 struct nfe_softc *sc = device_get_softc(dev);
386 struct ifnet *ifp = &sc->arpcom.ac_if;
387 uint8_t eaddr[ETHER_ADDR_LEN];
390 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
391 lwkt_serialize_init(&sc->sc_jbuf_serializer);
394 * Initialize sysctl variables
396 sc->sc_imtime = nfe_imtime;
397 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
398 sc->sc_rx_ring_count = nfe_rx_ring_count;
399 sc->sc_debug = nfe_debug;
401 sc->sc_mem_rid = PCIR_BAR(0);
404 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
407 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
408 irq = pci_read_config(dev, PCIR_INTLINE, 4);
410 device_printf(dev, "chip is in D%d power mode "
411 "-- setting to D0\n", pci_get_powerstate(dev));
413 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
415 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
416 pci_write_config(dev, PCIR_INTLINE, irq, 4);
418 #endif /* !BURN_BRIDGE */
420 /* Enable bus mastering */
421 pci_enable_busmaster(dev);
423 /* Allocate IO memory */
424 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
425 &sc->sc_mem_rid, RF_ACTIVE);
426 if (sc->sc_mem_res == NULL) {
427 device_printf(dev, "cound not allocate io memory\n");
430 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
431 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
435 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
437 RF_SHAREABLE | RF_ACTIVE);
438 if (sc->sc_irq_res == NULL) {
439 device_printf(dev, "could not allocate irq\n");
444 nfe_get_macaddr(sc, eaddr);
447 * Allocate Tx and Rx rings.
449 error = nfe_alloc_tx_ring(sc, &sc->txq);
451 device_printf(dev, "could not allocate Tx ring\n");
455 error = nfe_alloc_rx_ring(sc, &sc->rxq);
457 device_printf(dev, "could not allocate Rx ring\n");
464 sysctl_ctx_init(&sc->sc_sysctl_ctx);
465 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
466 SYSCTL_STATIC_CHILDREN(_hw),
468 device_get_nameunit(dev),
470 if (sc->sc_sysctl_tree == NULL) {
471 device_printf(dev, "can't add sysctl node\n");
475 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
476 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
477 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
478 sc, 0, nfe_sysctl_imtime, "I",
479 "Interrupt moderation time (usec). "
480 "-1 to disable interrupt moderation.");
481 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
482 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
484 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
485 "debug", CTLFLAG_RW, &sc->sc_debug,
486 0, "control debugging printfs");
488 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
491 device_printf(dev, "MII without any phy\n");
496 ifp->if_mtu = ETHERMTU;
497 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
498 ifp->if_ioctl = nfe_ioctl;
499 ifp->if_start = nfe_start;
500 #ifdef DEVICE_POLLING
501 ifp->if_poll = nfe_poll;
503 ifp->if_watchdog = nfe_watchdog;
504 ifp->if_init = nfe_init;
505 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
506 ifq_set_ready(&ifp->if_snd);
508 ifp->if_capabilities = IFCAP_VLAN_MTU;
510 if (sc->sc_flags & NFE_HW_VLAN)
511 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
514 if (sc->sc_flags & NFE_HW_CSUM) {
515 ifp->if_capabilities |= IFCAP_HWCSUM;
516 ifp->if_hwassist = NFE_CSUM_FEATURES;
519 sc->sc_flags &= ~NFE_HW_CSUM;
521 ifp->if_capenable = ifp->if_capabilities;
523 callout_init(&sc->sc_tick_ch);
525 ether_ifattach(ifp, eaddr, NULL);
527 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
528 &sc->sc_ih, ifp->if_serializer);
530 device_printf(dev, "could not setup intr\n");
535 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
536 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
545 nfe_detach(device_t dev)
547 struct nfe_softc *sc = device_get_softc(dev);
549 if (device_is_attached(dev)) {
550 struct ifnet *ifp = &sc->arpcom.ac_if;
552 lwkt_serialize_enter(ifp->if_serializer);
554 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
555 lwkt_serialize_exit(ifp->if_serializer);
560 if (sc->sc_miibus != NULL)
561 device_delete_child(dev, sc->sc_miibus);
562 bus_generic_detach(dev);
564 if (sc->sc_sysctl_tree != NULL)
565 sysctl_ctx_free(&sc->sc_sysctl_ctx);
567 if (sc->sc_irq_res != NULL) {
568 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
572 if (sc->sc_mem_res != NULL) {
573 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
577 nfe_free_tx_ring(sc, &sc->txq);
578 nfe_free_rx_ring(sc, &sc->rxq);
584 nfe_shutdown(device_t dev)
586 struct nfe_softc *sc = device_get_softc(dev);
587 struct ifnet *ifp = &sc->arpcom.ac_if;
589 lwkt_serialize_enter(ifp->if_serializer);
591 lwkt_serialize_exit(ifp->if_serializer);
595 nfe_suspend(device_t dev)
597 struct nfe_softc *sc = device_get_softc(dev);
598 struct ifnet *ifp = &sc->arpcom.ac_if;
600 lwkt_serialize_enter(ifp->if_serializer);
602 lwkt_serialize_exit(ifp->if_serializer);
608 nfe_resume(device_t dev)
610 struct nfe_softc *sc = device_get_softc(dev);
611 struct ifnet *ifp = &sc->arpcom.ac_if;
613 lwkt_serialize_enter(ifp->if_serializer);
614 if (ifp->if_flags & IFF_UP)
616 lwkt_serialize_exit(ifp->if_serializer);
622 nfe_miibus_statchg(device_t dev)
624 struct nfe_softc *sc = device_get_softc(dev);
625 struct mii_data *mii = device_get_softc(sc->sc_miibus);
626 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
628 phy = NFE_READ(sc, NFE_PHY_IFACE);
629 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
631 seed = NFE_READ(sc, NFE_RNDSEED);
632 seed &= ~NFE_SEED_MASK;
634 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
635 phy |= NFE_PHY_HDX; /* half-duplex */
636 misc |= NFE_MISC1_HDX;
639 switch (IFM_SUBTYPE(mii->mii_media_active)) {
640 case IFM_1000_T: /* full-duplex only */
641 link |= NFE_MEDIA_1000T;
642 seed |= NFE_SEED_1000T;
643 phy |= NFE_PHY_1000T;
646 link |= NFE_MEDIA_100TX;
647 seed |= NFE_SEED_100TX;
648 phy |= NFE_PHY_100TX;
651 link |= NFE_MEDIA_10T;
652 seed |= NFE_SEED_10T;
656 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
658 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
659 NFE_WRITE(sc, NFE_MISC1, misc);
660 NFE_WRITE(sc, NFE_LINKSPEED, link);
664 nfe_miibus_readreg(device_t dev, int phy, int reg)
666 struct nfe_softc *sc = device_get_softc(dev);
670 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
672 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
673 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
677 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
679 for (ntries = 0; ntries < 1000; ntries++) {
681 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
684 if (ntries == 1000) {
685 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
689 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
690 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
694 val = NFE_READ(sc, NFE_PHY_DATA);
695 if (val != 0xffffffff && val != 0)
696 sc->mii_phyaddr = phy;
698 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
704 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
706 struct nfe_softc *sc = device_get_softc(dev);
710 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
712 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
713 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
717 NFE_WRITE(sc, NFE_PHY_DATA, val);
718 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
719 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
721 for (ntries = 0; ntries < 1000; ntries++) {
723 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
729 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
733 #ifdef DEVICE_POLLING
736 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
738 struct nfe_softc *sc = ifp->if_softc;
740 ASSERT_SERIALIZED(ifp->if_serializer);
744 /* Disable interrupts */
745 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
747 case POLL_DEREGISTER:
748 /* enable interrupts */
749 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
751 case POLL_AND_CHECK_STATUS:
754 if (ifp->if_flags & IFF_RUNNING) {
767 struct nfe_softc *sc = arg;
768 struct ifnet *ifp = &sc->arpcom.ac_if;
771 r = NFE_READ(sc, NFE_IRQ_STATUS);
773 return; /* not for us */
774 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
776 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
778 if (r & NFE_IRQ_LINK) {
779 NFE_READ(sc, NFE_PHY_STATUS);
780 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
781 DPRINTF(sc, "link state changed %s\n", "");
784 if (ifp->if_flags & IFF_RUNNING) {
794 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
796 struct nfe_softc *sc = ifp->if_softc;
797 struct ifreq *ifr = (struct ifreq *)data;
798 struct mii_data *mii;
803 if (((sc->sc_flags & NFE_JUMBO_SUP) &&
804 ifr->ifr_mtu > NFE_JUMBO_MTU) ||
805 ((sc->sc_flags & NFE_JUMBO_SUP) == 0 &&
806 ifr->ifr_mtu > ETHERMTU)) {
808 } else if (ifp->if_mtu != ifr->ifr_mtu) {
809 ifp->if_mtu = ifr->ifr_mtu;
814 if (ifp->if_flags & IFF_UP) {
816 * If only the PROMISC or ALLMULTI flag changes, then
817 * don't do a full re-init of the chip, just update
820 if ((ifp->if_flags & IFF_RUNNING) &&
821 ((ifp->if_flags ^ sc->sc_if_flags) &
822 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
825 if (!(ifp->if_flags & IFF_RUNNING))
829 if (ifp->if_flags & IFF_RUNNING)
832 sc->sc_if_flags = ifp->if_flags;
836 if (ifp->if_flags & IFF_RUNNING)
841 mii = device_get_softc(sc->sc_miibus);
842 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
845 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
846 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
847 ifp->if_capenable ^= mask;
848 if (IFCAP_TXCSUM & ifp->if_capenable)
849 ifp->if_hwassist = NFE_CSUM_FEATURES;
851 ifp->if_hwassist = 0;
853 if (ifp->if_flags & IFF_RUNNING)
858 error = ether_ioctl(ifp, cmd, data);
865 nfe_rxeof(struct nfe_softc *sc)
867 struct ifnet *ifp = &sc->arpcom.ac_if;
868 struct nfe_rx_ring *ring = &sc->rxq;
870 #ifdef ETHER_INPUT_CHAIN
871 struct mbuf_chain chain[MAXCPU];
875 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
877 #ifdef ETHER_INPUT_CHAIN
878 ether_input_chain_init(chain);
882 struct nfe_rx_data *data = &ring->data[ring->cur];
887 if (sc->sc_flags & NFE_40BIT_ADDR) {
888 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
890 flags = le16toh(desc64->flags);
891 len = le16toh(desc64->length) & 0x3fff;
893 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
895 flags = le16toh(desc32->flags);
896 len = le16toh(desc32->length) & 0x3fff;
899 if (flags & NFE_RX_READY)
904 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
905 if (!(flags & NFE_RX_VALID_V1))
908 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
909 flags &= ~NFE_RX_ERROR;
910 len--; /* fix buffer length */
913 if (!(flags & NFE_RX_VALID_V2))
916 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
917 flags &= ~NFE_RX_ERROR;
918 len--; /* fix buffer length */
922 if (flags & NFE_RX_ERROR) {
929 if (sc->sc_flags & NFE_USE_JUMBO)
930 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
932 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
939 m->m_pkthdr.len = m->m_len = len;
940 m->m_pkthdr.rcvif = ifp;
942 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
943 (flags & NFE_RX_CSUMOK)) {
944 if (flags & NFE_RX_IP_CSUMOK_V2) {
945 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
950 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
951 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
953 CSUM_FRAG_NOT_CHECKED;
954 m->m_pkthdr.csum_data = 0xffff;
959 #ifdef ETHER_INPUT_CHAIN
961 ether_input_chain2(ifp, m, chain);
963 ether_input_chain(ifp, m, chain);
966 ifp->if_input(ifp, m);
969 nfe_set_ready_rxdesc(sc, ring, ring->cur);
970 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
974 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
975 #ifdef ETHER_INPUT_CHAIN
976 ether_input_dispatch(chain);
982 nfe_txeof(struct nfe_softc *sc)
984 struct ifnet *ifp = &sc->arpcom.ac_if;
985 struct nfe_tx_ring *ring = &sc->txq;
986 struct nfe_tx_data *data = NULL;
988 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
989 while (ring->next != ring->cur) {
992 if (sc->sc_flags & NFE_40BIT_ADDR)
993 flags = le16toh(ring->desc64[ring->next].flags);
995 flags = le16toh(ring->desc32[ring->next].flags);
997 if (flags & NFE_TX_VALID)
1000 data = &ring->data[ring->next];
1002 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1003 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1006 if ((flags & NFE_TX_ERROR_V1) != 0) {
1007 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1014 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1017 if ((flags & NFE_TX_ERROR_V2) != 0) {
1018 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1026 if (data->m == NULL) { /* should not get there */
1028 "last fragment bit w/o associated mbuf!\n");
1032 /* last fragment of the mbuf chain transmitted */
1033 bus_dmamap_sync(ring->data_tag, data->map,
1034 BUS_DMASYNC_POSTWRITE);
1035 bus_dmamap_unload(ring->data_tag, data->map);
1042 KKASSERT(ring->queued >= 0);
1043 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1046 if (data != NULL) { /* at least one slot freed */
1047 ifp->if_flags &= ~IFF_OACTIVE;
1053 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1055 struct nfe_dma_ctx ctx;
1056 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1057 struct nfe_tx_data *data, *data_map;
1059 struct nfe_desc64 *desc64 = NULL;
1060 struct nfe_desc32 *desc32 = NULL;
1065 data = &ring->data[ring->cur];
1067 data_map = data; /* Remember who owns the DMA map */
1069 ctx.nsegs = NFE_MAX_SCATTER;
1071 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1072 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1073 if (error && error != EFBIG) {
1074 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1078 if (error) { /* error == EFBIG */
1081 m_new = m_defrag(m0, MB_DONTWAIT);
1082 if (m_new == NULL) {
1083 if_printf(&sc->arpcom.ac_if,
1084 "could not defrag TX mbuf\n");
1091 ctx.nsegs = NFE_MAX_SCATTER;
1093 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1094 nfe_buf_dma_addr, &ctx,
1097 if_printf(&sc->arpcom.ac_if,
1098 "could not map defraged TX mbuf\n");
1105 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1106 bus_dmamap_unload(ring->data_tag, map);
1111 /* setup h/w VLAN tagging */
1112 if (m0->m_flags & M_VLANTAG)
1113 vtag = m0->m_pkthdr.ether_vlantag;
1115 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1116 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1117 flags |= NFE_TX_IP_CSUM;
1118 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1119 flags |= NFE_TX_TCP_CSUM;
1123 * XXX urm. somebody is unaware of how hardware works. You
1124 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1125 * the ring until the entire chain is actually *VALID*. Otherwise
1126 * the hardware may encounter a partially initialized chain that
1127 * is marked as being ready to go when it in fact is not ready to
1131 for (i = 0; i < ctx.nsegs; i++) {
1132 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1133 data = &ring->data[j];
1135 if (sc->sc_flags & NFE_40BIT_ADDR) {
1136 desc64 = &ring->desc64[j];
1137 #if defined(__LP64__)
1138 desc64->physaddr[0] =
1139 htole32(segs[i].ds_addr >> 32);
1141 desc64->physaddr[1] =
1142 htole32(segs[i].ds_addr & 0xffffffff);
1143 desc64->length = htole16(segs[i].ds_len - 1);
1144 desc64->vtag = htole32(vtag);
1145 desc64->flags = htole16(flags);
1147 desc32 = &ring->desc32[j];
1148 desc32->physaddr = htole32(segs[i].ds_addr);
1149 desc32->length = htole16(segs[i].ds_len - 1);
1150 desc32->flags = htole16(flags);
1153 /* csum flags and vtag belong to the first fragment only */
1154 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1158 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1161 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1162 if (sc->sc_flags & NFE_40BIT_ADDR) {
1163 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1165 if (sc->sc_flags & NFE_JUMBO_SUP)
1166 flags = NFE_TX_LASTFRAG_V2;
1168 flags = NFE_TX_LASTFRAG_V1;
1169 desc32->flags |= htole16(flags);
1173 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1174 * whole mess until the first descriptor in the map is flagged.
1176 for (i = ctx.nsegs - 1; i >= 0; --i) {
1177 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1178 if (sc->sc_flags & NFE_40BIT_ADDR) {
1179 desc64 = &ring->desc64[j];
1180 desc64->flags |= htole16(NFE_TX_VALID);
1182 desc32 = &ring->desc32[j];
1183 desc32->flags |= htole16(NFE_TX_VALID);
1186 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1188 /* Exchange DMA map */
1189 data_map->map = data->map;
1193 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1201 nfe_start(struct ifnet *ifp)
1203 struct nfe_softc *sc = ifp->if_softc;
1204 struct nfe_tx_ring *ring = &sc->txq;
1208 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1212 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1216 ETHER_BPF_MTAP(ifp, m0);
1218 if (nfe_encap(sc, ring, m0) != 0) {
1219 ifp->if_flags |= IFF_OACTIVE;
1226 * `m0' may be freed in nfe_encap(), so
1227 * it should not be touched any more.
1230 if (count == 0) /* nothing sent */
1233 /* Sync TX descriptor ring */
1234 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1237 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1240 * Set a timeout in case the chip goes out to lunch.
1246 nfe_watchdog(struct ifnet *ifp)
1248 struct nfe_softc *sc = ifp->if_softc;
1250 if (ifp->if_flags & IFF_RUNNING) {
1251 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1256 if_printf(ifp, "watchdog timeout\n");
1258 nfe_init(ifp->if_softc);
1266 struct nfe_softc *sc = xsc;
1267 struct ifnet *ifp = &sc->arpcom.ac_if;
1275 * Switching between jumbo frames and normal frames should
1276 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1278 if (ifp->if_mtu > ETHERMTU) {
1279 sc->sc_flags |= NFE_USE_JUMBO;
1280 sc->rxq.bufsz = NFE_JBYTES;
1282 if_printf(ifp, "use jumbo frames\n");
1284 sc->sc_flags &= ~NFE_USE_JUMBO;
1285 sc->rxq.bufsz = MCLBYTES;
1287 if_printf(ifp, "use non-jumbo frames\n");
1290 error = nfe_init_tx_ring(sc, &sc->txq);
1296 error = nfe_init_rx_ring(sc, &sc->rxq);
1302 NFE_WRITE(sc, NFE_TX_UNK, 0);
1303 NFE_WRITE(sc, NFE_STATUS, 0);
1305 sc->rxtxctl = NFE_RXTX_BIT2;
1306 if (sc->sc_flags & NFE_40BIT_ADDR)
1307 sc->rxtxctl |= NFE_RXTX_V3MAGIC;
1308 else if (sc->sc_flags & NFE_JUMBO_SUP)
1309 sc->rxtxctl |= NFE_RXTX_V2MAGIC;
1311 if (ifp->if_capenable & IFCAP_RXCSUM)
1312 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1315 * Although the adapter is capable of stripping VLAN tags from received
1316 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1317 * purpose. This will be done in software by our network stack.
1319 if (sc->sc_flags & NFE_HW_VLAN)
1320 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1322 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1324 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1326 if (sc->sc_flags & NFE_HW_VLAN)
1327 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1329 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1331 /* set MAC address */
1332 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1334 /* tell MAC where rings are in memory */
1336 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1338 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1340 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1342 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1344 NFE_WRITE(sc, NFE_RING_SIZE,
1345 (sc->sc_rx_ring_count - 1) << 16 |
1346 (NFE_TX_RING_COUNT - 1));
1348 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1350 /* force MAC to wakeup */
1351 tmp = NFE_READ(sc, NFE_PWR_STATE);
1352 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1354 tmp = NFE_READ(sc, NFE_PWR_STATE);
1355 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1358 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
1359 * It is unclear how wide the timer is. Base programming does
1360 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
1361 * we don't get any interrupt moderation. TX moderation is
1362 * possible by using the timer interrupt instead of TX_DONE.
1364 * It is unclear whether there are other bits that can be
1365 * set to make the NFE device actually do interrupt moderation
1368 * For now set a 128uS interval as a placemark, but don't use
1371 if (sc->sc_imtime < 0)
1372 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
1374 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
1376 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1377 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1378 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1380 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1381 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1383 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1384 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC);
1386 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1387 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1389 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1394 nfe_ifmedia_upd(ifp);
1397 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1400 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1402 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1404 #ifdef DEVICE_POLLING
1405 if ((ifp->if_flags & IFF_POLLING) == 0)
1407 /* enable interrupts */
1408 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
1410 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1412 ifp->if_flags |= IFF_RUNNING;
1413 ifp->if_flags &= ~IFF_OACTIVE;
1416 * If we had stuff in the tx ring before its all cleaned out now
1417 * so we are not going to get an interrupt, jump-start any pending
1424 nfe_stop(struct nfe_softc *sc)
1426 struct ifnet *ifp = &sc->arpcom.ac_if;
1428 callout_stop(&sc->sc_tick_ch);
1431 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1434 * Are NFE_TX_CTL and NFE_RX_CTL polled by the chip microcontroller
1435 * or do they directly reset/terminate the DMA hardware? Nobody
1440 * (1) Delay before zeroing out NFE_TX_CTL. This seems to help a
1441 * watchdog timeout that occurs after a stop/init sequence. I am
1442 * theorizing that a TX KICK occuring just prior to a reinit (e.g.
1443 * due to dhclient) is queueing an interrupt to the microcontroller
1444 * which gets delayed until after we clear the control registers
1445 * down below, resulting in mass confusion. TX KICK is clearly
1446 * hardware aided whereas the other bits in the control register
1447 * are more likely to be polled by the microcontroller.
1449 * (2) Delay after zeroing out TX and RX CTL registers, under the
1450 * assumption that primary DMA is initiated and terminated by
1451 * the microcontroller and not hardware (and anyway, one can hardly
1452 * expect the DMA engine to just instantly stop!). We don't want
1453 * to rip the rings out from under it before it has had a chance to
1459 NFE_WRITE(sc, NFE_TX_CTL, 0);
1462 NFE_WRITE(sc, NFE_RX_CTL, 0);
1464 /* Disable interrupts */
1465 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1469 /* Reset Tx and Rx rings */
1470 nfe_reset_tx_ring(sc, &sc->txq);
1471 nfe_reset_rx_ring(sc, &sc->rxq);
1475 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1477 int i, j, error, descsize;
1480 if (sc->sc_flags & NFE_40BIT_ADDR) {
1481 desc = (void **)&ring->desc64;
1482 descsize = sizeof(struct nfe_desc64);
1484 desc = (void **)&ring->desc32;
1485 descsize = sizeof(struct nfe_desc32);
1488 ring->jbuf = kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT,
1489 M_DEVBUF, M_WAITOK | M_ZERO);
1490 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1491 M_DEVBUF, M_WAITOK | M_ZERO);
1493 ring->bufsz = MCLBYTES;
1494 ring->cur = ring->next = 0;
1496 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1497 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1499 sc->sc_rx_ring_count * descsize, 1,
1500 sc->sc_rx_ring_count * descsize,
1503 if_printf(&sc->arpcom.ac_if,
1504 "could not create desc RX DMA tag\n");
1508 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1511 if_printf(&sc->arpcom.ac_if,
1512 "could not allocate RX desc DMA memory\n");
1513 bus_dma_tag_destroy(ring->tag);
1518 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1519 sc->sc_rx_ring_count * descsize,
1520 nfe_ring_dma_addr, &ring->physaddr,
1523 if_printf(&sc->arpcom.ac_if,
1524 "could not load RX desc DMA map\n");
1525 bus_dmamem_free(ring->tag, *desc, ring->map);
1526 bus_dma_tag_destroy(ring->tag);
1531 if (sc->sc_flags & NFE_JUMBO_SUP) {
1532 error = nfe_jpool_alloc(sc, ring);
1534 if_printf(&sc->arpcom.ac_if,
1535 "could not allocate jumbo frames\n");
1540 error = bus_dma_tag_create(NULL, 1, 0,
1541 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1543 MCLBYTES, 1, MCLBYTES,
1544 0, &ring->data_tag);
1546 if_printf(&sc->arpcom.ac_if,
1547 "could not create RX mbuf DMA tag\n");
1551 /* Create a spare RX mbuf DMA map */
1552 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1554 if_printf(&sc->arpcom.ac_if,
1555 "could not create spare RX mbuf DMA map\n");
1556 bus_dma_tag_destroy(ring->data_tag);
1557 ring->data_tag = NULL;
1561 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1562 error = bus_dmamap_create(ring->data_tag, 0,
1563 &ring->data[i].map);
1565 if_printf(&sc->arpcom.ac_if,
1566 "could not create %dth RX mbuf DMA mapn", i);
1572 for (j = 0; j < i; ++j)
1573 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1574 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1575 bus_dma_tag_destroy(ring->data_tag);
1576 ring->data_tag = NULL;
1581 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1585 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1586 struct nfe_rx_data *data = &ring->data[i];
1588 if (data->m != NULL) {
1589 if ((sc->sc_flags & NFE_USE_JUMBO) == 0)
1590 bus_dmamap_unload(ring->data_tag, data->map);
1595 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1597 ring->cur = ring->next = 0;
1601 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1605 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1608 /* XXX should use a function pointer */
1609 if (sc->sc_flags & NFE_USE_JUMBO)
1610 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1612 error = nfe_newbuf_std(sc, ring, i, 1);
1614 if_printf(&sc->arpcom.ac_if,
1615 "could not allocate RX buffer\n");
1619 nfe_set_ready_rxdesc(sc, ring, i);
1621 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1627 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1629 if (ring->data_tag != NULL) {
1630 struct nfe_rx_data *data;
1633 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1634 data = &ring->data[i];
1636 if (data->m != NULL) {
1637 bus_dmamap_unload(ring->data_tag, data->map);
1640 bus_dmamap_destroy(ring->data_tag, data->map);
1642 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1643 bus_dma_tag_destroy(ring->data_tag);
1646 nfe_jpool_free(sc, ring);
1648 if (ring->jbuf != NULL)
1649 kfree(ring->jbuf, M_DEVBUF);
1650 if (ring->data != NULL)
1651 kfree(ring->data, M_DEVBUF);
1653 if (ring->tag != NULL) {
1656 if (sc->sc_flags & NFE_40BIT_ADDR)
1657 desc = ring->desc64;
1659 desc = ring->desc32;
1661 bus_dmamap_unload(ring->tag, ring->map);
1662 bus_dmamem_free(ring->tag, desc, ring->map);
1663 bus_dma_tag_destroy(ring->tag);
1667 static struct nfe_jbuf *
1668 nfe_jalloc(struct nfe_softc *sc)
1670 struct ifnet *ifp = &sc->arpcom.ac_if;
1671 struct nfe_jbuf *jbuf;
1673 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1675 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1677 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1680 if_printf(ifp, "no free jumbo buffer\n");
1683 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1689 nfe_jfree(void *arg)
1691 struct nfe_jbuf *jbuf = arg;
1692 struct nfe_softc *sc = jbuf->sc;
1693 struct nfe_rx_ring *ring = jbuf->ring;
1695 if (&ring->jbuf[jbuf->slot] != jbuf)
1696 panic("%s: free wrong jumbo buffer\n", __func__);
1697 else if (jbuf->inuse == 0)
1698 panic("%s: jumbo buffer already freed\n", __func__);
1700 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1701 atomic_subtract_int(&jbuf->inuse, 1);
1702 if (jbuf->inuse == 0)
1703 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1704 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1710 struct nfe_jbuf *jbuf = arg;
1711 struct nfe_rx_ring *ring = jbuf->ring;
1713 if (&ring->jbuf[jbuf->slot] != jbuf)
1714 panic("%s: ref wrong jumbo buffer\n", __func__);
1715 else if (jbuf->inuse == 0)
1716 panic("%s: jumbo buffer already freed\n", __func__);
1718 atomic_add_int(&jbuf->inuse, 1);
1722 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1724 struct nfe_jbuf *jbuf;
1725 bus_addr_t physaddr;
1730 * Allocate a big chunk of DMA'able memory.
1732 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1733 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1735 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1738 if_printf(&sc->arpcom.ac_if,
1739 "could not create jumbo DMA tag\n");
1743 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1744 BUS_DMA_WAITOK, &ring->jmap);
1746 if_printf(&sc->arpcom.ac_if,
1747 "could not allocate jumbo DMA memory\n");
1748 bus_dma_tag_destroy(ring->jtag);
1753 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1754 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1757 if_printf(&sc->arpcom.ac_if,
1758 "could not load jumbo DMA map\n");
1759 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1760 bus_dma_tag_destroy(ring->jtag);
1765 /* ..and split it into 9KB chunks */
1766 SLIST_INIT(&ring->jfreelist);
1769 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1770 jbuf = &ring->jbuf[i];
1777 jbuf->physaddr = physaddr;
1779 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1782 physaddr += NFE_JBYTES;
1789 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1791 if (ring->jtag != NULL) {
1792 bus_dmamap_unload(ring->jtag, ring->jmap);
1793 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1794 bus_dma_tag_destroy(ring->jtag);
1799 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1801 int i, j, error, descsize;
1804 if (sc->sc_flags & NFE_40BIT_ADDR) {
1805 desc = (void **)&ring->desc64;
1806 descsize = sizeof(struct nfe_desc64);
1808 desc = (void **)&ring->desc32;
1809 descsize = sizeof(struct nfe_desc32);
1813 ring->cur = ring->next = 0;
1815 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1816 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1818 NFE_TX_RING_COUNT * descsize, 1,
1819 NFE_TX_RING_COUNT * descsize,
1822 if_printf(&sc->arpcom.ac_if,
1823 "could not create TX desc DMA map\n");
1827 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1830 if_printf(&sc->arpcom.ac_if,
1831 "could not allocate TX desc DMA memory\n");
1832 bus_dma_tag_destroy(ring->tag);
1837 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1838 NFE_TX_RING_COUNT * descsize,
1839 nfe_ring_dma_addr, &ring->physaddr,
1842 if_printf(&sc->arpcom.ac_if,
1843 "could not load TX desc DMA map\n");
1844 bus_dmamem_free(ring->tag, *desc, ring->map);
1845 bus_dma_tag_destroy(ring->tag);
1850 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1851 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1853 NFE_JBYTES * NFE_MAX_SCATTER,
1854 NFE_MAX_SCATTER, NFE_JBYTES,
1855 0, &ring->data_tag);
1857 if_printf(&sc->arpcom.ac_if,
1858 "could not create TX buf DMA tag\n");
1862 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1863 error = bus_dmamap_create(ring->data_tag, 0,
1864 &ring->data[i].map);
1866 if_printf(&sc->arpcom.ac_if,
1867 "could not create %dth TX buf DMA map\n", i);
1874 for (j = 0; j < i; ++j)
1875 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1876 bus_dma_tag_destroy(ring->data_tag);
1877 ring->data_tag = NULL;
1882 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1886 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1887 struct nfe_tx_data *data = &ring->data[i];
1889 if (sc->sc_flags & NFE_40BIT_ADDR)
1890 ring->desc64[i].flags = 0;
1892 ring->desc32[i].flags = 0;
1894 if (data->m != NULL) {
1895 bus_dmamap_sync(ring->data_tag, data->map,
1896 BUS_DMASYNC_POSTWRITE);
1897 bus_dmamap_unload(ring->data_tag, data->map);
1902 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1905 ring->cur = ring->next = 0;
1909 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1910 struct nfe_tx_ring *ring __unused)
1916 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1918 if (ring->data_tag != NULL) {
1919 struct nfe_tx_data *data;
1922 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
1923 data = &ring->data[i];
1925 if (data->m != NULL) {
1926 bus_dmamap_unload(ring->data_tag, data->map);
1929 bus_dmamap_destroy(ring->data_tag, data->map);
1932 bus_dma_tag_destroy(ring->data_tag);
1935 if (ring->tag != NULL) {
1938 if (sc->sc_flags & NFE_40BIT_ADDR)
1939 desc = ring->desc64;
1941 desc = ring->desc32;
1943 bus_dmamap_unload(ring->tag, ring->map);
1944 bus_dmamem_free(ring->tag, desc, ring->map);
1945 bus_dma_tag_destroy(ring->tag);
1950 nfe_ifmedia_upd(struct ifnet *ifp)
1952 struct nfe_softc *sc = ifp->if_softc;
1953 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1955 if (mii->mii_instance != 0) {
1956 struct mii_softc *miisc;
1958 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1959 mii_phy_reset(miisc);
1967 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1969 struct nfe_softc *sc = ifp->if_softc;
1970 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1973 ifmr->ifm_status = mii->mii_media_status;
1974 ifmr->ifm_active = mii->mii_media_active;
1978 nfe_setmulti(struct nfe_softc *sc)
1980 struct ifnet *ifp = &sc->arpcom.ac_if;
1981 struct ifmultiaddr *ifma;
1982 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
1983 uint32_t filter = NFE_RXFILTER_MAGIC;
1986 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
1987 bzero(addr, ETHER_ADDR_LEN);
1988 bzero(mask, ETHER_ADDR_LEN);
1992 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
1993 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
1995 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1998 if (ifma->ifma_addr->sa_family != AF_LINK)
2001 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2002 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2003 addr[i] &= maddr[i];
2004 mask[i] &= ~maddr[i];
2008 for (i = 0; i < ETHER_ADDR_LEN; i++)
2012 addr[0] |= 0x01; /* make sure multicast bit is set */
2014 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2015 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2016 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2017 addr[5] << 8 | addr[4]);
2018 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2019 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2020 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2021 mask[5] << 8 | mask[4]);
2023 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2024 NFE_WRITE(sc, NFE_RXFILTER, filter);
2028 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2032 tmp = NFE_READ(sc, NFE_MACADDR_LO);
2033 addr[0] = (tmp >> 8) & 0xff;
2034 addr[1] = (tmp & 0xff);
2036 tmp = NFE_READ(sc, NFE_MACADDR_HI);
2037 addr[2] = (tmp >> 24) & 0xff;
2038 addr[3] = (tmp >> 16) & 0xff;
2039 addr[4] = (tmp >> 8) & 0xff;
2040 addr[5] = (tmp & 0xff);
2044 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2046 NFE_WRITE(sc, NFE_MACADDR_LO,
2047 addr[5] << 8 | addr[4]);
2048 NFE_WRITE(sc, NFE_MACADDR_HI,
2049 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2055 struct nfe_softc *sc = arg;
2056 struct ifnet *ifp = &sc->arpcom.ac_if;
2057 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2059 lwkt_serialize_enter(ifp->if_serializer);
2062 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2064 lwkt_serialize_exit(ifp->if_serializer);
2068 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2073 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2075 *((uint32_t *)arg) = seg->ds_addr;
2079 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2080 bus_size_t mapsz __unused, int error)
2082 struct nfe_dma_ctx *ctx = arg;
2088 KASSERT(nsegs <= ctx->nsegs,
2089 ("too many segments(%d), should be <= %d\n",
2090 nsegs, ctx->nsegs));
2093 for (i = 0; i < nsegs; ++i)
2094 ctx->segs[i] = segs[i];
2098 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2101 struct nfe_rx_data *data = &ring->data[idx];
2102 struct nfe_dma_ctx ctx;
2103 bus_dma_segment_t seg;
2108 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2111 m->m_len = m->m_pkthdr.len = MCLBYTES;
2115 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2116 m, nfe_buf_dma_addr, &ctx,
2117 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2120 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2124 /* Unload originally mapped mbuf */
2125 bus_dmamap_unload(ring->data_tag, data->map);
2127 /* Swap this DMA map with tmp DMA map */
2129 data->map = ring->data_tmpmap;
2130 ring->data_tmpmap = map;
2132 /* Caller is assumed to have collected the old mbuf */
2135 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2137 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2142 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2145 struct nfe_rx_data *data = &ring->data[idx];
2146 struct nfe_jbuf *jbuf;
2149 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2153 jbuf = nfe_jalloc(sc);
2156 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2157 "-- packet dropped!\n");
2161 m->m_ext.ext_arg = jbuf;
2162 m->m_ext.ext_buf = jbuf->buf;
2163 m->m_ext.ext_free = nfe_jfree;
2164 m->m_ext.ext_ref = nfe_jref;
2165 m->m_ext.ext_size = NFE_JBYTES;
2167 m->m_data = m->m_ext.ext_buf;
2168 m->m_flags |= M_EXT;
2169 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2171 /* Caller is assumed to have collected the old mbuf */
2174 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2176 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2181 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2182 bus_addr_t physaddr)
2184 if (sc->sc_flags & NFE_40BIT_ADDR) {
2185 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2187 #if defined(__LP64__)
2188 desc64->physaddr[0] = htole32(physaddr >> 32);
2190 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2192 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2194 desc32->physaddr = htole32(physaddr);
2199 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2201 if (sc->sc_flags & NFE_40BIT_ADDR) {
2202 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2204 desc64->length = htole16(ring->bufsz);
2205 desc64->flags = htole16(NFE_RX_READY);
2207 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2209 desc32->length = htole16(ring->bufsz);
2210 desc32->flags = htole16(NFE_RX_READY);
2215 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2217 struct nfe_softc *sc = arg1;
2218 struct ifnet *ifp = &sc->arpcom.ac_if;
2221 lwkt_serialize_enter(ifp->if_serializer);
2224 error = sysctl_handle_int(oidp, &v, 0, req);
2225 if (error || req->newptr == NULL)
2232 if (sc->sc_imtime != v) {
2233 int old_imtime = sc->sc_imtime;
2236 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2238 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2240 if (old_imtime > 0 && sc->sc_imtime > 0) {
2241 NFE_WRITE(sc, NFE_IMTIMER,
2242 NFE_IMTIME(sc->sc_imtime));
2243 } else if ((old_imtime * sc->sc_imtime) < 0) {
2249 lwkt_serialize_exit(ifp->if_serializer);