2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.26 2006/11/14 10:54:21 joerg Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
44 #include <machine/stdarg.h>
45 #include <machine/clock.h>
47 #include <bus/pci/pcivar.h>
48 #include <bus/pci/pcireg.h>
51 /* device structures */
52 struct ata_pci_controller {
53 struct resource *bmio;
60 #define IOMASK 0xfffffffc
61 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
62 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
63 (pci_get_progif(dev) & 0x05) != 0x05)
66 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
71 if (device_get_children(device_get_parent(dev), &children, &nchildren))
74 for (i = 0; i < nchildren; i++) {
75 if (pci_get_devid(children[i]) == devid &&
76 pci_get_revid(children[i]) >= revid) {
77 kfree(children, M_TEMP);
81 kfree(children, M_TEMP);
86 ata_via_southbridge_fixup(device_t dev)
91 if (device_get_children(device_get_parent(dev), &children, &nchildren))
94 for (i = 0; i < nchildren; i++) {
95 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
96 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
97 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
98 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
99 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
101 if ((reg76 & 0xf0) != 0xd0) {
103 "Correcting VIA config for southbridge data corruption bug\n");
104 pci_write_config(children[i], 0x75, 0x80, 1);
105 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
110 kfree(children, M_TEMP);
114 ata_pci_match(device_t dev)
116 if (pci_get_class(dev) != PCIC_STORAGE)
119 switch (pci_get_devid(dev)) {
120 /* supported chipsets */
122 return "Intel PIIX ATA controller";
125 return "Intel PIIX3 ATA controller";
130 return "Intel PIIX4 ATA33 controller";
133 return "Intel ICH0 ATA33 controller";
137 return "Intel ICH ATA66 controller";
141 return "Intel ICH2 ATA100 controller";
145 return "Intel ICH3 ATA100 controller";
149 return "Intel ICH4 ATA100 controller";
152 return "Intel ICH5 SATA150 controller";
155 return "Intel ICH5 ATA100 controller";
159 return "Intel ICH6 SATA300 controller";
162 return "Intel ICH6/W SATA150 controller";
165 return "Intel ICH6R/RW SATA150 controller";
168 return "Intel ICH6R/RW ATA100 controller";
171 return "Intel ICH7 ATA controller";
174 return "Intel ICH7M SATA controller";
177 if (pci_get_revid(dev) >= 0xc4)
178 return "AcerLabs Aladdin ATA100 controller";
179 else if (pci_get_revid(dev) >= 0xc2)
180 return "AcerLabs Aladdin ATA66 controller";
181 else if (pci_get_revid(dev) >= 0x20)
182 return "AcerLabs Aladdin ATA33 controller";
184 return "AcerLabs Aladdin ATA controller";
187 if (ata_find_dev(dev, 0x05861106, 0x02))
188 return "VIA 82C586 ATA33 controller";
189 if (ata_find_dev(dev, 0x05861106, 0))
190 return "VIA 82C586 ATA controller";
191 if (ata_find_dev(dev, 0x05961106, 0x12))
192 return "VIA 82C596 ATA66 controller";
193 if (ata_find_dev(dev, 0x05961106, 0))
194 return "VIA 82C596 ATA33 controller";
195 if (ata_find_dev(dev, 0x06861106, 0x40))
196 return "VIA 82C686 ATA100 controller";
197 if (ata_find_dev(dev, 0x06861106, 0x10))
198 return "VIA 82C686 ATA66 controller";
199 if (ata_find_dev(dev, 0x06861106, 0))
200 return "VIA 82C686 ATA33 controller";
201 if (ata_find_dev(dev, 0x82311106, 0))
202 return "VIA 8231 ATA100 controller";
203 if (ata_find_dev(dev, 0x30741106, 0) ||
204 ata_find_dev(dev, 0x31091106, 0))
205 return "VIA 8233 ATA100 controller";
206 if (ata_find_dev(dev, 0x31471106, 0))
207 return "VIA 8233 ATA133 controller";
208 if (ata_find_dev(dev, 0x31771106, 0))
209 return "VIA 8235 ATA133 controller";
210 if (ata_find_dev(dev, 0x31491106, 0))
211 return "VIA 8237 ATA133 controller";
212 return "VIA Apollo ATA controller";
215 return "VIA 8237 SATA 150 controller";
218 if (ata_find_dev(dev, 0x07461039, 0))
219 return "SiS 5591 ATA133 controller";
220 if (ata_find_dev(dev, 0x06301039, 0x30) ||
221 ata_find_dev(dev, 0x06331039, 0) ||
222 ata_find_dev(dev, 0x06351039, 0) ||
223 ata_find_dev(dev, 0x06401039, 0) ||
224 ata_find_dev(dev, 0x06451039, 0) ||
225 ata_find_dev(dev, 0x06461039, 0) ||
226 ata_find_dev(dev, 0x06481039, 0) ||
227 ata_find_dev(dev, 0x06501039, 0) ||
228 ata_find_dev(dev, 0x07301039, 0) ||
229 ata_find_dev(dev, 0x07331039, 0) ||
230 ata_find_dev(dev, 0x07351039, 0) ||
231 ata_find_dev(dev, 0x07401039, 0) ||
232 ata_find_dev(dev, 0x07451039, 0) ||
233 ata_find_dev(dev, 0x07501039, 0))
234 return "SiS 5591 ATA100 controller";
235 else if (ata_find_dev(dev, 0x05301039, 0) ||
236 ata_find_dev(dev, 0x05401039, 0) ||
237 ata_find_dev(dev, 0x06201039, 0) ||
238 ata_find_dev(dev, 0x06301039, 0))
239 return "SiS 5591 ATA66 controller";
241 return "SiS 5591 ATA33 controller";
244 return "SiI 3512 SATA controller";
247 return "SiI 3112 SATA controller";
250 return "SiI 3114 SATA controller";
253 return "SiI 3124 SATA controller";
256 return "SiI 0680 ATA133 controller";
259 return "CMD 649 ATA100 controller";
262 return "CMD 648 ATA66 controller";
265 return "CMD 646 ATA controller";
268 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
269 return "Cypress 82C693 ATA controller";
273 return "Cyrix 5530 ATA33 controller";
276 return "AMD 756 ATA66 controller";
279 return "AMD 766 ATA100 controller";
282 return "AMD 768 ATA100 controller";
285 return "AMD 8111 UltraATA/133 controller";
288 return "nVIDIA nForce1 ATA100 controller";
291 return "nVIDIA nForce2 ATA133 controller";
294 return "nVIDIA nForce3 ATA133 controller";
297 return "nVIDIA nForce3 PRO S1 controller";
300 return "nVIDIA nForce3 PRO controller";
303 return "ServerWorks ROSB4 ATA33 controller";
306 if (pci_get_revid(dev) >= 0x92)
307 return "ServerWorks CSB5 ATA100 controller";
309 return "ServerWorks CSB5 ATA66 controller";
312 return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
315 return "ServerWorks CSB6 ATA66 controller (channel 2)";
318 return "Promise ATA33 controller";
322 return "Promise ATA66 controller";
326 return "Promise ATA100 controller";
330 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
331 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
332 static long start = 0, end = 0;
334 /* we belive we are on a TX4, now do our (simple) magic */
335 if (pci_get_slot(dev) == 1) {
336 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
337 return "Promise TX4 ATA100 controller (channel 0+1)";
339 else if (pci_get_slot(dev) == 2 && start && end) {
340 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
342 return "Promise TX4 ATA100 controller (channel 2+3)";
347 return "Promise TX2 ATA100 controller";
353 return "Promise TX2 ATA133 controller";
356 switch (pci_get_revid(dev)) {
359 return "HighPoint HPT366 ATA66 controller";
361 return "HighPoint HPT368 ATA66 controller";
364 return "HighPoint HPT370 ATA100 controller";
366 return "HighPoint HPT372 ATA133 controller";
371 switch (pci_get_revid(dev)) {
374 return "HighPoint HPT372 ATA133 controller";
379 switch (pci_get_revid(dev)) {
381 return "HighPoint HPT374 ATA133 controller";
386 return "Cenatek Rocket Drive controller";
388 /* unsupported but known chipsets, generic DMA only */
391 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
394 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
396 /* unknown chipsets, try generic DMA if it seems possible */
398 if (pci_get_class(dev) == PCIC_STORAGE &&
399 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
400 return "Generic PCI ATA controller";
406 ata_pci_probe(device_t dev)
408 const char *desc = ata_pci_match(dev);
411 device_set_desc(dev, desc);
419 ata_pci_add_child(device_t dev, int unit)
423 /* check if this is located at one of the std addresses */
424 if (ATA_MASTERDEV(dev)) {
425 if (!(child = device_add_child(dev, "ata", unit)))
429 if (!(child = device_add_child(dev, "ata", 2)))
436 ata_pci_attach(device_t dev)
438 struct ata_pci_controller *controller = device_get_softc(dev);
439 u_int8_t class, subclass;
444 /* set up vendor-specific stuff */
445 type = pci_get_devid(dev);
446 class = pci_get_class(dev);
447 subclass = pci_get_subclass(dev);
448 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
450 if (!(cmd & PCIM_CMD_PORTEN)) {
451 device_printf(dev, "ATA channel disabled by BIOS\n");
455 /* is busmastering supported ? */
456 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
457 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
459 /* is there a valid port range to connect to ? */
461 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
462 0, ~0, 1, RF_ACTIVE);
463 if (!controller->bmio)
464 device_printf(dev, "Busmastering DMA not configured\n");
467 device_printf(dev, "Busmastering DMA not supported\n");
469 /* do extra chipset specific setups */
473 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
474 pci_write_config(dev, 0x53,
475 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
478 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
481 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
484 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
485 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
488 case 0x00041103: /* HighPoint HPT366/368/370/372 */
489 if (pci_get_revid(dev) < 2) { /* HPT 366 */
490 /* turn off interrupt prediction */
491 pci_write_config(dev, 0x51,
492 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
495 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
496 /* turn off interrupt prediction */
497 pci_write_config(dev, 0x51,
498 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
499 pci_write_config(dev, 0x55,
500 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
502 /* turn on interrupts */
503 pci_write_config(dev, 0x5a,
504 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
507 pci_write_config(dev, 0x5b, 0x22, 1);
512 case 0x00051103: /* HighPoint HPT372 */
513 case 0x00081103: /* HighPoint HPT374 */
514 /* turn off interrupt prediction */
515 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
516 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
518 /* turn on interrupts */
519 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
522 pci_write_config(dev, 0x5b,
523 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
526 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
527 /* prepare for ATA-66 on the 82C686a and 82C596b */
528 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
529 !ata_find_dev(dev, 0x06861106, 0x40)) ||
530 ata_find_dev(dev, 0x05961106, 0x12))
531 pci_write_config(dev, 0x50, 0x030b030b, 4);
533 /* the southbridge might need the data corruption fix */
534 if (ata_find_dev(dev, 0x06861106, 0x40) ||
535 ata_find_dev(dev, 0x82311106, 0x10))
536 ata_via_southbridge_fixup(dev);
538 /* set fifo configuration half'n'half */
539 pci_write_config(dev, 0x43,
540 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
542 /* set status register read retry */
543 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
545 /* set DMA read & end-of-sector fifo flush */
546 pci_write_config(dev, 0x46,
547 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
549 /* set sector size */
550 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
551 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
553 case 0x74111022: /* AMD 766 default setup */
554 flags = 1; /* bugged */
556 case 0x74091022: /* AMD 756 default setup */
557 case 0x74411022: /* AMD 768 default setup */
558 case 0x746d1022: /* AMD 8111 default setup */
560 pci_write_config(dev, 0x41,
561 pci_read_config(dev, 0x41, 1) & 0x0f, 1);
563 pci_write_config(dev, 0x41,
564 pci_read_config(dev, 0x41, 1) | 0xf0, 1);
567 case 0x01bc10de: /* NVIDIA nForce1 default setup */
568 case 0x006510de: /* NVIDIA nForce2 default setup */
571 case 0x00d510de: /* NVIDIA nForce3 default setup */
573 pci_write_config(dev, 0x51,
574 pci_read_config(dev, 0x51, 1) & 0x0f, 1);
576 pci_write_config(dev, 0x51,
577 pci_read_config(dev, 0x51, 1) | 0xf0, 1);
581 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
582 pci_write_config(dev, 0x64,
583 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
587 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
588 pci_write_config(dev, 0x5a,
589 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
590 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
593 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
594 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
595 pci_write_config(dev, 0x8a,
596 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
597 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
598 device_printf(dev, "SiI 0680 could not set clock\n");
603 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
604 pci_write_config(dev, 0x71, 0x01, 1);
607 case 0x10001042: /* RZ 100? known bad, no DMA */
609 case 0x06401095: /* CMD 640 known bad, no DMA */
610 controller->bmio = NULL;
611 device_printf(dev, "Busmastering DMA disabled\n");
614 if (controller->bmio) {
615 controller->bmaddr = rman_get_start(controller->bmio);
616 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
617 SYS_RES_IOPORT, rid, controller->bmio);
618 controller->bmio = NULL;
622 * the Cypress chip is a mess, it contains two ATA functions, but
623 * both channels are visible on the first one.
624 * simply ignore the second function for now, as the right
625 * solution (ignoring the second channel on the first function)
626 * doesn't work with the crappy ATA interrupt setup on the alpha.
628 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
631 ata_pci_add_child(dev, 0);
633 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
634 ata_pci_add_child(dev, 1);
636 return bus_generic_attach(dev);
640 ata_pci_intr(struct ata_channel *ch)
645 * since we might share the IRQ with another device, and in some
646 * cases with our twin channel, we only want to process interrupts
647 * that we know this channel generated.
649 switch (ch->chiptype) {
650 case 0x00041103: /* HighPoint HPT366/368/370/372 */
651 case 0x00051103: /* HighPoint HPT372 */
652 case 0x00081103: /* HighPoint HPT374 */
653 if (((dmastat = ata_dmastatus(ch)) &
654 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
656 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
660 case 0x06481095: /* CMD 648 */
661 case 0x06491095: /* CMD 649 */
662 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
663 (ch->unit ? 0x08 : 0x04)))
665 #if !defined(NO_ATANG)
666 pci_write_config(device_get_parent(ch->dev), 0x71,
667 pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
668 ~(ch->unit ? 0x04 : 0x08), 1);
672 case 0x06801095: /* SiI 680 */
673 if (!(pci_read_config(device_get_parent(ch->dev),
674 (ch->unit ? 0xb1 : 0xa1), 1) & 0x08))
678 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
679 case 0x0d38105a: /* Promise Fasttrak 66 */
680 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
681 case 0x0d30105a: /* Promise OEM ATA100 */
682 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
683 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
684 (ch->unit ? 0x00004000 : 0x00000400)))
688 case 0x4d68105a: /* Promise TX2 ATA100 */
689 case 0x6268105a: /* Promise TX2 ATA100 */
690 case 0x4d69105a: /* Promise TX2 ATA133 */
691 case 0x5275105a: /* Promise TX2 ATA133 */
692 case 0x6269105a: /* Promise TX2 ATA133 */
693 case 0x7275105a: /* Promise TX2 ATA133 */
694 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
695 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
699 case 0x24d18086: /* Intel ICH5 SATA150 */
700 case 0x24db8086: /* Intel ICH5 ATA100 */
701 case 0x26518086: /* Intel ICH6 SATA150 */
702 case 0x26528086: /* Intel ICH6R SATA150 */
703 case 0x26808086: /* Intel ICH6R SATA150 */
704 case 0x260e8086: /* Intel ICH6 SATA300 */
705 dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
706 if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
707 ATA_BMSTAT_INTERRUPT)
709 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat &
710 ~(ATA_BMSTAT_DMA_SIMPLEX | ATA_BMSTAT_ERROR));
716 if (ch->flags & ATA_DMA_ACTIVE) {
717 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
719 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
726 ata_pci_print_child(device_t dev, device_t child)
728 struct ata_channel *ch = device_get_softc(child);
731 retval += bus_print_child_header(dev, child);
732 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
734 if (ATA_MASTERDEV(dev))
735 retval += printf(" irq %d", 14 + ch->unit);
737 retval += bus_print_child_footer(dev, child);
742 static struct resource *
743 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
744 u_long start, u_long end, u_long count, u_int flags)
746 struct ata_pci_controller *controller = device_get_softc(dev);
747 struct resource *res = NULL;
748 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
751 if (type == SYS_RES_IOPORT) {
754 if (ATA_MASTERDEV(dev)) {
756 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
757 end = start + ATA_IOSIZE - 1;
759 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
760 SYS_RES_IOPORT, &myrid,
761 start, end, count, flags);
764 myrid = 0x10 + 8 * unit;
765 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
766 SYS_RES_IOPORT, &myrid,
767 start, end, count, flags);
771 case ATA_ALTADDR_RID:
772 if (ATA_MASTERDEV(dev)) {
774 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
775 end = start + ATA_ALTIOSIZE - 1;
776 count = ATA_ALTIOSIZE;
777 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
778 SYS_RES_IOPORT, &myrid,
779 start, end, count, flags);
782 myrid = 0x14 + 8 * unit;
783 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
784 SYS_RES_IOPORT, &myrid,
785 start, end, count, flags);
787 start = rman_get_start(res) + 2;
788 end = start + ATA_ALTIOSIZE - 1;
789 count = ATA_ALTIOSIZE;
790 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
791 SYS_RES_IOPORT, myrid, res);
792 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
793 SYS_RES_IOPORT, &myrid,
794 start, end, count, flags);
800 if (controller->bmaddr) {
803 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
804 end = start + ATA_BMIOSIZE - 1;
805 count = ATA_BMIOSIZE;
806 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
807 SYS_RES_IOPORT, &myrid,
808 start, end, count, flags);
814 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
815 if (ATA_MASTERDEV(dev)) {
816 int irq = (unit == 0 ? 14 : 15);
818 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
819 SYS_RES_IRQ, rid, irq, irq, 1, flags);
822 /* primary and secondary channels share interrupt, keep track */
823 if (!controller->irq)
824 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
826 rid, 0, ~0, 1, flags);
827 controller->irqcnt++;
828 return controller->irq;
835 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
838 struct ata_pci_controller *controller = device_get_softc(dev);
839 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
841 if (type == SYS_RES_IOPORT) {
844 if (ATA_MASTERDEV(dev))
845 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
846 SYS_RES_IOPORT, 0x0, r);
848 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
849 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
852 case ATA_ALTADDR_RID:
853 if (ATA_MASTERDEV(dev))
854 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
855 SYS_RES_IOPORT, 0x0, r);
857 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
858 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
862 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
863 SYS_RES_IOPORT, 0x20, r);
868 if (type == SYS_RES_IRQ) {
869 if (rid != ATA_IRQ_RID)
872 if (ATA_MASTERDEV(dev)) {
873 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
874 SYS_RES_IRQ, rid, r);
877 /* primary and secondary channels share interrupt, keep track */
878 if (--controller->irqcnt)
880 controller->irq = NULL;
881 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
882 SYS_RES_IRQ, rid, r);
889 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
890 int flags, driver_intr_t *intr, void *arg,
891 void **cookiep, lwkt_serialize_t serializer)
893 if (ATA_MASTERDEV(dev)) {
894 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
895 flags, intr, arg, cookiep, serializer);
898 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
899 flags, intr, arg, cookiep, serializer);
903 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
906 if (ATA_MASTERDEV(dev)) {
907 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
910 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
913 static device_method_t ata_pci_methods[] = {
914 /* device interface */
915 DEVMETHOD(device_probe, ata_pci_probe),
916 DEVMETHOD(device_attach, ata_pci_attach),
917 DEVMETHOD(device_shutdown, bus_generic_shutdown),
918 DEVMETHOD(device_suspend, bus_generic_suspend),
919 DEVMETHOD(device_resume, bus_generic_resume),
922 DEVMETHOD(bus_print_child, ata_pci_print_child),
923 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
924 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
925 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
926 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
927 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
928 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
932 static driver_t ata_pci_driver = {
935 sizeof(struct ata_pci_controller),
938 static devclass_t ata_pci_devclass;
940 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
943 ata_pcisub_probe(device_t dev)
945 struct ata_channel *ch = device_get_softc(dev);
949 /* find channel number on this controller */
950 device_get_children(device_get_parent(dev), &children, &count);
951 for (i = 0; i < count; i++) {
952 if (children[i] == dev)
955 kfree(children, M_TEMP);
956 ch->chiptype = pci_get_devid(device_get_parent(dev));
957 ch->intr_func = ata_pci_intr;
958 return ata_probe(dev);
961 static device_method_t ata_pcisub_methods[] = {
962 /* device interface */
963 DEVMETHOD(device_probe, ata_pcisub_probe),
964 DEVMETHOD(device_attach, ata_attach),
965 DEVMETHOD(device_detach, ata_detach),
966 DEVMETHOD(device_resume, ata_resume),
967 DEVMETHOD(device_suspend, ata_suspend),
971 static driver_t ata_pcisub_driver = {
974 sizeof(struct ata_channel),
977 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);