1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.45 2008/09/17 08:51:29 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
60 #include <sys/param.h>
61 #include <sys/endian.h>
62 #include <sys/kernel.h>
64 #include <sys/interrupt.h>
67 #include <sys/serialize.h>
68 #include <sys/socket.h>
69 #include <sys/sockio.h>
70 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
75 #include <net/if_arp.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/ifq_var.h>
79 #include <net/if_types.h>
80 #include <net/if_var.h>
81 #include <net/vlan/if_vlan_var.h>
82 #include <net/vlan/if_vlan_ether.h>
84 #include <bus/pci/pcireg.h>
85 #include <bus/pci/pcivar.h>
86 #include <bus/pci/pcidevs.h>
88 #include <dev/netif/mii_layer/mii.h>
89 #include <dev/netif/mii_layer/miivar.h>
91 #include "miibus_if.h"
93 #include <dev/netif/nfe/if_nfereg.h>
94 #include <dev/netif/nfe/if_nfevar.h>
97 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
99 static int nfe_probe(device_t);
100 static int nfe_attach(device_t);
101 static int nfe_detach(device_t);
102 static void nfe_shutdown(device_t);
103 static int nfe_resume(device_t);
104 static int nfe_suspend(device_t);
106 static int nfe_miibus_readreg(device_t, int, int);
107 static void nfe_miibus_writereg(device_t, int, int, int);
108 static void nfe_miibus_statchg(device_t);
110 #ifdef DEVICE_POLLING
111 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
113 static void nfe_intr(void *);
114 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
115 static int nfe_rxeof(struct nfe_softc *);
116 static int nfe_txeof(struct nfe_softc *, int);
117 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
119 static void nfe_start(struct ifnet *);
120 static void nfe_watchdog(struct ifnet *);
121 static void nfe_init(void *);
122 static void nfe_stop(struct nfe_softc *);
123 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
124 static void nfe_jfree(void *);
125 static void nfe_jref(void *);
126 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
127 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
128 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
129 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
133 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static int nfe_ifmedia_upd(struct ifnet *);
137 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
138 static void nfe_setmulti(struct nfe_softc *);
139 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
140 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
141 static void nfe_powerup(device_t);
142 static void nfe_mac_reset(struct nfe_softc *);
143 static void nfe_tick(void *);
144 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
145 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
147 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
149 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
151 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
153 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
155 static void nfe_enable_intrs(struct nfe_softc *);
156 static void nfe_disable_intrs(struct nfe_softc *);
158 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
163 static int nfe_debug = 0;
164 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
165 static int nfe_tx_ring_count = NFE_TX_RING_DEF_COUNT;
166 /* hw timer simulated interrupt moderation @8000Hz */
167 static int nfe_imtime = -125;
169 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
170 TUNABLE_INT("hw.nfe.tx_ring_count", &nfe_tx_ring_count);
171 TUNABLE_INT("hw.nfe.imtimer", &nfe_imtime);
172 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
174 #define DPRINTF(sc, fmt, ...) do { \
175 if ((sc)->sc_debug) { \
176 if_printf(&(sc)->arpcom.ac_if, \
181 #define DPRINTFN(sc, lv, fmt, ...) do { \
182 if ((sc)->sc_debug >= (lv)) { \
183 if_printf(&(sc)->arpcom.ac_if, \
188 #else /* !NFE_DEBUG */
190 #define DPRINTF(sc, fmt, ...)
191 #define DPRINTFN(sc, lv, fmt, ...)
193 #endif /* NFE_DEBUG */
197 bus_dma_segment_t *segs;
200 static const struct nfe_dev {
205 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
206 "NVIDIA nForce Fast Ethernet" },
208 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
209 "NVIDIA nForce2 Fast Ethernet" },
211 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
212 "NVIDIA nForce3 Gigabit Ethernet" },
214 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
215 chipset, and possibly also the 400R; it might be both nForce2- and
216 nForce3-based boards can use the same MCPs (= southbridges) */
217 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
218 "NVIDIA nForce3 Gigabit Ethernet" },
220 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
221 "NVIDIA nForce3 Gigabit Ethernet" },
223 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
224 "NVIDIA nForce3 Gigabit Ethernet" },
226 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
227 "NVIDIA nForce3 Gigabit Ethernet" },
229 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
230 "NVIDIA CK804 Gigabit Ethernet" },
232 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
233 "NVIDIA CK804 Gigabit Ethernet" },
235 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
236 "NVIDIA MCP04 Gigabit Ethernet" },
238 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
239 "NVIDIA MCP04 Gigabit Ethernet" },
241 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
242 "NVIDIA MCP51 Gigabit Ethernet" },
244 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
245 "NVIDIA MCP51 Gigabit Ethernet" },
247 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
248 "NVIDIA MCP55 Gigabit Ethernet" },
250 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
251 "NVIDIA MCP55 Gigabit Ethernet" },
253 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
254 "NVIDIA MCP61 Gigabit Ethernet" },
256 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
257 "NVIDIA MCP61 Gigabit Ethernet" },
259 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
260 "NVIDIA MCP61 Gigabit Ethernet" },
262 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
263 "NVIDIA MCP61 Gigabit Ethernet" },
265 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
266 "NVIDIA MCP65 Gigabit Ethernet" },
268 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
269 "NVIDIA MCP65 Gigabit Ethernet" },
271 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
272 "NVIDIA MCP65 Gigabit Ethernet" },
274 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
275 "NVIDIA MCP65 Gigabit Ethernet" },
277 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
278 "NVIDIA MCP67 Gigabit Ethernet" },
280 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
281 "NVIDIA MCP67 Gigabit Ethernet" },
283 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
284 "NVIDIA MCP67 Gigabit Ethernet" },
286 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
287 "NVIDIA MCP67 Gigabit Ethernet" },
289 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
290 "NVIDIA MCP73 Gigabit Ethernet" },
292 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
293 "NVIDIA MCP73 Gigabit Ethernet" },
295 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
296 "NVIDIA MCP73 Gigabit Ethernet" },
298 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
299 "NVIDIA MCP73 Gigabit Ethernet" },
301 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
302 "NVIDIA MCP77 Gigabit Ethernet" },
304 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
305 "NVIDIA MCP77 Gigabit Ethernet" },
307 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
308 "NVIDIA MCP77 Gigabit Ethernet" },
310 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
311 "NVIDIA MCP77 Gigabit Ethernet" },
313 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
314 "NVIDIA MCP79 Gigabit Ethernet" },
316 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
317 "NVIDIA MCP79 Gigabit Ethernet" },
319 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
320 "NVIDIA MCP79 Gigabit Ethernet" },
322 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
323 "NVIDIA MCP79 Gigabit Ethernet" },
328 static device_method_t nfe_methods[] = {
329 /* Device interface */
330 DEVMETHOD(device_probe, nfe_probe),
331 DEVMETHOD(device_attach, nfe_attach),
332 DEVMETHOD(device_detach, nfe_detach),
333 DEVMETHOD(device_suspend, nfe_suspend),
334 DEVMETHOD(device_resume, nfe_resume),
335 DEVMETHOD(device_shutdown, nfe_shutdown),
338 DEVMETHOD(bus_print_child, bus_generic_print_child),
339 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
342 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
343 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
344 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
349 static driver_t nfe_driver = {
352 sizeof(struct nfe_softc)
355 static devclass_t nfe_devclass;
357 DECLARE_DUMMY_MODULE(if_nfe);
358 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
359 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
360 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
363 nfe_probe(device_t dev)
365 const struct nfe_dev *n;
368 vid = pci_get_vendor(dev);
369 did = pci_get_device(dev);
370 for (n = nfe_devices; n->desc != NULL; ++n) {
371 if (vid == n->vid && did == n->did) {
372 struct nfe_softc *sc = device_get_softc(dev);
375 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
376 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
377 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
378 sc->sc_caps = NFE_NO_PWRCTL |
381 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
382 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
383 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
384 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
385 sc->sc_caps = NFE_JUMBO_SUP |
390 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
391 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
392 sc->sc_caps = NFE_FIX_EADDR;
394 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
395 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
396 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
397 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
398 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
399 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
400 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
401 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
402 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
403 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
404 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
405 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
406 sc->sc_caps |= NFE_40BIT_ADDR;
408 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
409 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
410 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
411 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
412 sc->sc_caps = NFE_JUMBO_SUP |
418 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
419 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
420 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
421 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
422 sc->sc_caps = NFE_JUMBO_SUP |
425 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
426 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
427 sc->sc_caps = NFE_JUMBO_SUP |
433 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
434 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
435 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
436 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
437 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
438 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
439 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
440 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
441 sc->sc_caps = NFE_40BIT_ADDR |
446 device_set_desc(dev, n->desc);
447 device_set_async_attach(dev, TRUE);
455 nfe_attach(device_t dev)
457 struct nfe_softc *sc = device_get_softc(dev);
458 struct ifnet *ifp = &sc->arpcom.ac_if;
459 uint8_t eaddr[ETHER_ADDR_LEN];
462 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
463 lwkt_serialize_init(&sc->sc_jbuf_serializer);
466 * Initialize sysctl variables
468 sc->sc_rx_ring_count = nfe_rx_ring_count;
469 sc->sc_tx_ring_count = nfe_tx_ring_count;
470 sc->sc_debug = nfe_debug;
471 if (nfe_imtime < 0) {
472 sc->sc_flags |= NFE_F_DYN_IM;
473 sc->sc_imtime = -nfe_imtime;
475 sc->sc_imtime = nfe_imtime;
477 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
479 sc->sc_mem_rid = PCIR_BAR(0);
481 if (sc->sc_caps & NFE_40BIT_ADDR)
482 sc->rxtxctl_desc = NFE_RXTX_DESC_V3;
483 else if (sc->sc_caps & NFE_JUMBO_SUP)
484 sc->rxtxctl_desc = NFE_RXTX_DESC_V2;
487 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
490 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
491 irq = pci_read_config(dev, PCIR_INTLINE, 4);
493 device_printf(dev, "chip is in D%d power mode "
494 "-- setting to D0\n", pci_get_powerstate(dev));
496 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
498 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
499 pci_write_config(dev, PCIR_INTLINE, irq, 4);
501 #endif /* !BURN_BRIDGE */
503 /* Enable bus mastering */
504 pci_enable_busmaster(dev);
506 /* Allocate IO memory */
507 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
508 &sc->sc_mem_rid, RF_ACTIVE);
509 if (sc->sc_mem_res == NULL) {
510 device_printf(dev, "cound not allocate io memory\n");
513 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
514 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
518 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
520 RF_SHAREABLE | RF_ACTIVE);
521 if (sc->sc_irq_res == NULL) {
522 device_printf(dev, "could not allocate irq\n");
528 NFE_WRITE(sc, NFE_WOL_CTL, 0);
530 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
533 nfe_get_macaddr(sc, eaddr);
536 * Allocate Tx and Rx rings.
538 error = nfe_alloc_tx_ring(sc, &sc->txq);
540 device_printf(dev, "could not allocate Tx ring\n");
544 error = nfe_alloc_rx_ring(sc, &sc->rxq);
546 device_printf(dev, "could not allocate Rx ring\n");
553 sysctl_ctx_init(&sc->sc_sysctl_ctx);
554 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
555 SYSCTL_STATIC_CHILDREN(_hw),
557 device_get_nameunit(dev),
559 if (sc->sc_sysctl_tree == NULL) {
560 device_printf(dev, "can't add sysctl node\n");
564 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
565 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
566 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
567 sc, 0, nfe_sysctl_imtime, "I",
568 "Interrupt moderation time (usec). "
569 "0 to disable interrupt moderation.");
570 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
571 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
572 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
574 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
575 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
576 "tx_ring_count", CTLFLAG_RD, &sc->sc_tx_ring_count,
578 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
579 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
580 "debug", CTLFLAG_RW, &sc->sc_debug,
581 0, "control debugging printfs");
583 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
586 device_printf(dev, "MII without any phy\n");
591 ifp->if_mtu = ETHERMTU;
592 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
593 ifp->if_ioctl = nfe_ioctl;
594 ifp->if_start = nfe_start;
595 #ifdef DEVICE_POLLING
596 ifp->if_poll = nfe_poll;
598 ifp->if_watchdog = nfe_watchdog;
599 ifp->if_init = nfe_init;
600 ifq_set_maxlen(&ifp->if_snd, sc->sc_tx_ring_count);
601 ifq_set_ready(&ifp->if_snd);
603 ifp->if_capabilities = IFCAP_VLAN_MTU;
605 if (sc->sc_caps & NFE_HW_VLAN)
606 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
609 if (sc->sc_caps & NFE_HW_CSUM) {
610 ifp->if_capabilities |= IFCAP_HWCSUM;
611 ifp->if_hwassist = NFE_CSUM_FEATURES;
614 sc->sc_caps &= ~NFE_HW_CSUM;
616 ifp->if_capenable = ifp->if_capabilities;
618 callout_init(&sc->sc_tick_ch);
620 ether_ifattach(ifp, eaddr, NULL);
622 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
623 &sc->sc_ih, ifp->if_serializer);
625 device_printf(dev, "could not setup intr\n");
630 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
631 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
640 nfe_detach(device_t dev)
642 struct nfe_softc *sc = device_get_softc(dev);
644 if (device_is_attached(dev)) {
645 struct ifnet *ifp = &sc->arpcom.ac_if;
647 lwkt_serialize_enter(ifp->if_serializer);
649 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
650 lwkt_serialize_exit(ifp->if_serializer);
655 if (sc->sc_miibus != NULL)
656 device_delete_child(dev, sc->sc_miibus);
657 bus_generic_detach(dev);
659 if (sc->sc_sysctl_tree != NULL)
660 sysctl_ctx_free(&sc->sc_sysctl_ctx);
662 if (sc->sc_irq_res != NULL) {
663 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
667 if (sc->sc_mem_res != NULL) {
668 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
672 nfe_free_tx_ring(sc, &sc->txq);
673 nfe_free_rx_ring(sc, &sc->rxq);
679 nfe_shutdown(device_t dev)
681 struct nfe_softc *sc = device_get_softc(dev);
682 struct ifnet *ifp = &sc->arpcom.ac_if;
684 lwkt_serialize_enter(ifp->if_serializer);
686 lwkt_serialize_exit(ifp->if_serializer);
690 nfe_suspend(device_t dev)
692 struct nfe_softc *sc = device_get_softc(dev);
693 struct ifnet *ifp = &sc->arpcom.ac_if;
695 lwkt_serialize_enter(ifp->if_serializer);
697 lwkt_serialize_exit(ifp->if_serializer);
703 nfe_resume(device_t dev)
705 struct nfe_softc *sc = device_get_softc(dev);
706 struct ifnet *ifp = &sc->arpcom.ac_if;
708 lwkt_serialize_enter(ifp->if_serializer);
709 if (ifp->if_flags & IFF_UP)
711 lwkt_serialize_exit(ifp->if_serializer);
717 nfe_miibus_statchg(device_t dev)
719 struct nfe_softc *sc = device_get_softc(dev);
720 struct mii_data *mii = device_get_softc(sc->sc_miibus);
721 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
723 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
725 phy = NFE_READ(sc, NFE_PHY_IFACE);
726 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
728 seed = NFE_READ(sc, NFE_RNDSEED);
729 seed &= ~NFE_SEED_MASK;
731 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
732 phy |= NFE_PHY_HDX; /* half-duplex */
733 misc |= NFE_MISC1_HDX;
736 switch (IFM_SUBTYPE(mii->mii_media_active)) {
737 case IFM_1000_T: /* full-duplex only */
738 link |= NFE_MEDIA_1000T;
739 seed |= NFE_SEED_1000T;
740 phy |= NFE_PHY_1000T;
743 link |= NFE_MEDIA_100TX;
744 seed |= NFE_SEED_100TX;
745 phy |= NFE_PHY_100TX;
748 link |= NFE_MEDIA_10T;
749 seed |= NFE_SEED_10T;
753 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
755 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
756 NFE_WRITE(sc, NFE_MISC1, misc);
757 NFE_WRITE(sc, NFE_LINKSPEED, link);
761 nfe_miibus_readreg(device_t dev, int phy, int reg)
763 struct nfe_softc *sc = device_get_softc(dev);
767 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
769 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
770 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
774 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
776 for (ntries = 0; ntries < 1000; ntries++) {
778 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
781 if (ntries == 1000) {
782 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
786 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
787 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
791 val = NFE_READ(sc, NFE_PHY_DATA);
792 if (val != 0xffffffff && val != 0)
793 sc->mii_phyaddr = phy;
795 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
801 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
803 struct nfe_softc *sc = device_get_softc(dev);
807 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
809 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
810 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
814 NFE_WRITE(sc, NFE_PHY_DATA, val);
815 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
816 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
818 for (ntries = 0; ntries < 1000; ntries++) {
820 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
826 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
830 #ifdef DEVICE_POLLING
833 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
835 struct nfe_softc *sc = ifp->if_softc;
837 ASSERT_SERIALIZED(ifp->if_serializer);
841 nfe_disable_intrs(sc);
844 case POLL_DEREGISTER:
845 nfe_enable_intrs(sc);
848 case POLL_AND_CHECK_STATUS:
851 if (ifp->if_flags & IFF_RUNNING) {
864 struct nfe_softc *sc = arg;
865 struct ifnet *ifp = &sc->arpcom.ac_if;
868 r = NFE_READ(sc, NFE_IRQ_STATUS);
870 return; /* not for us */
871 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
873 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
875 if (r & NFE_IRQ_LINK) {
876 NFE_READ(sc, NFE_PHY_STATUS);
877 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
878 DPRINTF(sc, "link state changed %s\n", "");
881 if (ifp->if_flags & IFF_RUNNING) {
888 ret |= nfe_txeof(sc, 1);
890 if (sc->sc_flags & NFE_F_DYN_IM) {
891 if (ret && (sc->sc_flags & NFE_F_IRQ_TIMER) == 0) {
893 * Assume that using hardware timer could reduce
894 * the interrupt rate.
896 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_IMTIMER);
897 sc->sc_flags |= NFE_F_IRQ_TIMER;
898 } else if (!ret && (sc->sc_flags & NFE_F_IRQ_TIMER)) {
900 * Nothing needs to be processed, fall back to
901 * use TX/RX interrupts.
903 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_NOIMTIMER);
904 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
911 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
913 struct nfe_softc *sc = ifp->if_softc;
914 struct ifreq *ifr = (struct ifreq *)data;
915 struct mii_data *mii;
916 int error = 0, mask, jumbo_cap;
918 ASSERT_SERIALIZED(ifp->if_serializer);
922 if ((sc->sc_caps & NFE_JUMBO_SUP) && sc->rxq.jbuf != NULL)
927 if ((jumbo_cap && ifr->ifr_mtu > NFE_JUMBO_MTU) ||
928 (!jumbo_cap && ifr->ifr_mtu > ETHERMTU)) {
930 } else if (ifp->if_mtu != ifr->ifr_mtu) {
931 ifp->if_mtu = ifr->ifr_mtu;
932 if (ifp->if_flags & IFF_RUNNING)
937 if (ifp->if_flags & IFF_UP) {
939 * If only the PROMISC or ALLMULTI flag changes, then
940 * don't do a full re-init of the chip, just update
943 if ((ifp->if_flags & IFF_RUNNING) &&
944 ((ifp->if_flags ^ sc->sc_if_flags) &
945 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
948 if (!(ifp->if_flags & IFF_RUNNING))
952 if (ifp->if_flags & IFF_RUNNING)
955 sc->sc_if_flags = ifp->if_flags;
959 if (ifp->if_flags & IFF_RUNNING)
964 mii = device_get_softc(sc->sc_miibus);
965 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
968 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
969 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
970 ifp->if_capenable ^= mask;
971 if (IFCAP_TXCSUM & ifp->if_capenable)
972 ifp->if_hwassist = NFE_CSUM_FEATURES;
974 ifp->if_hwassist = 0;
976 if (ifp->if_flags & IFF_RUNNING)
981 error = ether_ioctl(ifp, cmd, data);
988 nfe_rxeof(struct nfe_softc *sc)
990 struct ifnet *ifp = &sc->arpcom.ac_if;
991 struct nfe_rx_ring *ring = &sc->rxq;
993 struct mbuf_chain chain[MAXCPU];
996 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
998 ether_input_chain_init(chain);
1001 struct nfe_rx_data *data = &ring->data[ring->cur];
1006 if (sc->sc_caps & NFE_40BIT_ADDR) {
1007 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
1009 flags = le16toh(desc64->flags);
1010 len = le16toh(desc64->length) & 0x3fff;
1012 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
1014 flags = le16toh(desc32->flags);
1015 len = le16toh(desc32->length) & 0x3fff;
1018 if (flags & NFE_RX_READY)
1023 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1024 if (!(flags & NFE_RX_VALID_V1))
1027 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
1028 flags &= ~NFE_RX_ERROR;
1029 len--; /* fix buffer length */
1032 if (!(flags & NFE_RX_VALID_V2))
1035 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
1036 flags &= ~NFE_RX_ERROR;
1037 len--; /* fix buffer length */
1041 if (flags & NFE_RX_ERROR) {
1048 if (sc->sc_flags & NFE_F_USE_JUMBO)
1049 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
1051 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1058 m->m_pkthdr.len = m->m_len = len;
1059 m->m_pkthdr.rcvif = ifp;
1061 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1062 (flags & NFE_RX_CSUMOK)) {
1063 if (flags & NFE_RX_IP_CSUMOK_V2) {
1064 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1069 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1070 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1072 CSUM_FRAG_NOT_CHECKED;
1073 m->m_pkthdr.csum_data = 0xffff;
1078 ether_input_chain(ifp, m, chain);
1080 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1081 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1085 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1086 ether_input_dispatch(chain);
1092 nfe_txeof(struct nfe_softc *sc, int start)
1094 struct ifnet *ifp = &sc->arpcom.ac_if;
1095 struct nfe_tx_ring *ring = &sc->txq;
1096 struct nfe_tx_data *data = NULL;
1098 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
1099 while (ring->next != ring->cur) {
1102 if (sc->sc_caps & NFE_40BIT_ADDR)
1103 flags = le16toh(ring->desc64[ring->next].flags);
1105 flags = le16toh(ring->desc32[ring->next].flags);
1107 if (flags & NFE_TX_VALID)
1110 data = &ring->data[ring->next];
1112 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1113 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1116 if ((flags & NFE_TX_ERROR_V1) != 0) {
1117 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1124 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1127 if ((flags & NFE_TX_ERROR_V2) != 0) {
1128 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1136 if (data->m == NULL) { /* should not get there */
1138 "last fragment bit w/o associated mbuf!\n");
1142 /* last fragment of the mbuf chain transmitted */
1143 bus_dmamap_sync(ring->data_tag, data->map,
1144 BUS_DMASYNC_POSTWRITE);
1145 bus_dmamap_unload(ring->data_tag, data->map);
1150 KKASSERT(ring->queued >= 0);
1151 ring->next = (ring->next + 1) % sc->sc_tx_ring_count;
1154 if (sc->sc_tx_ring_count - ring->queued >=
1155 sc->sc_tx_spare + NFE_NSEG_RSVD)
1156 ifp->if_flags &= ~IFF_OACTIVE;
1158 if (ring->queued == 0)
1161 if (start && !ifq_is_empty(&ifp->if_snd))
1171 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1173 struct nfe_dma_ctx ctx;
1174 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1175 struct nfe_tx_data *data, *data_map;
1177 struct nfe_desc64 *desc64 = NULL;
1178 struct nfe_desc32 *desc32 = NULL;
1181 int error, i, j, maxsegs;
1183 data = &ring->data[ring->cur];
1185 data_map = data; /* Remember who owns the DMA map */
1187 maxsegs = (sc->sc_tx_ring_count - ring->queued) - NFE_NSEG_RSVD;
1188 if (maxsegs > NFE_MAX_SCATTER)
1189 maxsegs = NFE_MAX_SCATTER;
1190 KASSERT(maxsegs >= sc->sc_tx_spare,
1191 ("no enough segments %d,%d\n", maxsegs, sc->sc_tx_spare));
1193 ctx.nsegs = maxsegs;
1195 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1196 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1197 if (!error && ctx.nsegs == 0) {
1198 bus_dmamap_unload(ring->data_tag, map);
1201 if (error && error != EFBIG) {
1202 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1205 if (error) { /* error == EFBIG */
1208 m_new = m_defrag(m0, MB_DONTWAIT);
1209 if (m_new == NULL) {
1210 if_printf(&sc->arpcom.ac_if,
1211 "could not defrag TX mbuf\n");
1218 ctx.nsegs = maxsegs;
1220 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1221 nfe_buf_dma_addr, &ctx,
1223 if (error || ctx.nsegs == 0) {
1225 bus_dmamap_unload(ring->data_tag, map);
1228 if_printf(&sc->arpcom.ac_if,
1229 "could not map defraged TX mbuf\n");
1236 /* setup h/w VLAN tagging */
1237 if (m0->m_flags & M_VLANTAG)
1238 vtag = m0->m_pkthdr.ether_vlantag;
1240 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1241 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1242 flags |= NFE_TX_IP_CSUM;
1243 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1244 flags |= NFE_TX_TCP_CSUM;
1248 * XXX urm. somebody is unaware of how hardware works. You
1249 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1250 * the ring until the entire chain is actually *VALID*. Otherwise
1251 * the hardware may encounter a partially initialized chain that
1252 * is marked as being ready to go when it in fact is not ready to
1256 for (i = 0; i < ctx.nsegs; i++) {
1257 j = (ring->cur + i) % sc->sc_tx_ring_count;
1258 data = &ring->data[j];
1260 if (sc->sc_caps & NFE_40BIT_ADDR) {
1261 desc64 = &ring->desc64[j];
1262 #if defined(__LP64__)
1263 desc64->physaddr[0] =
1264 htole32(segs[i].ds_addr >> 32);
1266 desc64->physaddr[1] =
1267 htole32(segs[i].ds_addr & 0xffffffff);
1268 desc64->length = htole16(segs[i].ds_len - 1);
1269 desc64->vtag = htole32(vtag);
1270 desc64->flags = htole16(flags);
1272 desc32 = &ring->desc32[j];
1273 desc32->physaddr = htole32(segs[i].ds_addr);
1274 desc32->length = htole16(segs[i].ds_len - 1);
1275 desc32->flags = htole16(flags);
1278 /* csum flags and vtag belong to the first fragment only */
1279 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1283 KKASSERT(ring->queued <= sc->sc_tx_ring_count);
1286 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1287 if (sc->sc_caps & NFE_40BIT_ADDR) {
1288 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1290 if (sc->sc_caps & NFE_JUMBO_SUP)
1291 flags = NFE_TX_LASTFRAG_V2;
1293 flags = NFE_TX_LASTFRAG_V1;
1294 desc32->flags |= htole16(flags);
1298 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1299 * whole mess until the first descriptor in the map is flagged.
1301 for (i = ctx.nsegs - 1; i >= 0; --i) {
1302 j = (ring->cur + i) % sc->sc_tx_ring_count;
1303 if (sc->sc_caps & NFE_40BIT_ADDR) {
1304 desc64 = &ring->desc64[j];
1305 desc64->flags |= htole16(NFE_TX_VALID);
1307 desc32 = &ring->desc32[j];
1308 desc32->flags |= htole16(NFE_TX_VALID);
1311 ring->cur = (ring->cur + ctx.nsegs) % sc->sc_tx_ring_count;
1313 /* Exchange DMA map */
1314 data_map->map = data->map;
1318 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1326 nfe_start(struct ifnet *ifp)
1328 struct nfe_softc *sc = ifp->if_softc;
1329 struct nfe_tx_ring *ring = &sc->txq;
1330 int count = 0, oactive = 0;
1333 ASSERT_SERIALIZED(ifp->if_serializer);
1335 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1341 if (sc->sc_tx_ring_count - ring->queued <
1342 sc->sc_tx_spare + NFE_NSEG_RSVD) {
1344 ifp->if_flags |= IFF_OACTIVE;
1353 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1357 ETHER_BPF_MTAP(ifp, m0);
1359 error = nfe_encap(sc, ring, m0);
1362 if (error == EFBIG) {
1364 ifp->if_flags |= IFF_OACTIVE;
1378 * `m0' may be freed in nfe_encap(), so
1379 * it should not be touched any more.
1382 if (count == 0) /* nothing sent */
1385 /* Sync TX descriptor ring */
1386 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1389 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1392 * Set a timeout in case the chip goes out to lunch.
1398 nfe_watchdog(struct ifnet *ifp)
1400 struct nfe_softc *sc = ifp->if_softc;
1402 ASSERT_SERIALIZED(ifp->if_serializer);
1404 if (ifp->if_flags & IFF_RUNNING) {
1405 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1410 if_printf(ifp, "watchdog timeout\n");
1412 nfe_init(ifp->if_softc);
1420 struct nfe_softc *sc = xsc;
1421 struct ifnet *ifp = &sc->arpcom.ac_if;
1425 ASSERT_SERIALIZED(ifp->if_serializer);
1429 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
1434 * Switching between jumbo frames and normal frames should
1435 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1437 if (ifp->if_mtu > ETHERMTU) {
1438 sc->sc_flags |= NFE_F_USE_JUMBO;
1439 sc->rxq.bufsz = NFE_JBYTES;
1440 sc->sc_tx_spare = NFE_NSEG_SPARE_JUMBO;
1442 if_printf(ifp, "use jumbo frames\n");
1444 sc->sc_flags &= ~NFE_F_USE_JUMBO;
1445 sc->rxq.bufsz = MCLBYTES;
1446 sc->sc_tx_spare = NFE_NSEG_SPARE;
1448 if_printf(ifp, "use non-jumbo frames\n");
1451 error = nfe_init_tx_ring(sc, &sc->txq);
1457 error = nfe_init_rx_ring(sc, &sc->rxq);
1463 NFE_WRITE(sc, NFE_TX_POLL, 0);
1464 NFE_WRITE(sc, NFE_STATUS, 0);
1466 sc->rxtxctl = NFE_RXTX_BIT2 | sc->rxtxctl_desc;
1468 if (ifp->if_capenable & IFCAP_RXCSUM)
1469 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1472 * Although the adapter is capable of stripping VLAN tags from received
1473 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1474 * purpose. This will be done in software by our network stack.
1476 if (sc->sc_caps & NFE_HW_VLAN)
1477 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1479 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1481 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1483 if (sc->sc_caps & NFE_HW_VLAN)
1484 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1486 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1488 /* set MAC address */
1489 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1491 /* tell MAC where rings are in memory */
1493 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1495 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1497 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1499 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1501 NFE_WRITE(sc, NFE_RING_SIZE,
1502 (sc->sc_rx_ring_count - 1) << 16 |
1503 (sc->sc_tx_ring_count - 1));
1505 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1507 /* force MAC to wakeup */
1508 tmp = NFE_READ(sc, NFE_PWR_STATE);
1509 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1511 tmp = NFE_READ(sc, NFE_PWR_STATE);
1512 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1514 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1515 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1516 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1518 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1519 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1521 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1523 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1524 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1526 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1531 nfe_ifmedia_upd(ifp);
1534 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1537 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1539 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1541 #ifdef DEVICE_POLLING
1542 if ((ifp->if_flags & IFF_POLLING))
1543 nfe_disable_intrs(sc);
1546 nfe_enable_intrs(sc);
1548 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1550 ifp->if_flags |= IFF_RUNNING;
1551 ifp->if_flags &= ~IFF_OACTIVE;
1554 * If we had stuff in the tx ring before its all cleaned out now
1555 * so we are not going to get an interrupt, jump-start any pending
1558 if (!ifq_is_empty(&ifp->if_snd))
1563 nfe_stop(struct nfe_softc *sc)
1565 struct ifnet *ifp = &sc->arpcom.ac_if;
1566 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
1569 ASSERT_SERIALIZED(ifp->if_serializer);
1571 callout_stop(&sc->sc_tick_ch);
1574 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1575 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
1577 #define WAITMAX 50000
1582 NFE_WRITE(sc, NFE_TX_CTL, 0);
1583 for (i = 0; i < WAITMAX; ++i) {
1585 if ((NFE_READ(sc, NFE_TX_STATUS) & NFE_TX_STATUS_BUSY) == 0)
1589 if_printf(ifp, "can't stop TX\n");
1595 NFE_WRITE(sc, NFE_RX_CTL, 0);
1596 for (i = 0; i < WAITMAX; ++i) {
1598 if ((NFE_READ(sc, NFE_RX_STATUS) & NFE_RX_STATUS_BUSY) == 0)
1602 if_printf(ifp, "can't stop RX\n");
1607 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
1609 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
1611 /* Disable interrupts */
1612 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1614 /* Reset Tx and Rx rings */
1615 nfe_reset_tx_ring(sc, &sc->txq);
1616 nfe_reset_rx_ring(sc, &sc->rxq);
1620 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1622 int i, j, error, descsize;
1625 if (sc->sc_caps & NFE_40BIT_ADDR) {
1626 desc = (void **)&ring->desc64;
1627 descsize = sizeof(struct nfe_desc64);
1629 desc = (void **)&ring->desc32;
1630 descsize = sizeof(struct nfe_desc32);
1633 ring->bufsz = MCLBYTES;
1634 ring->cur = ring->next = 0;
1636 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1637 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1639 sc->sc_rx_ring_count * descsize, 1,
1640 BUS_SPACE_MAXSIZE_32BIT,
1643 if_printf(&sc->arpcom.ac_if,
1644 "could not create desc RX DMA tag\n");
1648 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1651 if_printf(&sc->arpcom.ac_if,
1652 "could not allocate RX desc DMA memory\n");
1653 bus_dma_tag_destroy(ring->tag);
1658 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1659 sc->sc_rx_ring_count * descsize,
1660 nfe_ring_dma_addr, &ring->physaddr,
1663 if_printf(&sc->arpcom.ac_if,
1664 "could not load RX desc DMA map\n");
1665 bus_dmamem_free(ring->tag, *desc, ring->map);
1666 bus_dma_tag_destroy(ring->tag);
1671 if (sc->sc_caps & NFE_JUMBO_SUP) {
1673 kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT(sc),
1674 M_DEVBUF, M_WAITOK | M_ZERO);
1676 error = nfe_jpool_alloc(sc, ring);
1678 if_printf(&sc->arpcom.ac_if,
1679 "could not allocate jumbo frames\n");
1680 kfree(ring->jbuf, M_DEVBUF);
1682 /* Allow jumbo frame allocation to fail */
1686 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1687 M_DEVBUF, M_WAITOK | M_ZERO);
1689 error = bus_dma_tag_create(NULL, 1, 0,
1690 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1692 MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT,
1693 BUS_DMA_ALLOCNOW, &ring->data_tag);
1695 if_printf(&sc->arpcom.ac_if,
1696 "could not create RX mbuf DMA tag\n");
1700 /* Create a spare RX mbuf DMA map */
1701 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1703 if_printf(&sc->arpcom.ac_if,
1704 "could not create spare RX mbuf DMA map\n");
1705 bus_dma_tag_destroy(ring->data_tag);
1706 ring->data_tag = NULL;
1710 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1711 error = bus_dmamap_create(ring->data_tag, 0,
1712 &ring->data[i].map);
1714 if_printf(&sc->arpcom.ac_if,
1715 "could not create %dth RX mbuf DMA mapn", i);
1721 for (j = 0; j < i; ++j)
1722 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1723 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1724 bus_dma_tag_destroy(ring->data_tag);
1725 ring->data_tag = NULL;
1730 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1734 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1735 struct nfe_rx_data *data = &ring->data[i];
1737 if (data->m != NULL) {
1738 if ((sc->sc_flags & NFE_F_USE_JUMBO) == 0)
1739 bus_dmamap_unload(ring->data_tag, data->map);
1744 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1746 ring->cur = ring->next = 0;
1750 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1754 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1757 /* XXX should use a function pointer */
1758 if (sc->sc_flags & NFE_F_USE_JUMBO)
1759 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1761 error = nfe_newbuf_std(sc, ring, i, 1);
1763 if_printf(&sc->arpcom.ac_if,
1764 "could not allocate RX buffer\n");
1768 nfe_set_ready_rxdesc(sc, ring, i);
1770 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1776 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1778 if (ring->data_tag != NULL) {
1779 struct nfe_rx_data *data;
1782 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1783 data = &ring->data[i];
1785 if (data->m != NULL) {
1786 bus_dmamap_unload(ring->data_tag, data->map);
1789 bus_dmamap_destroy(ring->data_tag, data->map);
1791 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1792 bus_dma_tag_destroy(ring->data_tag);
1795 nfe_jpool_free(sc, ring);
1797 if (ring->jbuf != NULL)
1798 kfree(ring->jbuf, M_DEVBUF);
1799 if (ring->data != NULL)
1800 kfree(ring->data, M_DEVBUF);
1802 if (ring->tag != NULL) {
1805 if (sc->sc_caps & NFE_40BIT_ADDR)
1806 desc = ring->desc64;
1808 desc = ring->desc32;
1810 bus_dmamap_unload(ring->tag, ring->map);
1811 bus_dmamem_free(ring->tag, desc, ring->map);
1812 bus_dma_tag_destroy(ring->tag);
1816 static struct nfe_jbuf *
1817 nfe_jalloc(struct nfe_softc *sc)
1819 struct ifnet *ifp = &sc->arpcom.ac_if;
1820 struct nfe_jbuf *jbuf;
1822 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1824 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1826 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1829 if_printf(ifp, "no free jumbo buffer\n");
1832 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1838 nfe_jfree(void *arg)
1840 struct nfe_jbuf *jbuf = arg;
1841 struct nfe_softc *sc = jbuf->sc;
1842 struct nfe_rx_ring *ring = jbuf->ring;
1844 if (&ring->jbuf[jbuf->slot] != jbuf)
1845 panic("%s: free wrong jumbo buffer\n", __func__);
1846 else if (jbuf->inuse == 0)
1847 panic("%s: jumbo buffer already freed\n", __func__);
1849 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1850 atomic_subtract_int(&jbuf->inuse, 1);
1851 if (jbuf->inuse == 0)
1852 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1853 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1859 struct nfe_jbuf *jbuf = arg;
1860 struct nfe_rx_ring *ring = jbuf->ring;
1862 if (&ring->jbuf[jbuf->slot] != jbuf)
1863 panic("%s: ref wrong jumbo buffer\n", __func__);
1864 else if (jbuf->inuse == 0)
1865 panic("%s: jumbo buffer already freed\n", __func__);
1867 atomic_add_int(&jbuf->inuse, 1);
1871 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1873 struct nfe_jbuf *jbuf;
1874 bus_addr_t physaddr;
1879 * Allocate a big chunk of DMA'able memory.
1881 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1882 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1884 NFE_JPOOL_SIZE(sc), 1,
1885 BUS_SPACE_MAXSIZE_32BIT,
1888 if_printf(&sc->arpcom.ac_if,
1889 "could not create jumbo DMA tag\n");
1893 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1894 BUS_DMA_WAITOK, &ring->jmap);
1896 if_printf(&sc->arpcom.ac_if,
1897 "could not allocate jumbo DMA memory\n");
1898 bus_dma_tag_destroy(ring->jtag);
1903 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1905 nfe_ring_dma_addr, &physaddr, BUS_DMA_WAITOK);
1907 if_printf(&sc->arpcom.ac_if,
1908 "could not load jumbo DMA map\n");
1909 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1910 bus_dma_tag_destroy(ring->jtag);
1915 /* ..and split it into 9KB chunks */
1916 SLIST_INIT(&ring->jfreelist);
1919 for (i = 0; i < NFE_JPOOL_COUNT(sc); i++) {
1920 jbuf = &ring->jbuf[i];
1927 jbuf->physaddr = physaddr;
1929 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1932 physaddr += NFE_JBYTES;
1939 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1941 if (ring->jtag != NULL) {
1942 bus_dmamap_unload(ring->jtag, ring->jmap);
1943 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1944 bus_dma_tag_destroy(ring->jtag);
1949 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1951 int i, j, error, descsize;
1954 if (sc->sc_caps & NFE_40BIT_ADDR) {
1955 desc = (void **)&ring->desc64;
1956 descsize = sizeof(struct nfe_desc64);
1958 desc = (void **)&ring->desc32;
1959 descsize = sizeof(struct nfe_desc32);
1963 ring->cur = ring->next = 0;
1965 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1966 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1968 sc->sc_tx_ring_count * descsize, 1,
1969 BUS_SPACE_MAXSIZE_32BIT,
1972 if_printf(&sc->arpcom.ac_if,
1973 "could not create TX desc DMA map\n");
1977 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1980 if_printf(&sc->arpcom.ac_if,
1981 "could not allocate TX desc DMA memory\n");
1982 bus_dma_tag_destroy(ring->tag);
1987 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1988 sc->sc_tx_ring_count * descsize,
1989 nfe_ring_dma_addr, &ring->physaddr,
1992 if_printf(&sc->arpcom.ac_if,
1993 "could not load TX desc DMA map\n");
1994 bus_dmamem_free(ring->tag, *desc, ring->map);
1995 bus_dma_tag_destroy(ring->tag);
2000 ring->data = kmalloc(sizeof(struct nfe_tx_data) * sc->sc_tx_ring_count,
2001 M_DEVBUF, M_WAITOK | M_ZERO);
2003 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
2004 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
2006 NFE_JBYTES, NFE_MAX_SCATTER,
2007 BUS_SPACE_MAXSIZE_32BIT,
2008 BUS_DMA_ALLOCNOW, &ring->data_tag);
2010 if_printf(&sc->arpcom.ac_if,
2011 "could not create TX buf DMA tag\n");
2015 for (i = 0; i < sc->sc_tx_ring_count; i++) {
2016 error = bus_dmamap_create(ring->data_tag, 0,
2017 &ring->data[i].map);
2019 if_printf(&sc->arpcom.ac_if,
2020 "could not create %dth TX buf DMA map\n", i);
2027 for (j = 0; j < i; ++j)
2028 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
2029 bus_dma_tag_destroy(ring->data_tag);
2030 ring->data_tag = NULL;
2035 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
2039 for (i = 0; i < sc->sc_tx_ring_count; i++) {
2040 struct nfe_tx_data *data = &ring->data[i];
2042 if (sc->sc_caps & NFE_40BIT_ADDR)
2043 ring->desc64[i].flags = 0;
2045 ring->desc32[i].flags = 0;
2047 if (data->m != NULL) {
2048 bus_dmamap_sync(ring->data_tag, data->map,
2049 BUS_DMASYNC_POSTWRITE);
2050 bus_dmamap_unload(ring->data_tag, data->map);
2055 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
2058 ring->cur = ring->next = 0;
2062 nfe_init_tx_ring(struct nfe_softc *sc __unused,
2063 struct nfe_tx_ring *ring __unused)
2069 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
2071 if (ring->data_tag != NULL) {
2072 struct nfe_tx_data *data;
2075 for (i = 0; i < sc->sc_tx_ring_count; ++i) {
2076 data = &ring->data[i];
2078 if (data->m != NULL) {
2079 bus_dmamap_unload(ring->data_tag, data->map);
2082 bus_dmamap_destroy(ring->data_tag, data->map);
2085 bus_dma_tag_destroy(ring->data_tag);
2088 if (ring->data != NULL)
2089 kfree(ring->data, M_DEVBUF);
2091 if (ring->tag != NULL) {
2094 if (sc->sc_caps & NFE_40BIT_ADDR)
2095 desc = ring->desc64;
2097 desc = ring->desc32;
2099 bus_dmamap_unload(ring->tag, ring->map);
2100 bus_dmamem_free(ring->tag, desc, ring->map);
2101 bus_dma_tag_destroy(ring->tag);
2106 nfe_ifmedia_upd(struct ifnet *ifp)
2108 struct nfe_softc *sc = ifp->if_softc;
2109 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2111 ASSERT_SERIALIZED(ifp->if_serializer);
2113 if (mii->mii_instance != 0) {
2114 struct mii_softc *miisc;
2116 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2117 mii_phy_reset(miisc);
2125 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2127 struct nfe_softc *sc = ifp->if_softc;
2128 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2130 ASSERT_SERIALIZED(ifp->if_serializer);
2133 ifmr->ifm_status = mii->mii_media_status;
2134 ifmr->ifm_active = mii->mii_media_active;
2138 nfe_setmulti(struct nfe_softc *sc)
2140 struct ifnet *ifp = &sc->arpcom.ac_if;
2141 struct ifmultiaddr *ifma;
2142 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2143 uint32_t filter = NFE_RXFILTER_MAGIC;
2146 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2147 bzero(addr, ETHER_ADDR_LEN);
2148 bzero(mask, ETHER_ADDR_LEN);
2152 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2153 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2155 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2158 if (ifma->ifma_addr->sa_family != AF_LINK)
2161 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2162 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2163 addr[i] &= maddr[i];
2164 mask[i] &= ~maddr[i];
2168 for (i = 0; i < ETHER_ADDR_LEN; i++)
2172 addr[0] |= 0x01; /* make sure multicast bit is set */
2174 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2175 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2176 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2177 addr[5] << 8 | addr[4]);
2178 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2179 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2180 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2181 mask[5] << 8 | mask[4]);
2183 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2184 NFE_WRITE(sc, NFE_RXFILTER, filter);
2188 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2192 lo = NFE_READ(sc, NFE_MACADDR_LO);
2193 hi = NFE_READ(sc, NFE_MACADDR_HI);
2194 if (sc->sc_caps & NFE_FIX_EADDR) {
2195 addr[0] = (lo >> 8) & 0xff;
2196 addr[1] = (lo & 0xff);
2198 addr[2] = (hi >> 24) & 0xff;
2199 addr[3] = (hi >> 16) & 0xff;
2200 addr[4] = (hi >> 8) & 0xff;
2201 addr[5] = (hi & 0xff);
2203 addr[0] = (hi & 0xff);
2204 addr[1] = (hi >> 8) & 0xff;
2205 addr[2] = (hi >> 16) & 0xff;
2206 addr[3] = (hi >> 24) & 0xff;
2208 addr[4] = (lo & 0xff);
2209 addr[5] = (lo >> 8) & 0xff;
2214 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2216 NFE_WRITE(sc, NFE_MACADDR_LO,
2217 addr[5] << 8 | addr[4]);
2218 NFE_WRITE(sc, NFE_MACADDR_HI,
2219 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2225 struct nfe_softc *sc = arg;
2226 struct ifnet *ifp = &sc->arpcom.ac_if;
2227 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2229 lwkt_serialize_enter(ifp->if_serializer);
2232 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2234 lwkt_serialize_exit(ifp->if_serializer);
2238 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2243 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2245 *((uint32_t *)arg) = seg->ds_addr;
2249 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2250 bus_size_t mapsz __unused, int error)
2252 struct nfe_dma_ctx *ctx = arg;
2258 if (nsegs > ctx->nsegs) {
2264 for (i = 0; i < nsegs; ++i)
2265 ctx->segs[i] = segs[i];
2269 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2272 struct nfe_rx_data *data = &ring->data[idx];
2273 struct nfe_dma_ctx ctx;
2274 bus_dma_segment_t seg;
2279 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2282 m->m_len = m->m_pkthdr.len = MCLBYTES;
2286 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2287 m, nfe_buf_dma_addr, &ctx,
2288 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2289 if (error || ctx.nsegs == 0) {
2291 bus_dmamap_unload(ring->data_tag, ring->data_tmpmap);
2293 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
2298 if_printf(&sc->arpcom.ac_if,
2299 "could map RX mbuf %d\n", error);
2304 /* Unload originally mapped mbuf */
2305 bus_dmamap_unload(ring->data_tag, data->map);
2307 /* Swap this DMA map with tmp DMA map */
2309 data->map = ring->data_tmpmap;
2310 ring->data_tmpmap = map;
2312 /* Caller is assumed to have collected the old mbuf */
2315 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2317 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2322 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2325 struct nfe_rx_data *data = &ring->data[idx];
2326 struct nfe_jbuf *jbuf;
2329 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2333 jbuf = nfe_jalloc(sc);
2336 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2337 "-- packet dropped!\n");
2341 m->m_ext.ext_arg = jbuf;
2342 m->m_ext.ext_buf = jbuf->buf;
2343 m->m_ext.ext_free = nfe_jfree;
2344 m->m_ext.ext_ref = nfe_jref;
2345 m->m_ext.ext_size = NFE_JBYTES;
2347 m->m_data = m->m_ext.ext_buf;
2348 m->m_flags |= M_EXT;
2349 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2351 /* Caller is assumed to have collected the old mbuf */
2354 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2356 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2361 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2362 bus_addr_t physaddr)
2364 if (sc->sc_caps & NFE_40BIT_ADDR) {
2365 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2367 #if defined(__LP64__)
2368 desc64->physaddr[0] = htole32(physaddr >> 32);
2370 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2372 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2374 desc32->physaddr = htole32(physaddr);
2379 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2381 if (sc->sc_caps & NFE_40BIT_ADDR) {
2382 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2384 desc64->length = htole16(ring->bufsz);
2385 desc64->flags = htole16(NFE_RX_READY);
2387 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2389 desc32->length = htole16(ring->bufsz);
2390 desc32->flags = htole16(NFE_RX_READY);
2395 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2397 struct nfe_softc *sc = arg1;
2398 struct ifnet *ifp = &sc->arpcom.ac_if;
2402 lwkt_serialize_enter(ifp->if_serializer);
2404 flags = sc->sc_flags & ~NFE_F_DYN_IM;
2406 if (sc->sc_flags & NFE_F_DYN_IM)
2409 error = sysctl_handle_int(oidp, &v, 0, req);
2410 if (error || req->newptr == NULL)
2414 flags |= NFE_F_DYN_IM;
2418 if (v != sc->sc_imtime || (flags ^ sc->sc_flags)) {
2419 int old_imtime = sc->sc_imtime;
2420 uint32_t old_flags = sc->sc_flags;
2423 sc->sc_flags = flags;
2424 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2426 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2428 if (old_imtime * sc->sc_imtime == 0 ||
2429 (old_flags ^ sc->sc_flags)) {
2432 NFE_WRITE(sc, NFE_IMTIMER,
2433 NFE_IMTIME(sc->sc_imtime));
2438 lwkt_serialize_exit(ifp->if_serializer);
2443 nfe_powerup(device_t dev)
2445 struct nfe_softc *sc = device_get_softc(dev);
2450 * Bring MAC and PHY out of low power state
2453 pwr_state = NFE_READ(sc, NFE_PWR_STATE2) & ~NFE_PWRUP_MASK;
2455 did = pci_get_device(dev);
2456 if ((did == PCI_PRODUCT_NVIDIA_MCP51_LAN1 ||
2457 did == PCI_PRODUCT_NVIDIA_MCP51_LAN2) &&
2458 pci_get_revid(dev) >= 0xa3)
2459 pwr_state |= NFE_PWRUP_REV_A3;
2461 NFE_WRITE(sc, NFE_PWR_STATE2, pwr_state);
2465 nfe_mac_reset(struct nfe_softc *sc)
2467 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
2468 uint32_t macaddr_hi, macaddr_lo, tx_poll;
2470 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
2472 /* Save several registers for later restoration */
2473 macaddr_hi = NFE_READ(sc, NFE_MACADDR_HI);
2474 macaddr_lo = NFE_READ(sc, NFE_MACADDR_LO);
2475 tx_poll = NFE_READ(sc, NFE_TX_POLL);
2477 NFE_WRITE(sc, NFE_MAC_RESET, NFE_RESET_ASSERT);
2480 NFE_WRITE(sc, NFE_MAC_RESET, 0);
2483 /* Restore saved registers */
2484 NFE_WRITE(sc, NFE_MACADDR_HI, macaddr_hi);
2485 NFE_WRITE(sc, NFE_MACADDR_LO, macaddr_lo);
2486 NFE_WRITE(sc, NFE_TX_POLL, tx_poll);
2488 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
2492 nfe_enable_intrs(struct nfe_softc *sc)
2495 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
2496 * It is unclear how wide the timer is. Base programming does
2497 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
2498 * we don't get any interrupt moderation. TX moderation is
2499 * possible by using the timer interrupt instead of TX_DONE.
2501 * It is unclear whether there are other bits that can be
2502 * set to make the NFE device actually do interrupt moderation
2505 * For now set a 128uS interval as a placemark, but don't use
2508 if (sc->sc_imtime == 0)
2509 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
2511 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
2513 /* Enable interrupts */
2514 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
2516 if (sc->sc_irq_enable & NFE_IRQ_TIMER)
2517 sc->sc_flags |= NFE_F_IRQ_TIMER;
2519 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
2523 nfe_disable_intrs(struct nfe_softc *sc)
2525 /* Disable interrupts */
2526 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
2527 sc->sc_flags &= ~NFE_F_IRQ_TIMER;