1 /* $OpenBSD: if_nfereg.h,v 1.19 2006/05/28 00:20:21 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfereg.h,v 1.13 2008/07/12 11:44:17 sephe Exp $ */
5 * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org>
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define NFE_PCI_BA 0x10
22 #define NFE_RX_RING_DEF_COUNT 128
23 #define NFE_TX_RING_DEF_COUNT 256
25 #define NFE_JUMBO_FRAMELEN 9018
26 #define NFE_JUMBO_MTU (NFE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
28 #define NFE_JBYTES (NFE_JUMBO_FRAMELEN + ETHER_ALIGN)
29 #define NFE_JPOOL_COUNT(sc) (((sc)->sc_rx_ring_count * 3) / 2)
30 #define NFE_JPOOL_SIZE(sc) (NFE_JPOOL_COUNT((sc)) * NFE_JBYTES)
32 #define NFE_MAX_SCATTER 32
33 #define NFE_NSEG_SPARE_JUMBO 5
34 #define NFE_NSEG_SPARE 1
35 #define NFE_NSEG_RSVD 1
37 #define NFE_IRQ_STATUS 0x000
38 #define NFE_IRQ_MASK 0x004
39 #define NFE_SETUP_R6 0x008
40 #define NFE_IMTIMER 0x00c
41 #define NFE_MAC_RESET 0x034
42 #define NFE_MISC1 0x080
43 #define NFE_TX_CTL 0x084
44 #define NFE_TX_STATUS 0x088
45 #define NFE_RXFILTER 0x08c
46 #define NFE_RXBUFSZ 0x090
47 #define NFE_RX_CTL 0x094
48 #define NFE_RX_STATUS 0x098
49 #define NFE_RNDSEED 0x09c
50 #define NFE_SETUP_R1 0x0a0
51 #define NFE_SETUP_R2 0x0a4
52 #define NFE_MACADDR_HI 0x0a8
53 #define NFE_MACADDR_LO 0x0ac
54 #define NFE_MULTIADDR_HI 0x0b0
55 #define NFE_MULTIADDR_LO 0x0b4
56 #define NFE_MULTIMASK_HI 0x0b8
57 #define NFE_MULTIMASK_LO 0x0bc
58 #define NFE_PHY_IFACE 0x0c0
59 #define NFE_TX_RING_ADDR_LO 0x100
60 #define NFE_RX_RING_ADDR_LO 0x104
61 #define NFE_RING_SIZE 0x108
62 #define NFE_TX_POLL 0x10c
63 #define NFE_LINKSPEED 0x110
64 #define NFE_SETUP_R5 0x130
65 #define NFE_SETUP_R3 0x13C
66 #define NFE_SETUP_R7 0x140
67 #define NFE_RXTX_CTL 0x144
68 #define NFE_TX_RING_ADDR_HI 0x148
69 #define NFE_RX_RING_ADDR_HI 0x14c
70 #define NFE_PHY_STATUS 0x180
71 #define NFE_SETUP_R4 0x184
72 #define NFE_STATUS 0x188
73 #define NFE_PHY_SPEED 0x18c
74 #define NFE_PHY_CTL 0x190
75 #define NFE_PHY_DATA 0x194
76 #define NFE_WOL_CTL 0x200
77 #define NFE_PATTERN_CRC 0x204
78 #define NFE_PATTERN_MASK 0x208
79 #define NFE_PWR_CAP 0x268
80 #define NFE_PWR_STATE 0x26c
81 #define NFE_VTAG_CTL 0x300
82 #define NFE_PWR_STATE2 0x600
84 #define NFE_PHY_ERROR 0x00001
85 #define NFE_PHY_WRITE 0x00400
86 #define NFE_PHY_BUSY 0x08000
87 #define NFE_PHYADD_SHIFT 5
89 #define NFE_STATUS_MAGIC 0x140000
91 #define NFE_RESET_ASSERT 0xf3
93 #define NFE_TX_STATUS_BUSY 0x1
94 #define NFE_RX_STATUS_BUSY 0x1
96 #define NFE_R1_MAGIC 0x16070f
97 #define NFE_R2_MAGIC 0x16
98 #define NFE_R4_MAGIC 0x08
99 #define NFE_R6_MAGIC 0x03
100 #define NFE_WOL_ENABLE 0x1111
101 #define NFE_RX_START 0x01
102 #define NFE_TX_START 0x01
104 #define NFE_IRQ_RXERR 0x0001
105 #define NFE_IRQ_RX 0x0002
106 #define NFE_IRQ_RX_NOBUF 0x0004
107 #define NFE_IRQ_TXERR 0x0008
108 #define NFE_IRQ_TX_DONE 0x0010
109 #define NFE_IRQ_TIMER 0x0020
110 #define NFE_IRQ_LINK 0x0040
111 #define NFE_IRQ_TXERR2 0x0080
112 #define NFE_IRQ_TX1 0x0100
114 #define NFE_IRQ_NOIMTIMER \
115 (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \
116 NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \
118 #define NFE_IRQ_IMTIMER (NFE_IRQ_TIMER | NFE_IRQ_LINK)
120 #define NFE_RXTX_KICKTX 0x0001
121 #define NFE_RXTX_BIT1 0x0002
122 #define NFE_RXTX_BIT2 0x0004
123 #define NFE_RXTX_RESET 0x0010
124 #define NFE_RXTX_VTAG_STRIP 0x0040
125 #define NFE_RXTX_VTAG_INSERT 0x0080
126 #define NFE_RXTX_RXCSUM 0x0400
127 #define NFE_RXTX_DESC_V2 0x002100
128 #define NFE_RXTX_DESC_V3 0xc02200
129 #define NFE_RXFILTER_MAGIC 0x007f0008
130 #define NFE_U2M (1 << 5)
131 #define NFE_PROMISC (1 << 7)
133 #define NFE_IMTIME(t) ((((t) * 100) / 1024) & 0xffff)
134 /* default interrupt moderation timer of 128us */
135 #define NFE_IMTIME_DEFAULT NFE_IMTIME(128)
137 #define NFE_VTAG_ENABLE (1 << 13)
139 #define NFE_PWR_VALID (1 << 8)
140 #define NFE_PWR_WAKEUP (1 << 15)
142 #define NFE_PWRUP_MASK 0x0f11
143 #define NFE_PWRUP_REV_A3 0x1
145 #define NFE_MEDIA_SET 0x10000
146 #define NFE_MEDIA_1000T 0x00032
147 #define NFE_MEDIA_100TX 0x00064
148 #define NFE_MEDIA_10T 0x003e8
150 #define NFE_PHY_100TX (1 << 0)
151 #define NFE_PHY_1000T (1 << 1)
152 #define NFE_PHY_HDX (1 << 8)
154 #define NFE_MISC1_MAGIC 0x003b0f3c
155 #define NFE_MISC1_HDX (1 << 1)
157 #define NFE_SEED_MASK 0x0003ff00
158 #define NFE_SEED_10T 0x00007f00
159 #define NFE_SEED_100TX 0x00002d00
160 #define NFE_SEED_1000T 0x00007400
162 /* Rx/Tx descriptor */
167 #define NFE_RX_FIXME_V1 0x6004
168 #define NFE_RX_VALID_V1 (1 << 0)
169 #define NFE_TX_ERROR_V1 0x7808
170 #define NFE_TX_LASTFRAG_V1 (1 << 0)
173 #define NFE_V1_TXERR "\020" \
174 "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \
175 "\08FORCEDINT\03RETRY\00LASTPACKET"
177 /* V2 Rx/Tx descriptor */
179 uint32_t physaddr[2];
181 #define NFE_RX_VTAG (1 << 16)
182 #define NFE_TX_VTAG (1 << 18)
185 #define NFE_RX_FIXME_V2 0x4300
186 #define NFE_RX_VALID_V2 (1 << 13)
187 #define NFE_RX_IP_CSUMOK_V2 0x1000
188 #define NFE_RX_UDP_CSUMOK_V2 0x1400
189 #define NFE_RX_TCP_CSUMOK_V2 0x1800
190 #define NFE_TX_ERROR_V2 0x5c04
191 #define NFE_TX_LASTFRAG_V2 (1 << 13)
194 #define NFE_V2_TXERR "\020" \
195 "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
197 /* flags common to V1/V2 descriptors */
198 #define NFE_RX_CSUMOK 0x1c00
199 #define NFE_RX_ERROR (1 << 14)
200 #define NFE_RX_READY (1 << 15)
201 #define NFE_TX_TCP_CSUM (1 << 10)
202 #define NFE_TX_IP_CSUM (1 << 11)
203 #define NFE_TX_VALID (1 << 15)
205 #define NFE_READ(sc, reg) \
206 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))
208 #define NFE_WRITE(sc, reg, val) \
209 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))