1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This module is essentially the "combiner" phase of the U. of Arizona
24 Portable Optimizer, but redone to work on our list-structured
25 representation for RTL instead of their string representation.
27 The LOG_LINKS of each insn identify the most recent assignment
28 to each REG used in the insn. It is a list of previous insns,
29 each of which contains a SET for a REG that is used in this insn
30 and not used or set in between. LOG_LINKs never cross basic blocks.
31 They were set up by the preceding pass (lifetime analysis).
33 We try to combine each pair of insns joined by a logical link.
34 We also try to combine triples of insns A, B and C when
35 C has a link back to B and B has a link back to A.
37 LOG_LINKS does not have links for use of the CC0. They don't
38 need to, because the insn that sets the CC0 is always immediately
39 before the insn that tests it. So we always regard a branch
40 insn as having a logical link to the preceding insn. The same is true
41 for an insn explicitly using CC0.
43 We check (with use_crosses_set_p) to avoid combining in such a way
44 as to move a computation to a place where its value would be different.
46 Combination is done by mathematically substituting the previous
47 insn(s) values for the regs they set into the expressions in
48 the later insns that refer to these regs. If the result is a valid insn
49 for our target machine, according to the machine description,
50 we install it, delete the earlier insns, and update the data flow
51 information (LOG_LINKS and REG_NOTES) for what we did.
53 There are a few exceptions where the dataflow information created by
54 flow.c aren't completely updated:
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_regnotes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-flags.h"
89 #include "insn-codes.h"
90 #include "insn-attr.h"
95 /* It is not safe to use ordinary gen_lowpart in combine.
96 Use gen_lowpart_for_combine instead. See comments there. */
97 #define gen_lowpart dont_use_gen_lowpart_you_dummy
99 /* Number of attempts to combine instructions in this function. */
101 static int combine_attempts;
103 /* Number of attempts that got as far as substitution in this function. */
105 static int combine_merges;
107 /* Number of instructions combined with added SETs in this function. */
109 static int combine_extras;
111 /* Number of instructions combined in this function. */
113 static int combine_successes;
115 /* Totals over entire compilation. */
117 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Define a default value for REVERSIBLE_CC_MODE.
120 We can never assume that a condition code mode is safe to reverse unless
121 the md tells us so. */
122 #ifndef REVERSIBLE_CC_MODE
123 #define REVERSIBLE_CC_MODE(MODE) 0
126 /* Vector mapping INSN_UIDs to cuids.
127 The cuids are like uids but increase monotonically always.
128 Combine always uses cuids so that it can compare them.
129 But actually renumbering the uids, which we used to do,
130 proves to be a bad idea because it makes it hard to compare
131 the dumps produced by earlier passes with those from later passes. */
133 static int *uid_cuid;
134 static int max_uid_cuid;
136 /* Get the cuid of an insn. */
138 #define INSN_CUID(INSN) \
139 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
141 /* Maximum register number, which is the size of the tables below. */
143 static int combine_max_regno;
145 /* Record last point of death of (hard or pseudo) register n. */
147 static rtx *reg_last_death;
149 /* Record last point of modification of (hard or pseudo) register n. */
151 static rtx *reg_last_set;
153 /* Record the cuid of the last insn that invalidated memory
154 (anything that writes memory, and subroutine calls, but not pushes). */
156 static int mem_last_set;
158 /* Record the cuid of the last CALL_INSN
159 so we can tell whether a potential combination crosses any calls. */
161 static int last_call_cuid;
163 /* When `subst' is called, this is the insn that is being modified
164 (by combining in a previous insn). The PATTERN of this insn
165 is still the old pattern partially modified and it should not be
166 looked at, but this may be used to examine the successors of the insn
167 to judge whether a simplification is valid. */
169 static rtx subst_insn;
171 /* This is an insn that belongs before subst_insn, but is not currently
172 on the insn chain. */
174 static rtx subst_prev_insn;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn;
196 /* Basic block number of the block in which we are performing combines. */
197 static int this_basic_block;
199 /* The next group of arrays allows the recording of the last value assigned
200 to (hard or pseudo) register n. We use this information to see if a
201 operation being processed is redundant given a prior operation performed
202 on the register. For example, an `and' with a constant is redundant if
203 all the zero bits are already known to be turned off.
205 We use an approach similar to that used by cse, but change it in the
208 (1) We do not want to reinitialize at each label.
209 (2) It is useful, but not critical, to know the actual value assigned
210 to a register. Often just its form is helpful.
212 Therefore, we maintain the following arrays:
214 reg_last_set_value the last value assigned
215 reg_last_set_label records the value of label_tick when the
216 register was assigned
217 reg_last_set_table_tick records the value of label_tick when a
218 value using the register is assigned
219 reg_last_set_invalid set to non-zero when it is not valid
220 to use the value of this register in some
223 To understand the usage of these tables, it is important to understand
224 the distinction between the value in reg_last_set_value being valid
225 and the register being validly contained in some other expression in the
228 Entry I in reg_last_set_value is valid if it is non-zero, and either
229 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
231 Register I may validly appear in any expression returned for the value
232 of another register if reg_n_sets[i] is 1. It may also appear in the
233 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
234 reg_last_set_invalid[j] is zero.
236 If an expression is found in the table containing a register which may
237 not validly appear in an expression, the register is replaced by
238 something that won't match, (clobber (const_int 0)).
240 reg_last_set_invalid[i] is set non-zero when register I is being assigned
241 to and reg_last_set_table_tick[i] == label_tick. */
243 /* Record last value assigned to (hard or pseudo) register n. */
245 static rtx *reg_last_set_value;
247 /* Record the value of label_tick when the value for register n is placed in
248 reg_last_set_value[n]. */
250 static int *reg_last_set_label;
252 /* Record the value of label_tick when an expression involving register n
253 is placed in reg_last_set_value. */
255 static int *reg_last_set_table_tick;
257 /* Set non-zero if references to register n in expressions should not be
260 static char *reg_last_set_invalid;
262 /* Incremented for each label. */
264 static int label_tick;
266 /* Some registers that are set more than once and used in more than one
267 basic block are nevertheless always set in similar ways. For example,
268 a QImode register may be loaded from memory in two places on a machine
269 where byte loads zero extend.
271 We record in the following array what we know about the nonzero
272 bits of a register, specifically which bits are known to be zero.
274 If an entry is zero, it means that we don't know anything special. */
276 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
278 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
279 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
281 static enum machine_mode nonzero_bits_mode;
283 /* Nonzero if we know that a register has some leading bits that are always
284 equal to the sign bit. */
286 static char *reg_sign_bit_copies;
288 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
289 It is zero while computing them and after combine has completed. This
290 former test prevents propagating values based on previously set values,
291 which can be incorrect if a variable is modified in a loop. */
293 static int nonzero_sign_valid;
295 /* These arrays are maintained in parallel with reg_last_set_value
296 and are used to store the mode in which the register was last set,
297 the bits that were known to be zero when it was last set, and the
298 number of sign bits copies it was known to have when it was last set. */
300 static enum machine_mode *reg_last_set_mode;
301 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
302 static char *reg_last_set_sign_bit_copies;
304 /* Record one modification to rtl structure
305 to be undone by storing old_contents into *where.
306 is_int is 1 if the contents are an int. */
312 union {rtx r; int i;} old_contents;
313 union {rtx *r; int *i;} where;
316 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
317 num_undo says how many are currently recorded.
319 storage is nonzero if we must undo the allocation of new storage.
320 The value of storage is what to pass to obfree.
322 other_insn is nonzero if we have modified some other insn in the process
323 of working on subst_insn. It must be verified too.
325 previous_undos is the value of undobuf.undos when we started processing
326 this substitution. This will prevent gen_rtx_combine from re-used a piece
327 from the previous expression. Doing so can produce circular rtl
335 struct undo *previous_undos;
339 static struct undobuf undobuf;
341 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
342 insn. The substitution can be undone by undo_all. If INTO is already
343 set to NEWVAL, do not record this change. Because computing NEWVAL might
344 also call SUBST, we have to compute it before we put anything into
347 #define SUBST(INTO, NEWVAL) \
348 do { rtx _new = (NEWVAL); \
352 _buf = undobuf.frees, undobuf.frees = _buf->next; \
354 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
357 _buf->where.r = &INTO; \
358 _buf->old_contents.r = INTO; \
360 if (_buf->old_contents.r == INTO) \
361 _buf->next = undobuf.frees, undobuf.frees = _buf; \
363 _buf->next = undobuf.undos, undobuf.undos = _buf; \
366 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
367 for the value of a HOST_WIDE_INT value (including CONST_INT) is
370 #define SUBST_INT(INTO, NEWVAL) \
371 do { struct undo *_buf; \
374 _buf = undobuf.frees, undobuf.frees = _buf->next; \
376 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
379 _buf->where.i = (int *) &INTO; \
380 _buf->old_contents.i = INTO; \
382 if (_buf->old_contents.i == INTO) \
383 _buf->next = undobuf.frees, undobuf.frees = _buf; \
385 _buf->next = undobuf.undos, undobuf.undos = _buf; \
388 /* Number of times the pseudo being substituted for
389 was found and replaced. */
391 static int n_occurrences;
393 static void init_reg_last_arrays PROTO((void));
394 static void setup_incoming_promotions PROTO((void));
395 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
396 static int cant_combine_insn_p PROTO((rtx));
397 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
398 static int sets_function_arg_p PROTO((rtx));
399 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
400 static rtx try_combine PROTO((rtx, rtx, rtx));
401 static void undo_all PROTO((void));
402 static rtx *find_split_point PROTO((rtx *, rtx));
403 static rtx subst PROTO((rtx, rtx, rtx, int, int));
404 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
405 static rtx simplify_if_then_else PROTO((rtx));
406 static rtx simplify_set PROTO((rtx));
407 static rtx simplify_logical PROTO((rtx, int));
408 static rtx expand_compound_operation PROTO((rtx));
409 static rtx expand_field_assignment PROTO((rtx));
410 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
412 static rtx extract_left_shift PROTO((rtx, int));
413 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
414 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
415 static rtx force_to_mode PROTO((rtx, enum machine_mode,
416 unsigned HOST_WIDE_INT, rtx, int));
417 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
418 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
419 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
420 static rtx make_field_assignment PROTO((rtx));
421 static rtx apply_distributive_law PROTO((rtx));
422 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
423 unsigned HOST_WIDE_INT));
424 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
425 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
426 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
427 enum rtx_code, HOST_WIDE_INT,
428 enum machine_mode, int *));
429 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
431 static int recog_for_combine PROTO((rtx *, rtx, rtx *));
432 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
433 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
435 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
437 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
438 enum machine_mode, rtx));
439 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
440 static int reversible_comparison_p PROTO((rtx));
441 static void update_table_tick PROTO((rtx));
442 static void record_value_for_reg PROTO((rtx, rtx, rtx));
443 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
444 static void record_dead_and_set_regs PROTO((rtx));
445 static int get_last_value_validate PROTO((rtx *, rtx, int, int));
446 static rtx get_last_value PROTO((rtx));
447 static int use_crosses_set_p PROTO((rtx, int));
448 static void reg_dead_at_p_1 PROTO((rtx, rtx));
449 static int reg_dead_at_p PROTO((rtx, rtx));
450 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
451 static int reg_bitfield_target_p PROTO((rtx, rtx));
452 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
453 static void distribute_links PROTO((rtx));
454 static void mark_used_regs_combine PROTO((rtx));
455 static int insn_cuid PROTO((rtx));
457 /* Main entry point for combiner. F is the first insn of the function.
458 NREGS is the first unused pseudo-reg number. */
461 combine_instructions (f, nregs)
465 register rtx insn, next;
470 register rtx links, nextlinks;
472 combine_attempts = 0;
475 combine_successes = 0;
476 undobuf.undos = undobuf.previous_undos = 0;
478 combine_max_regno = nregs;
481 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
482 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
484 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
485 bzero (reg_sign_bit_copies, nregs * sizeof (char));
487 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
489 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
490 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
491 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
492 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
494 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
495 reg_last_set_nonzero_bits
496 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
497 reg_last_set_sign_bit_copies
498 = (char *) alloca (nregs * sizeof (char));
500 init_reg_last_arrays ();
502 init_recog_no_volatile ();
504 /* Compute maximum uid value so uid_cuid can be allocated. */
506 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
507 if (INSN_UID (insn) > i)
510 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
513 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
515 /* Don't use reg_nonzero_bits when computing it. This can cause problems
516 when, for example, we have j <<= 1 in a loop. */
518 nonzero_sign_valid = 0;
520 /* Compute the mapping from uids to cuids.
521 Cuids are numbers assigned to insns, like uids,
522 except that cuids increase monotonically through the code.
524 Scan all SETs and see if we can deduce anything about what
525 bits are known to be zero for some registers and how many copies
526 of the sign bit are known to exist for those registers.
528 Also set any known values so that we can use it while searching
529 for what bits are known to be set. */
533 /* We need to initialize it here, because record_dead_and_set_regs may call
535 subst_prev_insn = NULL_RTX;
537 setup_incoming_promotions ();
539 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
541 uid_cuid[INSN_UID (insn)] = ++i;
545 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
547 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
548 record_dead_and_set_regs (insn);
551 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
552 if (REG_NOTE_KIND (links) == REG_INC)
553 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
557 if (GET_CODE (insn) == CODE_LABEL)
561 nonzero_sign_valid = 1;
563 /* Now scan all the insns in forward order. */
565 this_basic_block = -1;
569 init_reg_last_arrays ();
570 setup_incoming_promotions ();
572 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
576 /* If INSN starts a new basic block, update our basic block number. */
577 if (this_basic_block + 1 < n_basic_blocks
578 && BLOCK_HEAD (this_basic_block + 1) == insn)
581 if (GET_CODE (insn) == CODE_LABEL)
584 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
586 /* Try this insn with each insn it links back to. */
588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
589 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
592 /* Try each sequence of three linked insns ending with this one. */
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
595 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
596 nextlinks = XEXP (nextlinks, 1))
597 if ((next = try_combine (insn, XEXP (links, 0),
598 XEXP (nextlinks, 0))) != 0)
602 /* Try to combine a jump insn that uses CC0
603 with a preceding insn that sets CC0, and maybe with its
604 logical predecessor as well.
605 This is how we make decrement-and-branch insns.
606 We need this special code because data flow connections
607 via CC0 do not get entered in LOG_LINKS. */
609 if (GET_CODE (insn) == JUMP_INSN
610 && (prev = prev_nonnote_insn (insn)) != 0
611 && GET_CODE (prev) == INSN
612 && sets_cc0_p (PATTERN (prev)))
614 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
617 for (nextlinks = LOG_LINKS (prev); nextlinks;
618 nextlinks = XEXP (nextlinks, 1))
619 if ((next = try_combine (insn, prev,
620 XEXP (nextlinks, 0))) != 0)
624 /* Do the same for an insn that explicitly references CC0. */
625 if (GET_CODE (insn) == INSN
626 && (prev = prev_nonnote_insn (insn)) != 0
627 && GET_CODE (prev) == INSN
628 && sets_cc0_p (PATTERN (prev))
629 && GET_CODE (PATTERN (insn)) == SET
630 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
632 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
635 for (nextlinks = LOG_LINKS (prev); nextlinks;
636 nextlinks = XEXP (nextlinks, 1))
637 if ((next = try_combine (insn, prev,
638 XEXP (nextlinks, 0))) != 0)
642 /* Finally, see if any of the insns that this insn links to
643 explicitly references CC0. If so, try this insn, that insn,
644 and its predecessor if it sets CC0. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 if (GET_CODE (XEXP (links, 0)) == INSN
647 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
648 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
649 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
650 && GET_CODE (prev) == INSN
651 && sets_cc0_p (PATTERN (prev))
652 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
656 /* Try combining an insn with two different insns whose results it
658 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
659 for (nextlinks = XEXP (links, 1); nextlinks;
660 nextlinks = XEXP (nextlinks, 1))
661 if ((next = try_combine (insn, XEXP (links, 0),
662 XEXP (nextlinks, 0))) != 0)
665 if (GET_CODE (insn) != NOTE)
666 record_dead_and_set_regs (insn);
673 total_attempts += combine_attempts;
674 total_merges += combine_merges;
675 total_extras += combine_extras;
676 total_successes += combine_successes;
678 nonzero_sign_valid = 0;
680 /* Make recognizer allow volatile MEMs again. */
684 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
687 init_reg_last_arrays ()
689 int nregs = combine_max_regno;
691 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
692 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
693 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
694 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
695 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
696 bzero (reg_last_set_invalid, nregs * sizeof (char));
697 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
698 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
699 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
702 /* Set up any promoted values for incoming argument registers. */
705 setup_incoming_promotions ()
707 #ifdef PROMOTE_FUNCTION_ARGS
710 enum machine_mode mode;
712 rtx first = get_insns ();
714 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
715 if (FUNCTION_ARG_REGNO_P (regno)
716 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
719 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
722 gen_rtx_CLOBBER (mode, const0_rtx)));
727 /* Called via note_stores. If X is a pseudo that is narrower than
728 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
730 If we are setting only a portion of X and we can't figure out what
731 portion, assume all bits will be used since we don't know what will
734 Similarly, set how many bits of X are known to be copies of the sign bit
735 at all locations in the function. This is the smallest number implied
739 set_nonzero_bits_and_sign_copies (x, set)
745 if (GET_CODE (x) == REG
746 && REGNO (x) >= FIRST_PSEUDO_REGISTER
747 /* If this register is undefined at the start of the file, we can't
748 say what its contents were. */
749 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
750 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
752 if (set == 0 || GET_CODE (set) == CLOBBER)
754 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
755 reg_sign_bit_copies[REGNO (x)] = 1;
759 /* If this is a complex assignment, see if we can convert it into a
760 simple assignment. */
761 set = expand_field_assignment (set);
763 /* If this is a simple assignment, or we have a paradoxical SUBREG,
764 set what we know about X. */
766 if (SET_DEST (set) == x
767 || (GET_CODE (SET_DEST (set)) == SUBREG
768 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
769 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
770 && SUBREG_REG (SET_DEST (set)) == x))
772 rtx src = SET_SRC (set);
774 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
775 /* If X is narrower than a word and SRC is a non-negative
776 constant that would appear negative in the mode of X,
777 sign-extend it for use in reg_nonzero_bits because some
778 machines (maybe most) will actually do the sign-extension
779 and this is the conservative approach.
781 ??? For 2.5, try to tighten up the MD files in this regard
782 instead of this kludge. */
784 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
785 && GET_CODE (src) == CONST_INT
787 && 0 != (INTVAL (src)
789 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
790 src = GEN_INT (INTVAL (src)
791 | ((HOST_WIDE_INT) (-1)
792 << GET_MODE_BITSIZE (GET_MODE (x))));
795 reg_nonzero_bits[REGNO (x)]
796 |= nonzero_bits (src, nonzero_bits_mode);
797 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
798 if (reg_sign_bit_copies[REGNO (x)] == 0
799 || reg_sign_bit_copies[REGNO (x)] > num)
800 reg_sign_bit_copies[REGNO (x)] = num;
804 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
805 reg_sign_bit_copies[REGNO (x)] = 1;
810 /* See if INSN can be combined into I3. PRED and SUCC are optionally
811 insns that were previously combined into I3 or that will be combined
812 into the merger of INSN and I3.
814 Return 0 if the combination is not allowed for any reason.
816 If the combination is allowed, *PDEST will be set to the single
817 destination of INSN and *PSRC to the single source, and this function
821 can_combine_p (insn, i3, pred, succ, pdest, psrc)
824 rtx pred ATTRIBUTE_UNUSED;
829 rtx set = 0, src, dest;
834 int all_adjacent = (succ ? (next_active_insn (insn) == succ
835 && next_active_insn (succ) == i3)
836 : next_active_insn (insn) == i3);
838 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
839 or a PARALLEL consisting of such a SET and CLOBBERs.
841 If INSN has CLOBBER parallel parts, ignore them for our processing.
842 By definition, these happen during the execution of the insn. When it
843 is merged with another insn, all bets are off. If they are, in fact,
844 needed and aren't also supplied in I3, they may be added by
845 recog_for_combine. Otherwise, it won't match.
847 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
850 Get the source and destination of INSN. If more than one, can't
853 if (GET_CODE (PATTERN (insn)) == SET)
854 set = PATTERN (insn);
855 else if (GET_CODE (PATTERN (insn)) == PARALLEL
856 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
858 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
860 rtx elt = XVECEXP (PATTERN (insn), 0, i);
862 switch (GET_CODE (elt))
864 /* This is important to combine floating point insns
867 /* Combining an isolated USE doesn't make sense.
868 We depend here on combinable_i3_pat to reject them. */
869 /* The code below this loop only verifies that the inputs of
870 the SET in INSN do not change. We call reg_set_between_p
871 to verify that the REG in the USE does not change betweeen
873 If the USE in INSN was for a pseudo register, the matching
874 insn pattern will likely match any register; combining this
875 with any other USE would only be safe if we knew that the
876 used registers have identical values, or if there was
877 something to tell them apart, e.g. different modes. For
878 now, we forgo such compilcated tests and simply disallow
879 combining of USES of pseudo registers with any other USE. */
880 if (GET_CODE (XEXP (elt, 0)) == REG
881 && GET_CODE (PATTERN (i3)) == PARALLEL)
883 rtx i3pat = PATTERN (i3);
884 int i = XVECLEN (i3pat, 0) - 1;
885 int regno = REGNO (XEXP (elt, 0));
888 rtx i3elt = XVECEXP (i3pat, 0, i);
889 if (GET_CODE (i3elt) == USE
890 && GET_CODE (XEXP (i3elt, 0)) == REG
891 && (REGNO (XEXP (i3elt, 0)) == regno
892 ? reg_set_between_p (XEXP (elt, 0),
893 PREV_INSN (insn), i3)
894 : regno >= FIRST_PSEUDO_REGISTER))
901 /* We can ignore CLOBBERs. */
906 /* Ignore SETs whose result isn't used but not those that
907 have side-effects. */
908 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
909 && ! side_effects_p (elt))
912 /* If we have already found a SET, this is a second one and
913 so we cannot combine with this insn. */
921 /* Anything else means we can't combine. */
927 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
928 so don't do anything with it. */
929 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
938 set = expand_field_assignment (set);
939 src = SET_SRC (set), dest = SET_DEST (set);
941 /* Don't eliminate a store in the stack pointer. */
942 if (dest == stack_pointer_rtx
943 /* If we couldn't eliminate a field assignment, we can't combine. */
944 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
945 /* Don't combine with an insn that sets a register to itself if it has
946 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
947 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
948 /* Can't merge a function call. */
949 || GET_CODE (src) == CALL
950 /* Don't eliminate a function call argument. */
951 || (GET_CODE (i3) == CALL_INSN
952 && (find_reg_fusage (i3, USE, dest)
953 || (GET_CODE (dest) == REG
954 && REGNO (dest) < FIRST_PSEUDO_REGISTER
955 && global_regs[REGNO (dest)])))
956 /* Don't substitute into an incremented register. */
957 || FIND_REG_INC_NOTE (i3, dest)
958 || (succ && FIND_REG_INC_NOTE (succ, dest))
960 /* Don't combine the end of a libcall into anything. */
961 /* ??? This gives worse code, and appears to be unnecessary, since no
962 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
963 use REG_RETVAL notes for noconflict blocks, but other code here
964 makes sure that those insns don't disappear. */
965 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
967 /* Make sure that DEST is not used after SUCC but before I3. */
968 || (succ && ! all_adjacent
969 && reg_used_between_p (dest, succ, i3))
970 /* Make sure that the value that is to be substituted for the register
971 does not use any registers whose values alter in between. However,
972 If the insns are adjacent, a use can't cross a set even though we
973 think it might (this can happen for a sequence of insns each setting
974 the same destination; reg_last_set of that register might point to
975 a NOTE). If INSN has a REG_EQUIV note, the register is always
976 equivalent to the memory so the substitution is valid even if there
977 are intervening stores. Also, don't move a volatile asm or
978 UNSPEC_VOLATILE across any other insns. */
980 && (((GET_CODE (src) != MEM
981 || ! find_reg_note (insn, REG_EQUIV, src))
982 && use_crosses_set_p (src, INSN_CUID (insn)))
983 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
984 || GET_CODE (src) == UNSPEC_VOLATILE))
985 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
986 better register allocation by not doing the combine. */
987 || find_reg_note (i3, REG_NO_CONFLICT, dest)
988 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
989 /* Don't combine across a CALL_INSN, because that would possibly
990 change whether the life span of some REGs crosses calls or not,
991 and it is a pain to update that information.
992 Exception: if source is a constant, moving it later can't hurt.
993 Accept that special case, because it helps -fforce-addr a lot. */
994 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
997 /* DEST must either be a REG or CC0. */
998 if (GET_CODE (dest) == REG)
1000 /* If register alignment is being enforced for multi-word items in all
1001 cases except for parameters, it is possible to have a register copy
1002 insn referencing a hard register that is not allowed to contain the
1003 mode being copied and which would not be valid as an operand of most
1004 insns. Eliminate this problem by not combining with such an insn.
1006 Also, on some machines we don't want to extend the life of a hard
1009 This is the same test done in can_combine except that we don't test
1010 if SRC is a CALL operation to permit a hard register with
1011 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1014 if (GET_CODE (src) == REG
1015 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1016 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1017 /* Don't extend the life of a hard register unless it is
1018 user variable (if we have few registers) or it can't
1019 fit into the desired register (meaning something special
1021 Also avoid substituting a return register into I3, because
1022 reload can't handle a conflict with constraints of other
1024 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1025 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1026 || (SMALL_REGISTER_CLASSES
1027 && ((! all_adjacent && ! REG_USERVAR_P (src))
1028 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1029 && ! REG_USERVAR_P (src))))))))
1032 else if (GET_CODE (dest) != CC0)
1035 /* Don't substitute for a register intended as a clobberable operand.
1036 Similarly, don't substitute an expression containing a register that
1037 will be clobbered in I3. */
1038 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1039 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1040 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1041 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1043 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1046 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1047 or not), reject, unless nothing volatile comes between it and I3 */
1049 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1051 /* Make sure succ doesn't contain a volatile reference. */
1052 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1055 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1056 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1057 && p != succ && volatile_refs_p (PATTERN (p)))
1061 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1062 to be an explicit register variable, and was chosen for a reason. */
1064 if (GET_CODE (src) == ASM_OPERANDS
1065 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1068 /* If there are any volatile insns between INSN and I3, reject, because
1069 they might affect machine state. */
1071 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1072 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1073 && p != succ && volatile_insn_p (PATTERN (p)))
1076 /* If INSN or I2 contains an autoincrement or autodecrement,
1077 make sure that register is not used between there and I3,
1078 and not already used in I3 either.
1079 Also insist that I3 not be a jump; if it were one
1080 and the incremented register were spilled, we would lose. */
1083 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1084 if (REG_NOTE_KIND (link) == REG_INC
1085 && (GET_CODE (i3) == JUMP_INSN
1086 || reg_used_between_p (XEXP (link, 0), insn, i3)
1087 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1092 /* Don't combine an insn that follows a CC0-setting insn.
1093 An insn that uses CC0 must not be separated from the one that sets it.
1094 We do, however, allow I2 to follow a CC0-setting insn if that insn
1095 is passed as I1; in that case it will be deleted also.
1096 We also allow combining in this case if all the insns are adjacent
1097 because that would leave the two CC0 insns adjacent as well.
1098 It would be more logical to test whether CC0 occurs inside I1 or I2,
1099 but that would be much slower, and this ought to be equivalent. */
1101 p = prev_nonnote_insn (insn);
1102 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1107 /* If we get here, we have passed all the tests and the combination is
1116 /* Check if PAT is an insn - or a part of it - used to set up an
1117 argument for a function in a hard register. */
1120 sets_function_arg_p (pat)
1126 switch (GET_CODE (pat))
1129 return sets_function_arg_p (PATTERN (pat));
1132 for (i = XVECLEN (pat, 0); --i >= 0;)
1133 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1139 inner_dest = SET_DEST (pat);
1140 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1141 || GET_CODE (inner_dest) == SUBREG
1142 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1143 inner_dest = XEXP (inner_dest, 0);
1145 return (GET_CODE (inner_dest) == REG
1146 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1147 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1156 /* LOC is the location within I3 that contains its pattern or the component
1157 of a PARALLEL of the pattern. We validate that it is valid for combining.
1159 One problem is if I3 modifies its output, as opposed to replacing it
1160 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1161 so would produce an insn that is not equivalent to the original insns.
1165 (set (reg:DI 101) (reg:DI 100))
1166 (set (subreg:SI (reg:DI 101) 0) <foo>)
1168 This is NOT equivalent to:
1170 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1171 (set (reg:DI 101) (reg:DI 100))])
1173 Not only does this modify 100 (in which case it might still be valid
1174 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1176 We can also run into a problem if I2 sets a register that I1
1177 uses and I1 gets directly substituted into I3 (not via I2). In that
1178 case, we would be getting the wrong value of I2DEST into I3, so we
1179 must reject the combination. This case occurs when I2 and I1 both
1180 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1181 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1182 of a SET must prevent combination from occurring.
1184 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1185 if the destination of a SET is a hard register that isn't a user
1188 Before doing the above check, we first try to expand a field assignment
1189 into a set of logical operations.
1191 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1192 we place a register that is both set and used within I3. If more than one
1193 such register is detected, we fail.
1195 Return 1 if the combination is valid, zero otherwise. */
1198 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1204 rtx *pi3dest_killed;
1208 if (GET_CODE (x) == SET)
1210 rtx set = expand_field_assignment (x);
1211 rtx dest = SET_DEST (set);
1212 rtx src = SET_SRC (set);
1213 rtx inner_dest = dest;
1216 rtx inner_src = src;
1221 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1222 || GET_CODE (inner_dest) == SUBREG
1223 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1224 inner_dest = XEXP (inner_dest, 0);
1226 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1229 while (GET_CODE (inner_src) == STRICT_LOW_PART
1230 || GET_CODE (inner_src) == SUBREG
1231 || GET_CODE (inner_src) == ZERO_EXTRACT)
1232 inner_src = XEXP (inner_src, 0);
1234 /* If it is better that two different modes keep two different pseudos,
1235 avoid combining them. This avoids producing the following pattern
1237 (set (subreg:SI (reg/v:QI 21) 0)
1238 (lshiftrt:SI (reg/v:SI 20)
1240 If that were made, reload could not handle the pair of
1241 reg 20/21, since it would try to get any GENERAL_REGS
1242 but some of them don't handle QImode. */
1244 if (rtx_equal_p (inner_src, i2dest)
1245 && GET_CODE (inner_dest) == REG
1246 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1250 /* Check for the case where I3 modifies its output, as
1252 if ((inner_dest != dest
1253 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1254 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1256 /* This is the same test done in can_combine_p except that we
1257 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1258 CALL operation. Moreover, we can't test all_adjacent; we don't
1259 have to, since this instruction will stay in place, thus we are
1260 not considering increasing the lifetime of INNER_DEST.
1262 Also, if this insn sets a function argument, combining it with
1263 something that might need a spill could clobber a previous
1264 function argument; the all_adjacent test in can_combine_p also
1265 checks this; here, we do a more specific test for this case. */
1267 || (GET_CODE (inner_dest) == REG
1268 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1269 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1270 GET_MODE (inner_dest))
1271 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1272 && ! REG_USERVAR_P (inner_dest)
1273 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1274 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1276 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1277 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1280 /* If DEST is used in I3, it is being killed in this insn,
1281 so record that for later.
1282 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1283 STACK_POINTER_REGNUM, since these are always considered to be
1284 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1285 if (pi3dest_killed && GET_CODE (dest) == REG
1286 && reg_referenced_p (dest, PATTERN (i3))
1287 && REGNO (dest) != FRAME_POINTER_REGNUM
1288 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1289 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1291 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1292 && (REGNO (dest) != ARG_POINTER_REGNUM
1293 || ! fixed_regs [REGNO (dest)])
1295 && REGNO (dest) != STACK_POINTER_REGNUM)
1297 if (*pi3dest_killed)
1300 *pi3dest_killed = dest;
1304 else if (GET_CODE (x) == PARALLEL)
1308 for (i = 0; i < XVECLEN (x, 0); i++)
1309 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1310 i1_not_in_src, pi3dest_killed))
1317 /* Determine whether INSN can be used in a combination. Return nonzero if
1318 not. This is used in try_combine to detect early some cases where we
1319 can't perform combinations. */
1322 cant_combine_insn_p (insn)
1328 /* If this isn't really an insn, we can't do anything.
1329 This can occur when flow deletes an insn that it has merged into an
1330 auto-increment address. */
1331 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
1334 /* For the 2.95.3 release, restrict this code to only handle the machines
1335 where it's strictly needed. */
1336 if (! SMALL_REGISTER_CLASSES)
1339 /* Never combine loads and stores involving hard regs. The register
1340 allocator can usually handle such reg-reg moves by tying. If we allow
1341 the combiner to make substitutions of hard regs, we risk aborting in
1342 reload on machines that have SMALL_REGISTER_CLASSES.
1343 As an exception, we allow combinations involving fixed regs; these are
1344 not available to the register allocator so there's no risk involved. */
1346 set = single_set (insn);
1349 src = SET_SRC (set);
1350 dest = SET_DEST (set);
1351 if (GET_CODE (src) == SUBREG)
1352 src = SUBREG_REG (src);
1353 if (GET_CODE (dest) == SUBREG)
1354 dest = SUBREG_REG (dest);
1355 if (REG_P (src) && REG_P (dest)
1356 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1357 && ! fixed_regs[REGNO (src)])
1358 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1359 && ! fixed_regs[REGNO (dest)])))
1365 /* Try to combine the insns I1 and I2 into I3.
1366 Here I1 and I2 appear earlier than I3.
1367 I1 can be zero; then we combine just I2 into I3.
1369 It we are combining three insns and the resulting insn is not recognized,
1370 try splitting it into two insns. If that happens, I2 and I3 are retained
1371 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1374 Return 0 if the combination does not work. Then nothing is changed.
1375 If we did the combination, return the insn at which combine should
1379 try_combine (i3, i2, i1)
1380 register rtx i3, i2, i1;
1382 /* New patterns for I3 and I3, respectively. */
1383 rtx newpat, newi2pat = 0;
1384 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1385 int added_sets_1, added_sets_2;
1386 /* Total number of SETs to put into I3. */
1388 /* Nonzero is I2's body now appears in I3. */
1390 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1391 int insn_code_number, i2_code_number, other_code_number;
1392 /* Contains I3 if the destination of I3 is used in its source, which means
1393 that the old life of I3 is being killed. If that usage is placed into
1394 I2 and not in I3, a REG_DEAD note must be made. */
1395 rtx i3dest_killed = 0;
1396 /* SET_DEST and SET_SRC of I2 and I1. */
1397 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1398 /* PATTERN (I2), or a copy of it in certain cases. */
1400 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1401 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1402 int i1_feeds_i3 = 0;
1403 /* Notes that must be added to REG_NOTES in I3 and I2. */
1404 rtx new_i3_notes, new_i2_notes;
1405 /* Notes that we substituted I3 into I2 instead of the normal case. */
1406 int i3_subst_into_i2 = 0;
1407 /* Notes that I1, I2 or I3 is a MULT operation. */
1415 /* Exit early if one of the insns involved can't be used for
1417 if (cant_combine_insn_p (i3)
1418 || cant_combine_insn_p (i2)
1419 || (i1 && cant_combine_insn_p (i1))
1420 /* We also can't do anything if I3 has a
1421 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1424 /* ??? This gives worse code, and appears to be unnecessary, since no
1425 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1426 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1433 undobuf.undos = undobuf.previous_undos = 0;
1434 undobuf.other_insn = 0;
1436 /* Save the current high-water-mark so we can free storage if we didn't
1437 accept this combination. */
1438 undobuf.storage = (char *) oballoc (0);
1440 /* Reset the hard register usage information. */
1441 CLEAR_HARD_REG_SET (newpat_used_regs);
1443 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1444 code below, set I1 to be the earlier of the two insns. */
1445 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1446 temp = i1, i1 = i2, i2 = temp;
1448 added_links_insn = 0;
1450 /* First check for one important special-case that the code below will
1451 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1452 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1453 we may be able to replace that destination with the destination of I3.
1454 This occurs in the common code where we compute both a quotient and
1455 remainder into a structure, in which case we want to do the computation
1456 directly into the structure to avoid register-register copies.
1458 We make very conservative checks below and only try to handle the
1459 most common cases of this. For example, we only handle the case
1460 where I2 and I3 are adjacent to avoid making difficult register
1463 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1464 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1465 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1466 && (! SMALL_REGISTER_CLASSES
1467 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1468 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1469 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1470 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1471 && GET_CODE (PATTERN (i2)) == PARALLEL
1472 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1473 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1474 below would need to check what is inside (and reg_overlap_mentioned_p
1475 doesn't support those codes anyway). Don't allow those destinations;
1476 the resulting insn isn't likely to be recognized anyway. */
1477 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1478 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1479 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1480 SET_DEST (PATTERN (i3)))
1481 && next_real_insn (i2) == i3)
1483 rtx p2 = PATTERN (i2);
1485 /* Make sure that the destination of I3,
1486 which we are going to substitute into one output of I2,
1487 is not used within another output of I2. We must avoid making this:
1488 (parallel [(set (mem (reg 69)) ...)
1489 (set (reg 69) ...)])
1490 which is not well-defined as to order of actions.
1491 (Besides, reload can't handle output reloads for this.)
1493 The problem can also happen if the dest of I3 is a memory ref,
1494 if another dest in I2 is an indirect memory ref. */
1495 for (i = 0; i < XVECLEN (p2, 0); i++)
1496 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1497 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1498 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1499 SET_DEST (XVECEXP (p2, 0, i))))
1502 if (i == XVECLEN (p2, 0))
1503 for (i = 0; i < XVECLEN (p2, 0); i++)
1504 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1509 subst_low_cuid = INSN_CUID (i2);
1511 added_sets_2 = added_sets_1 = 0;
1512 i2dest = SET_SRC (PATTERN (i3));
1514 /* Replace the dest in I2 with our dest and make the resulting
1515 insn the new pattern for I3. Then skip to where we
1516 validate the pattern. Everything was set up above. */
1517 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1518 SET_DEST (PATTERN (i3)));
1521 i3_subst_into_i2 = 1;
1522 goto validate_replacement;
1527 /* If we have no I1 and I2 looks like:
1528 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1530 make up a dummy I1 that is
1533 (set (reg:CC X) (compare:CC Y (const_int 0)))
1535 (We can ignore any trailing CLOBBERs.)
1537 This undoes a previous combination and allows us to match a branch-and-
1540 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1541 && XVECLEN (PATTERN (i2), 0) >= 2
1542 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1543 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1545 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1546 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1547 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1548 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1549 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1550 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1552 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1553 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1558 /* We make I1 with the same INSN_UID as I2. This gives it
1559 the same INSN_CUID for value tracking. Our fake I1 will
1560 never appear in the insn stream so giving it the same INSN_UID
1561 as I2 will not cause a problem. */
1563 subst_prev_insn = i1
1564 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1565 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1568 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1569 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1570 SET_DEST (PATTERN (i1)));
1575 /* Verify that I2 and I1 are valid for combining. */
1576 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1577 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1583 /* Record whether I2DEST is used in I2SRC and similarly for the other
1584 cases. Knowing this will help in register status updating below. */
1585 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1586 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1587 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1589 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1591 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1593 /* Ensure that I3's pattern can be the destination of combines. */
1594 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1595 i1 && i2dest_in_i1src && i1_feeds_i3,
1602 /* See if any of the insns is a MULT operation. Unless one is, we will
1603 reject a combination that is, since it must be slower. Be conservative
1605 if (GET_CODE (i2src) == MULT
1606 || (i1 != 0 && GET_CODE (i1src) == MULT)
1607 || (GET_CODE (PATTERN (i3)) == SET
1608 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1611 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1612 We used to do this EXCEPT in one case: I3 has a post-inc in an
1613 output operand. However, that exception can give rise to insns like
1615 which is a famous insn on the PDP-11 where the value of r3 used as the
1616 source was model-dependent. Avoid this sort of thing. */
1619 if (!(GET_CODE (PATTERN (i3)) == SET
1620 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1621 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1622 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1623 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1624 /* It's not the exception. */
1627 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1628 if (REG_NOTE_KIND (link) == REG_INC
1629 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1631 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1638 /* See if the SETs in I1 or I2 need to be kept around in the merged
1639 instruction: whenever the value set there is still needed past I3.
1640 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1642 For the SET in I1, we have two cases: If I1 and I2 independently
1643 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1644 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1645 in I1 needs to be kept around unless I1DEST dies or is set in either
1646 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1647 I1DEST. If so, we know I1 feeds into I2. */
1649 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1652 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1653 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1655 /* If the set in I2 needs to be kept around, we must make a copy of
1656 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1657 PATTERN (I2), we are only substituting for the original I1DEST, not into
1658 an already-substituted copy. This also prevents making self-referential
1659 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1662 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1663 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1667 i2pat = copy_rtx (i2pat);
1671 /* Substitute in the latest insn for the regs set by the earlier ones. */
1673 maxreg = max_reg_num ();
1677 /* It is possible that the source of I2 or I1 may be performing an
1678 unneeded operation, such as a ZERO_EXTEND of something that is known
1679 to have the high part zero. Handle that case by letting subst look at
1680 the innermost one of them.
1682 Another way to do this would be to have a function that tries to
1683 simplify a single insn instead of merging two or more insns. We don't
1684 do this because of the potential of infinite loops and because
1685 of the potential extra memory required. However, doing it the way
1686 we are is a bit of a kludge and doesn't catch all cases.
1688 But only do this if -fexpensive-optimizations since it slows things down
1689 and doesn't usually win. */
1691 if (flag_expensive_optimizations)
1693 /* Pass pc_rtx so no substitutions are done, just simplifications.
1694 The cases that we are interested in here do not involve the few
1695 cases were is_replaced is checked. */
1698 subst_low_cuid = INSN_CUID (i1);
1699 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1703 subst_low_cuid = INSN_CUID (i2);
1704 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1707 undobuf.previous_undos = undobuf.undos;
1711 /* Many machines that don't use CC0 have insns that can both perform an
1712 arithmetic operation and set the condition code. These operations will
1713 be represented as a PARALLEL with the first element of the vector
1714 being a COMPARE of an arithmetic operation with the constant zero.
1715 The second element of the vector will set some pseudo to the result
1716 of the same arithmetic operation. If we simplify the COMPARE, we won't
1717 match such a pattern and so will generate an extra insn. Here we test
1718 for this case, where both the comparison and the operation result are
1719 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1720 I2SRC. Later we will make the PARALLEL that contains I2. */
1722 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1723 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1724 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1725 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1727 #ifdef EXTRA_CC_MODES
1729 enum machine_mode compare_mode;
1732 newpat = PATTERN (i3);
1733 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1737 #ifdef EXTRA_CC_MODES
1738 /* See if a COMPARE with the operand we substituted in should be done
1739 with the mode that is currently being used. If not, do the same
1740 processing we do in `subst' for a SET; namely, if the destination
1741 is used only once, try to replace it with a register of the proper
1742 mode and also replace the COMPARE. */
1743 if (undobuf.other_insn == 0
1744 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1745 &undobuf.other_insn))
1746 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1748 != GET_MODE (SET_DEST (newpat))))
1750 int regno = REGNO (SET_DEST (newpat));
1751 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1753 if (regno < FIRST_PSEUDO_REGISTER
1754 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1755 && ! REG_USERVAR_P (SET_DEST (newpat))))
1757 if (regno >= FIRST_PSEUDO_REGISTER)
1758 SUBST (regno_reg_rtx[regno], new_dest);
1760 SUBST (SET_DEST (newpat), new_dest);
1761 SUBST (XEXP (*cc_use, 0), new_dest);
1762 SUBST (SET_SRC (newpat),
1763 gen_rtx_combine (COMPARE, compare_mode,
1764 i2src, const0_rtx));
1767 undobuf.other_insn = 0;
1774 n_occurrences = 0; /* `subst' counts here */
1776 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1777 need to make a unique copy of I2SRC each time we substitute it
1778 to avoid self-referential rtl. */
1780 subst_low_cuid = INSN_CUID (i2);
1781 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1782 ! i1_feeds_i3 && i1dest_in_i1src);
1783 undobuf.previous_undos = undobuf.undos;
1785 /* Record whether i2's body now appears within i3's body. */
1786 i2_is_used = n_occurrences;
1789 /* If we already got a failure, don't try to do more. Otherwise,
1790 try to substitute in I1 if we have it. */
1792 if (i1 && GET_CODE (newpat) != CLOBBER)
1794 /* Before we can do this substitution, we must redo the test done
1795 above (see detailed comments there) that ensures that I1DEST
1796 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1798 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1806 subst_low_cuid = INSN_CUID (i1);
1807 newpat = subst (newpat, i1dest, i1src, 0, 0);
1808 undobuf.previous_undos = undobuf.undos;
1811 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1812 to count all the ways that I2SRC and I1SRC can be used. */
1813 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1814 && i2_is_used + added_sets_2 > 1)
1815 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1816 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1818 /* Fail if we tried to make a new register (we used to abort, but there's
1819 really no reason to). */
1820 || max_reg_num () != maxreg
1821 /* Fail if we couldn't do something and have a CLOBBER. */
1822 || GET_CODE (newpat) == CLOBBER
1823 /* Fail if this new pattern is a MULT and we didn't have one before
1824 at the outer level. */
1825 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1832 /* If the actions of the earlier insns must be kept
1833 in addition to substituting them into the latest one,
1834 we must make a new PARALLEL for the latest insn
1835 to hold additional the SETs. */
1837 if (added_sets_1 || added_sets_2)
1841 if (GET_CODE (newpat) == PARALLEL)
1843 rtvec old = XVEC (newpat, 0);
1844 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1845 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1846 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1847 sizeof (old->elem[0]) * old->num_elem);
1852 total_sets = 1 + added_sets_1 + added_sets_2;
1853 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1854 XVECEXP (newpat, 0, 0) = old;
1858 XVECEXP (newpat, 0, --total_sets)
1859 = (GET_CODE (PATTERN (i1)) == PARALLEL
1860 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1864 /* If there is no I1, use I2's body as is. We used to also not do
1865 the subst call below if I2 was substituted into I3,
1866 but that could lose a simplification. */
1868 XVECEXP (newpat, 0, --total_sets) = i2pat;
1870 /* See comment where i2pat is assigned. */
1871 XVECEXP (newpat, 0, --total_sets)
1872 = subst (i2pat, i1dest, i1src, 0, 0);
1876 /* We come here when we are replacing a destination in I2 with the
1877 destination of I3. */
1878 validate_replacement:
1880 /* Note which hard regs this insn has as inputs. */
1881 mark_used_regs_combine (newpat);
1883 /* Is the result of combination a valid instruction? */
1884 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1886 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1887 the second SET's destination is a register that is unused. In that case,
1888 we just need the first SET. This can occur when simplifying a divmod
1889 insn. We *must* test for this case here because the code below that
1890 splits two independent SETs doesn't handle this case correctly when it
1891 updates the register status. Also check the case where the first
1892 SET's destination is unused. That would not cause incorrect code, but
1893 does cause an unneeded insn to remain. */
1895 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1896 && XVECLEN (newpat, 0) == 2
1897 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1898 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1899 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1900 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1901 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1902 && asm_noperands (newpat) < 0)
1904 newpat = XVECEXP (newpat, 0, 0);
1905 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1908 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1909 && XVECLEN (newpat, 0) == 2
1910 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1911 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1912 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1913 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1914 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1915 && asm_noperands (newpat) < 0)
1917 newpat = XVECEXP (newpat, 0, 1);
1918 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1921 /* If we were combining three insns and the result is a simple SET
1922 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1923 insns. There are two ways to do this. It can be split using a
1924 machine-specific method (like when you have an addition of a large
1925 constant) or by combine in the function find_split_point. */
1927 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1928 && asm_noperands (newpat) < 0)
1930 rtx m_split, *split;
1931 rtx ni2dest = i2dest;
1933 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1934 use I2DEST as a scratch register will help. In the latter case,
1935 convert I2DEST to the mode of the source of NEWPAT if we can. */
1937 m_split = split_insns (newpat, i3);
1939 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1940 inputs of NEWPAT. */
1942 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1943 possible to try that as a scratch reg. This would require adding
1944 more code to make it work though. */
1946 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1948 /* If I2DEST is a hard register or the only use of a pseudo,
1949 we can change its mode. */
1950 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1951 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1952 && GET_CODE (i2dest) == REG
1953 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1954 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1955 && ! REG_USERVAR_P (i2dest))))
1956 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
1959 m_split = split_insns
1960 (gen_rtx_PARALLEL (VOIDmode,
1961 gen_rtvec (2, newpat,
1962 gen_rtx_CLOBBER (VOIDmode,
1967 if (m_split && GET_CODE (m_split) == SEQUENCE
1968 && XVECLEN (m_split, 0) == 2
1969 && (next_real_insn (i2) == i3
1970 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1974 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1975 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1977 i3set = single_set (XVECEXP (m_split, 0, 1));
1978 i2set = single_set (XVECEXP (m_split, 0, 0));
1980 /* In case we changed the mode of I2DEST, replace it in the
1981 pseudo-register table here. We can't do it above in case this
1982 code doesn't get executed and we do a split the other way. */
1984 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1985 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1987 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1989 /* If I2 or I3 has multiple SETs, we won't know how to track
1990 register status, so don't use these insns. If I2's destination
1991 is used between I2 and I3, we also can't use these insns. */
1993 if (i2_code_number >= 0 && i2set && i3set
1994 && (next_real_insn (i2) == i3
1995 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1996 insn_code_number = recog_for_combine (&newi3pat, i3,
1998 if (insn_code_number >= 0)
2001 /* It is possible that both insns now set the destination of I3.
2002 If so, we must show an extra use of it. */
2004 if (insn_code_number >= 0)
2006 rtx new_i3_dest = SET_DEST (i3set);
2007 rtx new_i2_dest = SET_DEST (i2set);
2009 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2010 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2011 || GET_CODE (new_i3_dest) == SUBREG)
2012 new_i3_dest = XEXP (new_i3_dest, 0);
2014 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2015 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2016 || GET_CODE (new_i2_dest) == SUBREG)
2017 new_i2_dest = XEXP (new_i2_dest, 0);
2019 if (GET_CODE (new_i3_dest) == REG
2020 && GET_CODE (new_i2_dest) == REG
2021 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2022 REG_N_SETS (REGNO (new_i2_dest))++;
2026 /* If we can split it and use I2DEST, go ahead and see if that
2027 helps things be recognized. Verify that none of the registers
2028 are set between I2 and I3. */
2029 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2031 && GET_CODE (i2dest) == REG
2033 /* We need I2DEST in the proper mode. If it is a hard register
2034 or the only use of a pseudo, we can change its mode. */
2035 && (GET_MODE (*split) == GET_MODE (i2dest)
2036 || GET_MODE (*split) == VOIDmode
2037 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2038 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2039 && ! REG_USERVAR_P (i2dest)))
2040 && (next_real_insn (i2) == i3
2041 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2042 /* We can't overwrite I2DEST if its value is still used by
2044 && ! reg_referenced_p (i2dest, newpat))
2046 rtx newdest = i2dest;
2047 enum rtx_code split_code = GET_CODE (*split);
2048 enum machine_mode split_mode = GET_MODE (*split);
2050 /* Get NEWDEST as a register in the proper mode. We have already
2051 validated that we can do this. */
2052 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2054 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2056 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2057 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2060 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2061 an ASHIFT. This can occur if it was inside a PLUS and hence
2062 appeared to be a memory address. This is a kludge. */
2063 if (split_code == MULT
2064 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2065 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2067 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2068 XEXP (*split, 0), GEN_INT (i)));
2069 /* Update split_code because we may not have a multiply
2071 split_code = GET_CODE (*split);
2074 #ifdef INSN_SCHEDULING
2075 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2076 be written as a ZERO_EXTEND. */
2077 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2078 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2082 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2083 SUBST (*split, newdest);
2084 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2086 /* If the split point was a MULT and we didn't have one before,
2087 don't use one now. */
2088 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2089 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2093 /* Check for a case where we loaded from memory in a narrow mode and
2094 then sign extended it, but we need both registers. In that case,
2095 we have a PARALLEL with both loads from the same memory location.
2096 We can split this into a load from memory followed by a register-register
2097 copy. This saves at least one insn, more if register allocation can
2100 We cannot do this if the destination of the second assignment is
2101 a register that we have already assumed is zero-extended. Similarly
2102 for a SUBREG of such a register. */
2104 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2105 && GET_CODE (newpat) == PARALLEL
2106 && XVECLEN (newpat, 0) == 2
2107 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2108 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2109 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2110 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2111 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2112 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2114 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2115 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2116 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2117 (GET_CODE (temp) == REG
2118 && reg_nonzero_bits[REGNO (temp)] != 0
2119 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2120 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2121 && (reg_nonzero_bits[REGNO (temp)]
2122 != GET_MODE_MASK (word_mode))))
2123 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2124 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2125 (GET_CODE (temp) == REG
2126 && reg_nonzero_bits[REGNO (temp)] != 0
2127 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2128 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2129 && (reg_nonzero_bits[REGNO (temp)]
2130 != GET_MODE_MASK (word_mode)))))
2131 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2132 SET_SRC (XVECEXP (newpat, 0, 1)))
2133 && ! find_reg_note (i3, REG_UNUSED,
2134 SET_DEST (XVECEXP (newpat, 0, 0))))
2138 newi2pat = XVECEXP (newpat, 0, 0);
2139 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2140 newpat = XVECEXP (newpat, 0, 1);
2141 SUBST (SET_SRC (newpat),
2142 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2143 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2145 if (i2_code_number >= 0)
2146 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2148 if (insn_code_number >= 0)
2153 /* If we will be able to accept this, we have made a change to the
2154 destination of I3. This can invalidate a LOG_LINKS pointing
2155 to I3. No other part of combine.c makes such a transformation.
2157 The new I3 will have a destination that was previously the
2158 destination of I1 or I2 and which was used in i2 or I3. Call
2159 distribute_links to make a LOG_LINK from the next use of
2160 that destination. */
2162 PATTERN (i3) = newpat;
2163 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2165 /* I3 now uses what used to be its destination and which is
2166 now I2's destination. That means we need a LOG_LINK from
2167 I3 to I2. But we used to have one, so we still will.
2169 However, some later insn might be using I2's dest and have
2170 a LOG_LINK pointing at I3. We must remove this link.
2171 The simplest way to remove the link is to point it at I1,
2172 which we know will be a NOTE. */
2174 for (insn = NEXT_INSN (i3);
2175 insn && (this_basic_block == n_basic_blocks - 1
2176 || insn != BLOCK_HEAD (this_basic_block + 1));
2177 insn = NEXT_INSN (insn))
2179 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2180 && reg_referenced_p (ni2dest, PATTERN (insn)))
2182 for (link = LOG_LINKS (insn); link;
2183 link = XEXP (link, 1))
2184 if (XEXP (link, 0) == i3)
2185 XEXP (link, 0) = i1;
2193 /* Similarly, check for a case where we have a PARALLEL of two independent
2194 SETs but we started with three insns. In this case, we can do the sets
2195 as two separate insns. This case occurs when some SET allows two
2196 other insns to combine, but the destination of that SET is still live. */
2198 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2199 && GET_CODE (newpat) == PARALLEL
2200 && XVECLEN (newpat, 0) == 2
2201 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2202 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2203 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2204 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2205 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2206 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2207 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2209 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2210 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2211 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2212 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2213 XVECEXP (newpat, 0, 0))
2214 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2215 XVECEXP (newpat, 0, 1)))
2217 /* Normally, it doesn't matter which of the two is done first,
2218 but it does if one references cc0. In that case, it has to
2221 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2223 newi2pat = XVECEXP (newpat, 0, 0);
2224 newpat = XVECEXP (newpat, 0, 1);
2229 newi2pat = XVECEXP (newpat, 0, 1);
2230 newpat = XVECEXP (newpat, 0, 0);
2233 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2235 if (i2_code_number >= 0)
2236 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2239 /* If it still isn't recognized, fail and change things back the way they
2241 if ((insn_code_number < 0
2242 /* Is the result a reasonable ASM_OPERANDS? */
2243 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2249 /* If we had to change another insn, make sure it is valid also. */
2250 if (undobuf.other_insn)
2252 rtx other_pat = PATTERN (undobuf.other_insn);
2253 rtx new_other_notes;
2256 CLEAR_HARD_REG_SET (newpat_used_regs);
2258 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2261 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2267 PATTERN (undobuf.other_insn) = other_pat;
2269 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2270 are still valid. Then add any non-duplicate notes added by
2271 recog_for_combine. */
2272 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2274 next = XEXP (note, 1);
2276 if (REG_NOTE_KIND (note) == REG_UNUSED
2277 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2279 if (GET_CODE (XEXP (note, 0)) == REG)
2280 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2282 remove_note (undobuf.other_insn, note);
2286 for (note = new_other_notes; note; note = XEXP (note, 1))
2287 if (GET_CODE (XEXP (note, 0)) == REG)
2288 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2290 distribute_notes (new_other_notes, undobuf.other_insn,
2291 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2294 /* We now know that we can do this combination. Merge the insns and
2295 update the status of registers and LOG_LINKS. */
2298 rtx i3notes, i2notes, i1notes = 0;
2299 rtx i3links, i2links, i1links = 0;
2302 /* Compute which registers we expect to eliminate. newi2pat may be setting
2303 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2304 same as i3dest, in which case newi2pat may be setting i1dest. */
2305 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2306 || i2dest_in_i2src || i2dest_in_i1src
2308 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2309 || (newi2pat && reg_set_p (i1dest, newi2pat))
2312 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2314 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2315 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2317 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2319 /* Ensure that we do not have something that should not be shared but
2320 occurs multiple times in the new insns. Check this by first
2321 resetting all the `used' flags and then copying anything is shared. */
2323 reset_used_flags (i3notes);
2324 reset_used_flags (i2notes);
2325 reset_used_flags (i1notes);
2326 reset_used_flags (newpat);
2327 reset_used_flags (newi2pat);
2328 if (undobuf.other_insn)
2329 reset_used_flags (PATTERN (undobuf.other_insn));
2331 i3notes = copy_rtx_if_shared (i3notes);
2332 i2notes = copy_rtx_if_shared (i2notes);
2333 i1notes = copy_rtx_if_shared (i1notes);
2334 newpat = copy_rtx_if_shared (newpat);
2335 newi2pat = copy_rtx_if_shared (newi2pat);
2336 if (undobuf.other_insn)
2337 reset_used_flags (PATTERN (undobuf.other_insn));
2339 INSN_CODE (i3) = insn_code_number;
2340 PATTERN (i3) = newpat;
2341 if (undobuf.other_insn)
2342 INSN_CODE (undobuf.other_insn) = other_code_number;
2344 /* We had one special case above where I2 had more than one set and
2345 we replaced a destination of one of those sets with the destination
2346 of I3. In that case, we have to update LOG_LINKS of insns later
2347 in this basic block. Note that this (expensive) case is rare.
2349 Also, in this case, we must pretend that all REG_NOTEs for I2
2350 actually came from I3, so that REG_UNUSED notes from I2 will be
2351 properly handled. */
2353 if (i3_subst_into_i2)
2355 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2356 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2357 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2358 && ! find_reg_note (i2, REG_UNUSED,
2359 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2360 for (temp = NEXT_INSN (i2);
2361 temp && (this_basic_block == n_basic_blocks - 1
2362 || BLOCK_HEAD (this_basic_block) != temp);
2363 temp = NEXT_INSN (temp))
2364 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2365 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2366 if (XEXP (link, 0) == i2)
2367 XEXP (link, 0) = i3;
2372 while (XEXP (link, 1))
2373 link = XEXP (link, 1);
2374 XEXP (link, 1) = i2notes;
2388 INSN_CODE (i2) = i2_code_number;
2389 PATTERN (i2) = newi2pat;
2393 PUT_CODE (i2, NOTE);
2394 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2395 NOTE_SOURCE_FILE (i2) = 0;
2402 PUT_CODE (i1, NOTE);
2403 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2404 NOTE_SOURCE_FILE (i1) = 0;
2407 /* Get death notes for everything that is now used in either I3 or
2408 I2 and used to die in a previous insn. If we built two new
2409 patterns, move from I1 to I2 then I2 to I3 so that we get the
2410 proper movement on registers that I2 modifies. */
2414 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2415 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2418 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2421 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2423 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2426 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2429 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2432 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2435 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2436 know these are REG_UNUSED and want them to go to the desired insn,
2437 so we always pass it as i3. We have not counted the notes in
2438 reg_n_deaths yet, so we need to do so now. */
2440 if (newi2pat && new_i2_notes)
2442 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2443 if (GET_CODE (XEXP (temp, 0)) == REG)
2444 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2446 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2451 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2452 if (GET_CODE (XEXP (temp, 0)) == REG)
2453 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2455 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2458 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2459 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2460 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2461 in that case, it might delete I2. Similarly for I2 and I1.
2462 Show an additional death due to the REG_DEAD note we make here. If
2463 we discard it in distribute_notes, we will decrement it again. */
2467 if (GET_CODE (i3dest_killed) == REG)
2468 REG_N_DEATHS (REGNO (i3dest_killed))++;
2470 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2471 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2473 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2475 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2477 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2481 if (i2dest_in_i2src)
2483 if (GET_CODE (i2dest) == REG)
2484 REG_N_DEATHS (REGNO (i2dest))++;
2486 if (newi2pat && reg_set_p (i2dest, newi2pat))
2487 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2488 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2490 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2491 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2492 NULL_RTX, NULL_RTX);
2495 if (i1dest_in_i1src)
2497 if (GET_CODE (i1dest) == REG)
2498 REG_N_DEATHS (REGNO (i1dest))++;
2500 if (newi2pat && reg_set_p (i1dest, newi2pat))
2501 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2502 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2504 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2505 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2506 NULL_RTX, NULL_RTX);
2509 distribute_links (i3links);
2510 distribute_links (i2links);
2511 distribute_links (i1links);
2513 if (GET_CODE (i2dest) == REG)
2516 rtx i2_insn = 0, i2_val = 0, set;
2518 /* The insn that used to set this register doesn't exist, and
2519 this life of the register may not exist either. See if one of
2520 I3's links points to an insn that sets I2DEST. If it does,
2521 that is now the last known value for I2DEST. If we don't update
2522 this and I2 set the register to a value that depended on its old
2523 contents, we will get confused. If this insn is used, thing
2524 will be set correctly in combine_instructions. */
2526 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2527 if ((set = single_set (XEXP (link, 0))) != 0
2528 && rtx_equal_p (i2dest, SET_DEST (set)))
2529 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2531 record_value_for_reg (i2dest, i2_insn, i2_val);
2533 /* If the reg formerly set in I2 died only once and that was in I3,
2534 zero its use count so it won't make `reload' do any work. */
2536 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2537 && ! i2dest_in_i2src)
2539 regno = REGNO (i2dest);
2540 REG_N_SETS (regno)--;
2541 if (REG_N_SETS (regno) == 0
2542 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2544 REG_N_REFS (regno) = 0;
2548 if (i1 && GET_CODE (i1dest) == REG)
2551 rtx i1_insn = 0, i1_val = 0, set;
2553 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2554 if ((set = single_set (XEXP (link, 0))) != 0
2555 && rtx_equal_p (i1dest, SET_DEST (set)))
2556 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2558 record_value_for_reg (i1dest, i1_insn, i1_val);
2560 regno = REGNO (i1dest);
2561 if (! added_sets_1 && ! i1dest_in_i1src)
2563 REG_N_SETS (regno)--;
2564 if (REG_N_SETS (regno) == 0
2565 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2567 REG_N_REFS (regno) = 0;
2571 /* Update reg_nonzero_bits et al for any changes that may have been made
2574 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2576 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2578 /* If I3 is now an unconditional jump, ensure that it has a
2579 BARRIER following it since it may have initially been a
2580 conditional jump. It may also be the last nonnote insn. */
2582 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2583 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2584 || GET_CODE (temp) != BARRIER))
2585 emit_barrier_after (i3);
2588 combine_successes++;
2590 /* Clear this here, so that subsequent get_last_value calls are not
2592 subst_prev_insn = NULL_RTX;
2594 if (added_links_insn
2595 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2596 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2597 return added_links_insn;
2599 return newi2pat ? i2 : i3;
2602 /* Undo all the modifications recorded in undobuf. */
2607 struct undo *undo, *next;
2609 for (undo = undobuf.undos; undo; undo = next)
2613 *undo->where.i = undo->old_contents.i;
2615 *undo->where.r = undo->old_contents.r;
2617 undo->next = undobuf.frees;
2618 undobuf.frees = undo;
2621 obfree (undobuf.storage);
2622 undobuf.undos = undobuf.previous_undos = 0;
2624 /* Clear this here, so that subsequent get_last_value calls are not
2626 subst_prev_insn = NULL_RTX;
2629 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2630 where we have an arithmetic expression and return that point. LOC will
2633 try_combine will call this function to see if an insn can be split into
2637 find_split_point (loc, insn)
2642 enum rtx_code code = GET_CODE (x);
2644 int len = 0, pos, unsignedp;
2647 /* First special-case some codes. */
2651 #ifdef INSN_SCHEDULING
2652 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2654 if (GET_CODE (SUBREG_REG (x)) == MEM)
2657 return find_split_point (&SUBREG_REG (x), insn);
2661 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2662 using LO_SUM and HIGH. */
2663 if (GET_CODE (XEXP (x, 0)) == CONST
2664 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2667 gen_rtx_combine (LO_SUM, Pmode,
2668 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2670 return &XEXP (XEXP (x, 0), 0);
2674 /* If we have a PLUS whose second operand is a constant and the
2675 address is not valid, perhaps will can split it up using
2676 the machine-specific way to split large constants. We use
2677 the first pseudo-reg (one of the virtual regs) as a placeholder;
2678 it will not remain in the result. */
2679 if (GET_CODE (XEXP (x, 0)) == PLUS
2680 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2681 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2683 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2684 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2687 /* This should have produced two insns, each of which sets our
2688 placeholder. If the source of the second is a valid address,
2689 we can make put both sources together and make a split point
2692 if (seq && XVECLEN (seq, 0) == 2
2693 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2694 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2695 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2696 && ! reg_mentioned_p (reg,
2697 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2698 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2699 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2700 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2701 && memory_address_p (GET_MODE (x),
2702 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2704 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2705 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2707 /* Replace the placeholder in SRC2 with SRC1. If we can
2708 find where in SRC2 it was placed, that can become our
2709 split point and we can replace this address with SRC2.
2710 Just try two obvious places. */
2712 src2 = replace_rtx (src2, reg, src1);
2714 if (XEXP (src2, 0) == src1)
2715 split = &XEXP (src2, 0);
2716 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2717 && XEXP (XEXP (src2, 0), 0) == src1)
2718 split = &XEXP (XEXP (src2, 0), 0);
2722 SUBST (XEXP (x, 0), src2);
2727 /* If that didn't work, perhaps the first operand is complex and
2728 needs to be computed separately, so make a split point there.
2729 This will occur on machines that just support REG + CONST
2730 and have a constant moved through some previous computation. */
2732 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2733 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2734 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2736 return &XEXP (XEXP (x, 0), 0);
2742 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2743 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2744 we need to put the operand into a register. So split at that
2747 if (SET_DEST (x) == cc0_rtx
2748 && GET_CODE (SET_SRC (x)) != COMPARE
2749 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2750 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2751 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2752 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2753 return &SET_SRC (x);
2756 /* See if we can split SET_SRC as it stands. */
2757 split = find_split_point (&SET_SRC (x), insn);
2758 if (split && split != &SET_SRC (x))
2761 /* See if we can split SET_DEST as it stands. */
2762 split = find_split_point (&SET_DEST (x), insn);
2763 if (split && split != &SET_DEST (x))
2766 /* See if this is a bitfield assignment with everything constant. If
2767 so, this is an IOR of an AND, so split it into that. */
2768 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2769 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2770 <= HOST_BITS_PER_WIDE_INT)
2771 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2772 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2773 && GET_CODE (SET_SRC (x)) == CONST_INT
2774 && ((INTVAL (XEXP (SET_DEST (x), 1))
2775 + INTVAL (XEXP (SET_DEST (x), 2)))
2776 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2777 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2779 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2780 int len = INTVAL (XEXP (SET_DEST (x), 1));
2781 int src = INTVAL (SET_SRC (x));
2782 rtx dest = XEXP (SET_DEST (x), 0);
2783 enum machine_mode mode = GET_MODE (dest);
2784 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2786 if (BITS_BIG_ENDIAN)
2787 pos = GET_MODE_BITSIZE (mode) - len - pos;
2789 if ((unsigned HOST_WIDE_INT) src == mask)
2791 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2794 gen_binary (IOR, mode,
2795 gen_binary (AND, mode, dest,
2796 GEN_INT (~ (mask << pos)
2797 & GET_MODE_MASK (mode))),
2798 GEN_INT (src << pos)));
2800 SUBST (SET_DEST (x), dest);
2802 split = find_split_point (&SET_SRC (x), insn);
2803 if (split && split != &SET_SRC (x))
2807 /* Otherwise, see if this is an operation that we can split into two.
2808 If so, try to split that. */
2809 code = GET_CODE (SET_SRC (x));
2814 /* If we are AND'ing with a large constant that is only a single
2815 bit and the result is only being used in a context where we
2816 need to know if it is zero or non-zero, replace it with a bit
2817 extraction. This will avoid the large constant, which might
2818 have taken more than one insn to make. If the constant were
2819 not a valid argument to the AND but took only one insn to make,
2820 this is no worse, but if it took more than one insn, it will
2823 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2824 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2825 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2826 && GET_CODE (SET_DEST (x)) == REG
2827 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2828 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2829 && XEXP (*split, 0) == SET_DEST (x)
2830 && XEXP (*split, 1) == const0_rtx)
2832 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2833 XEXP (SET_SRC (x), 0),
2834 pos, NULL_RTX, 1, 1, 0, 0);
2835 if (extraction != 0)
2837 SUBST (SET_SRC (x), extraction);
2838 return find_split_point (loc, insn);
2844 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2845 is known to be on, this can be converted into a NEG of a shift. */
2846 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2847 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2848 && 1 <= (pos = exact_log2
2849 (nonzero_bits (XEXP (SET_SRC (x), 0),
2850 GET_MODE (XEXP (SET_SRC (x), 0))))))
2852 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2855 gen_rtx_combine (NEG, mode,
2856 gen_rtx_combine (LSHIFTRT, mode,
2857 XEXP (SET_SRC (x), 0),
2860 split = find_split_point (&SET_SRC (x), insn);
2861 if (split && split != &SET_SRC (x))
2867 inner = XEXP (SET_SRC (x), 0);
2869 /* We can't optimize if either mode is a partial integer
2870 mode as we don't know how many bits are significant
2872 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2873 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2877 len = GET_MODE_BITSIZE (GET_MODE (inner));
2883 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2884 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2886 inner = XEXP (SET_SRC (x), 0);
2887 len = INTVAL (XEXP (SET_SRC (x), 1));
2888 pos = INTVAL (XEXP (SET_SRC (x), 2));
2890 if (BITS_BIG_ENDIAN)
2891 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2892 unsignedp = (code == ZERO_EXTRACT);
2900 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2902 enum machine_mode mode = GET_MODE (SET_SRC (x));
2904 /* For unsigned, we have a choice of a shift followed by an
2905 AND or two shifts. Use two shifts for field sizes where the
2906 constant might be too large. We assume here that we can
2907 always at least get 8-bit constants in an AND insn, which is
2908 true for every current RISC. */
2910 if (unsignedp && len <= 8)
2915 gen_rtx_combine (LSHIFTRT, mode,
2916 gen_lowpart_for_combine (mode, inner),
2918 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2920 split = find_split_point (&SET_SRC (x), insn);
2921 if (split && split != &SET_SRC (x))
2928 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2929 gen_rtx_combine (ASHIFT, mode,
2930 gen_lowpart_for_combine (mode, inner),
2931 GEN_INT (GET_MODE_BITSIZE (mode)
2933 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2935 split = find_split_point (&SET_SRC (x), insn);
2936 if (split && split != &SET_SRC (x))
2941 /* See if this is a simple operation with a constant as the second
2942 operand. It might be that this constant is out of range and hence
2943 could be used as a split point. */
2944 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2945 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2946 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2947 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2948 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2949 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2950 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2952 return &XEXP (SET_SRC (x), 1);
2954 /* Finally, see if this is a simple operation with its first operand
2955 not in a register. The operation might require this operand in a
2956 register, so return it as a split point. We can always do this
2957 because if the first operand were another operation, we would have
2958 already found it as a split point. */
2959 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2960 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2961 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2962 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2963 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2964 return &XEXP (SET_SRC (x), 0);
2970 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2971 it is better to write this as (not (ior A B)) so we can split it.
2972 Similarly for IOR. */
2973 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2976 gen_rtx_combine (NOT, GET_MODE (x),
2977 gen_rtx_combine (code == IOR ? AND : IOR,
2979 XEXP (XEXP (x, 0), 0),
2980 XEXP (XEXP (x, 1), 0))));
2981 return find_split_point (loc, insn);
2984 /* Many RISC machines have a large set of logical insns. If the
2985 second operand is a NOT, put it first so we will try to split the
2986 other operand first. */
2987 if (GET_CODE (XEXP (x, 1)) == NOT)
2989 rtx tem = XEXP (x, 0);
2990 SUBST (XEXP (x, 0), XEXP (x, 1));
2991 SUBST (XEXP (x, 1), tem);
2999 /* Otherwise, select our actions depending on our rtx class. */
3000 switch (GET_RTX_CLASS (code))
3002 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3004 split = find_split_point (&XEXP (x, 2), insn);
3007 /* ... fall through ... */
3011 split = find_split_point (&XEXP (x, 1), insn);
3014 /* ... fall through ... */
3016 /* Some machines have (and (shift ...) ...) insns. If X is not
3017 an AND, but XEXP (X, 0) is, use it as our split point. */
3018 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3019 return &XEXP (x, 0);
3021 split = find_split_point (&XEXP (x, 0), insn);
3027 /* Otherwise, we don't have a split point. */
3031 /* Throughout X, replace FROM with TO, and return the result.
3032 The result is TO if X is FROM;
3033 otherwise the result is X, but its contents may have been modified.
3034 If they were modified, a record was made in undobuf so that
3035 undo_all will (among other things) return X to its original state.
3037 If the number of changes necessary is too much to record to undo,
3038 the excess changes are not made, so the result is invalid.
3039 The changes already made can still be undone.
3040 undobuf.num_undo is incremented for such changes, so by testing that
3041 the caller can tell whether the result is valid.
3043 `n_occurrences' is incremented each time FROM is replaced.
3045 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3047 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3048 by copying if `n_occurrences' is non-zero. */
3051 subst (x, from, to, in_dest, unique_copy)
3052 register rtx x, from, to;
3056 register enum rtx_code code = GET_CODE (x);
3057 enum machine_mode op0_mode = VOIDmode;
3059 register int len, i;
3062 /* Two expressions are equal if they are identical copies of a shared
3063 RTX or if they are both registers with the same register number
3066 #define COMBINE_RTX_EQUAL_P(X,Y) \
3068 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3069 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3071 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3074 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3077 /* If X and FROM are the same register but different modes, they will
3078 not have been seen as equal above. However, flow.c will make a
3079 LOG_LINKS entry for that case. If we do nothing, we will try to
3080 rerecognize our original insn and, when it succeeds, we will
3081 delete the feeding insn, which is incorrect.
3083 So force this insn not to match in this (rare) case. */
3084 if (! in_dest && code == REG && GET_CODE (from) == REG
3085 && REGNO (x) == REGNO (from))
3086 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3088 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3089 of which may contain things that can be combined. */
3090 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3093 /* It is possible to have a subexpression appear twice in the insn.
3094 Suppose that FROM is a register that appears within TO.
3095 Then, after that subexpression has been scanned once by `subst',
3096 the second time it is scanned, TO may be found. If we were
3097 to scan TO here, we would find FROM within it and create a
3098 self-referent rtl structure which is completely wrong. */
3099 if (COMBINE_RTX_EQUAL_P (x, to))
3102 /* Parallel asm_operands need special attention because all of the
3103 inputs are shared across the arms. Furthermore, unsharing the
3104 rtl results in recognition failures. Failure to handle this case
3105 specially can result in circular rtl.
3107 Solve this by doing a normal pass across the first entry of the
3108 parallel, and only processing the SET_DESTs of the subsequent
3111 if (code == PARALLEL
3112 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3113 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3115 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3117 /* If this substitution failed, this whole thing fails. */
3118 if (GET_CODE (new) == CLOBBER
3119 && XEXP (new, 0) == const0_rtx)
3122 SUBST (XVECEXP (x, 0, 0), new);
3124 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3126 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3128 if (GET_CODE (dest) != REG
3129 && GET_CODE (dest) != CC0
3130 && GET_CODE (dest) != PC)
3132 new = subst (dest, from, to, 0, unique_copy);
3134 /* If this substitution failed, this whole thing fails. */
3135 if (GET_CODE (new) == CLOBBER
3136 && XEXP (new, 0) == const0_rtx)
3139 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3145 len = GET_RTX_LENGTH (code);
3146 fmt = GET_RTX_FORMAT (code);
3148 /* We don't need to process a SET_DEST that is a register, CC0,
3149 or PC, so set up to skip this common case. All other cases
3150 where we want to suppress replacing something inside a
3151 SET_SRC are handled via the IN_DEST operand. */
3153 && (GET_CODE (SET_DEST (x)) == REG
3154 || GET_CODE (SET_DEST (x)) == CC0
3155 || GET_CODE (SET_DEST (x)) == PC))
3158 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3161 op0_mode = GET_MODE (XEXP (x, 0));
3163 for (i = 0; i < len; i++)
3168 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3170 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3172 new = (unique_copy && n_occurrences
3173 ? copy_rtx (to) : to);
3178 new = subst (XVECEXP (x, i, j), from, to, 0,
3181 /* If this substitution failed, this whole thing
3183 if (GET_CODE (new) == CLOBBER
3184 && XEXP (new, 0) == const0_rtx)
3188 SUBST (XVECEXP (x, i, j), new);
3191 else if (fmt[i] == 'e')
3193 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3195 /* In general, don't install a subreg involving two
3196 modes not tieable. It can worsen register
3197 allocation, and can even make invalid reload
3198 insns, since the reg inside may need to be copied
3199 from in the outside mode, and that may be invalid
3200 if it is an fp reg copied in integer mode.
3202 We allow two exceptions to this: It is valid if
3203 it is inside another SUBREG and the mode of that
3204 SUBREG and the mode of the inside of TO is
3205 tieable and it is valid if X is a SET that copies
3208 if (GET_CODE (to) == SUBREG
3209 && ! MODES_TIEABLE_P (GET_MODE (to),
3210 GET_MODE (SUBREG_REG (to)))
3211 && ! (code == SUBREG
3212 && MODES_TIEABLE_P (GET_MODE (x),
3213 GET_MODE (SUBREG_REG (to))))
3215 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3218 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3220 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3224 /* If we are in a SET_DEST, suppress most cases unless we
3225 have gone inside a MEM, in which case we want to
3226 simplify the address. We assume here that things that
3227 are actually part of the destination have their inner
3228 parts in the first expression. This is true for SUBREG,
3229 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3230 things aside from REG and MEM that should appear in a
3232 new = subst (XEXP (x, i), from, to,
3234 && (code == SUBREG || code == STRICT_LOW_PART
3235 || code == ZERO_EXTRACT))
3237 && i == 0), unique_copy);
3239 /* If we found that we will have to reject this combination,
3240 indicate that by returning the CLOBBER ourselves, rather than
3241 an expression containing it. This will speed things up as
3242 well as prevent accidents where two CLOBBERs are considered
3243 to be equal, thus producing an incorrect simplification. */
3245 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3248 SUBST (XEXP (x, i), new);
3253 /* Try to simplify X. If the simplification changed the code, it is likely
3254 that further simplification will help, so loop, but limit the number
3255 of repetitions that will be performed. */
3257 for (i = 0; i < 4; i++)
3259 /* If X is sufficiently simple, don't bother trying to do anything
3261 if (code != CONST_INT && code != REG && code != CLOBBER)
3262 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3264 if (GET_CODE (x) == code)
3267 code = GET_CODE (x);
3269 /* We no longer know the original mode of operand 0 since we
3270 have changed the form of X) */
3271 op0_mode = VOIDmode;
3277 /* Simplify X, a piece of RTL. We just operate on the expression at the
3278 outer level; call `subst' to simplify recursively. Return the new
3281 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3282 will be the iteration even if an expression with a code different from
3283 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3286 simplify_rtx (x, op0_mode, last, in_dest)
3288 enum machine_mode op0_mode;
3292 enum rtx_code code = GET_CODE (x);
3293 enum machine_mode mode = GET_MODE (x);
3297 /* If this is a commutative operation, put a constant last and a complex
3298 expression first. We don't need to do this for comparisons here. */
3299 if (GET_RTX_CLASS (code) == 'c'
3300 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3301 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3302 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3303 || (GET_CODE (XEXP (x, 0)) == SUBREG
3304 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3305 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3308 SUBST (XEXP (x, 0), XEXP (x, 1));
3309 SUBST (XEXP (x, 1), temp);
3312 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3313 sign extension of a PLUS with a constant, reverse the order of the sign
3314 extension and the addition. Note that this not the same as the original
3315 code, but overflow is undefined for signed values. Also note that the
3316 PLUS will have been partially moved "inside" the sign-extension, so that
3317 the first operand of X will really look like:
3318 (ashiftrt (plus (ashift A C4) C5) C4).
3320 (plus (ashiftrt (ashift A C4) C2) C4)
3321 and replace the first operand of X with that expression. Later parts
3322 of this function may simplify the expression further.
3324 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3325 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3326 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3328 We do this to simplify address expressions. */
3330 if ((code == PLUS || code == MINUS || code == MULT)
3331 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3332 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3333 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3334 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3335 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3336 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3337 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3338 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3339 XEXP (XEXP (XEXP (x, 0), 0), 1),
3340 XEXP (XEXP (x, 0), 1))) != 0)
3343 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3344 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3345 INTVAL (XEXP (XEXP (x, 0), 1)));
3347 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3348 INTVAL (XEXP (XEXP (x, 0), 1)));
3350 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3353 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3354 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3355 things. Check for cases where both arms are testing the same
3358 Don't do anything if all operands are very simple. */
3360 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3361 || GET_RTX_CLASS (code) == '<')
3362 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3363 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3364 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3366 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3367 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3368 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3370 || (GET_RTX_CLASS (code) == '1'
3371 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3372 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3373 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3376 rtx cond, true, false;
3378 cond = if_then_else_cond (x, &true, &false);
3380 /* If everything is a comparison, what we have is highly unlikely
3381 to be simpler, so don't use it. */
3382 && ! (GET_RTX_CLASS (code) == '<'
3383 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3384 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3386 rtx cop1 = const0_rtx;
3387 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3389 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3392 /* Simplify the alternative arms; this may collapse the true and
3393 false arms to store-flag values. */
3394 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3395 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3397 /* Restarting if we generate a store-flag expression will cause
3398 us to loop. Just drop through in this case. */
3400 /* If the result values are STORE_FLAG_VALUE and zero, we can
3401 just make the comparison operation. */
3402 if (true == const_true_rtx && false == const0_rtx)
3403 x = gen_binary (cond_code, mode, cond, cop1);
3404 else if (true == const0_rtx && false == const_true_rtx)
3405 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3407 /* Likewise, we can make the negate of a comparison operation
3408 if the result values are - STORE_FLAG_VALUE and zero. */
3409 else if (GET_CODE (true) == CONST_INT
3410 && INTVAL (true) == - STORE_FLAG_VALUE
3411 && false == const0_rtx)
3412 x = gen_unary (NEG, mode, mode,
3413 gen_binary (cond_code, mode, cond, cop1));
3414 else if (GET_CODE (false) == CONST_INT
3415 && INTVAL (false) == - STORE_FLAG_VALUE
3416 && true == const0_rtx)
3417 x = gen_unary (NEG, mode, mode,
3418 gen_binary (reverse_condition (cond_code),
3421 return gen_rtx_IF_THEN_ELSE (mode,
3422 gen_binary (cond_code, VOIDmode,
3426 code = GET_CODE (x);
3427 op0_mode = VOIDmode;
3431 /* Try to fold this expression in case we have constants that weren't
3434 switch (GET_RTX_CLASS (code))
3437 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3440 temp = simplify_relational_operation (code, op0_mode,
3441 XEXP (x, 0), XEXP (x, 1));
3442 #ifdef FLOAT_STORE_FLAG_VALUE
3443 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3444 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3445 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3450 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3454 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3455 XEXP (x, 1), XEXP (x, 2));
3460 x = temp, code = GET_CODE (temp);
3462 /* First see if we can apply the inverse distributive law. */
3463 if (code == PLUS || code == MINUS
3464 || code == AND || code == IOR || code == XOR)
3466 x = apply_distributive_law (x);
3467 code = GET_CODE (x);
3470 /* If CODE is an associative operation not otherwise handled, see if we
3471 can associate some operands. This can win if they are constants or
3472 if they are logically related (i.e. (a & b) & a. */
3473 if ((code == PLUS || code == MINUS
3474 || code == MULT || code == AND || code == IOR || code == XOR
3475 || code == DIV || code == UDIV
3476 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3477 && INTEGRAL_MODE_P (mode))
3479 if (GET_CODE (XEXP (x, 0)) == code)
3481 rtx other = XEXP (XEXP (x, 0), 0);
3482 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3483 rtx inner_op1 = XEXP (x, 1);
3486 #ifndef FRAME_GROWS_DOWNWARD
3487 if (flag_propolice_protection
3489 && other == frame_pointer_rtx
3490 && GET_CODE (inner_op0) == CONST_INT
3491 && GET_CODE (inner_op1) == CONST_INT
3492 && INTVAL (inner_op0) > 0
3493 && INTVAL (inner_op0) + INTVAL (inner_op1) <= 0)
3496 /* Make sure we pass the constant operand if any as the second
3497 one if this is a commutative operation. */
3498 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3500 rtx tem = inner_op0;
3501 inner_op0 = inner_op1;
3504 inner = simplify_binary_operation (code == MINUS ? PLUS
3505 : code == DIV ? MULT
3506 : code == UDIV ? MULT
3508 mode, inner_op0, inner_op1);
3510 /* For commutative operations, try the other pair if that one
3512 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3514 other = XEXP (XEXP (x, 0), 1);
3515 inner = simplify_binary_operation (code, mode,
3516 XEXP (XEXP (x, 0), 0),
3521 return gen_binary (code, mode, other, inner);
3525 /* A little bit of algebraic simplification here. */
3529 /* Ensure that our address has any ASHIFTs converted to MULT in case
3530 address-recognizing predicates are called later. */
3531 temp = make_compound_operation (XEXP (x, 0), MEM);
3532 SUBST (XEXP (x, 0), temp);
3536 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3537 is paradoxical. If we can't do that safely, then it becomes
3538 something nonsensical so that this combination won't take place. */
3540 if (GET_CODE (SUBREG_REG (x)) == MEM
3541 && (GET_MODE_SIZE (mode)
3542 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3544 rtx inner = SUBREG_REG (x);
3545 int endian_offset = 0;
3546 /* Don't change the mode of the MEM
3547 if that would change the meaning of the address. */
3548 if (MEM_VOLATILE_P (SUBREG_REG (x))
3549 || mode_dependent_address_p (XEXP (inner, 0)))
3550 return gen_rtx_CLOBBER (mode, const0_rtx);
3552 if (BYTES_BIG_ENDIAN)
3554 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3555 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3556 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3557 endian_offset -= (UNITS_PER_WORD
3558 - GET_MODE_SIZE (GET_MODE (inner)));
3560 /* Note if the plus_constant doesn't make a valid address
3561 then this combination won't be accepted. */
3562 x = gen_rtx_MEM (mode,
3563 plus_constant (XEXP (inner, 0),
3564 (SUBREG_WORD (x) * UNITS_PER_WORD
3566 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3567 MEM_COPY_ATTRIBUTES (x, inner);
3571 /* If we are in a SET_DEST, these other cases can't apply. */
3575 /* Changing mode twice with SUBREG => just change it once,
3576 or not at all if changing back to starting mode. */
3577 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3579 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3580 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3581 return SUBREG_REG (SUBREG_REG (x));
3583 SUBST_INT (SUBREG_WORD (x),
3584 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3585 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3588 /* SUBREG of a hard register => just change the register number
3589 and/or mode. If the hard register is not valid in that mode,
3590 suppress this combination. If the hard register is the stack,
3591 frame, or argument pointer, leave this as a SUBREG. */
3593 if (GET_CODE (SUBREG_REG (x)) == REG
3594 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3595 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3596 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3597 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3599 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3600 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3602 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3604 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3606 return gen_rtx_REG (mode,
3607 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3609 return gen_rtx_CLOBBER (mode, const0_rtx);
3612 /* For a constant, try to pick up the part we want. Handle a full
3613 word and low-order part. Only do this if we are narrowing
3614 the constant; if it is being widened, we have no idea what
3615 the extra bits will have been set to. */
3617 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3618 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3619 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3620 && GET_MODE_CLASS (mode) == MODE_INT)
3622 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3628 /* If we want a subreg of a constant, at offset 0,
3629 take the low bits. On a little-endian machine, that's
3630 always valid. On a big-endian machine, it's valid
3631 only if the constant's mode fits in one word. Note that we
3632 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3633 if (CONSTANT_P (SUBREG_REG (x))
3634 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3635 || ! WORDS_BIG_ENDIAN)
3636 ? SUBREG_WORD (x) == 0
3638 == ((GET_MODE_SIZE (op0_mode)
3639 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3641 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3642 && (! WORDS_BIG_ENDIAN
3643 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3644 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3646 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3647 since we are saying that the high bits don't matter. */
3648 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3649 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3650 return SUBREG_REG (x);
3652 /* Note that we cannot do any narrowing for non-constants since
3653 we might have been counting on using the fact that some bits were
3654 zero. We now do this in the SET. */
3659 /* (not (plus X -1)) can become (neg X). */
3660 if (GET_CODE (XEXP (x, 0)) == PLUS
3661 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3662 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3664 /* Similarly, (not (neg X)) is (plus X -1). */
3665 if (GET_CODE (XEXP (x, 0)) == NEG)
3666 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3669 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3670 if (GET_CODE (XEXP (x, 0)) == XOR
3671 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3672 && (temp = simplify_unary_operation (NOT, mode,
3673 XEXP (XEXP (x, 0), 1),
3675 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3677 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3678 other than 1, but that is not valid. We could do a similar
3679 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3680 but this doesn't seem common enough to bother with. */
3681 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3682 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3683 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3684 XEXP (XEXP (x, 0), 1));
3686 if (GET_CODE (XEXP (x, 0)) == SUBREG
3687 && subreg_lowpart_p (XEXP (x, 0))
3688 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3689 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3690 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3691 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3693 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3695 x = gen_rtx_ROTATE (inner_mode,
3696 gen_unary (NOT, inner_mode, inner_mode,
3698 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3699 return gen_lowpart_for_combine (mode, x);
3702 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3703 reversing the comparison code if valid. */
3704 if (STORE_FLAG_VALUE == -1
3705 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3706 && reversible_comparison_p (XEXP (x, 0)))
3707 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3708 mode, XEXP (XEXP (x, 0), 0),
3709 XEXP (XEXP (x, 0), 1));
3711 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3712 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3713 perform the above simplification. */
3715 if (STORE_FLAG_VALUE == -1
3716 && XEXP (x, 1) == const1_rtx
3717 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3718 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3719 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3720 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3722 /* Apply De Morgan's laws to reduce number of patterns for machines
3723 with negating logical insns (and-not, nand, etc.). If result has
3724 only one NOT, put it first, since that is how the patterns are
3727 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3729 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3731 if (GET_CODE (in1) == NOT)
3732 in1 = XEXP (in1, 0);
3734 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3736 if (GET_CODE (in2) == NOT)
3737 in2 = XEXP (in2, 0);
3738 else if (GET_CODE (in2) == CONST_INT
3739 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3740 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3742 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3744 if (GET_CODE (in2) == NOT)
3747 in2 = in1; in1 = tem;
3750 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3756 /* (neg (plus X 1)) can become (not X). */
3757 if (GET_CODE (XEXP (x, 0)) == PLUS
3758 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3759 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3761 /* Similarly, (neg (not X)) is (plus X 1). */
3762 if (GET_CODE (XEXP (x, 0)) == NOT)
3763 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3765 /* (neg (minus X Y)) can become (minus Y X). */
3766 if (GET_CODE (XEXP (x, 0)) == MINUS
3767 && (! FLOAT_MODE_P (mode)
3768 /* x-y != -(y-x) with IEEE floating point. */
3769 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3771 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3772 XEXP (XEXP (x, 0), 0));
3774 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3775 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3776 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3777 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3779 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3780 if we can then eliminate the NEG (e.g.,
3781 if the operand is a constant). */
3783 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3785 temp = simplify_unary_operation (NEG, mode,
3786 XEXP (XEXP (x, 0), 0), mode);
3789 SUBST (XEXP (XEXP (x, 0), 0), temp);
3794 temp = expand_compound_operation (XEXP (x, 0));
3796 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3797 replaced by (lshiftrt X C). This will convert
3798 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3800 if (GET_CODE (temp) == ASHIFTRT
3801 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3802 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3803 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3804 INTVAL (XEXP (temp, 1)));
3806 /* If X has only a single bit that might be nonzero, say, bit I, convert
3807 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3808 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3809 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3810 or a SUBREG of one since we'd be making the expression more
3811 complex if it was just a register. */
3813 if (GET_CODE (temp) != REG
3814 && ! (GET_CODE (temp) == SUBREG
3815 && GET_CODE (SUBREG_REG (temp)) == REG)
3816 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3818 rtx temp1 = simplify_shift_const
3819 (NULL_RTX, ASHIFTRT, mode,
3820 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3821 GET_MODE_BITSIZE (mode) - 1 - i),
3822 GET_MODE_BITSIZE (mode) - 1 - i);
3824 /* If all we did was surround TEMP with the two shifts, we
3825 haven't improved anything, so don't use it. Otherwise,
3826 we are better off with TEMP1. */
3827 if (GET_CODE (temp1) != ASHIFTRT
3828 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3829 || XEXP (XEXP (temp1, 0), 0) != temp)
3835 /* We can't handle truncation to a partial integer mode here
3836 because we don't know the real bitsize of the partial
3838 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3841 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3842 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3843 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3845 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3846 GET_MODE_MASK (mode), NULL_RTX, 0));
3848 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3849 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3850 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3851 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3852 return XEXP (XEXP (x, 0), 0);
3854 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3855 (OP:SI foo:SI) if OP is NEG or ABS. */
3856 if ((GET_CODE (XEXP (x, 0)) == ABS
3857 || GET_CODE (XEXP (x, 0)) == NEG)
3858 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3859 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3860 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3861 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3862 XEXP (XEXP (XEXP (x, 0), 0), 0));
3864 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3866 if (GET_CODE (XEXP (x, 0)) == SUBREG
3867 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3868 && subreg_lowpart_p (XEXP (x, 0)))
3869 return SUBREG_REG (XEXP (x, 0));
3871 /* If we know that the value is already truncated, we can
3872 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is
3873 nonzero for the corresponding modes. */
3874 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3875 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3876 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3877 >= GET_MODE_BITSIZE (mode) + 1)
3878 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3880 /* A truncate of a comparison can be replaced with a subreg if
3881 STORE_FLAG_VALUE permits. This is like the previous test,
3882 but it works even if the comparison is done in a mode larger
3883 than HOST_BITS_PER_WIDE_INT. */
3884 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3885 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3886 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3887 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3889 /* Similarly, a truncate of a register whose value is a
3890 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3892 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3893 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3894 && (temp = get_last_value (XEXP (x, 0)))
3895 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3896 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3900 case FLOAT_TRUNCATE:
3901 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3902 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3903 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3904 return XEXP (XEXP (x, 0), 0);
3906 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3907 (OP:SF foo:SF) if OP is NEG or ABS. */
3908 if ((GET_CODE (XEXP (x, 0)) == ABS
3909 || GET_CODE (XEXP (x, 0)) == NEG)
3910 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3911 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3912 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3913 XEXP (XEXP (XEXP (x, 0), 0), 0));
3915 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3916 is (float_truncate:SF x). */
3917 if (GET_CODE (XEXP (x, 0)) == SUBREG
3918 && subreg_lowpart_p (XEXP (x, 0))
3919 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3920 return SUBREG_REG (XEXP (x, 0));
3925 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3926 using cc0, in which case we want to leave it as a COMPARE
3927 so we can distinguish it from a register-register-copy. */
3928 if (XEXP (x, 1) == const0_rtx)
3931 /* In IEEE floating point, x-0 is not the same as x. */
3932 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3933 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3935 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3941 /* (const (const X)) can become (const X). Do it this way rather than
3942 returning the inner CONST since CONST can be shared with a
3944 if (GET_CODE (XEXP (x, 0)) == CONST)
3945 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3950 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3951 can add in an offset. find_split_point will split this address up
3952 again if it doesn't match. */
3953 if (GET_CODE (XEXP (x, 0)) == HIGH
3954 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3960 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3961 outermost. That's because that's the way indexed addresses are
3962 supposed to appear. This code used to check many more cases, but
3963 they are now checked elsewhere. */
3964 if (GET_CODE (XEXP (x, 0)) == PLUS
3965 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3966 #ifndef FRAME_GROWS_DOWNWARD
3967 if (! (flag_propolice_protection
3968 && XEXP (XEXP (x, 0), 0) == frame_pointer_rtx
3969 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3971 return gen_binary (PLUS, mode,
3972 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3974 XEXP (XEXP (x, 0), 1));
3976 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3977 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3978 bit-field and can be replaced by either a sign_extend or a
3979 sign_extract. The `and' may be a zero_extend. */
3980 if (GET_CODE (XEXP (x, 0)) == XOR
3981 && GET_CODE (XEXP (x, 1)) == CONST_INT
3982 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3983 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3984 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3985 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3986 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3987 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3988 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3989 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3990 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3991 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3993 return simplify_shift_const
3994 (NULL_RTX, ASHIFTRT, mode,
3995 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3996 XEXP (XEXP (XEXP (x, 0), 0), 0),
3997 GET_MODE_BITSIZE (mode) - (i + 1)),
3998 GET_MODE_BITSIZE (mode) - (i + 1));
4000 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4001 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4002 is 1. This produces better code than the alternative immediately
4004 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4005 && reversible_comparison_p (XEXP (x, 0))
4006 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4007 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4009 gen_unary (NEG, mode, mode,
4010 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4011 mode, XEXP (XEXP (x, 0), 0),
4012 XEXP (XEXP (x, 0), 1)));
4014 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4015 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4016 the bitsize of the mode - 1. This allows simplification of
4017 "a = (b & 8) == 0;" */
4018 if (XEXP (x, 1) == constm1_rtx
4019 && GET_CODE (XEXP (x, 0)) != REG
4020 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4021 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4022 && nonzero_bits (XEXP (x, 0), mode) == 1)
4023 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4024 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4025 gen_rtx_combine (XOR, mode,
4026 XEXP (x, 0), const1_rtx),
4027 GET_MODE_BITSIZE (mode) - 1),
4028 GET_MODE_BITSIZE (mode) - 1);
4030 /* If we are adding two things that have no bits in common, convert
4031 the addition into an IOR. This will often be further simplified,
4032 for example in cases like ((a & 1) + (a & 2)), which can
4035 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4036 && (nonzero_bits (XEXP (x, 0), mode)
4037 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4038 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4042 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4043 by reversing the comparison code if valid. */
4044 if (STORE_FLAG_VALUE == 1
4045 && XEXP (x, 0) == const1_rtx
4046 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4047 && reversible_comparison_p (XEXP (x, 1)))
4048 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
4049 mode, XEXP (XEXP (x, 1), 0),
4050 XEXP (XEXP (x, 1), 1));
4052 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4053 (and <foo> (const_int pow2-1)) */
4054 if (GET_CODE (XEXP (x, 1)) == AND
4055 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4056 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4057 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4058 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4059 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4061 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4063 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4064 return gen_binary (MINUS, mode,
4065 gen_binary (MINUS, mode, XEXP (x, 0),
4066 XEXP (XEXP (x, 1), 0)),
4067 XEXP (XEXP (x, 1), 1));
4071 /* If we have (mult (plus A B) C), apply the distributive law and then
4072 the inverse distributive law to see if things simplify. This
4073 occurs mostly in addresses, often when unrolling loops. */
4075 if (GET_CODE (XEXP (x, 0)) == PLUS)
4077 x = apply_distributive_law
4078 (gen_binary (PLUS, mode,
4079 gen_binary (MULT, mode,
4080 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4081 gen_binary (MULT, mode,
4082 XEXP (XEXP (x, 0), 1),
4083 copy_rtx (XEXP (x, 1)))));
4085 if (GET_CODE (x) != MULT)
4091 /* If this is a divide by a power of two, treat it as a shift if
4092 its first operand is a shift. */
4093 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4094 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4095 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4096 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4097 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4098 || GET_CODE (XEXP (x, 0)) == ROTATE
4099 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4100 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4104 case GT: case GTU: case GE: case GEU:
4105 case LT: case LTU: case LE: case LEU:
4106 /* If the first operand is a condition code, we can't do anything
4108 if (GET_CODE (XEXP (x, 0)) == COMPARE
4109 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4111 && XEXP (x, 0) != cc0_rtx
4115 rtx op0 = XEXP (x, 0);
4116 rtx op1 = XEXP (x, 1);
4117 enum rtx_code new_code;
4119 if (GET_CODE (op0) == COMPARE)
4120 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4122 /* Simplify our comparison, if possible. */
4123 new_code = simplify_comparison (code, &op0, &op1);
4125 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4126 if only the low-order bit is possibly nonzero in X (such as when
4127 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4128 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4129 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4132 Remove any ZERO_EXTRACT we made when thinking this was a
4133 comparison. It may now be simpler to use, e.g., an AND. If a
4134 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4135 the call to make_compound_operation in the SET case. */
4137 if (STORE_FLAG_VALUE == 1
4138 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4139 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4140 return gen_lowpart_for_combine (mode,
4141 expand_compound_operation (op0));
4143 else if (STORE_FLAG_VALUE == 1
4144 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4145 && op1 == const0_rtx
4146 && (num_sign_bit_copies (op0, mode)
4147 == GET_MODE_BITSIZE (mode)))
4149 op0 = expand_compound_operation (op0);
4150 return gen_unary (NEG, mode, mode,
4151 gen_lowpart_for_combine (mode, op0));
4154 else if (STORE_FLAG_VALUE == 1
4155 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4156 && op1 == const0_rtx
4157 && nonzero_bits (op0, mode) == 1)
4159 op0 = expand_compound_operation (op0);
4160 return gen_binary (XOR, mode,
4161 gen_lowpart_for_combine (mode, op0),
4165 else if (STORE_FLAG_VALUE == 1
4166 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4167 && op1 == const0_rtx
4168 && (num_sign_bit_copies (op0, mode)
4169 == GET_MODE_BITSIZE (mode)))
4171 op0 = expand_compound_operation (op0);
4172 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4175 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4177 if (STORE_FLAG_VALUE == -1
4178 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4179 && op1 == const0_rtx
4180 && (num_sign_bit_copies (op0, mode)
4181 == GET_MODE_BITSIZE (mode)))
4182 return gen_lowpart_for_combine (mode,
4183 expand_compound_operation (op0));
4185 else if (STORE_FLAG_VALUE == -1
4186 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4187 && op1 == const0_rtx
4188 && nonzero_bits (op0, mode) == 1)
4190 op0 = expand_compound_operation (op0);
4191 return gen_unary (NEG, mode, mode,
4192 gen_lowpart_for_combine (mode, op0));
4195 else if (STORE_FLAG_VALUE == -1
4196 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4197 && op1 == const0_rtx
4198 && (num_sign_bit_copies (op0, mode)
4199 == GET_MODE_BITSIZE (mode)))
4201 op0 = expand_compound_operation (op0);
4202 return gen_unary (NOT, mode, mode,
4203 gen_lowpart_for_combine (mode, op0));
4206 /* If X is 0/1, (eq X 0) is X-1. */
4207 else if (STORE_FLAG_VALUE == -1
4208 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4209 && op1 == const0_rtx
4210 && nonzero_bits (op0, mode) == 1)
4212 op0 = expand_compound_operation (op0);
4213 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4216 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4217 one bit that might be nonzero, we can convert (ne x 0) to
4218 (ashift x c) where C puts the bit in the sign bit. Remove any
4219 AND with STORE_FLAG_VALUE when we are done, since we are only
4220 going to test the sign bit. */
4221 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4222 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4223 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4224 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4225 && op1 == const0_rtx
4226 && mode == GET_MODE (op0)
4227 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4229 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4230 expand_compound_operation (op0),
4231 GET_MODE_BITSIZE (mode) - 1 - i);
4232 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4238 /* If the code changed, return a whole new comparison. */
4239 if (new_code != code)
4240 return gen_rtx_combine (new_code, mode, op0, op1);
4242 /* Otherwise, keep this operation, but maybe change its operands.
4243 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4244 SUBST (XEXP (x, 0), op0);
4245 SUBST (XEXP (x, 1), op1);
4250 return simplify_if_then_else (x);
4256 /* If we are processing SET_DEST, we are done. */
4260 return expand_compound_operation (x);
4263 return simplify_set (x);
4268 return simplify_logical (x, last);
4271 /* (abs (neg <foo>)) -> (abs <foo>) */
4272 if (GET_CODE (XEXP (x, 0)) == NEG)
4273 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4275 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4277 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4280 /* If operand is something known to be positive, ignore the ABS. */
4281 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4282 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4283 <= HOST_BITS_PER_WIDE_INT)
4284 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4285 & ((HOST_WIDE_INT) 1
4286 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4291 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4292 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4293 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4298 /* (ffs (*_extend <X>)) = (ffs <X>) */
4299 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4300 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4301 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4305 /* (float (sign_extend <X>)) = (float <X>). */
4306 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4307 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4315 /* If this is a shift by a constant amount, simplify it. */
4316 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4317 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4318 INTVAL (XEXP (x, 1)));
4320 #ifdef SHIFT_COUNT_TRUNCATED
4321 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4323 force_to_mode (XEXP (x, 1), GET_MODE (x),
4325 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4339 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4342 simplify_if_then_else (x)
4345 enum machine_mode mode = GET_MODE (x);
4346 rtx cond = XEXP (x, 0);
4347 rtx true = XEXP (x, 1);
4348 rtx false = XEXP (x, 2);
4349 enum rtx_code true_code = GET_CODE (cond);
4350 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4354 /* Simplify storing of the truth value. */
4355 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4356 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4358 /* Also when the truth value has to be reversed. */
4359 if (comparison_p && reversible_comparison_p (cond)
4360 && true == const0_rtx && false == const_true_rtx)
4361 return gen_binary (reverse_condition (true_code),
4362 mode, XEXP (cond, 0), XEXP (cond, 1));
4364 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4365 in it is being compared against certain values. Get the true and false
4366 comparisons and see if that says anything about the value of each arm. */
4368 if (comparison_p && reversible_comparison_p (cond)
4369 && GET_CODE (XEXP (cond, 0)) == REG)
4372 rtx from = XEXP (cond, 0);
4373 enum rtx_code false_code = reverse_condition (true_code);
4374 rtx true_val = XEXP (cond, 1);
4375 rtx false_val = true_val;
4378 /* If FALSE_CODE is EQ, swap the codes and arms. */
4380 if (false_code == EQ)
4382 swapped = 1, true_code = EQ, false_code = NE;
4383 temp = true, true = false, false = temp;
4386 /* If we are comparing against zero and the expression being tested has
4387 only a single bit that might be nonzero, that is its value when it is
4388 not equal to zero. Similarly if it is known to be -1 or 0. */
4390 if (true_code == EQ && true_val == const0_rtx
4391 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4392 false_code = EQ, false_val = GEN_INT (nzb);
4393 else if (true_code == EQ && true_val == const0_rtx
4394 && (num_sign_bit_copies (from, GET_MODE (from))
4395 == GET_MODE_BITSIZE (GET_MODE (from))))
4396 false_code = EQ, false_val = constm1_rtx;
4398 /* Now simplify an arm if we know the value of the register in the
4399 branch and it is used in the arm. Be careful due to the potential
4400 of locally-shared RTL. */
4402 if (reg_mentioned_p (from, true))
4403 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4404 pc_rtx, pc_rtx, 0, 0);
4405 if (reg_mentioned_p (from, false))
4406 false = subst (known_cond (copy_rtx (false), false_code,
4408 pc_rtx, pc_rtx, 0, 0);
4410 SUBST (XEXP (x, 1), swapped ? false : true);
4411 SUBST (XEXP (x, 2), swapped ? true : false);
4413 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4416 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4417 reversed, do so to avoid needing two sets of patterns for
4418 subtract-and-branch insns. Similarly if we have a constant in the true
4419 arm, the false arm is the same as the first operand of the comparison, or
4420 the false arm is more complicated than the true arm. */
4422 if (comparison_p && reversible_comparison_p (cond)
4424 || (CONSTANT_P (true)
4425 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4426 || true == const0_rtx
4427 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4428 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4429 || (GET_CODE (true) == SUBREG
4430 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4431 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4432 || reg_mentioned_p (true, false)
4433 || rtx_equal_p (false, XEXP (cond, 0))))
4435 true_code = reverse_condition (true_code);
4437 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4440 SUBST (XEXP (x, 1), false);
4441 SUBST (XEXP (x, 2), true);
4443 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4445 /* It is possible that the conditional has been simplified out. */
4446 true_code = GET_CODE (cond);
4447 comparison_p = GET_RTX_CLASS (true_code) == '<';
4450 /* If the two arms are identical, we don't need the comparison. */
4452 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4455 /* Convert a == b ? b : a to "a". */
4456 if (true_code == EQ && ! side_effects_p (cond)
4457 && rtx_equal_p (XEXP (cond, 0), false)
4458 && rtx_equal_p (XEXP (cond, 1), true))
4460 else if (true_code == NE && ! side_effects_p (cond)
4461 && rtx_equal_p (XEXP (cond, 0), true)
4462 && rtx_equal_p (XEXP (cond, 1), false))
4465 /* Look for cases where we have (abs x) or (neg (abs X)). */
4467 if (GET_MODE_CLASS (mode) == MODE_INT
4468 && GET_CODE (false) == NEG
4469 && rtx_equal_p (true, XEXP (false, 0))
4471 && rtx_equal_p (true, XEXP (cond, 0))
4472 && ! side_effects_p (true))
4477 return gen_unary (ABS, mode, mode, true);
4480 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4485 /* Look for MIN or MAX. */
4487 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4489 && rtx_equal_p (XEXP (cond, 0), true)
4490 && rtx_equal_p (XEXP (cond, 1), false)
4491 && ! side_effects_p (cond))
4496 return gen_binary (SMAX, mode, true, false);
4499 return gen_binary (SMIN, mode, true, false);
4502 return gen_binary (UMAX, mode, true, false);
4505 return gen_binary (UMIN, mode, true, false);
4510 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4511 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4512 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4513 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4514 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4515 neither 1 or -1, but it isn't worth checking for. */
4517 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4518 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4520 rtx t = make_compound_operation (true, SET);
4521 rtx f = make_compound_operation (false, SET);
4522 rtx cond_op0 = XEXP (cond, 0);
4523 rtx cond_op1 = XEXP (cond, 1);
4524 enum rtx_code op, extend_op = NIL;
4525 enum machine_mode m = mode;
4528 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4529 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4530 || GET_CODE (t) == ASHIFT
4531 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4532 && rtx_equal_p (XEXP (t, 0), f))
4533 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4535 /* If an identity-zero op is commutative, check whether there
4536 would be a match if we swapped the operands. */
4537 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4538 || GET_CODE (t) == XOR)
4539 && rtx_equal_p (XEXP (t, 1), f))
4540 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4541 else if (GET_CODE (t) == SIGN_EXTEND
4542 && (GET_CODE (XEXP (t, 0)) == PLUS
4543 || GET_CODE (XEXP (t, 0)) == MINUS
4544 || GET_CODE (XEXP (t, 0)) == IOR
4545 || GET_CODE (XEXP (t, 0)) == XOR
4546 || GET_CODE (XEXP (t, 0)) == ASHIFT
4547 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4548 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4549 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4550 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4551 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4552 && (num_sign_bit_copies (f, GET_MODE (f))
4553 > (GET_MODE_BITSIZE (mode)
4554 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4556 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4557 extend_op = SIGN_EXTEND;
4558 m = GET_MODE (XEXP (t, 0));
4560 else if (GET_CODE (t) == SIGN_EXTEND
4561 && (GET_CODE (XEXP (t, 0)) == PLUS
4562 || GET_CODE (XEXP (t, 0)) == IOR
4563 || GET_CODE (XEXP (t, 0)) == XOR)
4564 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4565 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4566 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4567 && (num_sign_bit_copies (f, GET_MODE (f))
4568 > (GET_MODE_BITSIZE (mode)
4569 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4571 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4572 extend_op = SIGN_EXTEND;
4573 m = GET_MODE (XEXP (t, 0));
4575 else if (GET_CODE (t) == ZERO_EXTEND
4576 && (GET_CODE (XEXP (t, 0)) == PLUS
4577 || GET_CODE (XEXP (t, 0)) == MINUS
4578 || GET_CODE (XEXP (t, 0)) == IOR
4579 || GET_CODE (XEXP (t, 0)) == XOR
4580 || GET_CODE (XEXP (t, 0)) == ASHIFT
4581 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4582 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4583 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4584 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4585 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4586 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4587 && ((nonzero_bits (f, GET_MODE (f))
4588 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4591 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4592 extend_op = ZERO_EXTEND;
4593 m = GET_MODE (XEXP (t, 0));
4595 else if (GET_CODE (t) == ZERO_EXTEND
4596 && (GET_CODE (XEXP (t, 0)) == PLUS
4597 || GET_CODE (XEXP (t, 0)) == IOR
4598 || GET_CODE (XEXP (t, 0)) == XOR)
4599 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4600 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4601 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4602 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4603 && ((nonzero_bits (f, GET_MODE (f))
4604 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4607 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4608 extend_op = ZERO_EXTEND;
4609 m = GET_MODE (XEXP (t, 0));
4614 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4615 pc_rtx, pc_rtx, 0, 0);
4616 temp = gen_binary (MULT, m, temp,
4617 gen_binary (MULT, m, c1, const_true_rtx));
4618 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4619 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4621 if (extend_op != NIL)
4622 temp = gen_unary (extend_op, mode, m, temp);
4628 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4629 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4630 negation of a single bit, we can convert this operation to a shift. We
4631 can actually do this more generally, but it doesn't seem worth it. */
4633 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4634 && false == const0_rtx && GET_CODE (true) == CONST_INT
4635 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4636 && (i = exact_log2 (INTVAL (true))) >= 0)
4637 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4638 == GET_MODE_BITSIZE (mode))
4639 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4641 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4642 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4647 /* Simplify X, a SET expression. Return the new expression. */
4653 rtx src = SET_SRC (x);
4654 rtx dest = SET_DEST (x);
4655 enum machine_mode mode
4656 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4660 /* (set (pc) (return)) gets written as (return). */
4661 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4664 /* Now that we know for sure which bits of SRC we are using, see if we can
4665 simplify the expression for the object knowing that we only need the
4668 if (GET_MODE_CLASS (mode) == MODE_INT)
4669 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4671 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4672 the comparison result and try to simplify it unless we already have used
4673 undobuf.other_insn. */
4674 if ((GET_CODE (src) == COMPARE
4679 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4680 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4681 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4682 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4684 enum rtx_code old_code = GET_CODE (*cc_use);
4685 enum rtx_code new_code;
4687 int other_changed = 0;
4688 enum machine_mode compare_mode = GET_MODE (dest);
4690 if (GET_CODE (src) == COMPARE)
4691 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4693 op0 = src, op1 = const0_rtx;
4695 /* Simplify our comparison, if possible. */
4696 new_code = simplify_comparison (old_code, &op0, &op1);
4698 #ifdef EXTRA_CC_MODES
4699 /* If this machine has CC modes other than CCmode, check to see if we
4700 need to use a different CC mode here. */
4701 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4702 #endif /* EXTRA_CC_MODES */
4704 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4705 /* If the mode changed, we have to change SET_DEST, the mode in the
4706 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4707 a hard register, just build new versions with the proper mode. If it
4708 is a pseudo, we lose unless it is only time we set the pseudo, in
4709 which case we can safely change its mode. */
4710 if (compare_mode != GET_MODE (dest))
4712 int regno = REGNO (dest);
4713 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4715 if (regno < FIRST_PSEUDO_REGISTER
4716 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4718 if (regno >= FIRST_PSEUDO_REGISTER)
4719 SUBST (regno_reg_rtx[regno], new_dest);
4721 SUBST (SET_DEST (x), new_dest);
4722 SUBST (XEXP (*cc_use, 0), new_dest);
4730 /* If the code changed, we have to build a new comparison in
4731 undobuf.other_insn. */
4732 if (new_code != old_code)
4734 unsigned HOST_WIDE_INT mask;
4736 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4739 /* If the only change we made was to change an EQ into an NE or
4740 vice versa, OP0 has only one bit that might be nonzero, and OP1
4741 is zero, check if changing the user of the condition code will
4742 produce a valid insn. If it won't, we can keep the original code
4743 in that insn by surrounding our operation with an XOR. */
4745 if (((old_code == NE && new_code == EQ)
4746 || (old_code == EQ && new_code == NE))
4747 && ! other_changed && op1 == const0_rtx
4748 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4749 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4751 rtx pat = PATTERN (other_insn), note = 0;
4753 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4754 && ! check_asm_operands (pat)))
4756 PUT_CODE (*cc_use, old_code);
4759 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4767 undobuf.other_insn = other_insn;
4770 /* If we are now comparing against zero, change our source if
4771 needed. If we do not use cc0, we always have a COMPARE. */
4772 if (op1 == const0_rtx && dest == cc0_rtx)
4774 SUBST (SET_SRC (x), op0);
4780 /* Otherwise, if we didn't previously have a COMPARE in the
4781 correct mode, we need one. */
4782 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4785 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4790 /* Otherwise, update the COMPARE if needed. */
4791 SUBST (XEXP (src, 0), op0);
4792 SUBST (XEXP (src, 1), op1);
4797 /* Get SET_SRC in a form where we have placed back any
4798 compound expressions. Then do the checks below. */
4799 src = make_compound_operation (src, SET);
4800 SUBST (SET_SRC (x), src);
4803 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4804 and X being a REG or (subreg (reg)), we may be able to convert this to
4805 (set (subreg:m2 x) (op)).
4807 We can always do this if M1 is narrower than M2 because that means that
4808 we only care about the low bits of the result.
4810 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4811 perform a narrower operation than requested since the high-order bits will
4812 be undefined. On machine where it is defined, this transformation is safe
4813 as long as M1 and M2 have the same number of words. */
4815 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4816 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4817 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4819 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4820 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4821 #ifndef WORD_REGISTER_OPERATIONS
4822 && (GET_MODE_SIZE (GET_MODE (src))
4823 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4825 #ifdef CLASS_CANNOT_CHANGE_SIZE
4826 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4827 && (TEST_HARD_REG_BIT
4828 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4830 && (GET_MODE_SIZE (GET_MODE (src))
4831 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4833 && (GET_CODE (dest) == REG
4834 || (GET_CODE (dest) == SUBREG
4835 && GET_CODE (SUBREG_REG (dest)) == REG)))
4837 SUBST (SET_DEST (x),
4838 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4840 SUBST (SET_SRC (x), SUBREG_REG (src));
4842 src = SET_SRC (x), dest = SET_DEST (x);
4845 #ifdef LOAD_EXTEND_OP
4846 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4847 would require a paradoxical subreg. Replace the subreg with a
4848 zero_extend to avoid the reload that would otherwise be required. */
4850 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4851 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4852 && SUBREG_WORD (src) == 0
4853 && (GET_MODE_SIZE (GET_MODE (src))
4854 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4855 && GET_CODE (SUBREG_REG (src)) == MEM)
4858 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4859 GET_MODE (src), XEXP (src, 0)));
4865 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4866 are comparing an item known to be 0 or -1 against 0, use a logical
4867 operation instead. Check for one of the arms being an IOR of the other
4868 arm with some value. We compute three terms to be IOR'ed together. In
4869 practice, at most two will be nonzero. Then we do the IOR's. */
4871 if (GET_CODE (dest) != PC
4872 && GET_CODE (src) == IF_THEN_ELSE
4873 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4874 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4875 && XEXP (XEXP (src, 0), 1) == const0_rtx
4876 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4877 #ifdef HAVE_conditional_move
4878 && ! can_conditionally_move_p (GET_MODE (src))
4880 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4881 GET_MODE (XEXP (XEXP (src, 0), 0)))
4882 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4883 && ! side_effects_p (src))
4885 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4886 ? XEXP (src, 1) : XEXP (src, 2));
4887 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4888 ? XEXP (src, 2) : XEXP (src, 1));
4889 rtx term1 = const0_rtx, term2, term3;
4891 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4892 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4893 else if (GET_CODE (true) == IOR
4894 && rtx_equal_p (XEXP (true, 1), false))
4895 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4896 else if (GET_CODE (false) == IOR
4897 && rtx_equal_p (XEXP (false, 0), true))
4898 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4899 else if (GET_CODE (false) == IOR
4900 && rtx_equal_p (XEXP (false, 1), true))
4901 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4903 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4904 term3 = gen_binary (AND, GET_MODE (src),
4905 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4906 XEXP (XEXP (src, 0), 0)),
4910 gen_binary (IOR, GET_MODE (src),
4911 gen_binary (IOR, GET_MODE (src), term1, term2),
4917 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4918 whole thing fail. */
4919 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4921 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4924 /* Convert this into a field assignment operation, if possible. */
4925 return make_field_assignment (x);
4928 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4929 result. LAST is nonzero if this is the last retry. */
4932 simplify_logical (x, last)
4936 enum machine_mode mode = GET_MODE (x);
4937 rtx op0 = XEXP (x, 0);
4938 rtx op1 = XEXP (x, 1);
4940 switch (GET_CODE (x))
4943 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4944 insn (and may simplify more). */
4945 if (GET_CODE (op0) == XOR
4946 && rtx_equal_p (XEXP (op0, 0), op1)
4947 && ! side_effects_p (op1))
4948 x = gen_binary (AND, mode,
4949 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4951 if (GET_CODE (op0) == XOR
4952 && rtx_equal_p (XEXP (op0, 1), op1)
4953 && ! side_effects_p (op1))
4954 x = gen_binary (AND, mode,
4955 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4957 /* Similarly for (~ (A ^ B)) & A. */
4958 if (GET_CODE (op0) == NOT
4959 && GET_CODE (XEXP (op0, 0)) == XOR
4960 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4961 && ! side_effects_p (op1))
4962 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4964 if (GET_CODE (op0) == NOT
4965 && GET_CODE (XEXP (op0, 0)) == XOR
4966 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4967 && ! side_effects_p (op1))
4968 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4970 if (GET_CODE (op1) == CONST_INT)
4972 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4974 /* If we have (ior (and (X C1) C2)) and the next restart would be
4975 the last, simplify this by making C1 as small as possible
4978 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4979 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4980 && GET_CODE (op1) == CONST_INT)
4981 return gen_binary (IOR, mode,
4982 gen_binary (AND, mode, XEXP (op0, 0),
4983 GEN_INT (INTVAL (XEXP (op0, 1))
4984 & ~ INTVAL (op1))), op1);
4986 if (GET_CODE (x) != AND)
4989 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4990 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4991 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4994 /* Convert (A | B) & A to A. */
4995 if (GET_CODE (op0) == IOR
4996 && (rtx_equal_p (XEXP (op0, 0), op1)
4997 || rtx_equal_p (XEXP (op0, 1), op1))
4998 && ! side_effects_p (XEXP (op0, 0))
4999 && ! side_effects_p (XEXP (op0, 1)))
5002 /* In the following group of tests (and those in case IOR below),
5003 we start with some combination of logical operations and apply
5004 the distributive law followed by the inverse distributive law.
5005 Most of the time, this results in no change. However, if some of
5006 the operands are the same or inverses of each other, simplifications
5009 For example, (and (ior A B) (not B)) can occur as the result of
5010 expanding a bit field assignment. When we apply the distributive
5011 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5012 which then simplifies to (and (A (not B))).
5014 If we have (and (ior A B) C), apply the distributive law and then
5015 the inverse distributive law to see if things simplify. */
5017 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5019 x = apply_distributive_law
5020 (gen_binary (GET_CODE (op0), mode,
5021 gen_binary (AND, mode, XEXP (op0, 0), op1),
5022 gen_binary (AND, mode, XEXP (op0, 1),
5024 if (GET_CODE (x) != AND)
5028 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5029 return apply_distributive_law
5030 (gen_binary (GET_CODE (op1), mode,
5031 gen_binary (AND, mode, XEXP (op1, 0), op0),
5032 gen_binary (AND, mode, XEXP (op1, 1),
5035 /* Similarly, taking advantage of the fact that
5036 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5038 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5039 return apply_distributive_law
5040 (gen_binary (XOR, mode,
5041 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5042 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5045 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5046 return apply_distributive_law
5047 (gen_binary (XOR, mode,
5048 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5049 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5053 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5054 if (GET_CODE (op1) == CONST_INT
5055 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5056 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
5059 /* Convert (A & B) | A to A. */
5060 if (GET_CODE (op0) == AND
5061 && (rtx_equal_p (XEXP (op0, 0), op1)
5062 || rtx_equal_p (XEXP (op0, 1), op1))
5063 && ! side_effects_p (XEXP (op0, 0))
5064 && ! side_effects_p (XEXP (op0, 1)))
5067 /* If we have (ior (and A B) C), apply the distributive law and then
5068 the inverse distributive law to see if things simplify. */
5070 if (GET_CODE (op0) == AND)
5072 x = apply_distributive_law
5073 (gen_binary (AND, mode,
5074 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5075 gen_binary (IOR, mode, XEXP (op0, 1),
5078 if (GET_CODE (x) != IOR)
5082 if (GET_CODE (op1) == AND)
5084 x = apply_distributive_law
5085 (gen_binary (AND, mode,
5086 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5087 gen_binary (IOR, mode, XEXP (op1, 1),
5090 if (GET_CODE (x) != IOR)
5094 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5095 mode size to (rotate A CX). */
5097 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5098 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5099 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5100 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5101 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5102 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5103 == GET_MODE_BITSIZE (mode)))
5104 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5105 (GET_CODE (op0) == ASHIFT
5106 ? XEXP (op0, 1) : XEXP (op1, 1)));
5108 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5109 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5110 does not affect any of the bits in OP1, it can really be done
5111 as a PLUS and we can associate. We do this by seeing if OP1
5112 can be safely shifted left C bits. */
5113 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5114 && GET_CODE (XEXP (op0, 0)) == PLUS
5115 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5116 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5117 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5119 int count = INTVAL (XEXP (op0, 1));
5120 HOST_WIDE_INT mask = INTVAL (op1) << count;
5122 if (mask >> count == INTVAL (op1)
5123 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5125 SUBST (XEXP (XEXP (op0, 0), 1),
5126 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5133 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5134 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5137 int num_negated = 0;
5139 if (GET_CODE (op0) == NOT)
5140 num_negated++, op0 = XEXP (op0, 0);
5141 if (GET_CODE (op1) == NOT)
5142 num_negated++, op1 = XEXP (op1, 0);
5144 if (num_negated == 2)
5146 SUBST (XEXP (x, 0), op0);
5147 SUBST (XEXP (x, 1), op1);
5149 else if (num_negated == 1)
5150 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5153 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5154 correspond to a machine insn or result in further simplifications
5155 if B is a constant. */
5157 if (GET_CODE (op0) == AND
5158 && rtx_equal_p (XEXP (op0, 1), op1)
5159 && ! side_effects_p (op1))
5160 return gen_binary (AND, mode,
5161 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5164 else if (GET_CODE (op0) == AND
5165 && rtx_equal_p (XEXP (op0, 0), op1)
5166 && ! side_effects_p (op1))
5167 return gen_binary (AND, mode,
5168 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5171 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5172 comparison if STORE_FLAG_VALUE is 1. */
5173 if (STORE_FLAG_VALUE == 1
5174 && op1 == const1_rtx
5175 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5176 && reversible_comparison_p (op0))
5177 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5178 mode, XEXP (op0, 0), XEXP (op0, 1));
5180 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5181 is (lt foo (const_int 0)), so we can perform the above
5182 simplification if STORE_FLAG_VALUE is 1. */
5184 if (STORE_FLAG_VALUE == 1
5185 && op1 == const1_rtx
5186 && GET_CODE (op0) == LSHIFTRT
5187 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5188 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5189 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5191 /* (xor (comparison foo bar) (const_int sign-bit))
5192 when STORE_FLAG_VALUE is the sign bit. */
5193 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5194 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5195 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5196 && op1 == const_true_rtx
5197 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5198 && reversible_comparison_p (op0))
5199 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5200 mode, XEXP (op0, 0), XEXP (op0, 1));
5210 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5211 operations" because they can be replaced with two more basic operations.
5212 ZERO_EXTEND is also considered "compound" because it can be replaced with
5213 an AND operation, which is simpler, though only one operation.
5215 The function expand_compound_operation is called with an rtx expression
5216 and will convert it to the appropriate shifts and AND operations,
5217 simplifying at each stage.
5219 The function make_compound_operation is called to convert an expression
5220 consisting of shifts and ANDs into the equivalent compound expression.
5221 It is the inverse of this function, loosely speaking. */
5224 expand_compound_operation (x)
5232 switch (GET_CODE (x))
5237 /* We can't necessarily use a const_int for a multiword mode;
5238 it depends on implicitly extending the value.
5239 Since we don't know the right way to extend it,
5240 we can't tell whether the implicit way is right.
5242 Even for a mode that is no wider than a const_int,
5243 we can't win, because we need to sign extend one of its bits through
5244 the rest of it, and we don't know which bit. */
5245 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5248 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5249 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5250 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5251 reloaded. If not for that, MEM's would very rarely be safe.
5253 Reject MODEs bigger than a word, because we might not be able
5254 to reference a two-register group starting with an arbitrary register
5255 (and currently gen_lowpart might crash for a SUBREG). */
5257 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5260 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5261 /* If the inner object has VOIDmode (the only way this can happen
5262 is if it is a ASM_OPERANDS), we can't do anything since we don't
5263 know how much masking to do. */
5272 /* If the operand is a CLOBBER, just return it. */
5273 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5276 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5277 || GET_CODE (XEXP (x, 2)) != CONST_INT
5278 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5281 len = INTVAL (XEXP (x, 1));
5282 pos = INTVAL (XEXP (x, 2));
5284 /* If this goes outside the object being extracted, replace the object
5285 with a (use (mem ...)) construct that only combine understands
5286 and is used only for this purpose. */
5287 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5288 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5290 if (BITS_BIG_ENDIAN)
5291 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5299 /* We can optimize some special cases of ZERO_EXTEND. */
5300 if (GET_CODE (x) == ZERO_EXTEND)
5302 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5303 know that the last value didn't have any inappropriate bits
5305 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5306 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5307 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5308 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5309 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5310 return XEXP (XEXP (x, 0), 0);
5312 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5313 if (GET_CODE (XEXP (x, 0)) == SUBREG
5314 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5315 && subreg_lowpart_p (XEXP (x, 0))
5316 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5317 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5318 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5319 return SUBREG_REG (XEXP (x, 0));
5321 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5322 is a comparison and STORE_FLAG_VALUE permits. This is like
5323 the first case, but it works even when GET_MODE (x) is larger
5324 than HOST_WIDE_INT. */
5325 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5326 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5327 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5328 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5329 <= HOST_BITS_PER_WIDE_INT)
5330 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5331 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5332 return XEXP (XEXP (x, 0), 0);
5334 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5335 if (GET_CODE (XEXP (x, 0)) == SUBREG
5336 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5337 && subreg_lowpart_p (XEXP (x, 0))
5338 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5339 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5340 <= HOST_BITS_PER_WIDE_INT)
5341 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5342 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5343 return SUBREG_REG (XEXP (x, 0));
5345 /* If sign extension is cheaper than zero extension, then use it
5346 if we know that no extraneous bits are set, and that the high
5348 if (flag_expensive_optimizations
5349 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5350 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5351 & ~ (((unsigned HOST_WIDE_INT)
5352 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5355 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5356 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5357 <= HOST_BITS_PER_WIDE_INT)
5358 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5359 & ~ (((unsigned HOST_WIDE_INT)
5360 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5364 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
5366 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5367 return expand_compound_operation (temp);
5371 /* If we reach here, we want to return a pair of shifts. The inner
5372 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5373 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5374 logical depending on the value of UNSIGNEDP.
5376 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5377 converted into an AND of a shift.
5379 We must check for the case where the left shift would have a negative
5380 count. This can happen in a case like (x >> 31) & 255 on machines
5381 that can't shift by a constant. On those machines, we would first
5382 combine the shift with the AND to produce a variable-position
5383 extraction. Then the constant of 31 would be substituted in to produce
5384 a such a position. */
5386 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5387 if (modewidth >= pos - len)
5388 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5390 simplify_shift_const (NULL_RTX, ASHIFT,
5393 modewidth - pos - len),
5396 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5397 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5398 simplify_shift_const (NULL_RTX, LSHIFTRT,
5401 ((HOST_WIDE_INT) 1 << len) - 1);
5403 /* Any other cases we can't handle. */
5407 /* If we couldn't do this for some reason, return the original
5409 if (GET_CODE (tem) == CLOBBER)
5415 /* X is a SET which contains an assignment of one object into
5416 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5417 or certain SUBREGS). If possible, convert it into a series of
5420 We half-heartedly support variable positions, but do not at all
5421 support variable lengths. */
5424 expand_field_assignment (x)
5428 rtx pos; /* Always counts from low bit. */
5431 enum machine_mode compute_mode;
5433 /* Loop until we find something we can't simplify. */
5436 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5437 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5439 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5440 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5441 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5443 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5444 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5446 inner = XEXP (SET_DEST (x), 0);
5447 len = INTVAL (XEXP (SET_DEST (x), 1));
5448 pos = XEXP (SET_DEST (x), 2);
5450 /* If the position is constant and spans the width of INNER,
5451 surround INNER with a USE to indicate this. */
5452 if (GET_CODE (pos) == CONST_INT
5453 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5454 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5456 if (BITS_BIG_ENDIAN)
5458 if (GET_CODE (pos) == CONST_INT)
5459 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5461 else if (GET_CODE (pos) == MINUS
5462 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5463 && (INTVAL (XEXP (pos, 1))
5464 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5465 /* If position is ADJUST - X, new position is X. */
5466 pos = XEXP (pos, 0);
5468 pos = gen_binary (MINUS, GET_MODE (pos),
5469 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5475 /* A SUBREG between two modes that occupy the same numbers of words
5476 can be done by moving the SUBREG to the source. */
5477 else if (GET_CODE (SET_DEST (x)) == SUBREG
5478 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5479 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5480 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5481 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5483 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5484 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5491 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5492 inner = SUBREG_REG (inner);
5494 compute_mode = GET_MODE (inner);
5496 /* Don't attempt bitwise arithmetic on non-integral modes. */
5497 if (! INTEGRAL_MODE_P (compute_mode))
5499 enum machine_mode imode;
5501 /* Something is probably seriously wrong if this matches. */
5502 if (! FLOAT_MODE_P (compute_mode))
5505 /* Try to find an integral mode to pun with. */
5506 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5507 if (imode == BLKmode)
5510 compute_mode = imode;
5511 inner = gen_lowpart_for_combine (imode, inner);
5514 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5515 if (len < HOST_BITS_PER_WIDE_INT)
5516 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5520 /* Now compute the equivalent expression. Make a copy of INNER
5521 for the SET_DEST in case it is a MEM into which we will substitute;
5522 we don't want shared RTL in that case. */
5523 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5524 gen_binary (IOR, compute_mode,
5525 gen_binary (AND, compute_mode,
5526 gen_unary (NOT, compute_mode,
5532 gen_binary (ASHIFT, compute_mode,
5533 gen_binary (AND, compute_mode,
5534 gen_lowpart_for_combine
5544 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5545 it is an RTX that represents a variable starting position; otherwise,
5546 POS is the (constant) starting bit position (counted from the LSB).
5548 INNER may be a USE. This will occur when we started with a bitfield
5549 that went outside the boundary of the object in memory, which is
5550 allowed on most machines. To isolate this case, we produce a USE
5551 whose mode is wide enough and surround the MEM with it. The only
5552 code that understands the USE is this routine. If it is not removed,
5553 it will cause the resulting insn not to match.
5555 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5558 IN_DEST is non-zero if this is a reference in the destination of a
5559 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5560 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5563 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5564 ZERO_EXTRACT should be built even for bits starting at bit 0.
5566 MODE is the desired mode of the result (if IN_DEST == 0).
5568 The result is an RTX for the extraction or NULL_RTX if the target
5572 make_extraction (mode, inner, pos, pos_rtx, len,
5573 unsignedp, in_dest, in_compare)
5574 enum machine_mode mode;
5580 int in_dest, in_compare;
5582 /* This mode describes the size of the storage area
5583 to fetch the overall value from. Within that, we
5584 ignore the POS lowest bits, etc. */
5585 enum machine_mode is_mode = GET_MODE (inner);
5586 enum machine_mode inner_mode;
5587 enum machine_mode wanted_inner_mode = byte_mode;
5588 enum machine_mode wanted_inner_reg_mode = word_mode;
5589 enum machine_mode pos_mode = word_mode;
5590 enum machine_mode extraction_mode = word_mode;
5591 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5594 rtx orig_pos_rtx = pos_rtx;
5597 /* Get some information about INNER and get the innermost object. */
5598 if (GET_CODE (inner) == USE)
5599 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5600 /* We don't need to adjust the position because we set up the USE
5601 to pretend that it was a full-word object. */
5602 spans_byte = 1, inner = XEXP (inner, 0);
5603 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5605 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5606 consider just the QI as the memory to extract from.
5607 The subreg adds or removes high bits; its mode is
5608 irrelevant to the meaning of this extraction,
5609 since POS and LEN count from the lsb. */
5610 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5611 is_mode = GET_MODE (SUBREG_REG (inner));
5612 inner = SUBREG_REG (inner);
5615 inner_mode = GET_MODE (inner);
5617 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5618 pos = INTVAL (pos_rtx), pos_rtx = 0;
5620 /* See if this can be done without an extraction. We never can if the
5621 width of the field is not the same as that of some integer mode. For
5622 registers, we can only avoid the extraction if the position is at the
5623 low-order bit and this is either not in the destination or we have the
5624 appropriate STRICT_LOW_PART operation available.
5626 For MEM, we can avoid an extract if the field starts on an appropriate
5627 boundary and we can change the mode of the memory reference. However,
5628 we cannot directly access the MEM if we have a USE and the underlying
5629 MEM is not TMODE. This combination means that MEM was being used in a
5630 context where bits outside its mode were being referenced; that is only
5631 valid in bit-field insns. */
5633 if (tmode != BLKmode
5634 && ! (spans_byte && inner_mode != tmode)
5635 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5636 && GET_CODE (inner) != MEM
5638 || (GET_CODE (inner) == REG
5639 && (movstrict_optab->handlers[(int) tmode].insn_code
5640 != CODE_FOR_nothing))))
5641 || (GET_CODE (inner) == MEM && pos_rtx == 0
5643 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5644 : BITS_PER_UNIT)) == 0
5645 /* We can't do this if we are widening INNER_MODE (it
5646 may not be aligned, for one thing). */
5647 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5648 && (inner_mode == tmode
5649 || (! mode_dependent_address_p (XEXP (inner, 0))
5650 && ! MEM_VOLATILE_P (inner))))))
5652 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5653 field. If the original and current mode are the same, we need not
5654 adjust the offset. Otherwise, we do if bytes big endian.
5656 If INNER is not a MEM, get a piece consisting of just the field
5657 of interest (in this case POS % BITS_PER_WORD must be 0). */
5659 if (GET_CODE (inner) == MEM)
5662 /* POS counts from lsb, but make OFFSET count in memory order. */
5663 if (BYTES_BIG_ENDIAN)
5664 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5666 offset = pos / BITS_PER_UNIT;
5668 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5669 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5670 MEM_COPY_ATTRIBUTES (new, inner);
5672 else if (GET_CODE (inner) == REG)
5674 /* We can't call gen_lowpart_for_combine here since we always want
5675 a SUBREG and it would sometimes return a new hard register. */
5676 if (tmode != inner_mode)
5677 new = gen_rtx_SUBREG (tmode, inner,
5679 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5680 ? (((GET_MODE_SIZE (inner_mode)
5681 - GET_MODE_SIZE (tmode))
5683 - pos / BITS_PER_WORD)
5684 : pos / BITS_PER_WORD));
5689 new = force_to_mode (inner, tmode,
5690 len >= HOST_BITS_PER_WIDE_INT
5691 ? GET_MODE_MASK (tmode)
5692 : ((HOST_WIDE_INT) 1 << len) - 1,
5695 /* If this extraction is going into the destination of a SET,
5696 make a STRICT_LOW_PART unless we made a MEM. */
5699 return (GET_CODE (new) == MEM ? new
5700 : (GET_CODE (new) != SUBREG
5701 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5702 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5704 /* Otherwise, sign- or zero-extend unless we already are in the
5707 return (mode == tmode ? new
5708 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5712 /* Unless this is a COMPARE or we have a funny memory reference,
5713 don't do anything with zero-extending field extracts starting at
5714 the low-order bit since they are simple AND operations. */
5715 if (pos_rtx == 0 && pos == 0 && ! in_dest
5716 && ! in_compare && ! spans_byte && unsignedp)
5719 /* Unless we are allowed to span bytes, reject this if we would be
5720 spanning bytes or if the position is not a constant and the length
5721 is not 1. In all other cases, we would only be going outside
5722 out object in cases when an original shift would have been
5725 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5726 || (pos_rtx != 0 && len != 1)))
5729 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5730 and the mode for the result. */
5734 wanted_inner_reg_mode
5735 = (insn_operand_mode[(int) CODE_FOR_insv][0] == VOIDmode
5737 : insn_operand_mode[(int) CODE_FOR_insv][0]);
5738 pos_mode = (insn_operand_mode[(int) CODE_FOR_insv][2] == VOIDmode
5739 ? word_mode : insn_operand_mode[(int) CODE_FOR_insv][2]);
5740 extraction_mode = (insn_operand_mode[(int) CODE_FOR_insv][3] == VOIDmode
5742 : insn_operand_mode[(int) CODE_FOR_insv][3]);
5747 if (! in_dest && unsignedp)
5749 wanted_inner_reg_mode
5750 = (insn_operand_mode[(int) CODE_FOR_extzv][1] == VOIDmode
5752 : insn_operand_mode[(int) CODE_FOR_extzv][1]);
5753 pos_mode = (insn_operand_mode[(int) CODE_FOR_extzv][3] == VOIDmode
5754 ? word_mode : insn_operand_mode[(int) CODE_FOR_extzv][3]);
5755 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extzv][0] == VOIDmode
5757 : insn_operand_mode[(int) CODE_FOR_extzv][0]);
5762 if (! in_dest && ! unsignedp)
5764 wanted_inner_reg_mode
5765 = (insn_operand_mode[(int) CODE_FOR_extv][1] == VOIDmode
5767 : insn_operand_mode[(int) CODE_FOR_extv][1]);
5768 pos_mode = (insn_operand_mode[(int) CODE_FOR_extv][3] == VOIDmode
5769 ? word_mode : insn_operand_mode[(int) CODE_FOR_extv][3]);
5770 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extv][0] == VOIDmode
5772 : insn_operand_mode[(int) CODE_FOR_extv][0]);
5776 /* Never narrow an object, since that might not be safe. */
5778 if (mode != VOIDmode
5779 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5780 extraction_mode = mode;
5782 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5783 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5784 pos_mode = GET_MODE (pos_rtx);
5786 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5787 if we have to change the mode of memory and cannot, the desired mode is
5789 if (GET_CODE (inner) != MEM)
5790 wanted_inner_mode = wanted_inner_reg_mode;
5791 else if (inner_mode != wanted_inner_mode
5792 && (mode_dependent_address_p (XEXP (inner, 0))
5793 || MEM_VOLATILE_P (inner)))
5794 wanted_inner_mode = extraction_mode;
5798 if (BITS_BIG_ENDIAN)
5800 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5801 BITS_BIG_ENDIAN style. If position is constant, compute new
5802 position. Otherwise, build subtraction.
5803 Note that POS is relative to the mode of the original argument.
5804 If it's a MEM we need to recompute POS relative to that.
5805 However, if we're extracting from (or inserting into) a register,
5806 we want to recompute POS relative to wanted_inner_mode. */
5807 int width = (GET_CODE (inner) == MEM
5808 ? GET_MODE_BITSIZE (is_mode)
5809 : GET_MODE_BITSIZE (wanted_inner_mode));
5812 pos = width - len - pos;
5815 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5816 GEN_INT (width - len), pos_rtx);
5817 /* POS may be less than 0 now, but we check for that below.
5818 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5821 /* If INNER has a wider mode, make it smaller. If this is a constant
5822 extract, try to adjust the byte to point to the byte containing
5824 if (wanted_inner_mode != VOIDmode
5825 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5826 && ((GET_CODE (inner) == MEM
5827 && (inner_mode == wanted_inner_mode
5828 || (! mode_dependent_address_p (XEXP (inner, 0))
5829 && ! MEM_VOLATILE_P (inner))))))
5833 /* The computations below will be correct if the machine is big
5834 endian in both bits and bytes or little endian in bits and bytes.
5835 If it is mixed, we must adjust. */
5837 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5838 adjust OFFSET to compensate. */
5839 if (BYTES_BIG_ENDIAN
5841 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5842 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5844 /* If this is a constant position, we can move to the desired byte. */
5847 offset += pos / BITS_PER_UNIT;
5848 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5851 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5853 && is_mode != wanted_inner_mode)
5854 offset = (GET_MODE_SIZE (is_mode)
5855 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5857 if (offset != 0 || inner_mode != wanted_inner_mode)
5859 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5860 plus_constant (XEXP (inner, 0), offset));
5861 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5862 MEM_COPY_ATTRIBUTES (newmem, inner);
5867 /* If INNER is not memory, we can always get it into the proper mode. If we
5868 are changing its mode, POS must be a constant and smaller than the size
5870 else if (GET_CODE (inner) != MEM)
5872 if (GET_MODE (inner) != wanted_inner_mode
5874 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5877 inner = force_to_mode (inner, wanted_inner_mode,
5879 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5880 ? GET_MODE_MASK (wanted_inner_mode)
5881 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5885 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5886 have to zero extend. Otherwise, we can just use a SUBREG. */
5888 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5889 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5890 else if (pos_rtx != 0
5891 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5892 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5894 /* Make POS_RTX unless we already have it and it is correct. If we don't
5895 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5897 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5898 pos_rtx = orig_pos_rtx;
5900 else if (pos_rtx == 0)
5901 pos_rtx = GEN_INT (pos);
5903 /* Make the required operation. See if we can use existing rtx. */
5904 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5905 extraction_mode, inner, GEN_INT (len), pos_rtx);
5907 new = gen_lowpart_for_combine (mode, new);
5912 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5913 with any other operations in X. Return X without that shift if so. */
5916 extract_left_shift (x, count)
5920 enum rtx_code code = GET_CODE (x);
5921 enum machine_mode mode = GET_MODE (x);
5927 /* This is the shift itself. If it is wide enough, we will return
5928 either the value being shifted if the shift count is equal to
5929 COUNT or a shift for the difference. */
5930 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5931 && INTVAL (XEXP (x, 1)) >= count)
5932 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5933 INTVAL (XEXP (x, 1)) - count);
5937 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5938 return gen_unary (code, mode, mode, tem);
5942 case PLUS: case IOR: case XOR: case AND:
5943 /* If we can safely shift this constant and we find the inner shift,
5944 make a new operation. */
5945 if (GET_CODE (XEXP (x,1)) == CONST_INT
5946 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
5947 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5948 return gen_binary (code, mode, tem,
5949 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5960 /* Look at the expression rooted at X. Look for expressions
5961 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5962 Form these expressions.
5964 Return the new rtx, usually just X.
5966 Also, for machines like the Vax that don't have logical shift insns,
5967 try to convert logical to arithmetic shift operations in cases where
5968 they are equivalent. This undoes the canonicalizations to logical
5969 shifts done elsewhere.
5971 We try, as much as possible, to re-use rtl expressions to save memory.
5973 IN_CODE says what kind of expression we are processing. Normally, it is
5974 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5975 being kludges), it is MEM. When processing the arguments of a comparison
5976 or a COMPARE against zero, it is COMPARE. */
5979 make_compound_operation (x, in_code)
5981 enum rtx_code in_code;
5983 enum rtx_code code = GET_CODE (x);
5984 enum machine_mode mode = GET_MODE (x);
5985 int mode_width = GET_MODE_BITSIZE (mode);
5987 enum rtx_code next_code;
5993 /* Select the code to be used in recursive calls. Once we are inside an
5994 address, we stay there. If we have a comparison, set to COMPARE,
5995 but once inside, go back to our default of SET. */
5997 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5998 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5999 && XEXP (x, 1) == const0_rtx) ? COMPARE
6000 : in_code == COMPARE ? SET : in_code);
6002 /* Process depending on the code of this operation. If NEW is set
6003 non-zero, it will be returned. */
6008 /* Convert shifts by constants into multiplications if inside
6010 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6011 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6012 && INTVAL (XEXP (x, 1)) >= 0)
6014 new = make_compound_operation (XEXP (x, 0), next_code);
6015 new = gen_rtx_combine (MULT, mode, new,
6016 GEN_INT ((HOST_WIDE_INT) 1
6017 << INTVAL (XEXP (x, 1))));
6022 /* If the second operand is not a constant, we can't do anything
6024 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6027 /* If the constant is a power of two minus one and the first operand
6028 is a logical right shift, make an extraction. */
6029 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6030 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6032 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6033 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6034 0, in_code == COMPARE);
6037 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6038 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6039 && subreg_lowpart_p (XEXP (x, 0))
6040 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6041 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6043 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6045 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6046 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6047 0, in_code == COMPARE);
6049 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6050 else if ((GET_CODE (XEXP (x, 0)) == XOR
6051 || GET_CODE (XEXP (x, 0)) == IOR)
6052 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6053 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6054 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6056 /* Apply the distributive law, and then try to make extractions. */
6057 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6058 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6060 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6062 new = make_compound_operation (new, in_code);
6065 /* If we are have (and (rotate X C) M) and C is larger than the number
6066 of bits in M, this is an extraction. */
6068 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6069 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6070 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6071 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6073 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6074 new = make_extraction (mode, new,
6075 (GET_MODE_BITSIZE (mode)
6076 - INTVAL (XEXP (XEXP (x, 0), 1))),
6077 NULL_RTX, i, 1, 0, in_code == COMPARE);
6080 /* On machines without logical shifts, if the operand of the AND is
6081 a logical shift and our mask turns off all the propagated sign
6082 bits, we can replace the logical shift with an arithmetic shift. */
6083 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6084 && (lshr_optab->handlers[(int) mode].insn_code
6085 == CODE_FOR_nothing)
6086 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6087 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6088 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6089 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6090 && mode_width <= HOST_BITS_PER_WIDE_INT)
6092 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6094 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6095 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6097 gen_rtx_combine (ASHIFTRT, mode,
6098 make_compound_operation (XEXP (XEXP (x, 0), 0),
6100 XEXP (XEXP (x, 0), 1)));
6103 /* If the constant is one less than a power of two, this might be
6104 representable by an extraction even if no shift is present.
6105 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6106 we are in a COMPARE. */
6107 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6108 new = make_extraction (mode,
6109 make_compound_operation (XEXP (x, 0),
6111 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6113 /* If we are in a comparison and this is an AND with a power of two,
6114 convert this into the appropriate bit extract. */
6115 else if (in_code == COMPARE
6116 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6117 new = make_extraction (mode,
6118 make_compound_operation (XEXP (x, 0),
6120 i, NULL_RTX, 1, 1, 0, 1);
6125 /* If the sign bit is known to be zero, replace this with an
6126 arithmetic shift. */
6127 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6128 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6129 && mode_width <= HOST_BITS_PER_WIDE_INT
6130 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6132 new = gen_rtx_combine (ASHIFTRT, mode,
6133 make_compound_operation (XEXP (x, 0),
6139 /* ... fall through ... */
6145 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6146 this is a SIGN_EXTRACT. */
6147 if (GET_CODE (rhs) == CONST_INT
6148 && GET_CODE (lhs) == ASHIFT
6149 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6150 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6152 new = make_compound_operation (XEXP (lhs, 0), next_code);
6153 new = make_extraction (mode, new,
6154 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6155 NULL_RTX, mode_width - INTVAL (rhs),
6156 code == LSHIFTRT, 0, in_code == COMPARE);
6159 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6160 If so, try to merge the shifts into a SIGN_EXTEND. We could
6161 also do this for some cases of SIGN_EXTRACT, but it doesn't
6162 seem worth the effort; the case checked for occurs on Alpha. */
6164 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6165 && ! (GET_CODE (lhs) == SUBREG
6166 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6167 && GET_CODE (rhs) == CONST_INT
6168 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6169 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6170 new = make_extraction (mode, make_compound_operation (new, next_code),
6171 0, NULL_RTX, mode_width - INTVAL (rhs),
6172 code == LSHIFTRT, 0, in_code == COMPARE);
6177 /* Call ourselves recursively on the inner expression. If we are
6178 narrowing the object and it has a different RTL code from
6179 what it originally did, do this SUBREG as a force_to_mode. */
6181 tem = make_compound_operation (SUBREG_REG (x), in_code);
6182 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6183 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6184 && subreg_lowpart_p (x))
6186 rtx newer = force_to_mode (tem, mode,
6187 GET_MODE_MASK (mode), NULL_RTX, 0);
6189 /* If we have something other than a SUBREG, we might have
6190 done an expansion, so rerun outselves. */
6191 if (GET_CODE (newer) != SUBREG)
6192 newer = make_compound_operation (newer, in_code);
6197 /* If this is a paradoxical subreg, and the new code is a sign or
6198 zero extension, omit the subreg and widen the extension. If it
6199 is a regular subreg, we can still get rid of the subreg by not
6200 widening so much, or in fact removing the extension entirely. */
6201 if ((GET_CODE (tem) == SIGN_EXTEND
6202 || GET_CODE (tem) == ZERO_EXTEND)
6203 && subreg_lowpart_p (x))
6205 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6206 || (GET_MODE_SIZE (mode) >
6207 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6208 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6210 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6221 x = gen_lowpart_for_combine (mode, new);
6222 code = GET_CODE (x);
6225 /* Now recursively process each operand of this operation. */
6226 fmt = GET_RTX_FORMAT (code);
6227 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6230 new = make_compound_operation (XEXP (x, i), next_code);
6231 SUBST (XEXP (x, i), new);
6237 /* Given M see if it is a value that would select a field of bits
6238 within an item, but not the entire word. Return -1 if not.
6239 Otherwise, return the starting position of the field, where 0 is the
6242 *PLEN is set to the length of the field. */
6245 get_pos_from_mask (m, plen)
6246 unsigned HOST_WIDE_INT m;
6249 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6250 int pos = exact_log2 (m & - m);
6255 /* Now shift off the low-order zero bits and see if we have a power of
6257 *plen = exact_log2 ((m >> pos) + 1);
6265 /* See if X can be simplified knowing that we will only refer to it in
6266 MODE and will only refer to those bits that are nonzero in MASK.
6267 If other bits are being computed or if masking operations are done
6268 that select a superset of the bits in MASK, they can sometimes be
6271 Return a possibly simplified expression, but always convert X to
6272 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6274 Also, if REG is non-zero and X is a register equal in value to REG,
6277 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6278 are all off in X. This is used when X will be complemented, by either
6279 NOT, NEG, or XOR. */
6282 force_to_mode (x, mode, mask, reg, just_select)
6284 enum machine_mode mode;
6285 unsigned HOST_WIDE_INT mask;
6289 enum rtx_code code = GET_CODE (x);
6290 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6291 enum machine_mode op_mode;
6292 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6295 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6296 code below will do the wrong thing since the mode of such an
6297 expression is VOIDmode.
6299 Also do nothing if X is a CLOBBER; this can happen if X was
6300 the return value from a call to gen_lowpart_for_combine. */
6301 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6304 /* We want to perform the operation is its present mode unless we know
6305 that the operation is valid in MODE, in which case we do the operation
6307 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6308 && code_to_optab[(int) code] != 0
6309 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6310 != CODE_FOR_nothing))
6311 ? mode : GET_MODE (x));
6313 /* It is not valid to do a right-shift in a narrower mode
6314 than the one it came in with. */
6315 if ((code == LSHIFTRT || code == ASHIFTRT)
6316 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6317 op_mode = GET_MODE (x);
6319 /* Truncate MASK to fit OP_MODE. */
6321 mask &= GET_MODE_MASK (op_mode);
6323 /* When we have an arithmetic operation, or a shift whose count we
6324 do not know, we need to assume that all bit the up to the highest-order
6325 bit in MASK will be needed. This is how we form such a mask. */
6327 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6328 ? GET_MODE_MASK (op_mode)
6329 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6331 fuller_mask = ~ (HOST_WIDE_INT) 0;
6333 /* Determine what bits of X are guaranteed to be (non)zero. */
6334 nonzero = nonzero_bits (x, mode);
6336 /* If none of the bits in X are needed, return a zero. */
6337 if (! just_select && (nonzero & mask) == 0)
6340 /* If X is a CONST_INT, return a new one. Do this here since the
6341 test below will fail. */
6342 if (GET_CODE (x) == CONST_INT)
6344 HOST_WIDE_INT cval = INTVAL (x) & mask;
6345 int width = GET_MODE_BITSIZE (mode);
6347 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6348 number, sign extend it. */
6349 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6350 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6351 cval |= (HOST_WIDE_INT) -1 << width;
6353 return GEN_INT (cval);
6356 /* If X is narrower than MODE and we want all the bits in X's mode, just
6357 get X in the proper mode. */
6358 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6359 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6360 return gen_lowpart_for_combine (mode, x);
6362 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6363 MASK are already known to be zero in X, we need not do anything. */
6364 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6370 /* If X is a (clobber (const_int)), return it since we know we are
6371 generating something that won't match. */
6375 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6376 spanned the boundary of the MEM. If we are now masking so it is
6377 within that boundary, we don't need the USE any more. */
6378 if (! BITS_BIG_ENDIAN
6379 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6380 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6387 x = expand_compound_operation (x);
6388 if (GET_CODE (x) != code)
6389 return force_to_mode (x, mode, mask, reg, next_select);
6393 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6394 || rtx_equal_p (reg, get_last_value (x))))
6399 if (subreg_lowpart_p (x)
6400 /* We can ignore the effect of this SUBREG if it narrows the mode or
6401 if the constant masks to zero all the bits the mode doesn't
6403 && ((GET_MODE_SIZE (GET_MODE (x))
6404 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6406 & GET_MODE_MASK (GET_MODE (x))
6407 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6408 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6412 /* If this is an AND with a constant, convert it into an AND
6413 whose constant is the AND of that constant with MASK. If it
6414 remains an AND of MASK, delete it since it is redundant. */
6416 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6418 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6419 mask & INTVAL (XEXP (x, 1)));
6421 /* If X is still an AND, see if it is an AND with a mask that
6422 is just some low-order bits. If so, and it is MASK, we don't
6425 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6426 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6429 /* If it remains an AND, try making another AND with the bits
6430 in the mode mask that aren't in MASK turned on. If the
6431 constant in the AND is wide enough, this might make a
6432 cheaper constant. */
6434 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6435 && GET_MODE_MASK (GET_MODE (x)) != mask
6436 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6438 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6439 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6440 int width = GET_MODE_BITSIZE (GET_MODE (x));
6443 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6444 number, sign extend it. */
6445 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6446 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6447 cval |= (HOST_WIDE_INT) -1 << width;
6449 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6450 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6460 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6461 low-order bits (as in an alignment operation) and FOO is already
6462 aligned to that boundary, mask C1 to that boundary as well.
6463 This may eliminate that PLUS and, later, the AND. */
6466 int width = GET_MODE_BITSIZE (mode);
6467 unsigned HOST_WIDE_INT smask = mask;
6469 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6470 number, sign extend it. */
6472 if (width < HOST_BITS_PER_WIDE_INT
6473 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6474 smask |= (HOST_WIDE_INT) -1 << width;
6476 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6477 && exact_log2 (- smask) >= 0)
6481 && (XEXP (x, 0) == stack_pointer_rtx
6482 || XEXP (x, 0) == frame_pointer_rtx))
6484 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6485 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6487 sp_mask &= ~ (sp_alignment - 1);
6488 if ((sp_mask & ~ smask) == 0
6489 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6490 return force_to_mode (plus_constant (XEXP (x, 0),
6491 ((INTVAL (XEXP (x, 1)) -
6492 STACK_BIAS) & smask)
6494 mode, smask, reg, next_select);
6497 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6498 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6499 return force_to_mode (plus_constant (XEXP (x, 0),
6500 (INTVAL (XEXP (x, 1))
6502 mode, smask, reg, next_select);
6506 /* ... fall through ... */
6510 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6511 most significant bit in MASK since carries from those bits will
6512 affect the bits we are interested in. */
6518 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6519 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6520 operation which may be a bitfield extraction. Ensure that the
6521 constant we form is not wider than the mode of X. */
6523 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6524 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6525 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6526 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6527 && GET_CODE (XEXP (x, 1)) == CONST_INT
6528 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6529 + floor_log2 (INTVAL (XEXP (x, 1))))
6530 < GET_MODE_BITSIZE (GET_MODE (x)))
6531 && (INTVAL (XEXP (x, 1))
6532 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6534 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6535 << INTVAL (XEXP (XEXP (x, 0), 1)));
6536 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6537 XEXP (XEXP (x, 0), 0), temp);
6538 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6539 XEXP (XEXP (x, 0), 1));
6540 return force_to_mode (x, mode, mask, reg, next_select);
6544 /* For most binary operations, just propagate into the operation and
6545 change the mode if we have an operation of that mode. */
6547 op0 = gen_lowpart_for_combine (op_mode,
6548 force_to_mode (XEXP (x, 0), mode, mask,
6550 op1 = gen_lowpart_for_combine (op_mode,
6551 force_to_mode (XEXP (x, 1), mode, mask,
6554 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6555 MASK since OP1 might have been sign-extended but we never want
6556 to turn on extra bits, since combine might have previously relied
6557 on them being off. */
6558 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6559 && (INTVAL (op1) & mask) != 0)
6560 op1 = GEN_INT (INTVAL (op1) & mask);
6562 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6563 x = gen_binary (code, op_mode, op0, op1);
6567 /* For left shifts, do the same, but just for the first operand.
6568 However, we cannot do anything with shifts where we cannot
6569 guarantee that the counts are smaller than the size of the mode
6570 because such a count will have a different meaning in a
6573 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6574 && INTVAL (XEXP (x, 1)) >= 0
6575 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6576 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6577 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6578 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6581 /* If the shift count is a constant and we can do arithmetic in
6582 the mode of the shift, refine which bits we need. Otherwise, use the
6583 conservative form of the mask. */
6584 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6585 && INTVAL (XEXP (x, 1)) >= 0
6586 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6587 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6588 mask >>= INTVAL (XEXP (x, 1));
6592 op0 = gen_lowpart_for_combine (op_mode,
6593 force_to_mode (XEXP (x, 0), op_mode,
6594 mask, reg, next_select));
6596 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6597 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6601 /* Here we can only do something if the shift count is a constant,
6602 this shift constant is valid for the host, and we can do arithmetic
6605 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6606 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6607 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6609 rtx inner = XEXP (x, 0);
6611 /* Select the mask of the bits we need for the shift operand. */
6612 mask <<= INTVAL (XEXP (x, 1));
6614 /* We can only change the mode of the shift if we can do arithmetic
6615 in the mode of the shift and MASK is no wider than the width of
6617 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6618 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6619 op_mode = GET_MODE (x);
6621 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6623 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6624 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6627 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6628 shift and AND produces only copies of the sign bit (C2 is one less
6629 than a power of two), we can do this with just a shift. */
6631 if (GET_CODE (x) == LSHIFTRT
6632 && GET_CODE (XEXP (x, 1)) == CONST_INT
6633 && ((INTVAL (XEXP (x, 1))
6634 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6635 >= GET_MODE_BITSIZE (GET_MODE (x)))
6636 && exact_log2 (mask + 1) >= 0
6637 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6638 >= exact_log2 (mask + 1)))
6639 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6640 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6641 - exact_log2 (mask + 1)));
6645 /* If we are just looking for the sign bit, we don't need this shift at
6646 all, even if it has a variable count. */
6647 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6648 && (mask == ((unsigned HOST_WIDE_INT) 1
6649 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6650 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6652 /* If this is a shift by a constant, get a mask that contains those bits
6653 that are not copies of the sign bit. We then have two cases: If
6654 MASK only includes those bits, this can be a logical shift, which may
6655 allow simplifications. If MASK is a single-bit field not within
6656 those bits, we are requesting a copy of the sign bit and hence can
6657 shift the sign bit to the appropriate location. */
6659 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6660 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6664 /* If the considered data is wider then HOST_WIDE_INT, we can't
6665 represent a mask for all its bits in a single scalar.
6666 But we only care about the lower bits, so calculate these. */
6668 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6670 nonzero = ~ (HOST_WIDE_INT) 0;
6672 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6673 is the number of bits a full-width mask would have set.
6674 We need only shift if these are fewer than nonzero can
6675 hold. If not, we must keep all bits set in nonzero. */
6677 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6678 < HOST_BITS_PER_WIDE_INT)
6679 nonzero >>= INTVAL (XEXP (x, 1))
6680 + HOST_BITS_PER_WIDE_INT
6681 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6685 nonzero = GET_MODE_MASK (GET_MODE (x));
6686 nonzero >>= INTVAL (XEXP (x, 1));
6689 if ((mask & ~ nonzero) == 0
6690 || (i = exact_log2 (mask)) >= 0)
6692 x = simplify_shift_const
6693 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6694 i < 0 ? INTVAL (XEXP (x, 1))
6695 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6697 if (GET_CODE (x) != ASHIFTRT)
6698 return force_to_mode (x, mode, mask, reg, next_select);
6702 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6703 even if the shift count isn't a constant. */
6705 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6707 /* If this is a sign-extension operation that just affects bits
6708 we don't care about, remove it. Be sure the call above returned
6709 something that is still a shift. */
6711 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6712 && GET_CODE (XEXP (x, 1)) == CONST_INT
6713 && INTVAL (XEXP (x, 1)) >= 0
6714 && (INTVAL (XEXP (x, 1))
6715 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6716 && GET_CODE (XEXP (x, 0)) == ASHIFT
6717 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6718 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6719 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6726 /* If the shift count is constant and we can do computations
6727 in the mode of X, compute where the bits we care about are.
6728 Otherwise, we can't do anything. Don't change the mode of
6729 the shift or propagate MODE into the shift, though. */
6730 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6731 && INTVAL (XEXP (x, 1)) >= 0)
6733 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6734 GET_MODE (x), GEN_INT (mask),
6736 if (temp && GET_CODE(temp) == CONST_INT)
6738 force_to_mode (XEXP (x, 0), GET_MODE (x),
6739 INTVAL (temp), reg, next_select));
6744 /* If we just want the low-order bit, the NEG isn't needed since it
6745 won't change the low-order bit. */
6747 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6749 /* We need any bits less significant than the most significant bit in
6750 MASK since carries from those bits will affect the bits we are
6756 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6757 same as the XOR case above. Ensure that the constant we form is not
6758 wider than the mode of X. */
6760 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6761 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6762 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6763 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6764 < GET_MODE_BITSIZE (GET_MODE (x)))
6765 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6767 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6768 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6769 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6771 return force_to_mode (x, mode, mask, reg, next_select);
6774 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6775 use the full mask inside the NOT. */
6779 op0 = gen_lowpart_for_combine (op_mode,
6780 force_to_mode (XEXP (x, 0), mode, mask,
6782 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6783 x = gen_unary (code, op_mode, op_mode, op0);
6787 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6788 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6789 which is equal to STORE_FLAG_VALUE. */
6790 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6791 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6792 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6793 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6798 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6799 written in a narrower mode. We play it safe and do not do so. */
6802 gen_lowpart_for_combine (GET_MODE (x),
6803 force_to_mode (XEXP (x, 1), mode,
6804 mask, reg, next_select)));
6806 gen_lowpart_for_combine (GET_MODE (x),
6807 force_to_mode (XEXP (x, 2), mode,
6808 mask, reg,next_select)));
6815 /* Ensure we return a value of the proper mode. */
6816 return gen_lowpart_for_combine (mode, x);
6819 /* Return nonzero if X is an expression that has one of two values depending on
6820 whether some other value is zero or nonzero. In that case, we return the
6821 value that is being tested, *PTRUE is set to the value if the rtx being
6822 returned has a nonzero value, and *PFALSE is set to the other alternative.
6824 If we return zero, we set *PTRUE and *PFALSE to X. */
6827 if_then_else_cond (x, ptrue, pfalse)
6829 rtx *ptrue, *pfalse;
6831 enum machine_mode mode = GET_MODE (x);
6832 enum rtx_code code = GET_CODE (x);
6833 int size = GET_MODE_BITSIZE (mode);
6834 rtx cond0, cond1, true0, true1, false0, false1;
6835 unsigned HOST_WIDE_INT nz;
6837 /* If this is a unary operation whose operand has one of two values, apply
6838 our opcode to compute those values. */
6839 if (GET_RTX_CLASS (code) == '1'
6840 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6842 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6843 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6847 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6848 make can't possibly match and would suppress other optimizations. */
6849 else if (code == COMPARE)
6852 /* If this is a binary operation, see if either side has only one of two
6853 values. If either one does or if both do and they are conditional on
6854 the same value, compute the new true and false values. */
6855 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6856 || GET_RTX_CLASS (code) == '<')
6858 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6859 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6861 if ((cond0 != 0 || cond1 != 0)
6862 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6864 /* If if_then_else_cond returned zero, then true/false are the
6865 same rtl. We must copy one of them to prevent invalid rtl
6868 true0 = copy_rtx (true0);
6869 else if (cond1 == 0)
6870 true1 = copy_rtx (true1);
6872 *ptrue = gen_binary (code, mode, true0, true1);
6873 *pfalse = gen_binary (code, mode, false0, false1);
6874 return cond0 ? cond0 : cond1;
6877 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6878 operands is zero when the other is non-zero, and vice-versa,
6879 and STORE_FLAG_VALUE is 1 or -1. */
6881 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6882 && (code == PLUS || code == IOR || code == XOR || code == MINUS
6884 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6886 rtx op0 = XEXP (XEXP (x, 0), 1);
6887 rtx op1 = XEXP (XEXP (x, 1), 1);
6889 cond0 = XEXP (XEXP (x, 0), 0);
6890 cond1 = XEXP (XEXP (x, 1), 0);
6892 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6893 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6894 && reversible_comparison_p (cond1)
6895 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6896 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6897 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6898 || ((swap_condition (GET_CODE (cond0))
6899 == reverse_condition (GET_CODE (cond1)))
6900 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6901 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6902 && ! side_effects_p (x))
6904 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6905 *pfalse = gen_binary (MULT, mode,
6907 ? gen_unary (NEG, mode, mode, op1) : op1),
6913 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6915 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6916 && (code == MULT || code == AND || code == UMIN)
6917 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6919 cond0 = XEXP (XEXP (x, 0), 0);
6920 cond1 = XEXP (XEXP (x, 1), 0);
6922 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6923 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6924 && reversible_comparison_p (cond1)
6925 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6926 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6927 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6928 || ((swap_condition (GET_CODE (cond0))
6929 == reverse_condition (GET_CODE (cond1)))
6930 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6931 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6932 && ! side_effects_p (x))
6934 *ptrue = *pfalse = const0_rtx;
6940 else if (code == IF_THEN_ELSE)
6942 /* If we have IF_THEN_ELSE already, extract the condition and
6943 canonicalize it if it is NE or EQ. */
6944 cond0 = XEXP (x, 0);
6945 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6946 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6947 return XEXP (cond0, 0);
6948 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6950 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6951 return XEXP (cond0, 0);
6957 /* If X is a normal SUBREG with both inner and outer modes integral,
6958 we can narrow both the true and false values of the inner expression,
6959 if there is a condition. */
6960 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6961 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6962 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6963 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6966 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6968 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6973 /* If X is a constant, this isn't special and will cause confusions
6974 if we treat it as such. Likewise if it is equivalent to a constant. */
6975 else if (CONSTANT_P (x)
6976 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6979 /* If X is known to be either 0 or -1, those are the true and
6980 false values when testing X. */
6981 else if (num_sign_bit_copies (x, mode) == size)
6983 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6987 /* Likewise for 0 or a single bit. */
6988 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6990 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6994 /* Otherwise fail; show no condition with true and false values the same. */
6995 *ptrue = *pfalse = x;
6999 /* Return the value of expression X given the fact that condition COND
7000 is known to be true when applied to REG as its first operand and VAL
7001 as its second. X is known to not be shared and so can be modified in
7004 We only handle the simplest cases, and specifically those cases that
7005 arise with IF_THEN_ELSE expressions. */
7008 known_cond (x, cond, reg, val)
7013 enum rtx_code code = GET_CODE (x);
7018 if (side_effects_p (x))
7021 if (cond == EQ && rtx_equal_p (x, reg))
7024 /* If X is (abs REG) and we know something about REG's relationship
7025 with zero, we may be able to simplify this. */
7027 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7030 case GE: case GT: case EQ:
7033 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7039 /* The only other cases we handle are MIN, MAX, and comparisons if the
7040 operands are the same as REG and VAL. */
7042 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7044 if (rtx_equal_p (XEXP (x, 0), val))
7045 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7047 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7049 if (GET_RTX_CLASS (code) == '<')
7050 return (comparison_dominates_p (cond, code) ? const_true_rtx
7051 : (comparison_dominates_p (cond,
7052 reverse_condition (code))
7055 else if (code == SMAX || code == SMIN
7056 || code == UMIN || code == UMAX)
7058 int unsignedp = (code == UMIN || code == UMAX);
7060 if (code == SMAX || code == UMAX)
7061 cond = reverse_condition (cond);
7066 return unsignedp ? x : XEXP (x, 1);
7068 return unsignedp ? x : XEXP (x, 0);
7070 return unsignedp ? XEXP (x, 1) : x;
7072 return unsignedp ? XEXP (x, 0) : x;
7080 fmt = GET_RTX_FORMAT (code);
7081 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7084 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7085 else if (fmt[i] == 'E')
7086 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7087 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7094 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7095 assignment as a field assignment. */
7098 rtx_equal_for_field_assignment_p (x, y)
7102 if (x == y || rtx_equal_p (x, y))
7105 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7108 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7109 Note that all SUBREGs of MEM are paradoxical; otherwise they
7110 would have been rewritten. */
7111 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7112 && GET_CODE (SUBREG_REG (y)) == MEM
7113 && rtx_equal_p (SUBREG_REG (y),
7114 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7117 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7118 && GET_CODE (SUBREG_REG (x)) == MEM
7119 && rtx_equal_p (SUBREG_REG (x),
7120 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7123 /* We used to see if get_last_value of X and Y were the same but that's
7124 not correct. In one direction, we'll cause the assignment to have
7125 the wrong destination and in the case, we'll import a register into this
7126 insn that might have already have been dead. So fail if none of the
7127 above cases are true. */
7131 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7132 Return that assignment if so.
7134 We only handle the most common cases. */
7137 make_field_assignment (x)
7140 rtx dest = SET_DEST (x);
7141 rtx src = SET_SRC (x);
7147 enum machine_mode mode;
7149 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7150 a clear of a one-bit field. We will have changed it to
7151 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7154 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7155 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7156 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7157 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7159 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7162 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7166 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7167 && subreg_lowpart_p (XEXP (src, 0))
7168 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7169 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7170 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7171 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7172 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7174 assign = make_extraction (VOIDmode, dest, 0,
7175 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7178 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7182 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7184 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7185 && XEXP (XEXP (src, 0), 0) == const1_rtx
7186 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7188 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7191 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7195 /* The other case we handle is assignments into a constant-position
7196 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7197 a mask that has all one bits except for a group of zero bits and
7198 OTHER is known to have zeros where C1 has ones, this is such an
7199 assignment. Compute the position and length from C1. Shift OTHER
7200 to the appropriate position, force it to the required mode, and
7201 make the extraction. Check for the AND in both operands. */
7203 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7206 rhs = expand_compound_operation (XEXP (src, 0));
7207 lhs = expand_compound_operation (XEXP (src, 1));
7209 if (GET_CODE (rhs) == AND
7210 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7211 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7212 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7213 else if (GET_CODE (lhs) == AND
7214 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7215 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7216 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7220 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7221 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7222 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7223 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7226 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7230 /* The mode to use for the source is the mode of the assignment, or of
7231 what is inside a possible STRICT_LOW_PART. */
7232 mode = (GET_CODE (assign) == STRICT_LOW_PART
7233 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7235 /* Shift OTHER right POS places and make it the source, restricting it
7236 to the proper length and mode. */
7238 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7239 GET_MODE (src), other, pos),
7241 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7242 ? GET_MODE_MASK (mode)
7243 : ((HOST_WIDE_INT) 1 << len) - 1,
7246 return gen_rtx_combine (SET, VOIDmode, assign, src);
7249 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7253 apply_distributive_law (x)
7256 enum rtx_code code = GET_CODE (x);
7257 rtx lhs, rhs, other;
7259 enum rtx_code inner_code;
7261 /* Distributivity is not true for floating point.
7262 It can change the value. So don't do it.
7263 -- rms and moshier@world.std.com. */
7264 if (FLOAT_MODE_P (GET_MODE (x)))
7267 /* The outer operation can only be one of the following: */
7268 if (code != IOR && code != AND && code != XOR
7269 && code != PLUS && code != MINUS)
7272 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7274 /* If either operand is a primitive we can't do anything, so get out
7276 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7277 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7280 lhs = expand_compound_operation (lhs);
7281 rhs = expand_compound_operation (rhs);
7282 inner_code = GET_CODE (lhs);
7283 if (inner_code != GET_CODE (rhs))
7286 /* See if the inner and outer operations distribute. */
7293 /* These all distribute except over PLUS. */
7294 if (code == PLUS || code == MINUS)
7299 if (code != PLUS && code != MINUS)
7304 /* This is also a multiply, so it distributes over everything. */
7308 /* Non-paradoxical SUBREGs distributes over all operations, provided
7309 the inner modes and word numbers are the same, this is an extraction
7310 of a low-order part, we don't convert an fp operation to int or
7311 vice versa, and we would not be converting a single-word
7312 operation into a multi-word operation. The latter test is not
7313 required, but it prevents generating unneeded multi-word operations.
7314 Some of the previous tests are redundant given the latter test, but
7315 are retained because they are required for correctness.
7317 We produce the result slightly differently in this case. */
7319 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7320 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7321 || ! subreg_lowpart_p (lhs)
7322 || (GET_MODE_CLASS (GET_MODE (lhs))
7323 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7324 || (GET_MODE_SIZE (GET_MODE (lhs))
7325 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7326 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7329 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7330 SUBREG_REG (lhs), SUBREG_REG (rhs));
7331 return gen_lowpart_for_combine (GET_MODE (x), tem);
7337 /* Set LHS and RHS to the inner operands (A and B in the example
7338 above) and set OTHER to the common operand (C in the example).
7339 These is only one way to do this unless the inner operation is
7341 if (GET_RTX_CLASS (inner_code) == 'c'
7342 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7343 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7344 else if (GET_RTX_CLASS (inner_code) == 'c'
7345 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7346 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7347 else if (GET_RTX_CLASS (inner_code) == 'c'
7348 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7349 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7350 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7351 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7355 /* Form the new inner operation, seeing if it simplifies first. */
7356 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7358 /* There is one exception to the general way of distributing:
7359 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7360 if (code == XOR && inner_code == IOR)
7363 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7366 /* We may be able to continuing distributing the result, so call
7367 ourselves recursively on the inner operation before forming the
7368 outer operation, which we return. */
7369 return gen_binary (inner_code, GET_MODE (x),
7370 apply_distributive_law (tem), other);
7373 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7376 Return an equivalent form, if different from X. Otherwise, return X. If
7377 X is zero, we are to always construct the equivalent form. */
7380 simplify_and_const_int (x, mode, varop, constop)
7382 enum machine_mode mode;
7384 unsigned HOST_WIDE_INT constop;
7386 unsigned HOST_WIDE_INT nonzero;
7387 int width = GET_MODE_BITSIZE (mode);
7390 /* Simplify VAROP knowing that we will be only looking at some of the
7392 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7394 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7395 CONST_INT, we are done. */
7396 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7399 /* See what bits may be nonzero in VAROP. Unlike the general case of
7400 a call to nonzero_bits, here we don't care about bits outside
7403 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7405 /* If this would be an entire word for the target, but is not for
7406 the host, then sign-extend on the host so that the number will look
7407 the same way on the host that it would on the target.
7409 For example, when building a 64 bit alpha hosted 32 bit sparc
7410 targeted compiler, then we want the 32 bit unsigned value -1 to be
7411 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7412 The later confuses the sparc backend. */
7414 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7415 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7416 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7418 /* Turn off all bits in the constant that are known to already be zero.
7419 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7420 which is tested below. */
7424 /* If we don't have any bits left, return zero. */
7428 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7429 a power of two, we can replace this with a ASHIFT. */
7430 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7431 && (i = exact_log2 (constop)) >= 0)
7432 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7434 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7435 or XOR, then try to apply the distributive law. This may eliminate
7436 operations if either branch can be simplified because of the AND.
7437 It may also make some cases more complex, but those cases probably
7438 won't match a pattern either with or without this. */
7440 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7442 gen_lowpart_for_combine
7444 apply_distributive_law
7445 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7446 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7447 XEXP (varop, 0), constop),
7448 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7449 XEXP (varop, 1), constop))));
7451 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7452 if we already had one (just check for the simplest cases). */
7453 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7454 && GET_MODE (XEXP (x, 0)) == mode
7455 && SUBREG_REG (XEXP (x, 0)) == varop)
7456 varop = XEXP (x, 0);
7458 varop = gen_lowpart_for_combine (mode, varop);
7460 /* If we can't make the SUBREG, try to return what we were given. */
7461 if (GET_CODE (varop) == CLOBBER)
7462 return x ? x : varop;
7464 /* If we are only masking insignificant bits, return VAROP. */
7465 if (constop == nonzero)
7468 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7469 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7470 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7474 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7475 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7476 SUBST (XEXP (x, 1), GEN_INT (constop));
7478 SUBST (XEXP (x, 0), varop);
7484 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7485 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7486 is less useful. We can't allow both, because that results in exponential
7487 run time recursion. There is a nullstone testcase that triggered
7488 this. This macro avoids accidental uses of num_sign_bit_copies. */
7489 #define num_sign_bit_copies()
7491 /* Given an expression, X, compute which bits in X can be non-zero.
7492 We don't care about bits outside of those defined in MODE.
7494 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7495 a shift, AND, or zero_extract, we can do better. */
7497 static unsigned HOST_WIDE_INT
7498 nonzero_bits (x, mode)
7500 enum machine_mode mode;
7502 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7503 unsigned HOST_WIDE_INT inner_nz;
7505 int mode_width = GET_MODE_BITSIZE (mode);
7508 /* For floating-point values, assume all bits are needed. */
7509 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7512 /* If X is wider than MODE, use its mode instead. */
7513 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7515 mode = GET_MODE (x);
7516 nonzero = GET_MODE_MASK (mode);
7517 mode_width = GET_MODE_BITSIZE (mode);
7520 if (mode_width > HOST_BITS_PER_WIDE_INT)
7521 /* Our only callers in this case look for single bit values. So
7522 just return the mode mask. Those tests will then be false. */
7525 #ifndef WORD_REGISTER_OPERATIONS
7526 /* If MODE is wider than X, but both are a single word for both the host
7527 and target machines, we can compute this from which bits of the
7528 object might be nonzero in its own mode, taking into account the fact
7529 that on many CISC machines, accessing an object in a wider mode
7530 causes the high-order bits to become undefined. So they are
7531 not known to be zero. */
7533 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7534 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7535 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7536 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7538 nonzero &= nonzero_bits (x, GET_MODE (x));
7539 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7544 code = GET_CODE (x);
7548 #ifdef POINTERS_EXTEND_UNSIGNED
7549 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7550 all the bits above ptr_mode are known to be zero. */
7551 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7552 && REGNO_POINTER_FLAG (REGNO (x)))
7553 nonzero &= GET_MODE_MASK (ptr_mode);
7556 #ifdef STACK_BOUNDARY
7557 /* If this is the stack pointer, we may know something about its
7558 alignment. If PUSH_ROUNDING is defined, it is possible for the
7559 stack to be momentarily aligned only to that amount, so we pick
7560 the least alignment. */
7562 /* We can't check for arg_pointer_rtx here, because it is not
7563 guaranteed to have as much alignment as the stack pointer.
7564 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7565 alignment but the argument pointer has only 64 bit alignment. */
7567 if ((x == frame_pointer_rtx
7568 || x == stack_pointer_rtx
7569 || x == hard_frame_pointer_rtx
7570 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7571 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7577 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7579 #ifdef PUSH_ROUNDING
7580 if (REGNO (x) == STACK_POINTER_REGNUM)
7581 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7584 /* We must return here, otherwise we may get a worse result from
7585 one of the choices below. There is nothing useful below as
7586 far as the stack pointer is concerned. */
7587 return nonzero &= ~ (sp_alignment - 1);
7591 /* If X is a register whose nonzero bits value is current, use it.
7592 Otherwise, if X is a register whose value we can find, use that
7593 value. Otherwise, use the previously-computed global nonzero bits
7594 for this register. */
7596 if (reg_last_set_value[REGNO (x)] != 0
7597 && reg_last_set_mode[REGNO (x)] == mode
7598 && (reg_last_set_label[REGNO (x)] == label_tick
7599 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7600 && REG_N_SETS (REGNO (x)) == 1
7601 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7603 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7604 return reg_last_set_nonzero_bits[REGNO (x)];
7606 tem = get_last_value (x);
7610 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7611 /* If X is narrower than MODE and TEM is a non-negative
7612 constant that would appear negative in the mode of X,
7613 sign-extend it for use in reg_nonzero_bits because some
7614 machines (maybe most) will actually do the sign-extension
7615 and this is the conservative approach.
7617 ??? For 2.5, try to tighten up the MD files in this regard
7618 instead of this kludge. */
7620 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7621 && GET_CODE (tem) == CONST_INT
7623 && 0 != (INTVAL (tem)
7624 & ((HOST_WIDE_INT) 1
7625 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7626 tem = GEN_INT (INTVAL (tem)
7627 | ((HOST_WIDE_INT) (-1)
7628 << GET_MODE_BITSIZE (GET_MODE (x))));
7630 return nonzero_bits (tem, mode);
7632 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7633 return reg_nonzero_bits[REGNO (x)] & nonzero;
7638 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7639 /* If X is negative in MODE, sign-extend the value. */
7640 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7641 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7642 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7648 #ifdef LOAD_EXTEND_OP
7649 /* In many, if not most, RISC machines, reading a byte from memory
7650 zeros the rest of the register. Noticing that fact saves a lot
7651 of extra zero-extends. */
7652 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7653 nonzero &= GET_MODE_MASK (GET_MODE (x));
7663 /* If this produces an integer result, we know which bits are set.
7664 Code here used to clear bits outside the mode of X, but that is
7667 if (GET_MODE_CLASS (mode) == MODE_INT
7668 && mode_width <= HOST_BITS_PER_WIDE_INT)
7669 nonzero = STORE_FLAG_VALUE;
7674 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7675 and num_sign_bit_copies. */
7676 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7677 == GET_MODE_BITSIZE (GET_MODE (x)))
7681 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7682 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7687 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7688 and num_sign_bit_copies. */
7689 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7690 == GET_MODE_BITSIZE (GET_MODE (x)))
7696 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7700 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7701 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7702 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7706 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7707 Otherwise, show all the bits in the outer mode but not the inner
7709 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7710 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7712 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7714 & (((HOST_WIDE_INT) 1
7715 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7716 inner_nz |= (GET_MODE_MASK (mode)
7717 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7720 nonzero &= inner_nz;
7724 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7725 & nonzero_bits (XEXP (x, 1), mode));
7729 case UMIN: case UMAX: case SMIN: case SMAX:
7730 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7731 | nonzero_bits (XEXP (x, 1), mode));
7734 case PLUS: case MINUS:
7736 case DIV: case UDIV:
7737 case MOD: case UMOD:
7738 /* We can apply the rules of arithmetic to compute the number of
7739 high- and low-order zero bits of these operations. We start by
7740 computing the width (position of the highest-order non-zero bit)
7741 and the number of low-order zero bits for each value. */
7743 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7744 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7745 int width0 = floor_log2 (nz0) + 1;
7746 int width1 = floor_log2 (nz1) + 1;
7747 int low0 = floor_log2 (nz0 & -nz0);
7748 int low1 = floor_log2 (nz1 & -nz1);
7749 HOST_WIDE_INT op0_maybe_minusp
7750 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7751 HOST_WIDE_INT op1_maybe_minusp
7752 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7753 int result_width = mode_width;
7761 && (XEXP (x, 0) == stack_pointer_rtx
7762 || XEXP (x, 0) == frame_pointer_rtx)
7763 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7765 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7767 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7768 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7769 width0 = floor_log2 (nz0) + 1;
7770 width1 = floor_log2 (nz1) + 1;
7771 low0 = floor_log2 (nz0 & -nz0);
7772 low1 = floor_log2 (nz1 & -nz1);
7775 result_width = MAX (width0, width1) + 1;
7776 result_low = MIN (low0, low1);
7779 result_low = MIN (low0, low1);
7782 result_width = width0 + width1;
7783 result_low = low0 + low1;
7786 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7787 result_width = width0;
7790 result_width = width0;
7793 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7794 result_width = MIN (width0, width1);
7795 result_low = MIN (low0, low1);
7798 result_width = MIN (width0, width1);
7799 result_low = MIN (low0, low1);
7805 if (result_width < mode_width)
7806 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7809 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7814 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7815 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7816 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7820 /* If this is a SUBREG formed for a promoted variable that has
7821 been zero-extended, we know that at least the high-order bits
7822 are zero, though others might be too. */
7824 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7825 nonzero = (GET_MODE_MASK (GET_MODE (x))
7826 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7828 /* If the inner mode is a single word for both the host and target
7829 machines, we can compute this from which bits of the inner
7830 object might be nonzero. */
7831 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7832 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7833 <= HOST_BITS_PER_WIDE_INT))
7835 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7837 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7838 /* If this is a typical RISC machine, we only have to worry
7839 about the way loads are extended. */
7840 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7842 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7843 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
7846 /* On many CISC machines, accessing an object in a wider mode
7847 causes the high-order bits to become undefined. So they are
7848 not known to be zero. */
7849 if (GET_MODE_SIZE (GET_MODE (x))
7850 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7851 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7852 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7861 /* The nonzero bits are in two classes: any bits within MODE
7862 that aren't in GET_MODE (x) are always significant. The rest of the
7863 nonzero bits are those that are significant in the operand of
7864 the shift when shifted the appropriate number of bits. This
7865 shows that high-order bits are cleared by the right shift and
7866 low-order bits by left shifts. */
7867 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7868 && INTVAL (XEXP (x, 1)) >= 0
7869 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7871 enum machine_mode inner_mode = GET_MODE (x);
7872 int width = GET_MODE_BITSIZE (inner_mode);
7873 int count = INTVAL (XEXP (x, 1));
7874 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7875 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7876 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7877 unsigned HOST_WIDE_INT outer = 0;
7879 if (mode_width > width)
7880 outer = (op_nonzero & nonzero & ~ mode_mask);
7882 if (code == LSHIFTRT)
7884 else if (code == ASHIFTRT)
7888 /* If the sign bit may have been nonzero before the shift, we
7889 need to mark all the places it could have been copied to
7890 by the shift as possibly nonzero. */
7891 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7892 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7894 else if (code == ASHIFT)
7897 inner = ((inner << (count % width)
7898 | (inner >> (width - (count % width)))) & mode_mask);
7900 nonzero &= (outer | inner);
7905 /* This is at most the number of bits in the mode. */
7906 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7910 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7911 | nonzero_bits (XEXP (x, 2), mode));
7921 /* See the macro definition above. */
7922 #undef num_sign_bit_copies
7924 /* Return the number of bits at the high-order end of X that are known to
7925 be equal to the sign bit. X will be used in mode MODE; if MODE is
7926 VOIDmode, X will be used in its own mode. The returned value will always
7927 be between 1 and the number of bits in MODE. */
7930 num_sign_bit_copies (x, mode)
7932 enum machine_mode mode;
7934 enum rtx_code code = GET_CODE (x);
7936 int num0, num1, result;
7937 unsigned HOST_WIDE_INT nonzero;
7940 /* If we weren't given a mode, use the mode of X. If the mode is still
7941 VOIDmode, we don't know anything. Likewise if one of the modes is
7944 if (mode == VOIDmode)
7945 mode = GET_MODE (x);
7947 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7950 bitwidth = GET_MODE_BITSIZE (mode);
7952 /* For a smaller object, just ignore the high bits. */
7953 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7954 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7955 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7957 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7959 #ifndef WORD_REGISTER_OPERATIONS
7960 /* If this machine does not do all register operations on the entire
7961 register and MODE is wider than the mode of X, we can say nothing
7962 at all about the high-order bits. */
7965 /* Likewise on machines that do, if the mode of the object is smaller
7966 than a word and loads of that size don't sign extend, we can say
7967 nothing about the high order bits. */
7968 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7969 #ifdef LOAD_EXTEND_OP
7970 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7981 #ifdef POINTERS_EXTEND_UNSIGNED
7982 /* If pointers extend signed and this is a pointer in Pmode, say that
7983 all the bits above ptr_mode are known to be sign bit copies. */
7984 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7985 && REGNO_POINTER_FLAG (REGNO (x)))
7986 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7989 if (reg_last_set_value[REGNO (x)] != 0
7990 && reg_last_set_mode[REGNO (x)] == mode
7991 && (reg_last_set_label[REGNO (x)] == label_tick
7992 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7993 && REG_N_SETS (REGNO (x)) == 1
7994 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7996 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7997 return reg_last_set_sign_bit_copies[REGNO (x)];
7999 tem = get_last_value (x);
8001 return num_sign_bit_copies (tem, mode);
8003 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8004 return reg_sign_bit_copies[REGNO (x)];
8008 #ifdef LOAD_EXTEND_OP
8009 /* Some RISC machines sign-extend all loads of smaller than a word. */
8010 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8011 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
8016 /* If the constant is negative, take its 1's complement and remask.
8017 Then see how many zero bits we have. */
8018 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8019 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8020 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8021 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
8023 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8026 /* If this is a SUBREG for a promoted object that is sign-extended
8027 and we are looking at it in a wider mode, we know that at least the
8028 high-order bits are known to be sign bit copies. */
8030 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8031 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8032 num_sign_bit_copies (SUBREG_REG (x), mode));
8034 /* For a smaller object, just ignore the high bits. */
8035 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8037 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8038 return MAX (1, (num0
8039 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8043 #ifdef WORD_REGISTER_OPERATIONS
8044 #ifdef LOAD_EXTEND_OP
8045 /* For paradoxical SUBREGs on machines where all register operations
8046 affect the entire register, just look inside. Note that we are
8047 passing MODE to the recursive call, so the number of sign bit copies
8048 will remain relative to that mode, not the inner mode. */
8050 /* This works only if loads sign extend. Otherwise, if we get a
8051 reload for the inner part, it may be loaded from the stack, and
8052 then we lose all sign bit copies that existed before the store
8055 if ((GET_MODE_SIZE (GET_MODE (x))
8056 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8057 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8058 return num_sign_bit_copies (SUBREG_REG (x), mode);
8064 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8065 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
8069 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8070 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8073 /* For a smaller object, just ignore the high bits. */
8074 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8075 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8079 return num_sign_bit_copies (XEXP (x, 0), mode);
8081 case ROTATE: case ROTATERT:
8082 /* If we are rotating left by a number of bits less than the number
8083 of sign bit copies, we can just subtract that amount from the
8085 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8086 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8088 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8089 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8090 : bitwidth - INTVAL (XEXP (x, 1))));
8095 /* In general, this subtracts one sign bit copy. But if the value
8096 is known to be positive, the number of sign bit copies is the
8097 same as that of the input. Finally, if the input has just one bit
8098 that might be nonzero, all the bits are copies of the sign bit. */
8099 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8100 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8101 return num0 > 1 ? num0 - 1 : 1;
8103 nonzero = nonzero_bits (XEXP (x, 0), mode);
8108 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8113 case IOR: case AND: case XOR:
8114 case SMIN: case SMAX: case UMIN: case UMAX:
8115 /* Logical operations will preserve the number of sign-bit copies.
8116 MIN and MAX operations always return one of the operands. */
8117 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8118 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8119 return MIN (num0, num1);
8121 case PLUS: case MINUS:
8122 /* For addition and subtraction, we can have a 1-bit carry. However,
8123 if we are subtracting 1 from a positive number, there will not
8124 be such a carry. Furthermore, if the positive number is known to
8125 be 0 or 1, we know the result is either -1 or 0. */
8127 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8128 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8130 nonzero = nonzero_bits (XEXP (x, 0), mode);
8131 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8132 return (nonzero == 1 || nonzero == 0 ? bitwidth
8133 : bitwidth - floor_log2 (nonzero) - 1);
8136 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8137 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8138 return MAX (1, MIN (num0, num1) - 1);
8141 /* The number of bits of the product is the sum of the number of
8142 bits of both terms. However, unless one of the terms if known
8143 to be positive, we must allow for an additional bit since negating
8144 a negative number can remove one sign bit copy. */
8146 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8147 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8149 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8151 && (bitwidth > HOST_BITS_PER_WIDE_INT
8152 || (((nonzero_bits (XEXP (x, 0), mode)
8153 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8154 && ((nonzero_bits (XEXP (x, 1), mode)
8155 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8158 return MAX (1, result);
8161 /* The result must be <= the first operand. If the first operand
8162 has the high bit set, we know nothing about the number of sign
8164 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8166 else if ((nonzero_bits (XEXP (x, 0), mode)
8167 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8170 return num_sign_bit_copies (XEXP (x, 0), mode);
8173 /* The result must be <= the scond operand. */
8174 return num_sign_bit_copies (XEXP (x, 1), mode);
8177 /* Similar to unsigned division, except that we have to worry about
8178 the case where the divisor is negative, in which case we have
8180 result = num_sign_bit_copies (XEXP (x, 0), mode);
8182 && (bitwidth > HOST_BITS_PER_WIDE_INT
8183 || (nonzero_bits (XEXP (x, 1), mode)
8184 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8190 result = num_sign_bit_copies (XEXP (x, 1), mode);
8192 && (bitwidth > HOST_BITS_PER_WIDE_INT
8193 || (nonzero_bits (XEXP (x, 1), mode)
8194 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8200 /* Shifts by a constant add to the number of bits equal to the
8202 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8203 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8204 && INTVAL (XEXP (x, 1)) > 0)
8205 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8210 /* Left shifts destroy copies. */
8211 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8212 || INTVAL (XEXP (x, 1)) < 0
8213 || INTVAL (XEXP (x, 1)) >= bitwidth)
8216 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8217 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8220 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8221 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8222 return MIN (num0, num1);
8224 case EQ: case NE: case GE: case GT: case LE: case LT:
8225 case GEU: case GTU: case LEU: case LTU:
8226 if (STORE_FLAG_VALUE == -1)
8234 /* If we haven't been able to figure it out by one of the above rules,
8235 see if some of the high-order bits are known to be zero. If so,
8236 count those bits and return one less than that amount. If we can't
8237 safely compute the mask for this mode, always return BITWIDTH. */
8239 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8242 nonzero = nonzero_bits (x, mode);
8243 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8244 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8247 /* Return the number of "extended" bits there are in X, when interpreted
8248 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8249 unsigned quantities, this is the number of high-order zero bits.
8250 For signed quantities, this is the number of copies of the sign bit
8251 minus 1. In both case, this function returns the number of "spare"
8252 bits. For example, if two quantities for which this function returns
8253 at least 1 are added, the addition is known not to overflow.
8255 This function will always return 0 unless called during combine, which
8256 implies that it must be called from a define_split. */
8259 extended_count (x, mode, unsignedp)
8261 enum machine_mode mode;
8264 if (nonzero_sign_valid == 0)
8268 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8269 && (GET_MODE_BITSIZE (mode) - 1
8270 - floor_log2 (nonzero_bits (x, mode))))
8271 : num_sign_bit_copies (x, mode) - 1);
8274 /* This function is called from `simplify_shift_const' to merge two
8275 outer operations. Specifically, we have already found that we need
8276 to perform operation *POP0 with constant *PCONST0 at the outermost
8277 position. We would now like to also perform OP1 with constant CONST1
8278 (with *POP0 being done last).
8280 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8281 the resulting operation. *PCOMP_P is set to 1 if we would need to
8282 complement the innermost operand, otherwise it is unchanged.
8284 MODE is the mode in which the operation will be done. No bits outside
8285 the width of this mode matter. It is assumed that the width of this mode
8286 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8288 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8289 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8290 result is simply *PCONST0.
8292 If the resulting operation cannot be expressed as one operation, we
8293 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8296 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8297 enum rtx_code *pop0;
8298 HOST_WIDE_INT *pconst0;
8300 HOST_WIDE_INT const1;
8301 enum machine_mode mode;
8304 enum rtx_code op0 = *pop0;
8305 HOST_WIDE_INT const0 = *pconst0;
8306 int width = GET_MODE_BITSIZE (mode);
8308 const0 &= GET_MODE_MASK (mode);
8309 const1 &= GET_MODE_MASK (mode);
8311 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8315 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8318 if (op1 == NIL || op0 == SET)
8321 else if (op0 == NIL)
8322 op0 = op1, const0 = const1;
8324 else if (op0 == op1)
8348 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8349 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8352 /* If the two constants aren't the same, we can't do anything. The
8353 remaining six cases can all be done. */
8354 else if (const0 != const1)
8362 /* (a & b) | b == b */
8364 else /* op1 == XOR */
8365 /* (a ^ b) | b == a | b */
8371 /* (a & b) ^ b == (~a) & b */
8372 op0 = AND, *pcomp_p = 1;
8373 else /* op1 == IOR */
8374 /* (a | b) ^ b == a & ~b */
8375 op0 = AND, *pconst0 = ~ const0;
8380 /* (a | b) & b == b */
8382 else /* op1 == XOR */
8383 /* (a ^ b) & b) == (~a) & b */
8390 /* Check for NO-OP cases. */
8391 const0 &= GET_MODE_MASK (mode);
8393 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8395 else if (const0 == 0 && op0 == AND)
8397 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8401 /* If this would be an entire word for the target, but is not for
8402 the host, then sign-extend on the host so that the number will look
8403 the same way on the host that it would on the target.
8405 For example, when building a 64 bit alpha hosted 32 bit sparc
8406 targeted compiler, then we want the 32 bit unsigned value -1 to be
8407 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8408 The later confuses the sparc backend. */
8410 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8411 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8412 const0 |= ((HOST_WIDE_INT) (-1) << width);
8420 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8421 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8422 that we started with.
8424 The shift is normally computed in the widest mode we find in VAROP, as
8425 long as it isn't a different number of words than RESULT_MODE. Exceptions
8426 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8429 simplify_shift_const (x, code, result_mode, varop, count)
8432 enum machine_mode result_mode;
8436 enum rtx_code orig_code = code;
8437 int orig_count = count;
8438 enum machine_mode mode = result_mode;
8439 enum machine_mode shift_mode, tmode;
8441 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8442 /* We form (outer_op (code varop count) (outer_const)). */
8443 enum rtx_code outer_op = NIL;
8444 HOST_WIDE_INT outer_const = 0;
8446 int complement_p = 0;
8449 /* If we were given an invalid count, don't do anything except exactly
8450 what was requested. */
8452 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8457 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
8460 /* Unless one of the branches of the `if' in this loop does a `continue',
8461 we will `break' the loop after the `if'. */
8465 /* If we have an operand of (clobber (const_int 0)), just return that
8467 if (GET_CODE (varop) == CLOBBER)
8470 /* If we discovered we had to complement VAROP, leave. Making a NOT
8471 here would cause an infinite loop. */
8475 /* Convert ROTATERT to ROTATE. */
8476 if (code == ROTATERT)
8477 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8479 /* We need to determine what mode we will do the shift in. If the
8480 shift is a right shift or a ROTATE, we must always do it in the mode
8481 it was originally done in. Otherwise, we can do it in MODE, the
8482 widest mode encountered. */
8484 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8485 ? result_mode : mode);
8487 /* Handle cases where the count is greater than the size of the mode
8488 minus 1. For ASHIFT, use the size minus one as the count (this can
8489 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8490 take the count modulo the size. For other shifts, the result is
8493 Since these shifts are being produced by the compiler by combining
8494 multiple operations, each of which are defined, we know what the
8495 result is supposed to be. */
8497 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8499 if (code == ASHIFTRT)
8500 count = GET_MODE_BITSIZE (shift_mode) - 1;
8501 else if (code == ROTATE || code == ROTATERT)
8502 count %= GET_MODE_BITSIZE (shift_mode);
8505 /* We can't simply return zero because there may be an
8513 /* Negative counts are invalid and should not have been made (a
8514 programmer-specified negative count should have been handled
8519 /* An arithmetic right shift of a quantity known to be -1 or 0
8521 if (code == ASHIFTRT
8522 && (num_sign_bit_copies (varop, shift_mode)
8523 == GET_MODE_BITSIZE (shift_mode)))
8529 /* If we are doing an arithmetic right shift and discarding all but
8530 the sign bit copies, this is equivalent to doing a shift by the
8531 bitsize minus one. Convert it into that shift because it will often
8532 allow other simplifications. */
8534 if (code == ASHIFTRT
8535 && (count + num_sign_bit_copies (varop, shift_mode)
8536 >= GET_MODE_BITSIZE (shift_mode)))
8537 count = GET_MODE_BITSIZE (shift_mode) - 1;
8539 /* We simplify the tests below and elsewhere by converting
8540 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8541 `make_compound_operation' will convert it to a ASHIFTRT for
8542 those machines (such as Vax) that don't have a LSHIFTRT. */
8543 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8545 && ((nonzero_bits (varop, shift_mode)
8546 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8550 switch (GET_CODE (varop))
8556 new = expand_compound_operation (varop);
8565 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8566 minus the width of a smaller mode, we can do this with a
8567 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8568 if ((code == ASHIFTRT || code == LSHIFTRT)
8569 && ! mode_dependent_address_p (XEXP (varop, 0))
8570 && ! MEM_VOLATILE_P (varop)
8571 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8572 MODE_INT, 1)) != BLKmode)
8574 if (BYTES_BIG_ENDIAN)
8575 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8577 new = gen_rtx_MEM (tmode,
8578 plus_constant (XEXP (varop, 0),
8579 count / BITS_PER_UNIT));
8580 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8581 MEM_COPY_ATTRIBUTES (new, varop);
8582 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8583 : ZERO_EXTEND, mode, new);
8590 /* Similar to the case above, except that we can only do this if
8591 the resulting mode is the same as that of the underlying
8592 MEM and adjust the address depending on the *bits* endianness
8593 because of the way that bit-field extract insns are defined. */
8594 if ((code == ASHIFTRT || code == LSHIFTRT)
8595 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8596 MODE_INT, 1)) != BLKmode
8597 && tmode == GET_MODE (XEXP (varop, 0)))
8599 if (BITS_BIG_ENDIAN)
8600 new = XEXP (varop, 0);
8603 new = copy_rtx (XEXP (varop, 0));
8604 SUBST (XEXP (new, 0),
8605 plus_constant (XEXP (new, 0),
8606 count / BITS_PER_UNIT));
8609 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8610 : ZERO_EXTEND, mode, new);
8617 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8618 the same number of words as what we've seen so far. Then store
8619 the widest mode in MODE. */
8620 if (subreg_lowpart_p (varop)
8621 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8622 > GET_MODE_SIZE (GET_MODE (varop)))
8623 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8624 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8627 varop = SUBREG_REG (varop);
8628 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8629 mode = GET_MODE (varop);
8635 /* Some machines use MULT instead of ASHIFT because MULT
8636 is cheaper. But it is still better on those machines to
8637 merge two shifts into one. */
8638 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8639 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8641 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8642 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8648 /* Similar, for when divides are cheaper. */
8649 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8650 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8652 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8653 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8659 /* If we are extracting just the sign bit of an arithmetic right
8660 shift, that shift is not needed. */
8661 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8663 varop = XEXP (varop, 0);
8667 /* ... fall through ... */
8672 /* Here we have two nested shifts. The result is usually the
8673 AND of a new shift with a mask. We compute the result below. */
8674 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8675 && INTVAL (XEXP (varop, 1)) >= 0
8676 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8677 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8678 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8680 enum rtx_code first_code = GET_CODE (varop);
8681 int first_count = INTVAL (XEXP (varop, 1));
8682 unsigned HOST_WIDE_INT mask;
8685 /* We have one common special case. We can't do any merging if
8686 the inner code is an ASHIFTRT of a smaller mode. However, if
8687 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8688 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8689 we can convert it to
8690 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8691 This simplifies certain SIGN_EXTEND operations. */
8692 if (code == ASHIFT && first_code == ASHIFTRT
8693 && (GET_MODE_BITSIZE (result_mode)
8694 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8696 /* C3 has the low-order C1 bits zero. */
8698 mask = (GET_MODE_MASK (mode)
8699 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8701 varop = simplify_and_const_int (NULL_RTX, result_mode,
8702 XEXP (varop, 0), mask);
8703 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8705 count = first_count;
8710 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8711 than C1 high-order bits equal to the sign bit, we can convert
8712 this to either an ASHIFT or a ASHIFTRT depending on the
8715 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8717 if (code == ASHIFTRT && first_code == ASHIFT
8718 && GET_MODE (varop) == shift_mode
8719 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8722 count -= first_count;
8724 count = - count, code = ASHIFT;
8725 varop = XEXP (varop, 0);
8729 /* There are some cases we can't do. If CODE is ASHIFTRT,
8730 we can only do this if FIRST_CODE is also ASHIFTRT.
8732 We can't do the case when CODE is ROTATE and FIRST_CODE is
8735 If the mode of this shift is not the mode of the outer shift,
8736 we can't do this if either shift is a right shift or ROTATE.
8738 Finally, we can't do any of these if the mode is too wide
8739 unless the codes are the same.
8741 Handle the case where the shift codes are the same
8744 if (code == first_code)
8746 if (GET_MODE (varop) != result_mode
8747 && (code == ASHIFTRT || code == LSHIFTRT
8751 count += first_count;
8752 varop = XEXP (varop, 0);
8756 if (code == ASHIFTRT
8757 || (code == ROTATE && first_code == ASHIFTRT)
8758 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8759 || (GET_MODE (varop) != result_mode
8760 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8761 || first_code == ROTATE
8762 || code == ROTATE)))
8765 /* To compute the mask to apply after the shift, shift the
8766 nonzero bits of the inner shift the same way the
8767 outer shift will. */
8769 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8772 = simplify_binary_operation (code, result_mode, mask_rtx,
8775 /* Give up if we can't compute an outer operation to use. */
8777 || GET_CODE (mask_rtx) != CONST_INT
8778 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8780 result_mode, &complement_p))
8783 /* If the shifts are in the same direction, we add the
8784 counts. Otherwise, we subtract them. */
8785 if ((code == ASHIFTRT || code == LSHIFTRT)
8786 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8787 count += first_count;
8789 count -= first_count;
8791 /* If COUNT is positive, the new shift is usually CODE,
8792 except for the two exceptions below, in which case it is
8793 FIRST_CODE. If the count is negative, FIRST_CODE should
8796 && ((first_code == ROTATE && code == ASHIFT)
8797 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8800 code = first_code, count = - count;
8802 varop = XEXP (varop, 0);
8806 /* If we have (A << B << C) for any shift, we can convert this to
8807 (A << C << B). This wins if A is a constant. Only try this if
8808 B is not a constant. */
8810 else if (GET_CODE (varop) == code
8811 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8813 = simplify_binary_operation (code, mode,
8817 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8824 /* Make this fit the case below. */
8825 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8826 GEN_INT (GET_MODE_MASK (mode)));
8832 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8833 with C the size of VAROP - 1 and the shift is logical if
8834 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8835 we have an (le X 0) operation. If we have an arithmetic shift
8836 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8837 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8839 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8840 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8841 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8842 && (code == LSHIFTRT || code == ASHIFTRT)
8843 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8844 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8847 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8850 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8851 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8856 /* If we have (shift (logical)), move the logical to the outside
8857 to allow it to possibly combine with another logical and the
8858 shift to combine with another shift. This also canonicalizes to
8859 what a ZERO_EXTRACT looks like. Also, some machines have
8860 (and (shift)) insns. */
8862 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8863 && (new = simplify_binary_operation (code, result_mode,
8865 GEN_INT (count))) != 0
8866 && GET_CODE(new) == CONST_INT
8867 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8868 INTVAL (new), result_mode, &complement_p))
8870 varop = XEXP (varop, 0);
8874 /* If we can't do that, try to simplify the shift in each arm of the
8875 logical expression, make a new logical expression, and apply
8876 the inverse distributive law. */
8878 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8879 XEXP (varop, 0), count);
8880 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8881 XEXP (varop, 1), count);
8883 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8884 varop = apply_distributive_law (varop);
8891 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8892 says that the sign bit can be tested, FOO has mode MODE, C is
8893 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8894 that may be nonzero. */
8895 if (code == LSHIFTRT
8896 && XEXP (varop, 1) == const0_rtx
8897 && GET_MODE (XEXP (varop, 0)) == result_mode
8898 && count == GET_MODE_BITSIZE (result_mode) - 1
8899 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8900 && ((STORE_FLAG_VALUE
8901 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8902 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8903 && merge_outer_ops (&outer_op, &outer_const, XOR,
8904 (HOST_WIDE_INT) 1, result_mode,
8907 varop = XEXP (varop, 0);
8914 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8915 than the number of bits in the mode is equivalent to A. */
8916 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8917 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8919 varop = XEXP (varop, 0);
8924 /* NEG commutes with ASHIFT since it is multiplication. Move the
8925 NEG outside to allow shifts to combine. */
8927 && merge_outer_ops (&outer_op, &outer_const, NEG,
8928 (HOST_WIDE_INT) 0, result_mode,
8931 varop = XEXP (varop, 0);
8937 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8938 is one less than the number of bits in the mode is
8939 equivalent to (xor A 1). */
8940 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8941 && XEXP (varop, 1) == constm1_rtx
8942 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8943 && merge_outer_ops (&outer_op, &outer_const, XOR,
8944 (HOST_WIDE_INT) 1, result_mode,
8948 varop = XEXP (varop, 0);
8952 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8953 that might be nonzero in BAR are those being shifted out and those
8954 bits are known zero in FOO, we can replace the PLUS with FOO.
8955 Similarly in the other operand order. This code occurs when
8956 we are computing the size of a variable-size array. */
8958 if ((code == ASHIFTRT || code == LSHIFTRT)
8959 && count < HOST_BITS_PER_WIDE_INT
8960 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8961 && (nonzero_bits (XEXP (varop, 1), result_mode)
8962 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8964 varop = XEXP (varop, 0);
8967 else if ((code == ASHIFTRT || code == LSHIFTRT)
8968 && count < HOST_BITS_PER_WIDE_INT
8969 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8970 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8972 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8973 & nonzero_bits (XEXP (varop, 1),
8976 varop = XEXP (varop, 1);
8980 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8982 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8983 && (new = simplify_binary_operation (ASHIFT, result_mode,
8985 GEN_INT (count))) != 0
8986 && GET_CODE(new) == CONST_INT
8987 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8988 INTVAL (new), result_mode, &complement_p))
8990 varop = XEXP (varop, 0);
8996 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8997 with C the size of VAROP - 1 and the shift is logical if
8998 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8999 we have a (gt X 0) operation. If the shift is arithmetic with
9000 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9001 we have a (neg (gt X 0)) operation. */
9003 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9004 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9005 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9006 && (code == LSHIFTRT || code == ASHIFTRT)
9007 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9008 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9009 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9012 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9015 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9016 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9023 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9024 if the truncate does not affect the value. */
9025 if (code == LSHIFTRT
9026 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9027 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9028 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9029 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9030 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9032 rtx varop_inner = XEXP (varop, 0);
9034 varop_inner = gen_rtx_combine (LSHIFTRT,
9035 GET_MODE (varop_inner),
9036 XEXP (varop_inner, 0),
9037 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
9038 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9052 /* We need to determine what mode to do the shift in. If the shift is
9053 a right shift or ROTATE, we must always do it in the mode it was
9054 originally done in. Otherwise, we can do it in MODE, the widest mode
9055 encountered. The code we care about is that of the shift that will
9056 actually be done, not the shift that was originally requested. */
9058 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9059 ? result_mode : mode);
9061 /* We have now finished analyzing the shift. The result should be
9062 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9063 OUTER_OP is non-NIL, it is an operation that needs to be applied
9064 to the result of the shift. OUTER_CONST is the relevant constant,
9065 but we must turn off all bits turned off in the shift.
9067 If we were passed a value for X, see if we can use any pieces of
9068 it. If not, make new rtx. */
9070 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9071 && GET_CODE (XEXP (x, 1)) == CONST_INT
9072 && INTVAL (XEXP (x, 1)) == count)
9073 const_rtx = XEXP (x, 1);
9075 const_rtx = GEN_INT (count);
9077 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9078 && GET_MODE (XEXP (x, 0)) == shift_mode
9079 && SUBREG_REG (XEXP (x, 0)) == varop)
9080 varop = XEXP (x, 0);
9081 else if (GET_MODE (varop) != shift_mode)
9082 varop = gen_lowpart_for_combine (shift_mode, varop);
9084 /* If we can't make the SUBREG, try to return what we were given. */
9085 if (GET_CODE (varop) == CLOBBER)
9086 return x ? x : varop;
9088 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9093 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9094 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9096 SUBST (XEXP (x, 0), varop);
9097 SUBST (XEXP (x, 1), const_rtx);
9100 /* If we have an outer operation and we just made a shift, it is
9101 possible that we could have simplified the shift were it not
9102 for the outer operation. So try to do the simplification
9105 if (outer_op != NIL && GET_CODE (x) == code
9106 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9107 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9108 INTVAL (XEXP (x, 1)));
9110 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9111 turn off all the bits that the shift would have turned off. */
9112 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9113 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9114 GET_MODE_MASK (result_mode) >> orig_count);
9116 /* Do the remainder of the processing in RESULT_MODE. */
9117 x = gen_lowpart_for_combine (result_mode, x);
9119 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9122 x = gen_unary (NOT, result_mode, result_mode, x);
9124 if (outer_op != NIL)
9126 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9128 int width = GET_MODE_BITSIZE (result_mode);
9130 outer_const &= GET_MODE_MASK (result_mode);
9132 /* If this would be an entire word for the target, but is not for
9133 the host, then sign-extend on the host so that the number will
9134 look the same way on the host that it would on the target.
9136 For example, when building a 64 bit alpha hosted 32 bit sparc
9137 targeted compiler, then we want the 32 bit unsigned value -1 to be
9138 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
9139 The later confuses the sparc backend. */
9141 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
9142 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
9143 outer_const |= ((HOST_WIDE_INT) (-1) << width);
9146 if (outer_op == AND)
9147 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9148 else if (outer_op == SET)
9149 /* This means that we have determined that the result is
9150 equivalent to a constant. This should be rare. */
9151 x = GEN_INT (outer_const);
9152 else if (GET_RTX_CLASS (outer_op) == '1')
9153 x = gen_unary (outer_op, result_mode, result_mode, x);
9155 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9161 /* Like recog, but we receive the address of a pointer to a new pattern.
9162 We try to match the rtx that the pointer points to.
9163 If that fails, we may try to modify or replace the pattern,
9164 storing the replacement into the same pointer object.
9166 Modifications include deletion or addition of CLOBBERs.
9168 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9169 the CLOBBERs are placed.
9171 The value is the final insn code from the pattern ultimately matched,
9175 recog_for_combine (pnewpat, insn, pnotes)
9180 register rtx pat = *pnewpat;
9181 int insn_code_number;
9182 int num_clobbers_to_add = 0;
9186 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9187 we use to indicate that something didn't match. If we find such a
9188 thing, force rejection. */
9189 if (GET_CODE (pat) == PARALLEL)
9190 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9191 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9192 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9195 /* Is the result of combination a valid instruction? */
9196 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9198 /* If it isn't, there is the possibility that we previously had an insn
9199 that clobbered some register as a side effect, but the combined
9200 insn doesn't need to do that. So try once more without the clobbers
9201 unless this represents an ASM insn. */
9203 if (insn_code_number < 0 && ! check_asm_operands (pat)
9204 && GET_CODE (pat) == PARALLEL)
9208 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9209 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9212 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9216 SUBST_INT (XVECLEN (pat, 0), pos);
9219 pat = XVECEXP (pat, 0, 0);
9221 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9224 /* If we had any clobbers to add, make a new pattern than contains
9225 them. Then check to make sure that all of them are dead. */
9226 if (num_clobbers_to_add)
9228 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9229 gen_rtvec (GET_CODE (pat) == PARALLEL
9230 ? XVECLEN (pat, 0) + num_clobbers_to_add
9231 : num_clobbers_to_add + 1));
9233 if (GET_CODE (pat) == PARALLEL)
9234 for (i = 0; i < XVECLEN (pat, 0); i++)
9235 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9237 XVECEXP (newpat, 0, 0) = pat;
9239 add_clobbers (newpat, insn_code_number);
9241 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9242 i < XVECLEN (newpat, 0); i++)
9244 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9245 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9247 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9248 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9256 return insn_code_number;
9259 /* Like gen_lowpart but for use by combine. In combine it is not possible
9260 to create any new pseudoregs. However, it is safe to create
9261 invalid memory addresses, because combine will try to recognize
9262 them and all they will do is make the combine attempt fail.
9264 If for some reason this cannot do its job, an rtx
9265 (clobber (const_int 0)) is returned.
9266 An insn containing that will not be recognized. */
9271 gen_lowpart_for_combine (mode, x)
9272 enum machine_mode mode;
9277 if (GET_MODE (x) == mode)
9280 /* We can only support MODE being wider than a word if X is a
9281 constant integer or has a mode the same size. */
9283 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9284 && ! ((GET_MODE (x) == VOIDmode
9285 && (GET_CODE (x) == CONST_INT
9286 || GET_CODE (x) == CONST_DOUBLE))
9287 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9288 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9290 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9291 won't know what to do. So we will strip off the SUBREG here and
9292 process normally. */
9293 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9296 if (GET_MODE (x) == mode)
9300 result = gen_lowpart_common (mode, x);
9302 && GET_CODE (result) == SUBREG
9303 && GET_CODE (SUBREG_REG (result)) == REG
9304 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9305 && (GET_MODE_SIZE (GET_MODE (result))
9306 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9307 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9312 if (GET_CODE (x) == MEM)
9314 register int offset = 0;
9317 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9319 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9320 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9322 /* If we want to refer to something bigger than the original memref,
9323 generate a perverse subreg instead. That will force a reload
9324 of the original memref X. */
9325 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9326 return gen_rtx_SUBREG (mode, x, 0);
9328 if (WORDS_BIG_ENDIAN)
9329 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9330 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9331 if (BYTES_BIG_ENDIAN)
9333 /* Adjust the address so that the address-after-the-data is
9335 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9336 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9338 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9339 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9340 MEM_COPY_ATTRIBUTES (new, x);
9344 /* If X is a comparison operator, rewrite it in a new mode. This
9345 probably won't match, but may allow further simplifications. */
9346 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9347 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9349 /* If we couldn't simplify X any other way, just enclose it in a
9350 SUBREG. Normally, this SUBREG won't match, but some patterns may
9351 include an explicit SUBREG or we may simplify it further in combine. */
9356 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9357 word = ((GET_MODE_SIZE (GET_MODE (x))
9358 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9360 return gen_rtx_SUBREG (mode, x, word);
9364 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9365 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9367 If the identical expression was previously in the insn (in the undobuf),
9368 it will be returned. Only if it is not found will a new expression
9373 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9375 #ifndef ANSI_PROTOTYPES
9377 enum machine_mode mode;
9389 #ifndef ANSI_PROTOTYPES
9390 code = va_arg (p, enum rtx_code);
9391 mode = va_arg (p, enum machine_mode);
9394 n_args = GET_RTX_LENGTH (code);
9395 fmt = GET_RTX_FORMAT (code);
9397 if (n_args == 0 || n_args > 3)
9400 /* Get each arg and verify that it is supposed to be an expression. */
9401 for (j = 0; j < n_args; j++)
9406 args[j] = va_arg (p, rtx);
9409 /* See if this is in undobuf. Be sure we don't use objects that came
9410 from another insn; this could produce circular rtl structures. */
9412 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9414 && GET_CODE (undo->old_contents.r) == code
9415 && GET_MODE (undo->old_contents.r) == mode)
9417 for (j = 0; j < n_args; j++)
9418 if (XEXP (undo->old_contents.r, j) != args[j])
9422 return undo->old_contents.r;
9425 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9426 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9427 rt = rtx_alloc (code);
9428 PUT_MODE (rt, mode);
9429 XEXP (rt, 0) = args[0];
9432 XEXP (rt, 1) = args[1];
9434 XEXP (rt, 2) = args[2];
9439 /* These routines make binary and unary operations by first seeing if they
9440 fold; if not, a new expression is allocated. */
9443 gen_binary (code, mode, op0, op1)
9445 enum machine_mode mode;
9451 if (GET_RTX_CLASS (code) == 'c'
9452 && (GET_CODE (op0) == CONST_INT
9453 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9454 tem = op0, op0 = op1, op1 = tem;
9456 if (GET_RTX_CLASS (code) == '<')
9458 enum machine_mode op_mode = GET_MODE (op0);
9460 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9461 just (REL_OP X Y). */
9462 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9464 op1 = XEXP (op0, 1);
9465 op0 = XEXP (op0, 0);
9466 op_mode = GET_MODE (op0);
9469 if (op_mode == VOIDmode)
9470 op_mode = GET_MODE (op1);
9471 result = simplify_relational_operation (code, op_mode, op0, op1);
9474 result = simplify_binary_operation (code, mode, op0, op1);
9479 /* Put complex operands first and constants second. */
9480 if (GET_RTX_CLASS (code) == 'c'
9481 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9482 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9483 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9484 || (GET_CODE (op0) == SUBREG
9485 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9486 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9487 return gen_rtx_combine (code, mode, op1, op0);
9489 /* If we are turning off bits already known off in OP0, we need not do
9491 else if (code == AND && GET_CODE (op1) == CONST_INT
9492 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9493 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9496 return gen_rtx_combine (code, mode, op0, op1);
9500 gen_unary (code, mode, op0_mode, op0)
9502 enum machine_mode mode, op0_mode;
9505 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9510 return gen_rtx_combine (code, mode, op0);
9513 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9514 comparison code that will be tested.
9516 The result is a possibly different comparison code to use. *POP0 and
9517 *POP1 may be updated.
9519 It is possible that we might detect that a comparison is either always
9520 true or always false. However, we do not perform general constant
9521 folding in combine, so this knowledge isn't useful. Such tautologies
9522 should have been detected earlier. Hence we ignore all such cases. */
9524 static enum rtx_code
9525 simplify_comparison (code, pop0, pop1)
9534 enum machine_mode mode, tmode;
9536 /* Try a few ways of applying the same transformation to both operands. */
9539 #ifndef WORD_REGISTER_OPERATIONS
9540 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9541 so check specially. */
9542 if (code != GTU && code != GEU && code != LTU && code != LEU
9543 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9544 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9545 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9546 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9547 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9548 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9549 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9550 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9551 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9552 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9553 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9554 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9555 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9556 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9557 && (INTVAL (XEXP (op0, 1))
9558 == (GET_MODE_BITSIZE (GET_MODE (op0))
9560 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9562 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9563 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9567 /* If both operands are the same constant shift, see if we can ignore the
9568 shift. We can if the shift is a rotate or if the bits shifted out of
9569 this shift are known to be zero for both inputs and if the type of
9570 comparison is compatible with the shift. */
9571 if (GET_CODE (op0) == GET_CODE (op1)
9572 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9573 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9574 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9575 && (code != GT && code != LT && code != GE && code != LE))
9576 || (GET_CODE (op0) == ASHIFTRT
9577 && (code != GTU && code != LTU
9578 && code != GEU && code != GEU)))
9579 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9580 && INTVAL (XEXP (op0, 1)) >= 0
9581 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9582 && XEXP (op0, 1) == XEXP (op1, 1))
9584 enum machine_mode mode = GET_MODE (op0);
9585 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9586 int shift_count = INTVAL (XEXP (op0, 1));
9588 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9589 mask &= (mask >> shift_count) << shift_count;
9590 else if (GET_CODE (op0) == ASHIFT)
9591 mask = (mask & (mask << shift_count)) >> shift_count;
9593 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9594 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9595 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9600 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9601 SUBREGs are of the same mode, and, in both cases, the AND would
9602 be redundant if the comparison was done in the narrower mode,
9603 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9604 and the operand's possibly nonzero bits are 0xffffff01; in that case
9605 if we only care about QImode, we don't need the AND). This case
9606 occurs if the output mode of an scc insn is not SImode and
9607 STORE_FLAG_VALUE == 1 (e.g., the 386).
9609 Similarly, check for a case where the AND's are ZERO_EXTEND
9610 operations from some narrower mode even though a SUBREG is not
9613 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9614 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9615 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9617 rtx inner_op0 = XEXP (op0, 0);
9618 rtx inner_op1 = XEXP (op1, 0);
9619 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9620 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9623 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9624 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9625 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9626 && (GET_MODE (SUBREG_REG (inner_op0))
9627 == GET_MODE (SUBREG_REG (inner_op1)))
9628 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9629 <= HOST_BITS_PER_WIDE_INT)
9630 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9631 GET_MODE (SUBREG_REG (inner_op0)))))
9632 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9633 GET_MODE (SUBREG_REG (inner_op1))))))
9635 op0 = SUBREG_REG (inner_op0);
9636 op1 = SUBREG_REG (inner_op1);
9638 /* The resulting comparison is always unsigned since we masked
9639 off the original sign bit. */
9640 code = unsigned_condition (code);
9646 for (tmode = GET_CLASS_NARROWEST_MODE
9647 (GET_MODE_CLASS (GET_MODE (op0)));
9648 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9649 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9651 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9652 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9653 code = unsigned_condition (code);
9662 /* If both operands are NOT, we can strip off the outer operation
9663 and adjust the comparison code for swapped operands; similarly for
9664 NEG, except that this must be an equality comparison. */
9665 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9666 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9667 && (code == EQ || code == NE)))
9668 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9674 /* If the first operand is a constant, swap the operands and adjust the
9675 comparison code appropriately, but don't do this if the second operand
9676 is already a constant integer. */
9677 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9679 tem = op0, op0 = op1, op1 = tem;
9680 code = swap_condition (code);
9683 /* We now enter a loop during which we will try to simplify the comparison.
9684 For the most part, we only are concerned with comparisons with zero,
9685 but some things may really be comparisons with zero but not start
9686 out looking that way. */
9688 while (GET_CODE (op1) == CONST_INT)
9690 enum machine_mode mode = GET_MODE (op0);
9691 int mode_width = GET_MODE_BITSIZE (mode);
9692 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9693 int equality_comparison_p;
9694 int sign_bit_comparison_p;
9695 int unsigned_comparison_p;
9696 HOST_WIDE_INT const_op;
9698 /* We only want to handle integral modes. This catches VOIDmode,
9699 CCmode, and the floating-point modes. An exception is that we
9700 can handle VOIDmode if OP0 is a COMPARE or a comparison
9703 if (GET_MODE_CLASS (mode) != MODE_INT
9704 && ! (mode == VOIDmode
9705 && (GET_CODE (op0) == COMPARE
9706 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9709 /* Get the constant we are comparing against and turn off all bits
9710 not on in our mode. */
9711 const_op = INTVAL (op1);
9712 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9715 /* If we are comparing against a constant power of two and the value
9716 being compared can only have that single bit nonzero (e.g., it was
9717 `and'ed with that bit), we can replace this with a comparison
9720 && (code == EQ || code == NE || code == GE || code == GEU
9721 || code == LT || code == LTU)
9722 && mode_width <= HOST_BITS_PER_WIDE_INT
9723 && exact_log2 (const_op) >= 0
9724 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9726 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9727 op1 = const0_rtx, const_op = 0;
9730 /* Similarly, if we are comparing a value known to be either -1 or
9731 0 with -1, change it to the opposite comparison against zero. */
9734 && (code == EQ || code == NE || code == GT || code == LE
9735 || code == GEU || code == LTU)
9736 && num_sign_bit_copies (op0, mode) == mode_width)
9738 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9739 op1 = const0_rtx, const_op = 0;
9742 /* Do some canonicalizations based on the comparison code. We prefer
9743 comparisons against zero and then prefer equality comparisons.
9744 If we can reduce the size of a constant, we will do that too. */
9749 /* < C is equivalent to <= (C - 1) */
9753 op1 = GEN_INT (const_op);
9755 /* ... fall through to LE case below. */
9761 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9765 op1 = GEN_INT (const_op);
9769 /* If we are doing a <= 0 comparison on a value known to have
9770 a zero sign bit, we can replace this with == 0. */
9771 else if (const_op == 0
9772 && mode_width <= HOST_BITS_PER_WIDE_INT
9773 && (nonzero_bits (op0, mode)
9774 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9779 /* >= C is equivalent to > (C - 1). */
9783 op1 = GEN_INT (const_op);
9785 /* ... fall through to GT below. */
9791 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9795 op1 = GEN_INT (const_op);
9799 /* If we are doing a > 0 comparison on a value known to have
9800 a zero sign bit, we can replace this with != 0. */
9801 else if (const_op == 0
9802 && mode_width <= HOST_BITS_PER_WIDE_INT
9803 && (nonzero_bits (op0, mode)
9804 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9809 /* < C is equivalent to <= (C - 1). */
9813 op1 = GEN_INT (const_op);
9815 /* ... fall through ... */
9818 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9819 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9820 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9822 const_op = 0, op1 = const0_rtx;
9830 /* unsigned <= 0 is equivalent to == 0 */
9834 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9835 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9836 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9838 const_op = 0, op1 = const0_rtx;
9844 /* >= C is equivalent to < (C - 1). */
9848 op1 = GEN_INT (const_op);
9850 /* ... fall through ... */
9853 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9854 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9855 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9857 const_op = 0, op1 = const0_rtx;
9865 /* unsigned > 0 is equivalent to != 0 */
9869 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9870 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9871 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9873 const_op = 0, op1 = const0_rtx;
9882 /* Compute some predicates to simplify code below. */
9884 equality_comparison_p = (code == EQ || code == NE);
9885 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9886 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9889 /* If this is a sign bit comparison and we can do arithmetic in
9890 MODE, say that we will only be needing the sign bit of OP0. */
9891 if (sign_bit_comparison_p
9892 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9893 op0 = force_to_mode (op0, mode,
9895 << (GET_MODE_BITSIZE (mode) - 1)),
9898 /* Now try cases based on the opcode of OP0. If none of the cases
9899 does a "continue", we exit this loop immediately after the
9902 switch (GET_CODE (op0))
9905 /* If we are extracting a single bit from a variable position in
9906 a constant that has only a single bit set and are comparing it
9907 with zero, we can convert this into an equality comparison
9908 between the position and the location of the single bit. */
9910 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9911 && XEXP (op0, 1) == const1_rtx
9912 && equality_comparison_p && const_op == 0
9913 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9915 if (BITS_BIG_ENDIAN)
9918 mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
9919 if (mode == VOIDmode)
9921 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9923 i = BITS_PER_WORD - 1 - i;
9927 op0 = XEXP (op0, 2);
9931 /* Result is nonzero iff shift count is equal to I. */
9932 code = reverse_condition (code);
9936 /* ... fall through ... */
9939 tem = expand_compound_operation (op0);
9948 /* If testing for equality, we can take the NOT of the constant. */
9949 if (equality_comparison_p
9950 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9952 op0 = XEXP (op0, 0);
9957 /* If just looking at the sign bit, reverse the sense of the
9959 if (sign_bit_comparison_p)
9961 op0 = XEXP (op0, 0);
9962 code = (code == GE ? LT : GE);
9968 /* If testing for equality, we can take the NEG of the constant. */
9969 if (equality_comparison_p
9970 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9972 op0 = XEXP (op0, 0);
9977 /* The remaining cases only apply to comparisons with zero. */
9981 /* When X is ABS or is known positive,
9982 (neg X) is < 0 if and only if X != 0. */
9984 if (sign_bit_comparison_p
9985 && (GET_CODE (XEXP (op0, 0)) == ABS
9986 || (mode_width <= HOST_BITS_PER_WIDE_INT
9987 && (nonzero_bits (XEXP (op0, 0), mode)
9988 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9990 op0 = XEXP (op0, 0);
9991 code = (code == LT ? NE : EQ);
9995 /* If we have NEG of something whose two high-order bits are the
9996 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9997 if (num_sign_bit_copies (op0, mode) >= 2)
9999 op0 = XEXP (op0, 0);
10000 code = swap_condition (code);
10006 /* If we are testing equality and our count is a constant, we
10007 can perform the inverse operation on our RHS. */
10008 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10009 && (tem = simplify_binary_operation (ROTATERT, mode,
10010 op1, XEXP (op0, 1))) != 0)
10012 op0 = XEXP (op0, 0);
10017 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10018 a particular bit. Convert it to an AND of a constant of that
10019 bit. This will be converted into a ZERO_EXTRACT. */
10020 if (const_op == 0 && sign_bit_comparison_p
10021 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10022 && mode_width <= HOST_BITS_PER_WIDE_INT)
10024 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10027 - INTVAL (XEXP (op0, 1)))));
10028 code = (code == LT ? NE : EQ);
10032 /* ... fall through ... */
10035 /* ABS is ignorable inside an equality comparison with zero. */
10036 if (const_op == 0 && equality_comparison_p)
10038 op0 = XEXP (op0, 0);
10045 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10046 to (compare FOO CONST) if CONST fits in FOO's mode and we
10047 are either testing inequality or have an unsigned comparison
10048 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10049 if (! unsigned_comparison_p
10050 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10051 <= HOST_BITS_PER_WIDE_INT)
10052 && ((unsigned HOST_WIDE_INT) const_op
10053 < (((unsigned HOST_WIDE_INT) 1
10054 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10056 op0 = XEXP (op0, 0);
10062 /* Check for the case where we are comparing A - C1 with C2,
10063 both constants are smaller than 1/2 the maximum positive
10064 value in MODE, and the comparison is equality or unsigned.
10065 In that case, if A is either zero-extended to MODE or has
10066 sufficient sign bits so that the high-order bit in MODE
10067 is a copy of the sign in the inner mode, we can prove that it is
10068 safe to do the operation in the wider mode. This simplifies
10069 many range checks. */
10071 if (mode_width <= HOST_BITS_PER_WIDE_INT
10072 && subreg_lowpart_p (op0)
10073 && GET_CODE (SUBREG_REG (op0)) == PLUS
10074 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10075 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10076 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
10077 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
10078 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10079 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10080 GET_MODE (SUBREG_REG (op0)))
10081 & ~ GET_MODE_MASK (mode))
10082 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10083 GET_MODE (SUBREG_REG (op0)))
10084 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10085 - GET_MODE_BITSIZE (mode)))))
10087 op0 = SUBREG_REG (op0);
10091 /* If the inner mode is narrower and we are extracting the low part,
10092 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10093 if (subreg_lowpart_p (op0)
10094 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10095 /* Fall through */ ;
10099 /* ... fall through ... */
10102 if ((unsigned_comparison_p || equality_comparison_p)
10103 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10104 <= HOST_BITS_PER_WIDE_INT)
10105 && ((unsigned HOST_WIDE_INT) const_op
10106 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10108 op0 = XEXP (op0, 0);
10114 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10115 this for equality comparisons due to pathological cases involving
10117 if (equality_comparison_p
10118 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10119 op1, XEXP (op0, 1))))
10121 op0 = XEXP (op0, 0);
10126 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10127 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10128 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10130 op0 = XEXP (XEXP (op0, 0), 0);
10131 code = (code == LT ? EQ : NE);
10137 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10138 (eq B (minus A C)), whichever simplifies. We can only do
10139 this for equality comparisons due to pathological cases involving
10141 if (equality_comparison_p
10142 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10143 XEXP (op0, 1), op1)))
10145 op0 = XEXP (op0, 0);
10150 if (equality_comparison_p
10151 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10152 XEXP (op0, 0), op1)))
10154 op0 = XEXP (op0, 1);
10159 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10160 of bits in X minus 1, is one iff X > 0. */
10161 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10162 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10163 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10164 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10166 op0 = XEXP (op0, 1);
10167 code = (code == GE ? LE : GT);
10173 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10174 if C is zero or B is a constant. */
10175 if (equality_comparison_p
10176 && 0 != (tem = simplify_binary_operation (XOR, mode,
10177 XEXP (op0, 1), op1)))
10179 op0 = XEXP (op0, 0);
10186 case LT: case LTU: case LE: case LEU:
10187 case GT: case GTU: case GE: case GEU:
10188 /* We can't do anything if OP0 is a condition code value, rather
10189 than an actual data value. */
10192 || XEXP (op0, 0) == cc0_rtx
10194 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10197 /* Get the two operands being compared. */
10198 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10199 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10201 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10203 /* Check for the cases where we simply want the result of the
10204 earlier test or the opposite of that result. */
10206 || (code == EQ && reversible_comparison_p (op0))
10207 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10208 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10209 && (STORE_FLAG_VALUE
10210 & (((HOST_WIDE_INT) 1
10211 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10213 || (code == GE && reversible_comparison_p (op0)))))
10215 code = (code == LT || code == NE
10216 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10217 op0 = tem, op1 = tem1;
10223 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10225 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10226 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10227 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10229 op0 = XEXP (op0, 1);
10230 code = (code == GE ? GT : LE);
10236 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10237 will be converted to a ZERO_EXTRACT later. */
10238 if (const_op == 0 && equality_comparison_p
10239 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10240 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10242 op0 = simplify_and_const_int
10243 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10245 XEXP (XEXP (op0, 0), 1)),
10246 (HOST_WIDE_INT) 1);
10250 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10251 zero and X is a comparison and C1 and C2 describe only bits set
10252 in STORE_FLAG_VALUE, we can compare with X. */
10253 if (const_op == 0 && equality_comparison_p
10254 && mode_width <= HOST_BITS_PER_WIDE_INT
10255 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10256 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10257 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10258 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10259 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10261 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10262 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10263 if ((~ STORE_FLAG_VALUE & mask) == 0
10264 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10265 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10266 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10268 op0 = XEXP (XEXP (op0, 0), 0);
10273 /* If we are doing an equality comparison of an AND of a bit equal
10274 to the sign bit, replace this with a LT or GE comparison of
10275 the underlying value. */
10276 if (equality_comparison_p
10278 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10279 && mode_width <= HOST_BITS_PER_WIDE_INT
10280 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10281 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10283 op0 = XEXP (op0, 0);
10284 code = (code == EQ ? GE : LT);
10288 /* If this AND operation is really a ZERO_EXTEND from a narrower
10289 mode, the constant fits within that mode, and this is either an
10290 equality or unsigned comparison, try to do this comparison in
10291 the narrower mode. */
10292 if ((equality_comparison_p || unsigned_comparison_p)
10293 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10294 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10295 & GET_MODE_MASK (mode))
10297 && const_op >> i == 0
10298 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10300 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10304 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10305 in both M1 and M2 and the SUBREG is either paradoxical or
10306 represents the low part, permute the SUBREG and the AND and
10308 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10310 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10311 #ifdef WORD_REGISTER_OPERATIONS
10312 || subreg_lowpart_p (XEXP (op0, 0))
10315 #ifndef WORD_REGISTER_OPERATIONS
10316 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10317 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10318 As originally written the upper bits have a defined value
10319 due to the AND operation. However, if we commute the AND
10320 inside the SUBREG then they no longer have defined values
10321 and the meaning of the code has been changed. */
10322 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10323 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10325 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10326 && mode_width <= HOST_BITS_PER_WIDE_INT
10327 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10328 <= HOST_BITS_PER_WIDE_INT)
10329 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10330 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10331 & INTVAL (XEXP (op0, 1)))
10332 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10333 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10334 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10338 = gen_lowpart_for_combine
10340 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10341 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10348 /* If we have (compare (ashift FOO N) (const_int C)) and
10349 the high order N bits of FOO (N+1 if an inequality comparison)
10350 are known to be zero, we can do this by comparing FOO with C
10351 shifted right N bits so long as the low-order N bits of C are
10353 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10354 && INTVAL (XEXP (op0, 1)) >= 0
10355 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10356 < HOST_BITS_PER_WIDE_INT)
10358 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10359 && mode_width <= HOST_BITS_PER_WIDE_INT
10360 && (nonzero_bits (XEXP (op0, 0), mode)
10361 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10362 + ! equality_comparison_p))) == 0)
10364 const_op >>= INTVAL (XEXP (op0, 1));
10365 op1 = GEN_INT (const_op);
10366 op0 = XEXP (op0, 0);
10370 /* If we are doing a sign bit comparison, it means we are testing
10371 a particular bit. Convert it to the appropriate AND. */
10372 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10373 && mode_width <= HOST_BITS_PER_WIDE_INT)
10375 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10378 - INTVAL (XEXP (op0, 1)))));
10379 code = (code == LT ? NE : EQ);
10383 /* If this an equality comparison with zero and we are shifting
10384 the low bit to the sign bit, we can convert this to an AND of the
10386 if (const_op == 0 && equality_comparison_p
10387 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10388 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10390 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10391 (HOST_WIDE_INT) 1);
10397 /* If this is an equality comparison with zero, we can do this
10398 as a logical shift, which might be much simpler. */
10399 if (equality_comparison_p && const_op == 0
10400 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10402 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10404 INTVAL (XEXP (op0, 1)));
10408 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10409 do the comparison in a narrower mode. */
10410 if (! unsigned_comparison_p
10411 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10412 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10413 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10414 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10415 MODE_INT, 1)) != BLKmode
10416 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10417 || ((unsigned HOST_WIDE_INT) - const_op
10418 <= GET_MODE_MASK (tmode))))
10420 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10424 /* ... fall through ... */
10426 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10427 the low order N bits of FOO are known to be zero, we can do this
10428 by comparing FOO with C shifted left N bits so long as no
10429 overflow occurs. */
10430 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10431 && INTVAL (XEXP (op0, 1)) >= 0
10432 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10433 && mode_width <= HOST_BITS_PER_WIDE_INT
10434 && (nonzero_bits (XEXP (op0, 0), mode)
10435 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10437 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10440 const_op <<= INTVAL (XEXP (op0, 1));
10441 op1 = GEN_INT (const_op);
10442 op0 = XEXP (op0, 0);
10446 /* If we are using this shift to extract just the sign bit, we
10447 can replace this with an LT or GE comparison. */
10449 && (equality_comparison_p || sign_bit_comparison_p)
10450 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10451 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10453 op0 = XEXP (op0, 0);
10454 code = (code == NE || code == GT ? LT : GE);
10466 /* Now make any compound operations involved in this comparison. Then,
10467 check for an outmost SUBREG on OP0 that is not doing anything or is
10468 paradoxical. The latter case can only occur when it is known that the
10469 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10470 We can never remove a SUBREG for a non-equality comparison because the
10471 sign bit is in a different place in the underlying object. */
10473 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10474 op1 = make_compound_operation (op1, SET);
10476 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10477 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10478 && (code == NE || code == EQ)
10479 && ((GET_MODE_SIZE (GET_MODE (op0))
10480 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10482 op0 = SUBREG_REG (op0);
10483 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10486 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10487 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10488 && (code == NE || code == EQ)
10489 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10490 <= HOST_BITS_PER_WIDE_INT)
10491 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10492 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10493 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10495 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10496 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10497 op0 = SUBREG_REG (op0), op1 = tem;
10499 /* We now do the opposite procedure: Some machines don't have compare
10500 insns in all modes. If OP0's mode is an integer mode smaller than a
10501 word and we can't do a compare in that mode, see if there is a larger
10502 mode for which we can do the compare. There are a number of cases in
10503 which we can use the wider mode. */
10505 mode = GET_MODE (op0);
10506 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10507 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10508 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10509 for (tmode = GET_MODE_WIDER_MODE (mode);
10511 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10512 tmode = GET_MODE_WIDER_MODE (tmode))
10513 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10515 /* If the only nonzero bits in OP0 and OP1 are those in the
10516 narrower mode and this is an equality or unsigned comparison,
10517 we can use the wider mode. Similarly for sign-extended
10518 values, in which case it is true for all comparisons. */
10519 if (((code == EQ || code == NE
10520 || code == GEU || code == GTU || code == LEU || code == LTU)
10521 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10522 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10523 || ((num_sign_bit_copies (op0, tmode)
10524 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10525 && (num_sign_bit_copies (op1, tmode)
10526 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10528 op0 = gen_lowpart_for_combine (tmode, op0);
10529 op1 = gen_lowpart_for_combine (tmode, op1);
10533 /* If this is a test for negative, we can make an explicit
10534 test of the sign bit. */
10536 if (op1 == const0_rtx && (code == LT || code == GE)
10537 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10539 op0 = gen_binary (AND, tmode,
10540 gen_lowpart_for_combine (tmode, op0),
10541 GEN_INT ((HOST_WIDE_INT) 1
10542 << (GET_MODE_BITSIZE (mode) - 1)));
10543 code = (code == LT) ? NE : EQ;
10548 #ifdef CANONICALIZE_COMPARISON
10549 /* If this machine only supports a subset of valid comparisons, see if we
10550 can convert an unsupported one into a supported one. */
10551 CANONICALIZE_COMPARISON (code, op0, op1);
10560 /* Return 1 if we know that X, a comparison operation, is not operating
10561 on a floating-point value or is EQ or NE, meaning that we can safely
10565 reversible_comparison_p (x)
10568 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10570 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10573 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10576 case MODE_PARTIAL_INT:
10577 case MODE_COMPLEX_INT:
10581 /* If the mode of the condition codes tells us that this is safe,
10582 we need look no further. */
10583 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10586 /* Otherwise try and find where the condition codes were last set and
10588 x = get_last_value (XEXP (x, 0));
10589 return (x && GET_CODE (x) == COMPARE
10590 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10597 /* Utility function for following routine. Called when X is part of a value
10598 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10599 for each register mentioned. Similar to mention_regs in cse.c */
10602 update_table_tick (x)
10605 register enum rtx_code code = GET_CODE (x);
10606 register char *fmt = GET_RTX_FORMAT (code);
10611 int regno = REGNO (x);
10612 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10613 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10615 for (i = regno; i < endregno; i++)
10616 reg_last_set_table_tick[i] = label_tick;
10621 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10622 /* Note that we can't have an "E" in values stored; see
10623 get_last_value_validate. */
10625 update_table_tick (XEXP (x, i));
10628 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10629 are saying that the register is clobbered and we no longer know its
10630 value. If INSN is zero, don't update reg_last_set; this is only permitted
10631 with VALUE also zero and is used to invalidate the register. */
10634 record_value_for_reg (reg, insn, value)
10639 int regno = REGNO (reg);
10640 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10641 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10644 /* If VALUE contains REG and we have a previous value for REG, substitute
10645 the previous value. */
10646 if (value && insn && reg_overlap_mentioned_p (reg, value))
10650 /* Set things up so get_last_value is allowed to see anything set up to
10652 subst_low_cuid = INSN_CUID (insn);
10653 tem = get_last_value (reg);
10656 value = replace_rtx (copy_rtx (value), reg, tem);
10659 /* For each register modified, show we don't know its value, that
10660 we don't know about its bitwise content, that its value has been
10661 updated, and that we don't know the location of the death of the
10663 for (i = regno; i < endregno; i ++)
10666 reg_last_set[i] = insn;
10667 reg_last_set_value[i] = 0;
10668 reg_last_set_mode[i] = 0;
10669 reg_last_set_nonzero_bits[i] = 0;
10670 reg_last_set_sign_bit_copies[i] = 0;
10671 reg_last_death[i] = 0;
10674 /* Mark registers that are being referenced in this value. */
10676 update_table_tick (value);
10678 /* Now update the status of each register being set.
10679 If someone is using this register in this block, set this register
10680 to invalid since we will get confused between the two lives in this
10681 basic block. This makes using this register always invalid. In cse, we
10682 scan the table to invalidate all entries using this register, but this
10683 is too much work for us. */
10685 for (i = regno; i < endregno; i++)
10687 reg_last_set_label[i] = label_tick;
10688 if (value && reg_last_set_table_tick[i] == label_tick)
10689 reg_last_set_invalid[i] = 1;
10691 reg_last_set_invalid[i] = 0;
10694 /* The value being assigned might refer to X (like in "x++;"). In that
10695 case, we must replace it with (clobber (const_int 0)) to prevent
10697 if (value && ! get_last_value_validate (&value, insn,
10698 reg_last_set_label[regno], 0))
10700 value = copy_rtx (value);
10701 if (! get_last_value_validate (&value, insn,
10702 reg_last_set_label[regno], 1))
10706 /* For the main register being modified, update the value, the mode, the
10707 nonzero bits, and the number of sign bit copies. */
10709 reg_last_set_value[regno] = value;
10713 subst_low_cuid = INSN_CUID (insn);
10714 reg_last_set_mode[regno] = GET_MODE (reg);
10715 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10716 reg_last_set_sign_bit_copies[regno]
10717 = num_sign_bit_copies (value, GET_MODE (reg));
10721 /* Used for communication between the following two routines. */
10722 static rtx record_dead_insn;
10724 /* Called via note_stores from record_dead_and_set_regs to handle one
10725 SET or CLOBBER in an insn. */
10728 record_dead_and_set_regs_1 (dest, setter)
10731 if (GET_CODE (dest) == SUBREG)
10732 dest = SUBREG_REG (dest);
10734 if (GET_CODE (dest) == REG)
10736 /* If we are setting the whole register, we know its value. Otherwise
10737 show that we don't know the value. We can handle SUBREG in
10739 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10740 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10741 else if (GET_CODE (setter) == SET
10742 && GET_CODE (SET_DEST (setter)) == SUBREG
10743 && SUBREG_REG (SET_DEST (setter)) == dest
10744 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10745 && subreg_lowpart_p (SET_DEST (setter)))
10746 record_value_for_reg (dest, record_dead_insn,
10747 gen_lowpart_for_combine (GET_MODE (dest),
10748 SET_SRC (setter)));
10750 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10752 else if (GET_CODE (dest) == MEM
10753 /* Ignore pushes, they clobber nothing. */
10754 && ! push_operand (dest, GET_MODE (dest)))
10755 mem_last_set = INSN_CUID (record_dead_insn);
10758 /* Update the records of when each REG was most recently set or killed
10759 for the things done by INSN. This is the last thing done in processing
10760 INSN in the combiner loop.
10762 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10763 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10764 and also the similar information mem_last_set (which insn most recently
10765 modified memory) and last_call_cuid (which insn was the most recent
10766 subroutine call). */
10769 record_dead_and_set_regs (insn)
10775 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10777 if (REG_NOTE_KIND (link) == REG_DEAD
10778 && GET_CODE (XEXP (link, 0)) == REG)
10780 int regno = REGNO (XEXP (link, 0));
10782 = regno + (regno < FIRST_PSEUDO_REGISTER
10783 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10786 for (i = regno; i < endregno; i++)
10787 reg_last_death[i] = insn;
10789 else if (REG_NOTE_KIND (link) == REG_INC)
10790 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10793 if (GET_CODE (insn) == CALL_INSN)
10795 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10796 if (call_used_regs[i])
10798 reg_last_set_value[i] = 0;
10799 reg_last_set_mode[i] = 0;
10800 reg_last_set_nonzero_bits[i] = 0;
10801 reg_last_set_sign_bit_copies[i] = 0;
10802 reg_last_death[i] = 0;
10805 last_call_cuid = mem_last_set = INSN_CUID (insn);
10808 record_dead_insn = insn;
10809 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10812 /* Utility routine for the following function. Verify that all the registers
10813 mentioned in *LOC are valid when *LOC was part of a value set when
10814 label_tick == TICK. Return 0 if some are not.
10816 If REPLACE is non-zero, replace the invalid reference with
10817 (clobber (const_int 0)) and return 1. This replacement is useful because
10818 we often can get useful information about the form of a value (e.g., if
10819 it was produced by a shift that always produces -1 or 0) even though
10820 we don't know exactly what registers it was produced from. */
10823 get_last_value_validate (loc, insn, tick, replace)
10830 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10831 int len = GET_RTX_LENGTH (GET_CODE (x));
10834 if (GET_CODE (x) == REG)
10836 int regno = REGNO (x);
10837 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10838 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10841 for (j = regno; j < endregno; j++)
10842 if (reg_last_set_invalid[j]
10843 /* If this is a pseudo-register that was only set once and not
10844 live at the beginning of the function, it is always valid. */
10845 || (! (regno >= FIRST_PSEUDO_REGISTER
10846 && REG_N_SETS (regno) == 1
10847 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))
10848 && reg_last_set_label[j] > tick))
10851 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10857 /* If this is a memory reference, make sure that there were
10858 no stores after it that might have clobbered the value. We don't
10859 have alias info, so we assume any store invalidates it. */
10860 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10861 && INSN_CUID (insn) <= mem_last_set)
10864 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10868 for (i = 0; i < len; i++)
10870 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10871 /* Don't bother with these. They shouldn't occur anyway. */
10875 /* If we haven't found a reason for it to be invalid, it is valid. */
10879 /* Get the last value assigned to X, if known. Some registers
10880 in the value may be replaced with (clobber (const_int 0)) if their value
10881 is known longer known reliably. */
10890 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10891 then convert it to the desired mode. If this is a paradoxical SUBREG,
10892 we cannot predict what values the "extra" bits might have. */
10893 if (GET_CODE (x) == SUBREG
10894 && subreg_lowpart_p (x)
10895 && (GET_MODE_SIZE (GET_MODE (x))
10896 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10897 && (value = get_last_value (SUBREG_REG (x))) != 0)
10898 return gen_lowpart_for_combine (GET_MODE (x), value);
10900 if (GET_CODE (x) != REG)
10904 value = reg_last_set_value[regno];
10906 /* If we don't have a value, or if it isn't for this basic block and
10907 it's either a hard register, set more than once, or it's a live
10908 at the beginning of the function, return 0.
10910 Because if it's not live at the beginnning of the function then the reg
10911 is always set before being used (is never used without being set).
10912 And, if it's set only once, and it's always set before use, then all
10913 uses must have the same last value, even if it's not from this basic
10917 || (reg_last_set_label[regno] != label_tick
10918 && (regno < FIRST_PSEUDO_REGISTER
10919 || REG_N_SETS (regno) != 1
10920 || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))))
10923 /* If the value was set in a later insn than the ones we are processing,
10924 we can't use it even if the register was only set once. */
10925 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10928 /* If the value has all its registers valid, return it. */
10929 if (get_last_value_validate (&value, reg_last_set[regno],
10930 reg_last_set_label[regno], 0))
10933 /* Otherwise, make a copy and replace any invalid register with
10934 (clobber (const_int 0)). If that fails for some reason, return 0. */
10936 value = copy_rtx (value);
10937 if (get_last_value_validate (&value, reg_last_set[regno],
10938 reg_last_set_label[regno], 1))
10944 /* Return nonzero if expression X refers to a REG or to memory
10945 that is set in an instruction more recent than FROM_CUID. */
10948 use_crosses_set_p (x, from_cuid)
10952 register char *fmt;
10954 register enum rtx_code code = GET_CODE (x);
10958 register int regno = REGNO (x);
10959 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10960 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10962 #ifdef PUSH_ROUNDING
10963 /* Don't allow uses of the stack pointer to be moved,
10964 because we don't know whether the move crosses a push insn. */
10965 if (regno == STACK_POINTER_REGNUM)
10968 for (;regno < endreg; regno++)
10969 if (reg_last_set[regno]
10970 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10975 if (code == MEM && mem_last_set > from_cuid)
10978 fmt = GET_RTX_FORMAT (code);
10980 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10985 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10986 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10989 else if (fmt[i] == 'e'
10990 && use_crosses_set_p (XEXP (x, i), from_cuid))
10996 /* Define three variables used for communication between the following
10999 static int reg_dead_regno, reg_dead_endregno;
11000 static int reg_dead_flag;
11002 /* Function called via note_stores from reg_dead_at_p.
11004 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11005 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11008 reg_dead_at_p_1 (dest, x)
11012 int regno, endregno;
11014 if (GET_CODE (dest) != REG)
11017 regno = REGNO (dest);
11018 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11019 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11021 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11022 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11025 /* Return non-zero if REG is known to be dead at INSN.
11027 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11028 referencing REG, it is dead. If we hit a SET referencing REG, it is
11029 live. Otherwise, see if it is live or dead at the start of the basic
11030 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11031 must be assumed to be always live. */
11034 reg_dead_at_p (reg, insn)
11040 /* Set variables for reg_dead_at_p_1. */
11041 reg_dead_regno = REGNO (reg);
11042 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11043 ? HARD_REGNO_NREGS (reg_dead_regno,
11049 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11050 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11052 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11053 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11057 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11058 beginning of function. */
11059 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11060 insn = prev_nonnote_insn (insn))
11062 note_stores (PATTERN (insn), reg_dead_at_p_1);
11064 return reg_dead_flag == 1 ? 1 : 0;
11066 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11070 /* Get the basic block number that we were in. */
11075 for (block = 0; block < n_basic_blocks; block++)
11076 if (insn == BLOCK_HEAD (block))
11079 if (block == n_basic_blocks)
11083 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11084 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11090 /* Note hard registers in X that are used. This code is similar to
11091 that in flow.c, but much simpler since we don't care about pseudos. */
11094 mark_used_regs_combine (x)
11097 register RTX_CODE code = GET_CODE (x);
11098 register int regno;
11110 case ADDR_DIFF_VEC:
11113 /* CC0 must die in the insn after it is set, so we don't need to take
11114 special note of it here. */
11120 /* If we are clobbering a MEM, mark any hard registers inside the
11121 address as used. */
11122 if (GET_CODE (XEXP (x, 0)) == MEM)
11123 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11128 /* A hard reg in a wide mode may really be multiple registers.
11129 If so, mark all of them just like the first. */
11130 if (regno < FIRST_PSEUDO_REGISTER)
11132 /* None of this applies to the stack, frame or arg pointers */
11133 if (regno == STACK_POINTER_REGNUM
11134 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11135 || regno == HARD_FRAME_POINTER_REGNUM
11137 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11138 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11140 || regno == FRAME_POINTER_REGNUM)
11143 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11145 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11151 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11153 register rtx testreg = SET_DEST (x);
11155 while (GET_CODE (testreg) == SUBREG
11156 || GET_CODE (testreg) == ZERO_EXTRACT
11157 || GET_CODE (testreg) == SIGN_EXTRACT
11158 || GET_CODE (testreg) == STRICT_LOW_PART)
11159 testreg = XEXP (testreg, 0);
11161 if (GET_CODE (testreg) == MEM)
11162 mark_used_regs_combine (XEXP (testreg, 0));
11164 mark_used_regs_combine (SET_SRC (x));
11172 /* Recursively scan the operands of this expression. */
11175 register char *fmt = GET_RTX_FORMAT (code);
11177 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11180 mark_used_regs_combine (XEXP (x, i));
11181 else if (fmt[i] == 'E')
11185 for (j = 0; j < XVECLEN (x, i); j++)
11186 mark_used_regs_combine (XVECEXP (x, i, j));
11193 /* Remove register number REGNO from the dead registers list of INSN.
11195 Return the note used to record the death, if there was one. */
11198 remove_death (regno, insn)
11202 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11206 REG_N_DEATHS (regno)--;
11207 remove_note (insn, note);
11213 /* For each register (hardware or pseudo) used within expression X, if its
11214 death is in an instruction with cuid between FROM_CUID (inclusive) and
11215 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11216 list headed by PNOTES.
11218 That said, don't move registers killed by maybe_kill_insn.
11220 This is done when X is being merged by combination into TO_INSN. These
11221 notes will then be distributed as needed. */
11224 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11226 rtx maybe_kill_insn;
11231 register char *fmt;
11232 register int len, i;
11233 register enum rtx_code code = GET_CODE (x);
11237 register int regno = REGNO (x);
11238 register rtx where_dead = reg_last_death[regno];
11239 register rtx before_dead, after_dead;
11241 /* Don't move the register if it gets killed in between from and to */
11242 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11243 && !reg_referenced_p (x, maybe_kill_insn))
11246 /* WHERE_DEAD could be a USE insn made by combine, so first we
11247 make sure that we have insns with valid INSN_CUID values. */
11248 before_dead = where_dead;
11249 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11250 before_dead = PREV_INSN (before_dead);
11251 after_dead = where_dead;
11252 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11253 after_dead = NEXT_INSN (after_dead);
11255 if (before_dead && after_dead
11256 && INSN_CUID (before_dead) >= from_cuid
11257 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11258 || (where_dead != after_dead
11259 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11261 rtx note = remove_death (regno, where_dead);
11263 /* It is possible for the call above to return 0. This can occur
11264 when reg_last_death points to I2 or I1 that we combined with.
11265 In that case make a new note.
11267 We must also check for the case where X is a hard register
11268 and NOTE is a death note for a range of hard registers
11269 including X. In that case, we must put REG_DEAD notes for
11270 the remaining registers in place of NOTE. */
11272 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11273 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11274 > GET_MODE_SIZE (GET_MODE (x))))
11276 int deadregno = REGNO (XEXP (note, 0));
11278 = (deadregno + HARD_REGNO_NREGS (deadregno,
11279 GET_MODE (XEXP (note, 0))));
11280 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11283 for (i = deadregno; i < deadend; i++)
11284 if (i < regno || i >= ourend)
11285 REG_NOTES (where_dead)
11286 = gen_rtx_EXPR_LIST (REG_DEAD,
11287 gen_rtx_REG (reg_raw_mode[i], i),
11288 REG_NOTES (where_dead));
11290 /* If we didn't find any note, or if we found a REG_DEAD note that
11291 covers only part of the given reg, and we have a multi-reg hard
11292 register, then to be safe we must check for REG_DEAD notes
11293 for each register other than the first. They could have
11294 their own REG_DEAD notes lying around. */
11295 else if ((note == 0
11297 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11298 < GET_MODE_SIZE (GET_MODE (x)))))
11299 && regno < FIRST_PSEUDO_REGISTER
11300 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11302 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11307 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11311 for (i = regno + offset; i < ourend; i++)
11312 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11313 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11316 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11318 XEXP (note, 1) = *pnotes;
11322 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11324 REG_N_DEATHS (regno)++;
11330 else if (GET_CODE (x) == SET)
11332 rtx dest = SET_DEST (x);
11334 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11336 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11337 that accesses one word of a multi-word item, some
11338 piece of everything register in the expression is used by
11339 this insn, so remove any old death. */
11341 if (GET_CODE (dest) == ZERO_EXTRACT
11342 || GET_CODE (dest) == STRICT_LOW_PART
11343 || (GET_CODE (dest) == SUBREG
11344 && (((GET_MODE_SIZE (GET_MODE (dest))
11345 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11346 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11347 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11349 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11353 /* If this is some other SUBREG, we know it replaces the entire
11354 value, so use that as the destination. */
11355 if (GET_CODE (dest) == SUBREG)
11356 dest = SUBREG_REG (dest);
11358 /* If this is a MEM, adjust deaths of anything used in the address.
11359 For a REG (the only other possibility), the entire value is
11360 being replaced so the old value is not used in this insn. */
11362 if (GET_CODE (dest) == MEM)
11363 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11368 else if (GET_CODE (x) == CLOBBER)
11371 len = GET_RTX_LENGTH (code);
11372 fmt = GET_RTX_FORMAT (code);
11374 for (i = 0; i < len; i++)
11379 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11380 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11383 else if (fmt[i] == 'e')
11384 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11388 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11389 pattern of an insn. X must be a REG. */
11392 reg_bitfield_target_p (x, body)
11398 if (GET_CODE (body) == SET)
11400 rtx dest = SET_DEST (body);
11402 int regno, tregno, endregno, endtregno;
11404 if (GET_CODE (dest) == ZERO_EXTRACT)
11405 target = XEXP (dest, 0);
11406 else if (GET_CODE (dest) == STRICT_LOW_PART)
11407 target = SUBREG_REG (XEXP (dest, 0));
11411 if (GET_CODE (target) == SUBREG)
11412 target = SUBREG_REG (target);
11414 if (GET_CODE (target) != REG)
11417 tregno = REGNO (target), regno = REGNO (x);
11418 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11419 return target == x;
11421 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11422 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11424 return endregno > tregno && regno < endtregno;
11427 else if (GET_CODE (body) == PARALLEL)
11428 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11429 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11435 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11436 as appropriate. I3 and I2 are the insns resulting from the combination
11437 insns including FROM (I2 may be zero).
11439 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11440 not need REG_DEAD notes because they are being substituted for. This
11441 saves searching in the most common cases.
11443 Each note in the list is either ignored or placed on some insns, depending
11444 on the type of note. */
11447 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11451 rtx elim_i2, elim_i1;
11453 rtx note, next_note;
11456 for (note = notes; note; note = next_note)
11458 rtx place = 0, place2 = 0;
11460 /* If this NOTE references a pseudo register, ensure it references
11461 the latest copy of that register. */
11462 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11463 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11464 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11466 next_note = XEXP (note, 1);
11467 switch (REG_NOTE_KIND (note))
11470 case REG_EXEC_COUNT:
11471 /* Doesn't matter much where we put this, as long as it's somewhere.
11472 It is preferable to keep these notes on branches, which is most
11473 likely to be i3. */
11477 case REG_EH_REGION:
11478 /* This note must remain with the call. It should not be possible
11479 for both I2 and I3 to be a call. */
11480 if (GET_CODE (i3) == CALL_INSN)
11482 else if (i2 && GET_CODE (i2) == CALL_INSN)
11489 /* Any clobbers for i3 may still exist, and so we must process
11490 REG_UNUSED notes from that insn.
11492 Any clobbers from i2 or i1 can only exist if they were added by
11493 recog_for_combine. In that case, recog_for_combine created the
11494 necessary REG_UNUSED notes. Trying to keep any original
11495 REG_UNUSED notes from these insns can cause incorrect output
11496 if it is for the same register as the original i3 dest.
11497 In that case, we will notice that the register is set in i3,
11498 and then add a REG_UNUSED note for the destination of i3, which
11499 is wrong. However, it is possible to have REG_UNUSED notes from
11500 i2 or i1 for register which were both used and clobbered, so
11501 we keep notes from i2 or i1 if they will turn into REG_DEAD
11504 /* If this register is set or clobbered in I3, put the note there
11505 unless there is one already. */
11506 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11508 if (from_insn != i3)
11511 if (! (GET_CODE (XEXP (note, 0)) == REG
11512 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11513 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11516 /* Otherwise, if this register is used by I3, then this register
11517 now dies here, so we must put a REG_DEAD note here unless there
11519 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11520 && ! (GET_CODE (XEXP (note, 0)) == REG
11521 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11522 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11524 PUT_REG_NOTE_KIND (note, REG_DEAD);
11533 /* These notes say something about results of an insn. We can
11534 only support them if they used to be on I3 in which case they
11535 remain on I3. Otherwise they are ignored.
11537 If the note refers to an expression that is not a constant, we
11538 must also ignore the note since we cannot tell whether the
11539 equivalence is still true. It might be possible to do
11540 slightly better than this (we only have a problem if I2DEST
11541 or I1DEST is present in the expression), but it doesn't
11542 seem worth the trouble. */
11544 if (from_insn == i3
11545 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11550 case REG_NO_CONFLICT:
11551 /* These notes say something about how a register is used. They must
11552 be present on any use of the register in I2 or I3. */
11553 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11556 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11566 /* This can show up in several ways -- either directly in the
11567 pattern, or hidden off in the constant pool with (or without?)
11568 a REG_EQUAL note. */
11569 /* ??? Ignore the without-reg_equal-note problem for now. */
11570 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11571 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11572 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11573 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11577 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11578 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11579 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11580 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11590 /* It is too much trouble to try to see if this note is still
11591 correct in all situations. It is better to simply delete it. */
11595 /* If the insn previously containing this note still exists,
11596 put it back where it was. Otherwise move it to the previous
11597 insn. Adjust the corresponding REG_LIBCALL note. */
11598 if (GET_CODE (from_insn) != NOTE)
11602 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11603 place = prev_real_insn (from_insn);
11605 XEXP (tem, 0) = place;
11610 /* This is handled similarly to REG_RETVAL. */
11611 if (GET_CODE (from_insn) != NOTE)
11615 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11616 place = next_real_insn (from_insn);
11618 XEXP (tem, 0) = place;
11623 /* If the register is used as an input in I3, it dies there.
11624 Similarly for I2, if it is non-zero and adjacent to I3.
11626 If the register is not used as an input in either I3 or I2
11627 and it is not one of the registers we were supposed to eliminate,
11628 there are two possibilities. We might have a non-adjacent I2
11629 or we might have somehow eliminated an additional register
11630 from a computation. For example, we might have had A & B where
11631 we discover that B will always be zero. In this case we will
11632 eliminate the reference to A.
11634 In both cases, we must search to see if we can find a previous
11635 use of A and put the death note there. */
11638 && GET_CODE (from_insn) == CALL_INSN
11639 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11641 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11643 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11644 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11647 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11650 /* If the register is used in both I2 and I3 and it dies in I3,
11651 we might have added another reference to it. If reg_n_refs
11652 was 2, bump it to 3. This has to be correct since the
11653 register must have been set somewhere. The reason this is
11654 done is because local-alloc.c treats 2 references as a
11657 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11658 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11659 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11660 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11664 for (tem = prev_nonnote_insn (i3);
11666 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11667 tem = prev_nonnote_insn (tem))
11669 /* If the register is being set at TEM, see if that is all
11670 TEM is doing. If so, delete TEM. Otherwise, make this
11671 into a REG_UNUSED note instead. */
11672 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11674 rtx set = single_set (tem);
11675 rtx inner_dest = 0;
11677 rtx cc0_setter = NULL_RTX;
11681 for (inner_dest = SET_DEST (set);
11682 GET_CODE (inner_dest) == STRICT_LOW_PART
11683 || GET_CODE (inner_dest) == SUBREG
11684 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11685 inner_dest = XEXP (inner_dest, 0))
11688 /* Verify that it was the set, and not a clobber that
11689 modified the register.
11691 CC0 targets must be careful to maintain setter/user
11692 pairs. If we cannot delete the setter due to side
11693 effects, mark the user with an UNUSED note instead
11696 if (set != 0 && ! side_effects_p (SET_SRC (set))
11697 && rtx_equal_p (XEXP (note, 0), inner_dest)
11699 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11700 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11701 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11705 /* Move the notes and links of TEM elsewhere.
11706 This might delete other dead insns recursively.
11707 First set the pattern to something that won't use
11710 PATTERN (tem) = pc_rtx;
11712 distribute_notes (REG_NOTES (tem), tem, tem,
11713 NULL_RTX, NULL_RTX, NULL_RTX);
11714 distribute_links (LOG_LINKS (tem));
11716 PUT_CODE (tem, NOTE);
11717 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11718 NOTE_SOURCE_FILE (tem) = 0;
11721 /* Delete the setter too. */
11724 PATTERN (cc0_setter) = pc_rtx;
11726 distribute_notes (REG_NOTES (cc0_setter),
11727 cc0_setter, cc0_setter,
11728 NULL_RTX, NULL_RTX, NULL_RTX);
11729 distribute_links (LOG_LINKS (cc0_setter));
11731 PUT_CODE (cc0_setter, NOTE);
11732 NOTE_LINE_NUMBER (cc0_setter) = NOTE_INSN_DELETED;
11733 NOTE_SOURCE_FILE (cc0_setter) = 0;
11737 /* If the register is both set and used here, put the
11738 REG_DEAD note here, but place a REG_UNUSED note
11739 here too unless there already is one. */
11740 else if (reg_referenced_p (XEXP (note, 0),
11745 if (! find_regno_note (tem, REG_UNUSED,
11746 REGNO (XEXP (note, 0))))
11748 = gen_rtx_EXPR_LIST (REG_UNUSED,
11754 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11756 /* If there isn't already a REG_UNUSED note, put one
11758 if (! find_regno_note (tem, REG_UNUSED,
11759 REGNO (XEXP (note, 0))))
11764 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11765 || (GET_CODE (tem) == CALL_INSN
11766 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11770 /* If we are doing a 3->2 combination, and we have a
11771 register which formerly died in i3 and was not used
11772 by i2, which now no longer dies in i3 and is used in
11773 i2 but does not die in i2, and place is between i2
11774 and i3, then we may need to move a link from place to
11776 if (i2 && INSN_UID (place) <= max_uid_cuid
11777 && INSN_CUID (place) > INSN_CUID (i2)
11778 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11779 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11781 rtx links = LOG_LINKS (place);
11782 LOG_LINKS (place) = 0;
11783 distribute_links (links);
11789 /* If we haven't found an insn for the death note and it
11790 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11791 insert a USE insn for the register at that label and
11792 put the death node there. This prevents problems with
11793 call-state tracking in caller-save.c. */
11794 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11797 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
11800 /* If this insn was emitted between blocks, then update
11801 BLOCK_HEAD of the current block to include it. */
11802 if (BLOCK_END (this_basic_block - 1) == tem)
11803 BLOCK_HEAD (this_basic_block) = place;
11807 /* If the register is set or already dead at PLACE, we needn't do
11808 anything with this note if it is still a REG_DEAD note.
11809 We can here if it is set at all, not if is it totally replace,
11810 which is what `dead_or_set_p' checks, so also check for it being
11814 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11816 int regno = REGNO (XEXP (note, 0));
11818 if (dead_or_set_p (place, XEXP (note, 0))
11819 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11821 /* Unless the register previously died in PLACE, clear
11822 reg_last_death. [I no longer understand why this is
11824 if (reg_last_death[regno] != place)
11825 reg_last_death[regno] = 0;
11829 reg_last_death[regno] = place;
11831 /* If this is a death note for a hard reg that is occupying
11832 multiple registers, ensure that we are still using all
11833 parts of the object. If we find a piece of the object
11834 that is unused, we must add a USE for that piece before
11835 PLACE and put the appropriate REG_DEAD note on it.
11837 An alternative would be to put a REG_UNUSED for the pieces
11838 on the insn that set the register, but that can't be done if
11839 it is not in the same block. It is simpler, though less
11840 efficient, to add the USE insns. */
11842 if (place && regno < FIRST_PSEUDO_REGISTER
11843 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11846 = regno + HARD_REGNO_NREGS (regno,
11847 GET_MODE (XEXP (note, 0)));
11851 for (i = regno; i < endregno; i++)
11852 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11853 && ! find_regno_fusage (place, USE, i))
11855 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11858 /* See if we already placed a USE note for this
11859 register in front of PLACE. */
11861 GET_CODE (PREV_INSN (p)) == INSN
11862 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11864 if (rtx_equal_p (piece,
11865 XEXP (PATTERN (PREV_INSN (p)), 0)))
11874 = emit_insn_before (gen_rtx_USE (VOIDmode,
11877 REG_NOTES (use_insn)
11878 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11879 REG_NOTES (use_insn));
11885 /* Check for the case where the register dying partially
11886 overlaps the register set by this insn. */
11888 for (i = regno; i < endregno; i++)
11889 if (dead_or_set_regno_p (place, i))
11897 /* Put only REG_DEAD notes for pieces that are
11898 still used and that are not already dead or set. */
11900 for (i = regno; i < endregno; i++)
11902 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11904 if ((reg_referenced_p (piece, PATTERN (place))
11905 || (GET_CODE (place) == CALL_INSN
11906 && find_reg_fusage (place, USE, piece)))
11907 && ! dead_or_set_p (place, piece)
11908 && ! reg_bitfield_target_p (piece,
11911 = gen_rtx_EXPR_LIST (REG_DEAD,
11912 piece, REG_NOTES (place));
11922 /* Any other notes should not be present at this point in the
11929 XEXP (note, 1) = REG_NOTES (place);
11930 REG_NOTES (place) = note;
11932 else if ((REG_NOTE_KIND (note) == REG_DEAD
11933 || REG_NOTE_KIND (note) == REG_UNUSED)
11934 && GET_CODE (XEXP (note, 0)) == REG)
11935 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11939 if ((REG_NOTE_KIND (note) == REG_DEAD
11940 || REG_NOTE_KIND (note) == REG_UNUSED)
11941 && GET_CODE (XEXP (note, 0)) == REG)
11942 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11944 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11945 REG_NOTE_KIND (note),
11947 REG_NOTES (place2));
11952 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11953 I3, I2, and I1 to new locations. This is also called in one case to
11954 add a link pointing at I3 when I3's destination is changed. */
11957 distribute_links (links)
11960 rtx link, next_link;
11962 for (link = links; link; link = next_link)
11968 next_link = XEXP (link, 1);
11970 /* If the insn that this link points to is a NOTE or isn't a single
11971 set, ignore it. In the latter case, it isn't clear what we
11972 can do other than ignore the link, since we can't tell which
11973 register it was for. Such links wouldn't be used by combine
11976 It is not possible for the destination of the target of the link to
11977 have been changed by combine. The only potential of this is if we
11978 replace I3, I2, and I1 by I3 and I2. But in that case the
11979 destination of I2 also remains unchanged. */
11981 if (GET_CODE (XEXP (link, 0)) == NOTE
11982 || (set = single_set (XEXP (link, 0))) == 0)
11985 reg = SET_DEST (set);
11986 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11987 || GET_CODE (reg) == SIGN_EXTRACT
11988 || GET_CODE (reg) == STRICT_LOW_PART)
11989 reg = XEXP (reg, 0);
11991 /* A LOG_LINK is defined as being placed on the first insn that uses
11992 a register and points to the insn that sets the register. Start
11993 searching at the next insn after the target of the link and stop
11994 when we reach a set of the register or the end of the basic block.
11996 Note that this correctly handles the link that used to point from
11997 I3 to I2. Also note that not much searching is typically done here
11998 since most links don't point very far away. */
12000 for (insn = NEXT_INSN (XEXP (link, 0));
12001 (insn && (this_basic_block == n_basic_blocks - 1
12002 || BLOCK_HEAD (this_basic_block + 1) != insn));
12003 insn = NEXT_INSN (insn))
12004 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
12005 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12007 if (reg_referenced_p (reg, PATTERN (insn)))
12011 else if (GET_CODE (insn) == CALL_INSN
12012 && find_reg_fusage (insn, USE, reg))
12018 /* If we found a place to put the link, place it there unless there
12019 is already a link to the same insn as LINK at that point. */
12025 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12026 if (XEXP (link2, 0) == XEXP (link, 0))
12031 XEXP (link, 1) = LOG_LINKS (place);
12032 LOG_LINKS (place) = link;
12034 /* Set added_links_insn to the earliest insn we added a
12036 if (added_links_insn == 0
12037 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12038 added_links_insn = place;
12044 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12050 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12051 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12052 insn = NEXT_INSN (insn);
12054 if (INSN_UID (insn) > max_uid_cuid)
12057 return INSN_CUID (insn);
12061 dump_combine_stats (file)
12066 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12067 combine_attempts, combine_merges, combine_extras, combine_successes);
12071 dump_combine_total_stats (file)
12076 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12077 total_attempts, total_merges, total_extras, total_successes);