3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.38 2008/03/10 12:59:51 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
118 #include <sys/endian.h>
119 #include <sys/kernel.h>
120 #include <sys/malloc.h>
121 #include <sys/mbuf.h>
122 /* #include <sys/module.h> */
123 #include <sys/rman.h>
124 #include <sys/serialize.h>
125 #include <sys/socket.h>
126 #include <sys/sockio.h>
127 #include <sys/sysctl.h>
130 #include <net/ethernet.h>
132 #include <net/ifq_var.h>
133 #include <net/if_arp.h>
134 #include <net/if_dl.h>
135 #include <net/if_media.h>
136 #include <net/if_types.h>
137 #include <net/vlan/if_vlan_var.h>
138 #include <net/vlan/if_vlan_ether.h>
140 #include <dev/netif/mii_layer/mii.h>
141 #include <dev/netif/mii_layer/miivar.h>
143 #include <bus/pci/pcidevs.h>
144 #include <bus/pci/pcireg.h>
145 #include <bus/pci/pcivar.h>
147 /* "device miibus" required. See GENERIC if you get errors here. */
148 #include "miibus_if.h"
150 #include <dev/netif/re/if_rereg.h>
151 #include <dev/netif/re/if_revar.h>
153 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
155 #define RE_DISABLE_HWCSUM
159 * Various supported device vendors/types and their names.
161 static const struct re_type re_devs[] = {
162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
163 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
164 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
165 "RealTek 8139C+ 10/100BaseTX" },
166 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E,
167 "RealTek 8101E PCIe 10/100baseTX" },
168 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1,
169 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
170 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2,
171 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
172 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN3,
173 "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
175 "RealTek 8169 Gigabit Ethernet" },
176 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
177 "RealTek 8169S Single-chip Gigabit Ethernet" },
178 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB,
179 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC,
181 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
182 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC,
183 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
184 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
185 "RealTek 8110S Single-chip Gigabit Ethernet" },
186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S,
187 "Corega CG-LAPCIGT Gigabit Ethernet" },
188 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S,
189 "Linksys EG1032 Gigabit Ethernet" },
190 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S,
191 "US Robotics 997902 Gigabit Ethernet" },
195 static const struct re_hwrev re_hwrevs[] = {
196 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" },
197 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" },
198 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" },
199 { RE_HWREV_8168_SPIN3, RE_8169, RE_F_PCIE, "8168" },
200 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" },
201 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" },
202 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" },
203 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" },
204 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" },
205 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" },
206 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" },
210 static int re_probe(device_t);
211 static int re_attach(device_t);
212 static int re_detach(device_t);
214 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
216 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
217 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
219 static int re_allocmem(device_t, struct re_softc *);
220 static int re_newbuf(struct re_softc *, int, struct mbuf *);
221 static int re_rx_list_init(struct re_softc *);
222 static int re_tx_list_init(struct re_softc *);
223 static void re_rxeof(struct re_softc *);
224 static void re_txeof(struct re_softc *);
225 static void re_intr(void *);
226 static void re_tick(void *);
227 static void re_tick_serialized(void *);
228 static void re_start(struct ifnet *);
229 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
230 static void re_init(void *);
231 static void re_stop(struct re_softc *);
232 static void re_watchdog(struct ifnet *);
233 static int re_suspend(device_t);
234 static int re_resume(device_t);
235 static void re_shutdown(device_t);
236 static int re_ifmedia_upd(struct ifnet *);
237 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
239 static void re_eeprom_putbyte(struct re_softc *, int);
240 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
241 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
242 static int re_gmii_readreg(device_t, int, int);
243 static int re_gmii_writereg(device_t, int, int, int);
245 static int re_miibus_readreg(device_t, int, int);
246 static int re_miibus_writereg(device_t, int, int, int);
247 static void re_miibus_statchg(device_t);
249 static void re_setmulti(struct re_softc *);
250 static void re_reset(struct re_softc *);
253 static int re_diag(struct re_softc *);
256 #ifdef DEVICE_POLLING
257 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
260 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS);
262 static device_method_t re_methods[] = {
263 /* Device interface */
264 DEVMETHOD(device_probe, re_probe),
265 DEVMETHOD(device_attach, re_attach),
266 DEVMETHOD(device_detach, re_detach),
267 DEVMETHOD(device_suspend, re_suspend),
268 DEVMETHOD(device_resume, re_resume),
269 DEVMETHOD(device_shutdown, re_shutdown),
272 DEVMETHOD(bus_print_child, bus_generic_print_child),
273 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
276 DEVMETHOD(miibus_readreg, re_miibus_readreg),
277 DEVMETHOD(miibus_writereg, re_miibus_writereg),
278 DEVMETHOD(miibus_statchg, re_miibus_statchg),
283 static driver_t re_driver = {
286 sizeof(struct re_softc)
289 static devclass_t re_devclass;
291 DECLARE_DUMMY_MODULE(if_re);
292 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
293 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
294 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
297 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
300 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
303 * Send a read command and address to the EEPROM, check for ACK.
306 re_eeprom_putbyte(struct re_softc *sc, int addr)
310 d = addr | (RE_9346_READ << sc->re_eewidth);
313 * Feed in each bit and strobe the clock.
315 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
317 EE_SET(RE_EE_DATAIN);
319 EE_CLR(RE_EE_DATAIN);
329 * Read a word of data stored in the EEPROM at address 'addr.'
332 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
338 * Send address of word we want to read.
340 re_eeprom_putbyte(sc, addr);
343 * Start reading bits from EEPROM.
345 for (i = 0x8000; i != 0; i >>= 1) {
348 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
358 * Read a sequence of words from the EEPROM.
361 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
364 uint16_t word = 0, *ptr;
366 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
369 for (i = 0; i < cnt; i++) {
370 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
371 re_eeprom_getword(sc, off + i, &word);
372 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
373 ptr = (uint16_t *)(dest + (i * 2));
377 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
381 re_gmii_readreg(device_t dev, int phy, int reg)
383 struct re_softc *sc = device_get_softc(dev);
390 /* Let the rgephy driver read the GMEDIASTAT register */
392 if (reg == RE_GMEDIASTAT)
393 return(CSR_READ_1(sc, RE_GMEDIASTAT));
395 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
398 for (i = 0; i < RE_TIMEOUT; i++) {
399 rval = CSR_READ_4(sc, RE_PHYAR);
400 if (rval & RE_PHYAR_BUSY)
405 if (i == RE_TIMEOUT) {
406 device_printf(dev, "PHY read failed\n");
410 return(rval & RE_PHYAR_PHYDATA);
414 re_gmii_writereg(device_t dev, int phy, int reg, int data)
416 struct re_softc *sc = device_get_softc(dev);
420 CSR_WRITE_4(sc, RE_PHYAR,
421 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
424 for (i = 0; i < RE_TIMEOUT; i++) {
425 rval = CSR_READ_4(sc, RE_PHYAR);
426 if ((rval & RE_PHYAR_BUSY) == 0)
432 device_printf(dev, "PHY write failed\n");
438 re_miibus_readreg(device_t dev, int phy, int reg)
440 struct re_softc *sc = device_get_softc(dev);
442 uint16_t re8139_reg = 0;
444 if (sc->re_type == RE_8169) {
445 rval = re_gmii_readreg(dev, phy, reg);
449 /* Pretend the internal PHY is only at address 0 */
455 re8139_reg = RE_BMCR;
458 re8139_reg = RE_BMSR;
461 re8139_reg = RE_ANAR;
464 re8139_reg = RE_ANER;
467 re8139_reg = RE_LPAR;
473 * Allow the rlphy driver to read the media status
474 * register. If we have a link partner which does not
475 * support NWAY, this is the register which will tell
476 * us the results of parallel detection.
479 return(CSR_READ_1(sc, RE_MEDIASTAT));
481 device_printf(dev, "bad phy register\n");
484 rval = CSR_READ_2(sc, re8139_reg);
485 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) {
486 /* 8139C+ has different bit layout. */
487 rval &= ~(BMCR_LOOP | BMCR_ISO);
493 re_miibus_writereg(device_t dev, int phy, int reg, int data)
495 struct re_softc *sc= device_get_softc(dev);
496 u_int16_t re8139_reg = 0;
498 if (sc->re_type == RE_8169)
499 return(re_gmii_writereg(dev, phy, reg, data));
501 /* Pretend the internal PHY is only at address 0 */
507 re8139_reg = RE_BMCR;
508 if (sc->re_type == RE_8139CPLUS) {
509 /* 8139C+ has different bit layout. */
510 data &= ~(BMCR_LOOP | BMCR_ISO);
514 re8139_reg = RE_BMSR;
517 re8139_reg = RE_ANAR;
520 re8139_reg = RE_ANER;
523 re8139_reg = RE_LPAR;
529 device_printf(dev, "bad phy register\n");
532 CSR_WRITE_2(sc, re8139_reg, data);
537 re_miibus_statchg(device_t dev)
542 * Program the 64-bit multicast hash filter.
545 re_setmulti(struct re_softc *sc)
547 struct ifnet *ifp = &sc->arpcom.ac_if;
549 uint32_t hashes[2] = { 0, 0 };
550 struct ifmultiaddr *ifma;
554 rxfilt = CSR_READ_4(sc, RE_RXCFG);
556 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
557 rxfilt |= RE_RXCFG_RX_MULTI;
558 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
559 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
560 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
564 /* first, zot all the existing hash bits */
565 CSR_WRITE_4(sc, RE_MAR0, 0);
566 CSR_WRITE_4(sc, RE_MAR4, 0);
568 /* now program new ones */
569 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
570 if (ifma->ifma_addr->sa_family != AF_LINK)
572 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
573 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
575 hashes[0] |= (1 << h);
577 hashes[1] |= (1 << (h - 32));
582 rxfilt |= RE_RXCFG_RX_MULTI;
584 rxfilt &= ~RE_RXCFG_RX_MULTI;
586 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
589 * For some unfathomable reason, RealTek decided to reverse
590 * the order of the multicast hash registers in the PCI Express
591 * parts. This means we have to write the hash pattern in reverse
592 * order for those devices.
594 if (sc->re_flags & RE_F_PCIE) {
595 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0]));
596 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1]));
598 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
599 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
604 re_reset(struct re_softc *sc)
608 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
610 for (i = 0; i < RE_TIMEOUT; i++) {
612 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
616 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
618 CSR_WRITE_1(sc, 0x82, 1);
623 * The following routine is designed to test for a defect on some
624 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
625 * lines connected to the bus, however for a 32-bit only card, they
626 * should be pulled high. The result of this defect is that the
627 * NIC will not work right if you plug it into a 64-bit slot: DMA
628 * operations will be done with 64-bit transfers, which will fail
629 * because the 64-bit data lines aren't connected.
631 * There's no way to work around this (short of talking a soldering
632 * iron to the board), however we can detect it. The method we use
633 * here is to put the NIC into digital loopback mode, set the receiver
634 * to promiscuous mode, and then try to send a frame. We then compare
635 * the frame data we sent to what was received. If the data matches,
636 * then the NIC is working correctly, otherwise we know the user has
637 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
638 * slot. In the latter case, there's no way the NIC can work correctly,
639 * so we print out a message on the console and abort the device attach.
643 re_diag(struct re_softc *sc)
645 struct ifnet *ifp = &sc->arpcom.ac_if;
647 struct ether_header *eh;
648 struct re_desc *cur_rx;
651 int total_len, i, error = 0, phyaddr;
652 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
653 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
655 /* Allocate a single mbuf */
657 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
662 * Initialize the NIC in test mode. This sets the chip up
663 * so that it can send and receive frames, but performs the
664 * following special functions:
665 * - Puts receiver in promiscuous mode
666 * - Enables digital loopback mode
667 * - Leaves interrupts turned off
670 ifp->if_flags |= IFF_PROMISC;
675 if (sc->re_type == RE_8169)
680 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
681 for (i = 0; i < RE_TIMEOUT; i++) {
682 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
683 if (!(status & BMCR_RESET))
687 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
688 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
692 /* Put some data in the mbuf */
694 eh = mtod(m0, struct ether_header *);
695 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
696 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
697 eh->ether_type = htons(ETHERTYPE_IP);
698 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
701 * Queue the packet, start transmission.
702 * Note: ifq_handoff() ultimately calls re_start() for us.
705 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
706 error = ifq_handoff(ifp, m0, NULL);
713 /* Wait for it to propagate through the chip */
716 for (i = 0; i < RE_TIMEOUT; i++) {
717 status = CSR_READ_2(sc, RE_ISR);
718 CSR_WRITE_2(sc, RE_ISR, status);
719 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
720 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
725 if (i == RE_TIMEOUT) {
726 if_printf(ifp, "diagnostic failed to receive packet "
727 "in loopback mode\n");
733 * The packet should have been dumped into the first
734 * entry in the RX DMA ring. Grab it from there.
737 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
738 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
739 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
740 BUS_DMASYNC_POSTWRITE);
741 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
743 m0 = sc->re_ldata.re_rx_mbuf[0];
744 sc->re_ldata.re_rx_mbuf[0] = NULL;
745 eh = mtod(m0, struct ether_header *);
747 cur_rx = &sc->re_ldata.re_rx_list[0];
748 total_len = RE_RXBYTES(cur_rx);
749 rxstat = le32toh(cur_rx->re_cmdstat);
751 if (total_len != ETHER_MIN_LEN) {
752 if_printf(ifp, "diagnostic failed, received short packet\n");
757 /* Test that the received packet data matches what we sent. */
759 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
760 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
761 be16toh(eh->ether_type) != ETHERTYPE_IP) {
762 if_printf(ifp, "WARNING, DMA FAILURE!\n");
763 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
764 dst, ":", src, ":", ETHERTYPE_IP);
765 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
766 eh->ether_dhost, ":", eh->ether_shost, ":",
767 ntohs(eh->ether_type));
768 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
769 "into a 64-bit PCI slot.\n");
770 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
771 "for proper operation.\n");
772 if_printf(ifp, "Read the re(4) man page for more details.\n");
777 /* Turn interface off, release resources */
781 ifp->if_flags &= ~IFF_PROMISC;
791 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
792 * IDs against our list and return a device name if we find a match.
795 re_probe(device_t dev)
797 const struct re_type *t;
801 uint16_t vendor, product;
805 vendor = pci_get_vendor(dev);
806 product = pci_get_device(dev);
809 * Only attach to rev.3 of the Linksys EG1032 adapter.
810 * Rev.2 is supported by sk(4).
812 if (vendor == PCI_VENDOR_LINKSYS &&
813 product == PCI_PRODUCT_LINKSYS_EG1032 &&
814 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
817 for (t = re_devs; t->re_name != NULL; t++) {
818 if (product == t->re_did && vendor == t->re_vid)
823 * Check if we found a RealTek device.
825 if (t->re_name == NULL)
829 * Temporarily map the I/O space so we can read the chip ID register.
831 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
833 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
835 if (sc->re_res == NULL) {
836 device_printf(dev, "couldn't map ports/memory\n");
841 sc->re_btag = rman_get_bustag(sc->re_res);
842 sc->re_bhandle = rman_get_bushandle(sc->re_res);
844 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
845 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
849 * and continue matching for the specific chip...
851 for (; t->re_name != NULL; t++) {
852 if (product == t->re_did && vendor == t->re_vid &&
853 t->re_basetype == hwrev) {
854 device_set_desc(dev, t->re_name);
862 * This routine takes the segment list provided as the result of
863 * a bus_dma_map_load() operation and assigns the addresses/lengths
864 * to RealTek DMA descriptors. This can be called either by the RX
865 * code or the TX code. In the RX case, we'll probably wind up mapping
866 * at most one segment. For the TX case, there could be any number of
867 * segments since TX packets may span multiple mbufs. In either case,
868 * if the number of segments is larger than the re_maxsegs limit
869 * specified by the caller, we abort the mapping operation. Sadly,
870 * whoever designed the buffer mapping API did not provide a way to
871 * return an error from here, so we have to fake it a bit.
875 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
876 bus_size_t mapsize, int error)
878 struct re_dmaload_arg *ctx;
879 struct re_desc *d = NULL;
888 /* Signal error to caller if there's too many segments */
889 if (nseg > ctx->re_maxsegs) {
895 * Map the segment array into descriptors. Note that we set the
896 * start-of-frame and end-of-frame markers for either TX or RX, but
897 * they really only have meaning in the TX case. (In the RX case,
898 * it's the chip that tells us where packets begin and end.)
899 * We also keep track of the end of the ring and set the
900 * end-of-ring bits as needed, and we set the ownership bits
901 * in all except the very first descriptor. (The caller will
902 * set this descriptor later when it start transmission or
907 d = &ctx->re_ring[idx];
908 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
912 cmdstat = segs[i].ds_len;
913 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
914 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
916 cmdstat |= RE_TDESC_CMD_SOF;
918 cmdstat |= RE_TDESC_CMD_OWN;
919 if (idx == (RE_RX_DESC_CNT - 1))
920 cmdstat |= RE_TDESC_CMD_EOR;
921 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
928 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
929 ctx->re_maxsegs = nseg;
934 * Map a single buffer address.
938 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
945 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
947 *addr = segs->ds_addr;
951 re_allocmem(device_t dev, struct re_softc *sc)
956 * Allocate map for RX mbufs.
959 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
960 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
961 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
962 &sc->re_ldata.re_mtag);
964 device_printf(dev, "could not allocate dma tag\n");
969 * Allocate map for TX descriptor list.
971 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
972 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
973 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
974 &sc->re_ldata.re_tx_list_tag);
976 device_printf(dev, "could not allocate dma tag\n");
980 /* Allocate DMA'able memory for the TX ring */
982 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
983 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
984 &sc->re_ldata.re_tx_list_map);
986 device_printf(dev, "could not allocate TX ring\n");
990 /* Load the map for the TX ring. */
992 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
993 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
994 RE_TX_LIST_SZ, re_dma_map_addr,
995 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
997 device_printf(dev, "could not get addres of TX ring\n");
1001 /* Create DMA maps for TX buffers */
1003 for (i = 0; i < RE_TX_DESC_CNT; i++) {
1004 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1005 &sc->re_ldata.re_tx_dmamap[i]);
1007 device_printf(dev, "can't create DMA map for TX\n");
1013 * Allocate map for RX descriptor list.
1015 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
1016 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1017 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1018 &sc->re_ldata.re_rx_list_tag);
1020 device_printf(dev, "could not allocate dma tag\n");
1024 /* Allocate DMA'able memory for the RX ring */
1026 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1027 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1028 &sc->re_ldata.re_rx_list_map);
1030 device_printf(dev, "could not allocate RX ring\n");
1034 /* Load the map for the RX ring. */
1036 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1037 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
1038 RE_RX_LIST_SZ, re_dma_map_addr,
1039 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
1041 device_printf(dev, "could not get address of RX ring\n");
1045 /* Create DMA maps for RX buffers */
1047 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1048 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1049 &sc->re_ldata.re_rx_dmamap[i]);
1051 device_printf(dev, "can't create DMA map for RX\n");
1060 * Attach the interface. Allocate softc structures, do ifmedia
1061 * setup and ethernet/BPF attach.
1064 re_attach(device_t dev)
1066 struct re_softc *sc = device_get_softc(dev);
1068 const struct re_hwrev *hw_rev;
1069 uint8_t eaddr[ETHER_ADDR_LEN];
1070 uint16_t as[ETHER_ADDR_LEN / 2];
1071 uint16_t re_did = 0;
1073 int error = 0, rid, i;
1075 callout_init(&sc->re_timer);
1080 RE_ENABLE_TX_MODERATION(sc);
1082 sysctl_ctx_init(&sc->re_sysctl_ctx);
1083 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1084 SYSCTL_STATIC_CHILDREN(_hw),
1086 device_get_nameunit(dev),
1088 if (sc->re_sysctl_tree == NULL) {
1089 device_printf(dev, "can't add sysctl node\n");
1093 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1094 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1095 OID_AUTO, "tx_moderation",
1096 CTLTYPE_INT | CTLFLAG_RW,
1097 sc, 0, re_sysctl_tx_moderation, "I",
1098 "Enable/Disable TX moderation");
1100 #ifndef BURN_BRIDGES
1102 * Handle power management nonsense.
1105 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1106 uint32_t membase, irq;
1108 /* Save important PCI config data. */
1109 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1110 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1112 /* Reset the power state. */
1113 device_printf(dev, "chip is in D%d power mode "
1114 "-- setting to D0\n", pci_get_powerstate(dev));
1116 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1118 /* Restore PCI config data. */
1119 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1120 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1124 * Map control/status registers.
1126 pci_enable_busmaster(dev);
1129 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1132 if (sc->re_res == NULL) {
1133 device_printf(dev, "couldn't map ports\n");
1138 sc->re_btag = rman_get_bustag(sc->re_res);
1139 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1141 /* Allocate interrupt */
1143 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1144 RF_SHAREABLE | RF_ACTIVE);
1146 if (sc->re_irq == NULL) {
1147 device_printf(dev, "couldn't map interrupt\n");
1152 /* Reset the adapter. */
1155 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1156 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1157 if (hw_rev->re_rev == hwrev) {
1158 sc->re_type = hw_rev->re_type;
1159 sc->re_flags = hw_rev->re_flags;
1165 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1166 if (re_did != 0x8129)
1170 * Get station address from the EEPROM.
1172 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
1173 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1174 as[i] = le16toh(as[i]);
1175 bcopy(as, eaddr, sizeof(eaddr));
1177 if (sc->re_type == RE_8169) {
1178 /* Set RX length mask */
1179 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1180 sc->re_txstart = RE_GTXSTART;
1182 /* Set RX length mask */
1183 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1184 sc->re_txstart = RE_TXSTART;
1188 * Allocate the parent bus DMA tag appropriate for PCI.
1190 #define RE_NSEG_NEW 32
1191 error = bus_dma_tag_create(NULL, /* parent */
1192 1, 0, /* alignment, boundary */
1193 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1194 BUS_SPACE_MAXADDR, /* highaddr */
1195 NULL, NULL, /* filter, filterarg */
1196 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1197 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1198 BUS_DMA_ALLOCNOW, /* flags */
1199 &sc->re_parent_tag);
1203 error = re_allocmem(dev, sc);
1209 if (mii_phy_probe(dev, &sc->re_miibus,
1210 re_ifmedia_upd, re_ifmedia_sts)) {
1211 device_printf(dev, "MII without any phy!\n");
1216 ifp = &sc->arpcom.ac_if;
1218 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1219 ifp->if_mtu = ETHERMTU;
1220 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1221 ifp->if_ioctl = re_ioctl;
1222 ifp->if_capabilities = IFCAP_VLAN_MTU;
1223 ifp->if_start = re_start;
1224 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1225 #ifdef DEVICE_POLLING
1226 ifp->if_poll = re_poll;
1228 ifp->if_watchdog = re_watchdog;
1229 ifp->if_init = re_init;
1230 if (sc->re_type == RE_8169)
1231 ifp->if_baudrate = 1000000000;
1233 ifp->if_baudrate = 100000000;
1234 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1235 ifq_set_ready(&ifp->if_snd);
1237 #ifdef RE_DISABLE_HWCSUM
1238 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1239 ifp->if_hwassist = 0;
1241 ifp->if_capenable = ifp->if_capabilities;
1242 ifp->if_hwassist = RE_CSUM_FEATURES;
1243 #endif /* RE_DISABLE_HWCSUM */
1246 * Call MI attach routine.
1248 ether_ifattach(ifp, eaddr, NULL);
1252 * Perform hardware diagnostic on the original RTL8169.
1253 * Some 32-bit cards were incorrectly wired and would
1254 * malfunction if plugged into a 64-bit slot.
1256 if (hwrev == RE_HWREV_8169) {
1257 lwkt_serialize_enter(ifp->if_serializer);
1258 error = re_diag(sc);
1259 lwkt_serialize_exit(ifp->if_serializer);
1262 device_printf(dev, "hardware diagnostic failure\n");
1263 ether_ifdetach(ifp);
1267 #endif /* RE_DIAG */
1269 /* Hook interrupt last to avoid having to lock softc */
1270 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc,
1271 &sc->re_intrhand, ifp->if_serializer);
1274 device_printf(dev, "couldn't set up irq\n");
1275 ether_ifdetach(ifp);
1287 * Shutdown hardware and free up resources. This can be called any
1288 * time after the mutex has been initialized. It is called in both
1289 * the error case in attach and the normal detach case so it needs
1290 * to be careful about only freeing resources that have actually been
1294 re_detach(device_t dev)
1296 struct re_softc *sc = device_get_softc(dev);
1297 struct ifnet *ifp = &sc->arpcom.ac_if;
1300 /* These should only be active if attach succeeded */
1301 if (device_is_attached(dev)) {
1302 lwkt_serialize_enter(ifp->if_serializer);
1304 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1305 lwkt_serialize_exit(ifp->if_serializer);
1307 ether_ifdetach(ifp);
1310 device_delete_child(dev, sc->re_miibus);
1311 bus_generic_detach(dev);
1314 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1316 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1320 /* Unload and free the RX DMA ring memory and map */
1322 if (sc->re_ldata.re_rx_list_tag) {
1323 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1324 sc->re_ldata.re_rx_list_map);
1325 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1326 sc->re_ldata.re_rx_list,
1327 sc->re_ldata.re_rx_list_map);
1328 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1331 /* Unload and free the TX DMA ring memory and map */
1333 if (sc->re_ldata.re_tx_list_tag) {
1334 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1335 sc->re_ldata.re_tx_list_map);
1336 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1337 sc->re_ldata.re_tx_list,
1338 sc->re_ldata.re_tx_list_map);
1339 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1342 /* Destroy all the RX and TX buffer maps */
1344 if (sc->re_ldata.re_mtag) {
1345 for (i = 0; i < RE_TX_DESC_CNT; i++)
1346 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1347 sc->re_ldata.re_tx_dmamap[i]);
1348 for (i = 0; i < RE_RX_DESC_CNT; i++)
1349 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1350 sc->re_ldata.re_rx_dmamap[i]);
1351 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1354 /* Unload and free the stats buffer and map */
1356 if (sc->re_ldata.re_stag) {
1357 bus_dmamap_unload(sc->re_ldata.re_stag,
1358 sc->re_ldata.re_rx_list_map);
1359 bus_dmamem_free(sc->re_ldata.re_stag,
1360 sc->re_ldata.re_stats,
1361 sc->re_ldata.re_smap);
1362 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1365 if (sc->re_parent_tag)
1366 bus_dma_tag_destroy(sc->re_parent_tag);
1372 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1374 struct re_dmaload_arg arg;
1375 struct mbuf *n = NULL;
1379 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1384 m->m_data = m->m_ext.ext_buf;
1386 m->m_len = m->m_pkthdr.len = MCLBYTES;
1390 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1391 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1398 arg.re_ring = sc->re_ldata.re_rx_list;
1400 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1401 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1402 &arg, BUS_DMA_NOWAIT);
1403 if (error || arg.re_maxsegs != 1) {
1409 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1410 sc->re_ldata.re_rx_mbuf[idx] = m;
1412 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1413 BUS_DMASYNC_PREREAD);
1419 re_tx_list_init(struct re_softc *sc)
1421 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1422 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1424 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1425 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1426 sc->re_ldata.re_tx_prodidx = 0;
1427 sc->re_ldata.re_tx_considx = 0;
1428 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1434 re_rx_list_init(struct re_softc *sc)
1438 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1439 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1441 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1442 error = re_newbuf(sc, i, NULL);
1447 /* Flush the RX descriptors */
1449 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1450 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1452 sc->re_ldata.re_rx_prodidx = 0;
1453 sc->re_head = sc->re_tail = NULL;
1459 * RX handler for C+ and 8169. For the gigE chips, we support
1460 * the reception of jumbo frames that have been fragmented
1461 * across multiple 2K mbuf cluster buffers.
1464 re_rxeof(struct re_softc *sc)
1466 struct ifnet *ifp = &sc->arpcom.ac_if;
1468 struct re_desc *cur_rx;
1469 uint32_t rxstat, rxvlan;
1472 /* Invalidate the descriptor memory */
1474 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1475 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1477 for (i = sc->re_ldata.re_rx_prodidx;
1478 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1479 cur_rx = &sc->re_ldata.re_rx_list[i];
1480 m = sc->re_ldata.re_rx_mbuf[i];
1481 total_len = RE_RXBYTES(cur_rx);
1482 rxstat = le32toh(cur_rx->re_cmdstat);
1483 rxvlan = le32toh(cur_rx->re_vlanctl);
1485 /* Invalidate the RX mbuf and unload its map */
1487 bus_dmamap_sync(sc->re_ldata.re_mtag,
1488 sc->re_ldata.re_rx_dmamap[i],
1489 BUS_DMASYNC_POSTWRITE);
1490 bus_dmamap_unload(sc->re_ldata.re_mtag,
1491 sc->re_ldata.re_rx_dmamap[i]);
1493 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1494 m->m_len = MCLBYTES - ETHER_ALIGN;
1495 if (sc->re_head == NULL) {
1496 sc->re_head = sc->re_tail = m;
1498 sc->re_tail->m_next = m;
1501 re_newbuf(sc, i, NULL);
1506 * NOTE: for the 8139C+, the frame length field
1507 * is always 12 bits in size, but for the gigE chips,
1508 * it is 13 bits (since the max RX frame length is 16K).
1509 * Unfortunately, all 32 bits in the status word
1510 * were already used, so to make room for the extra
1511 * length bit, RealTek took out the 'frame alignment
1512 * error' bit and shifted the other status bits
1513 * over one slot. The OWN, EOR, FS and LS bits are
1514 * still in the same places. We have already extracted
1515 * the frame length and checked the OWN bit, so rather
1516 * than using an alternate bit mapping, we shift the
1517 * status bits one space to the right so we can evaluate
1518 * them using the 8169 status as though it was in the
1519 * same format as that of the 8139C+.
1521 if (sc->re_type == RE_8169)
1524 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1527 * If this is part of a multi-fragment packet,
1528 * discard all the pieces.
1530 if (sc->re_head != NULL) {
1531 m_freem(sc->re_head);
1532 sc->re_head = sc->re_tail = NULL;
1534 re_newbuf(sc, i, m);
1539 * If allocating a replacement mbuf fails,
1540 * reload the current one.
1543 if (re_newbuf(sc, i, NULL)) {
1545 if (sc->re_head != NULL) {
1546 m_freem(sc->re_head);
1547 sc->re_head = sc->re_tail = NULL;
1549 re_newbuf(sc, i, m);
1553 if (sc->re_head != NULL) {
1554 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1556 * Special case: if there's 4 bytes or less
1557 * in this buffer, the mbuf can be discarded:
1558 * the last 4 bytes is the CRC, which we don't
1559 * care about anyway.
1561 if (m->m_len <= ETHER_CRC_LEN) {
1562 sc->re_tail->m_len -=
1563 (ETHER_CRC_LEN - m->m_len);
1566 m->m_len -= ETHER_CRC_LEN;
1567 sc->re_tail->m_next = m;
1570 sc->re_head = sc->re_tail = NULL;
1571 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1573 m->m_pkthdr.len = m->m_len =
1574 (total_len - ETHER_CRC_LEN);
1577 m->m_pkthdr.rcvif = ifp;
1579 /* Do RX checksumming if enabled */
1581 if (ifp->if_capenable & IFCAP_RXCSUM) {
1583 /* Check IP header checksum */
1584 if (rxstat & RE_RDESC_STAT_PROTOID)
1585 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1586 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1587 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1589 /* Check TCP/UDP checksum */
1590 if ((RE_TCPPKT(rxstat) &&
1591 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1592 (RE_UDPPKT(rxstat) &&
1593 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1594 m->m_pkthdr.csum_flags |=
1595 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1596 CSUM_FRAG_NOT_CHECKED;
1597 m->m_pkthdr.csum_data = 0xffff;
1601 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1603 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1605 ifp->if_input(ifp, m);
1609 /* Flush the RX DMA ring */
1611 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1612 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1614 sc->re_ldata.re_rx_prodidx = i;
1618 re_txeof(struct re_softc *sc)
1620 struct ifnet *ifp = &sc->arpcom.ac_if;
1624 /* Invalidate the TX descriptor list */
1626 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1627 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
1629 for (idx = sc->re_ldata.re_tx_considx;
1630 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) {
1631 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1632 if (txstat & RE_TDESC_CMD_OWN)
1635 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
1638 * We only stash mbufs in the last descriptor
1639 * in a fragment chain, which also happens to
1640 * be the only place where the TX status bits
1643 if (txstat & RE_TDESC_CMD_EOF) {
1644 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1645 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1646 bus_dmamap_unload(sc->re_ldata.re_mtag,
1647 sc->re_ldata.re_tx_dmamap[idx]);
1648 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1649 RE_TDESC_STAT_COLCNT))
1650 ifp->if_collisions++;
1651 if (txstat & RE_TDESC_STAT_TXERRSUM)
1656 sc->re_ldata.re_tx_free++;
1659 /* No changes made to the TX ring, so no flush needed */
1660 if (sc->re_ldata.re_tx_free) {
1661 sc->re_ldata.re_tx_considx = idx;
1662 ifp->if_flags &= ~IFF_OACTIVE;
1667 * Some chips will ignore a second TX request issued while an
1668 * existing transmission is in progress. If the transmitter goes
1669 * idle but there are still packets waiting to be sent, we need
1670 * to restart the channel here to flush them out. This only seems
1671 * to be required with the PCIe devices.
1673 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1674 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
1677 * If not all descriptors have been released reaped yet,
1678 * reload the timer so that we will eventually get another
1679 * interrupt that will cause us to re-enter this routine.
1680 * This is done in case the transmitter has gone idle.
1682 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
1683 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1684 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1690 struct re_softc *sc = xsc;
1692 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1693 re_tick_serialized(xsc);
1694 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1698 re_tick_serialized(void *xsc)
1700 struct re_softc *sc = xsc;
1701 struct ifnet *ifp = &sc->arpcom.ac_if;
1702 struct mii_data *mii;
1704 mii = device_get_softc(sc->re_miibus);
1707 if (!(mii->mii_media_status & IFM_ACTIVE))
1710 if (mii->mii_media_status & IFM_ACTIVE &&
1711 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1713 if (!ifq_is_empty(&ifp->if_snd))
1718 callout_reset(&sc->re_timer, hz, re_tick, sc);
1721 #ifdef DEVICE_POLLING
1724 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1726 struct re_softc *sc = ifp->if_softc;
1730 /* disable interrupts */
1731 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1733 case POLL_DEREGISTER:
1734 /* enable interrupts */
1735 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1738 sc->rxcycles = count;
1742 if (!ifq_is_empty(&ifp->if_snd))
1743 (*ifp->if_start)(ifp);
1745 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1748 status = CSR_READ_2(sc, RE_ISR);
1749 if (status == 0xffff)
1752 CSR_WRITE_2(sc, RE_ISR, status);
1755 * XXX check behaviour on receiver stalls.
1758 if (status & RE_ISR_SYSTEM_ERR) {
1766 #endif /* DEVICE_POLLING */
1771 struct re_softc *sc = arg;
1772 struct ifnet *ifp = &sc->arpcom.ac_if;
1775 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1779 status = CSR_READ_2(sc, RE_ISR);
1780 /* If the card has gone away the read returns 0xffff. */
1781 if (status == 0xffff)
1784 CSR_WRITE_2(sc, RE_ISR, status);
1786 if ((status & sc->re_intrs) == 0)
1789 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW))
1792 if ((status & sc->re_tx_ack) ||
1793 (status & RE_ISR_TX_ERR) ||
1794 (status & RE_ISR_TX_DESC_UNAVAIL))
1797 if (status & RE_ISR_SYSTEM_ERR) {
1802 if (status & RE_ISR_LINKCHG) {
1803 callout_stop(&sc->re_timer);
1804 re_tick_serialized(sc);
1808 if (!ifq_is_empty(&ifp->if_snd))
1809 (*ifp->if_start)(ifp);
1813 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1815 struct ifnet *ifp = &sc->arpcom.ac_if;
1816 struct mbuf *m, *m_new = NULL;
1817 struct re_dmaload_arg arg;
1822 if (sc->re_ldata.re_tx_free <= 4)
1828 * Set up checksum offload. Note: checksum offload bits must
1829 * appear in all descriptors of a multi-descriptor transmit
1830 * attempt. (This is according to testing done with an 8169
1831 * chip. I'm not sure if this is a requirement or a bug.)
1836 if (m->m_pkthdr.csum_flags & CSUM_IP)
1837 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1838 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1839 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1840 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1841 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1845 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1846 if (arg.re_maxsegs > 4)
1847 arg.re_maxsegs -= 4;
1848 arg.re_ring = sc->re_ldata.re_tx_list;
1850 map = sc->re_ldata.re_tx_dmamap[*idx];
1853 * With some of the RealTek chips, using the checksum offload
1854 * support in conjunction with the autopadding feature results
1855 * in the transmission of corrupt frames. For example, if we
1856 * need to send a really small IP fragment that's less than 60
1857 * bytes in size, and IP header checksumming is enabled, the
1858 * resulting ethernet frame that appears on the wire will
1859 * have garbled payload. To work around this, if TX checksum
1860 * offload is enabled, we always manually pad short frames out
1861 * to the minimum ethernet frame size. We do this by pretending
1862 * the mbuf chain has too many fragments so the coalescing code
1863 * below can assemble the packet into a single buffer that's
1864 * padded out to the mininum frame size.
1866 * Note: this appears unnecessary for TCP, and doing it for TCP
1867 * with PCIe adapters seems to result in bad checksums.
1869 if (arg.re_flags && !(arg.re_flags & RE_TDESC_CMD_TCPCSUM) &&
1870 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
1873 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1874 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1877 if (error && error != EFBIG) {
1878 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1882 /* Too many segments to map, coalesce into a single mbuf */
1884 if (error || arg.re_maxsegs == 0) {
1885 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1886 if (m_new == NULL) {
1894 * Manually pad short frames, and zero the pad space
1895 * to avoid leaking data.
1897 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) {
1898 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
1899 RE_MIN_FRAMELEN - m_new->m_pkthdr.len);
1900 m_new->m_pkthdr.len += RE_MIN_FRAMELEN -
1901 m_new->m_pkthdr.len;
1902 m_new->m_len = m_new->m_pkthdr.len;
1908 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1909 arg.re_ring = sc->re_ldata.re_tx_list;
1911 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1912 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1915 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1921 * Insure that the map for this transmission
1922 * is placed at the array index of the last descriptor
1925 sc->re_ldata.re_tx_dmamap[*idx] =
1926 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1927 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1929 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1930 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1933 * Set up hardware VLAN tagging. Note: vlan tag info must
1934 * appear in the first descriptor of a multi-descriptor
1935 * transmission attempt.
1938 if (m->m_flags & M_VLANTAG) {
1939 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1940 htole32(htobe16(m->m_pkthdr.ether_vlantag) |
1941 RE_TDESC_VLANCTL_TAG);
1944 /* Transfer ownership of packet to the chip. */
1946 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1947 htole32(RE_TDESC_CMD_OWN);
1948 if (*idx != arg.re_idx)
1949 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1950 htole32(RE_TDESC_CMD_OWN);
1952 RE_DESC_INC(arg.re_idx);
1959 * Main transmit routine for C+ and gigE NICs.
1963 re_start(struct ifnet *ifp)
1965 struct re_softc *sc = ifp->if_softc;
1966 struct mbuf *m_head;
1967 struct mbuf *m_head2;
1968 int called_defrag, idx, need_trans;
1970 if (!sc->re_link || (ifp->if_flags & IFF_OACTIVE))
1973 idx = sc->re_ldata.re_tx_prodidx;
1976 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1977 m_head = ifq_poll(&ifp->if_snd);
1981 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
1983 * If we could not encapsulate the defragged packet,
1984 * the returned m_head2 is garbage and we must dequeue
1985 * and throw away the original packet.
1987 if (called_defrag) {
1988 ifq_dequeue(&ifp->if_snd, m_head);
1991 ifp->if_flags |= IFF_OACTIVE;
1996 * Clean out the packet we encapsulated. If we defragged
1997 * the packet the m_head2 is the one that got encapsulated
1998 * and the original must be thrown away. Otherwise m_head2
1999 * *IS* the original.
2001 ifq_dequeue(&ifp->if_snd, m_head);
2007 * If there's a BPF listener, bounce a copy of this frame
2010 ETHER_BPF_MTAP(ifp, m_head2);
2014 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
2015 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
2016 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2020 /* Flush the TX descriptors */
2021 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2022 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2024 sc->re_ldata.re_tx_prodidx = idx;
2027 * RealTek put the TX poll request register in a different
2028 * location on the 8169 gigE chip. I don't know why.
2030 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2032 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2034 * Use the countdown timer for interrupt moderation.
2035 * 'TX done' interrupts are disabled. Instead, we reset the
2036 * countdown timer, which will begin counting until it hits
2037 * the value in the TIMERINT register, and then trigger an
2038 * interrupt. Each time we write to the TIMERCNT register,
2039 * the timer count is reset to 0.
2041 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2045 * Set a timeout in case the chip goes out to lunch.
2053 struct re_softc *sc = xsc;
2054 struct ifnet *ifp = &sc->arpcom.ac_if;
2055 struct mii_data *mii;
2058 mii = device_get_softc(sc->re_miibus);
2061 * Cancel pending I/O and free all RX/TX buffers.
2066 * Enable C+ RX and TX mode, as well as VLAN stripping and
2067 * RX checksum offload. We must configure the C+ register
2068 * before all others.
2070 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2071 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
2072 (ifp->if_capenable & IFCAP_RXCSUM ?
2073 RE_CPLUSCMD_RXCSUM_ENB : 0));
2076 * Init our MAC address. Even though the chipset
2077 * documentation doesn't mention it, we need to enter "Config
2078 * register write enable" mode to modify the ID registers.
2080 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2081 CSR_WRITE_4(sc, RE_IDR0,
2082 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2083 CSR_WRITE_2(sc, RE_IDR4,
2084 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2085 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2088 * For C+ mode, initialize the RX descriptors and mbufs.
2090 re_rx_list_init(sc);
2091 re_tx_list_init(sc);
2094 * Load the addresses of the RX and TX lists into the chip.
2096 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2097 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2098 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2099 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2101 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2102 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2103 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2104 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2107 * Enable transmit and receive.
2109 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2112 * Set the initial TX and RX configuration.
2114 if (sc->re_testmode) {
2115 if (sc->re_type == RE_8169)
2116 CSR_WRITE_4(sc, RE_TXCFG,
2117 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2119 CSR_WRITE_4(sc, RE_TXCFG,
2120 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2122 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2124 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2126 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2128 /* Set the individual bit to receive frames for this host only. */
2129 rxcfg = CSR_READ_4(sc, RE_RXCFG);
2130 rxcfg |= RE_RXCFG_RX_INDIV;
2132 /* If we want promiscuous mode, set the allframes bit. */
2133 if (ifp->if_flags & IFF_PROMISC) {
2134 rxcfg |= RE_RXCFG_RX_ALLPHYS;
2135 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2137 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
2138 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2142 * Set capture broadcast bit to capture broadcast frames.
2144 if (ifp->if_flags & IFF_BROADCAST) {
2145 rxcfg |= RE_RXCFG_RX_BROAD;
2146 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2148 rxcfg &= ~RE_RXCFG_RX_BROAD;
2149 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2153 * Program the multicast filter, if necessary.
2157 #ifdef DEVICE_POLLING
2159 * Disable interrupts if we are polling.
2161 if (ifp->if_flags & IFF_POLLING)
2162 CSR_WRITE_2(sc, RE_IMR, 0);
2163 else /* otherwise ... */
2164 #endif /* DEVICE_POLLING */
2166 * Enable interrupts.
2168 if (sc->re_testmode)
2169 CSR_WRITE_2(sc, RE_IMR, 0);
2171 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2172 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2174 /* Set initial TX threshold */
2175 sc->re_txthresh = RE_TX_THRESH_INIT;
2177 /* Start RX/TX process. */
2178 if (sc->re_flags & RE_F_HASMPC)
2179 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2181 /* Enable receiver and transmitter. */
2182 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2185 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2187 * Initialize the timer interrupt register so that
2188 * a timer interrupt will be generated once the timer
2189 * reaches a certain number of ticks. The timer is
2190 * reloaded on each transmit. This gives us TX interrupt
2191 * moderation, which dramatically improves TX frame rate.
2193 if (sc->re_type == RE_8169)
2194 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2196 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2200 * For 8169 gigE NICs, set the max allowed RX packet
2201 * size so we can receive jumbo frames.
2203 if (sc->re_type == RE_8169)
2204 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2206 if (sc->re_testmode) {
2212 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2214 ifp->if_flags |= IFF_RUNNING;
2215 ifp->if_flags &= ~IFF_OACTIVE;
2218 callout_reset(&sc->re_timer, hz, re_tick, sc);
2222 * Set media options.
2225 re_ifmedia_upd(struct ifnet *ifp)
2227 struct re_softc *sc = ifp->if_softc;
2228 struct mii_data *mii;
2230 mii = device_get_softc(sc->re_miibus);
2237 * Report current media status.
2240 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2242 struct re_softc *sc = ifp->if_softc;
2243 struct mii_data *mii;
2245 mii = device_get_softc(sc->re_miibus);
2248 ifmr->ifm_active = mii->mii_media_active;
2249 ifmr->ifm_status = mii->mii_media_status;
2253 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2255 struct re_softc *sc = ifp->if_softc;
2256 struct ifreq *ifr = (struct ifreq *) data;
2257 struct mii_data *mii;
2262 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2264 ifp->if_mtu = ifr->ifr_mtu;
2267 if (ifp->if_flags & IFF_UP)
2269 else if (ifp->if_flags & IFF_RUNNING)
2279 mii = device_get_softc(sc->re_miibus);
2280 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2283 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2284 ifp->if_capenable |=
2285 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2286 if (ifp->if_capenable & IFCAP_TXCSUM)
2287 ifp->if_hwassist = RE_CSUM_FEATURES;
2289 ifp->if_hwassist = 0;
2290 if (ifp->if_flags & IFF_RUNNING)
2294 error = ether_ioctl(ifp, command, data);
2301 re_watchdog(struct ifnet *ifp)
2303 struct re_softc *sc = ifp->if_softc;
2305 if_printf(ifp, "watchdog timeout\n");
2314 if (!ifq_is_empty(&ifp->if_snd))
2319 * Stop the adapter and free any mbufs allocated to the
2323 re_stop(struct re_softc *sc)
2325 struct ifnet *ifp = &sc->arpcom.ac_if;
2329 callout_stop(&sc->re_timer);
2331 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2333 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2334 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2335 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2337 if (sc->re_head != NULL) {
2338 m_freem(sc->re_head);
2339 sc->re_head = sc->re_tail = NULL;
2342 /* Free the TX list buffers. */
2343 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2344 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2345 bus_dmamap_unload(sc->re_ldata.re_mtag,
2346 sc->re_ldata.re_tx_dmamap[i]);
2347 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2348 sc->re_ldata.re_tx_mbuf[i] = NULL;
2352 /* Free the RX list buffers. */
2353 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2354 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2355 bus_dmamap_unload(sc->re_ldata.re_mtag,
2356 sc->re_ldata.re_rx_dmamap[i]);
2357 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2358 sc->re_ldata.re_rx_mbuf[i] = NULL;
2364 * Device suspend routine. Stop the interface and save some PCI
2365 * settings in case the BIOS doesn't restore them properly on
2369 re_suspend(device_t dev)
2371 #ifndef BURN_BRIDGES
2374 struct re_softc *sc = device_get_softc(dev);
2378 #ifndef BURN_BRIDGES
2379 for (i = 0; i < 5; i++)
2380 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2381 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2382 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2383 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2384 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2393 * Device resume routine. Restore some PCI settings in case the BIOS
2394 * doesn't, re-enable busmastering, and restart the interface if
2398 re_resume(device_t dev)
2400 struct re_softc *sc = device_get_softc(dev);
2401 struct ifnet *ifp = &sc->arpcom.ac_if;
2402 #ifndef BURN_BRIDGES
2406 #ifndef BURN_BRIDGES
2407 /* better way to do this? */
2408 for (i = 0; i < 5; i++)
2409 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2410 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2411 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2412 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2413 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2415 /* reenable busmastering */
2416 pci_enable_busmaster(dev);
2417 pci_enable_io(dev, SYS_RES_IOPORT);
2420 /* reinitialize interface if necessary */
2421 if (ifp->if_flags & IFF_UP)
2430 * Stop all chip I/O so that the kernel's probe routines don't
2431 * get confused by errant DMAs when rebooting.
2434 re_shutdown(device_t dev)
2436 struct re_softc *sc = device_get_softc(dev);
2437 struct ifnet *ifp = &sc->arpcom.ac_if;
2439 lwkt_serialize_enter(ifp->if_serializer);
2441 lwkt_serialize_exit(ifp->if_serializer);
2445 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS)
2447 struct re_softc *sc = arg1;
2448 struct ifnet *ifp = &sc->arpcom.ac_if;
2449 int error = 0, mod, mod_old;
2451 lwkt_serialize_enter(ifp->if_serializer);
2453 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc);
2455 error = sysctl_handle_int(oidp, &mod, 0, req);
2456 if (error || req->newptr == NULL || mod == mod_old)
2458 if (mod != 0 && mod != 1) {
2464 RE_ENABLE_TX_MODERATION(sc);
2466 RE_DISABLE_TX_MODERATION(sc);
2468 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP))
2471 lwkt_serialize_exit(ifp->if_serializer);