3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.34 2007/08/10 03:48:02 dillon Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
118 #include <sys/endian.h>
119 #include <sys/kernel.h>
120 #include <sys/malloc.h>
121 #include <sys/mbuf.h>
122 /* #include <sys/module.h> */
123 #include <sys/rman.h>
124 #include <sys/serialize.h>
125 #include <sys/socket.h>
126 #include <sys/sockio.h>
127 #include <sys/sysctl.h>
130 #include <net/ethernet.h>
132 #include <net/ifq_var.h>
133 #include <net/if_arp.h>
134 #include <net/if_dl.h>
135 #include <net/if_media.h>
136 #include <net/if_types.h>
137 #include <net/vlan/if_vlan_var.h>
139 #include <dev/netif/mii_layer/mii.h>
140 #include <dev/netif/mii_layer/miivar.h>
142 #include <bus/pci/pcidevs.h>
143 #include <bus/pci/pcireg.h>
144 #include <bus/pci/pcivar.h>
146 /* "device miibus" required. See GENERIC if you get errors here. */
147 #include "miibus_if.h"
149 #include <dev/netif/re/if_rereg.h>
150 #include <dev/netif/re/if_revar.h>
152 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
154 #define RE_DISABLE_HWCSUM
158 * Various supported device vendors/types and their names.
160 static const struct re_type re_devs[] = {
161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
162 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
163 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
164 "RealTek 8139C+ 10/100BaseTX" },
165 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E,
166 "RealTek 8101E PCIe 10/100baseTX" },
167 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1,
168 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2,
170 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN3,
172 "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
174 "RealTek 8169 Gigabit Ethernet" },
175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
176 "RealTek 8169S Single-chip Gigabit Ethernet" },
177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB,
178 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC,
180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC,
182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
184 "RealTek 8110S Single-chip Gigabit Ethernet" },
185 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S,
186 "Corega CG-LAPCIGT Gigabit Ethernet" },
187 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S,
188 "Linksys EG1032 Gigabit Ethernet" },
189 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S,
190 "US Robotics 997902 Gigabit Ethernet" },
194 static const struct re_hwrev re_hwrevs[] = {
195 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" },
196 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" },
197 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" },
198 { RE_HWREV_8168_SPIN3, RE_8169, RE_F_PCIE, "8168" },
199 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" },
200 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" },
201 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" },
202 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" },
203 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" },
204 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" },
205 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" },
209 static int re_probe(device_t);
210 static int re_attach(device_t);
211 static int re_detach(device_t);
213 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
215 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
216 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
218 static int re_allocmem(device_t, struct re_softc *);
219 static int re_newbuf(struct re_softc *, int, struct mbuf *);
220 static int re_rx_list_init(struct re_softc *);
221 static int re_tx_list_init(struct re_softc *);
222 static void re_rxeof(struct re_softc *);
223 static void re_txeof(struct re_softc *);
224 static void re_intr(void *);
225 static void re_tick(void *);
226 static void re_tick_serialized(void *);
227 static void re_start(struct ifnet *);
228 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
229 static void re_init(void *);
230 static void re_stop(struct re_softc *);
231 static void re_watchdog(struct ifnet *);
232 static int re_suspend(device_t);
233 static int re_resume(device_t);
234 static void re_shutdown(device_t);
235 static int re_ifmedia_upd(struct ifnet *);
236 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
238 static void re_eeprom_putbyte(struct re_softc *, int);
239 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
240 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
241 static int re_gmii_readreg(device_t, int, int);
242 static int re_gmii_writereg(device_t, int, int, int);
244 static int re_miibus_readreg(device_t, int, int);
245 static int re_miibus_writereg(device_t, int, int, int);
246 static void re_miibus_statchg(device_t);
248 static void re_setmulti(struct re_softc *);
249 static void re_reset(struct re_softc *);
252 static int re_diag(struct re_softc *);
255 #ifdef DEVICE_POLLING
256 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
259 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS);
261 static device_method_t re_methods[] = {
262 /* Device interface */
263 DEVMETHOD(device_probe, re_probe),
264 DEVMETHOD(device_attach, re_attach),
265 DEVMETHOD(device_detach, re_detach),
266 DEVMETHOD(device_suspend, re_suspend),
267 DEVMETHOD(device_resume, re_resume),
268 DEVMETHOD(device_shutdown, re_shutdown),
271 DEVMETHOD(bus_print_child, bus_generic_print_child),
272 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
275 DEVMETHOD(miibus_readreg, re_miibus_readreg),
276 DEVMETHOD(miibus_writereg, re_miibus_writereg),
277 DEVMETHOD(miibus_statchg, re_miibus_statchg),
282 static driver_t re_driver = {
285 sizeof(struct re_softc)
288 static devclass_t re_devclass;
290 DECLARE_DUMMY_MODULE(if_re);
291 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
292 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
293 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
296 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
299 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
302 * Send a read command and address to the EEPROM, check for ACK.
305 re_eeprom_putbyte(struct re_softc *sc, int addr)
309 d = addr | (RE_9346_READ << sc->re_eewidth);
312 * Feed in each bit and strobe the clock.
314 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
316 EE_SET(RE_EE_DATAIN);
318 EE_CLR(RE_EE_DATAIN);
328 * Read a word of data stored in the EEPROM at address 'addr.'
331 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
337 * Send address of word we want to read.
339 re_eeprom_putbyte(sc, addr);
342 * Start reading bits from EEPROM.
344 for (i = 0x8000; i != 0; i >>= 1) {
347 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
357 * Read a sequence of words from the EEPROM.
360 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
363 uint16_t word = 0, *ptr;
365 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
368 for (i = 0; i < cnt; i++) {
369 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
370 re_eeprom_getword(sc, off + i, &word);
371 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
372 ptr = (uint16_t *)(dest + (i * 2));
376 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
380 re_gmii_readreg(device_t dev, int phy, int reg)
382 struct re_softc *sc = device_get_softc(dev);
389 /* Let the rgephy driver read the GMEDIASTAT register */
391 if (reg == RE_GMEDIASTAT)
392 return(CSR_READ_1(sc, RE_GMEDIASTAT));
394 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
397 for (i = 0; i < RE_TIMEOUT; i++) {
398 rval = CSR_READ_4(sc, RE_PHYAR);
399 if (rval & RE_PHYAR_BUSY)
404 if (i == RE_TIMEOUT) {
405 device_printf(dev, "PHY read failed\n");
409 return(rval & RE_PHYAR_PHYDATA);
413 re_gmii_writereg(device_t dev, int phy, int reg, int data)
415 struct re_softc *sc = device_get_softc(dev);
419 CSR_WRITE_4(sc, RE_PHYAR,
420 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
423 for (i = 0; i < RE_TIMEOUT; i++) {
424 rval = CSR_READ_4(sc, RE_PHYAR);
425 if ((rval & RE_PHYAR_BUSY) == 0)
431 device_printf(dev, "PHY write failed\n");
437 re_miibus_readreg(device_t dev, int phy, int reg)
439 struct re_softc *sc = device_get_softc(dev);
441 uint16_t re8139_reg = 0;
443 if (sc->re_type == RE_8169) {
444 rval = re_gmii_readreg(dev, phy, reg);
448 /* Pretend the internal PHY is only at address 0 */
454 re8139_reg = RE_BMCR;
457 re8139_reg = RE_BMSR;
460 re8139_reg = RE_ANAR;
463 re8139_reg = RE_ANER;
466 re8139_reg = RE_LPAR;
472 * Allow the rlphy driver to read the media status
473 * register. If we have a link partner which does not
474 * support NWAY, this is the register which will tell
475 * us the results of parallel detection.
478 return(CSR_READ_1(sc, RE_MEDIASTAT));
480 device_printf(dev, "bad phy register\n");
483 rval = CSR_READ_2(sc, re8139_reg);
484 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) {
485 /* 8139C+ has different bit layout. */
486 rval &= ~(BMCR_LOOP | BMCR_ISO);
492 re_miibus_writereg(device_t dev, int phy, int reg, int data)
494 struct re_softc *sc= device_get_softc(dev);
495 u_int16_t re8139_reg = 0;
497 if (sc->re_type == RE_8169)
498 return(re_gmii_writereg(dev, phy, reg, data));
500 /* Pretend the internal PHY is only at address 0 */
506 re8139_reg = RE_BMCR;
507 if (sc->re_type == RE_8139CPLUS) {
508 /* 8139C+ has different bit layout. */
509 data &= ~(BMCR_LOOP | BMCR_ISO);
513 re8139_reg = RE_BMSR;
516 re8139_reg = RE_ANAR;
519 re8139_reg = RE_ANER;
522 re8139_reg = RE_LPAR;
528 device_printf(dev, "bad phy register\n");
531 CSR_WRITE_2(sc, re8139_reg, data);
536 re_miibus_statchg(device_t dev)
541 * Program the 64-bit multicast hash filter.
544 re_setmulti(struct re_softc *sc)
546 struct ifnet *ifp = &sc->arpcom.ac_if;
548 uint32_t hashes[2] = { 0, 0 };
549 struct ifmultiaddr *ifma;
553 rxfilt = CSR_READ_4(sc, RE_RXCFG);
555 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
556 rxfilt |= RE_RXCFG_RX_MULTI;
557 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
558 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
559 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
563 /* first, zot all the existing hash bits */
564 CSR_WRITE_4(sc, RE_MAR0, 0);
565 CSR_WRITE_4(sc, RE_MAR4, 0);
567 /* now program new ones */
568 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
569 if (ifma->ifma_addr->sa_family != AF_LINK)
571 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
572 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
574 hashes[0] |= (1 << h);
576 hashes[1] |= (1 << (h - 32));
581 rxfilt |= RE_RXCFG_RX_MULTI;
583 rxfilt &= ~RE_RXCFG_RX_MULTI;
585 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
586 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
587 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
591 re_reset(struct re_softc *sc)
595 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
597 for (i = 0; i < RE_TIMEOUT; i++) {
599 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
603 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
605 CSR_WRITE_1(sc, 0x82, 1);
610 * The following routine is designed to test for a defect on some
611 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
612 * lines connected to the bus, however for a 32-bit only card, they
613 * should be pulled high. The result of this defect is that the
614 * NIC will not work right if you plug it into a 64-bit slot: DMA
615 * operations will be done with 64-bit transfers, which will fail
616 * because the 64-bit data lines aren't connected.
618 * There's no way to work around this (short of talking a soldering
619 * iron to the board), however we can detect it. The method we use
620 * here is to put the NIC into digital loopback mode, set the receiver
621 * to promiscuous mode, and then try to send a frame. We then compare
622 * the frame data we sent to what was received. If the data matches,
623 * then the NIC is working correctly, otherwise we know the user has
624 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
625 * slot. In the latter case, there's no way the NIC can work correctly,
626 * so we print out a message on the console and abort the device attach.
630 re_diag(struct re_softc *sc)
632 struct ifnet *ifp = &sc->arpcom.ac_if;
634 struct ether_header *eh;
635 struct re_desc *cur_rx;
638 int total_len, i, error = 0, phyaddr;
639 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
640 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
642 /* Allocate a single mbuf */
644 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
649 * Initialize the NIC in test mode. This sets the chip up
650 * so that it can send and receive frames, but performs the
651 * following special functions:
652 * - Puts receiver in promiscuous mode
653 * - Enables digital loopback mode
654 * - Leaves interrupts turned off
657 ifp->if_flags |= IFF_PROMISC;
662 if (sc->re_type == RE_8169)
667 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
668 for (i = 0; i < RE_TIMEOUT; i++) {
669 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
670 if (!(status & BMCR_RESET))
674 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
675 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
679 /* Put some data in the mbuf */
681 eh = mtod(m0, struct ether_header *);
682 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
683 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
684 eh->ether_type = htons(ETHERTYPE_IP);
685 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
688 * Queue the packet, start transmission.
689 * Note: ifq_handoff() ultimately calls re_start() for us.
692 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
693 error = ifq_handoff(ifp, m0, NULL);
700 /* Wait for it to propagate through the chip */
703 for (i = 0; i < RE_TIMEOUT; i++) {
704 status = CSR_READ_2(sc, RE_ISR);
705 CSR_WRITE_2(sc, RE_ISR, status);
706 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
707 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
712 if (i == RE_TIMEOUT) {
713 if_printf(ifp, "diagnostic failed to receive packet "
714 "in loopback mode\n");
720 * The packet should have been dumped into the first
721 * entry in the RX DMA ring. Grab it from there.
724 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
725 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
726 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
727 BUS_DMASYNC_POSTWRITE);
728 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
730 m0 = sc->re_ldata.re_rx_mbuf[0];
731 sc->re_ldata.re_rx_mbuf[0] = NULL;
732 eh = mtod(m0, struct ether_header *);
734 cur_rx = &sc->re_ldata.re_rx_list[0];
735 total_len = RE_RXBYTES(cur_rx);
736 rxstat = le32toh(cur_rx->re_cmdstat);
738 if (total_len != ETHER_MIN_LEN) {
739 if_printf(ifp, "diagnostic failed, received short packet\n");
744 /* Test that the received packet data matches what we sent. */
746 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
747 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
748 be16toh(eh->ether_type) != ETHERTYPE_IP) {
749 if_printf(ifp, "WARNING, DMA FAILURE!\n");
750 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
751 dst, ":", src, ":", ETHERTYPE_IP);
752 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
753 eh->ether_dhost, ":", eh->ether_shost, ":",
754 ntohs(eh->ether_type));
755 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
756 "into a 64-bit PCI slot.\n");
757 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
758 "for proper operation.\n");
759 if_printf(ifp, "Read the re(4) man page for more details.\n");
764 /* Turn interface off, release resources */
768 ifp->if_flags &= ~IFF_PROMISC;
778 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
779 * IDs against our list and return a device name if we find a match.
782 re_probe(device_t dev)
784 const struct re_type *t;
788 uint16_t vendor, product;
792 vendor = pci_get_vendor(dev);
793 product = pci_get_device(dev);
796 * Only attach to rev.3 of the Linksys EG1032 adapter.
797 * Rev.2 is supported by sk(4).
799 if (vendor == PCI_VENDOR_LINKSYS &&
800 product == PCI_PRODUCT_LINKSYS_EG1032 &&
801 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
804 for (t = re_devs; t->re_name != NULL; t++) {
805 if (product == t->re_did && vendor == t->re_vid)
810 * Check if we found a RealTek device.
812 if (t->re_name == NULL)
816 * Temporarily map the I/O space so we can read the chip ID register.
818 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
820 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
822 if (sc->re_res == NULL) {
823 device_printf(dev, "couldn't map ports/memory\n");
828 sc->re_btag = rman_get_bustag(sc->re_res);
829 sc->re_bhandle = rman_get_bushandle(sc->re_res);
831 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
832 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
836 * and continue matching for the specific chip...
838 for (; t->re_name != NULL; t++) {
839 if (product == t->re_did && vendor == t->re_vid &&
840 t->re_basetype == hwrev) {
841 device_set_desc(dev, t->re_name);
849 * This routine takes the segment list provided as the result of
850 * a bus_dma_map_load() operation and assigns the addresses/lengths
851 * to RealTek DMA descriptors. This can be called either by the RX
852 * code or the TX code. In the RX case, we'll probably wind up mapping
853 * at most one segment. For the TX case, there could be any number of
854 * segments since TX packets may span multiple mbufs. In either case,
855 * if the number of segments is larger than the re_maxsegs limit
856 * specified by the caller, we abort the mapping operation. Sadly,
857 * whoever designed the buffer mapping API did not provide a way to
858 * return an error from here, so we have to fake it a bit.
862 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
863 bus_size_t mapsize, int error)
865 struct re_dmaload_arg *ctx;
866 struct re_desc *d = NULL;
875 /* Signal error to caller if there's too many segments */
876 if (nseg > ctx->re_maxsegs) {
882 * Map the segment array into descriptors. Note that we set the
883 * start-of-frame and end-of-frame markers for either TX or RX, but
884 * they really only have meaning in the TX case. (In the RX case,
885 * it's the chip that tells us where packets begin and end.)
886 * We also keep track of the end of the ring and set the
887 * end-of-ring bits as needed, and we set the ownership bits
888 * in all except the very first descriptor. (The caller will
889 * set this descriptor later when it start transmission or
894 d = &ctx->re_ring[idx];
895 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
899 cmdstat = segs[i].ds_len;
900 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
901 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
903 cmdstat |= RE_TDESC_CMD_SOF;
905 cmdstat |= RE_TDESC_CMD_OWN;
906 if (idx == (RE_RX_DESC_CNT - 1))
907 cmdstat |= RE_TDESC_CMD_EOR;
908 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
915 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
916 ctx->re_maxsegs = nseg;
921 * Map a single buffer address.
925 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
932 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
934 *addr = segs->ds_addr;
938 re_allocmem(device_t dev, struct re_softc *sc)
943 * Allocate map for RX mbufs.
946 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
947 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
948 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
949 &sc->re_ldata.re_mtag);
951 device_printf(dev, "could not allocate dma tag\n");
956 * Allocate map for TX descriptor list.
958 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
959 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
960 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
961 &sc->re_ldata.re_tx_list_tag);
963 device_printf(dev, "could not allocate dma tag\n");
967 /* Allocate DMA'able memory for the TX ring */
969 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
970 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
971 &sc->re_ldata.re_tx_list_map);
973 device_printf(dev, "could not allocate TX ring\n");
977 /* Load the map for the TX ring. */
979 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
980 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
981 RE_TX_LIST_SZ, re_dma_map_addr,
982 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
984 device_printf(dev, "could not get addres of TX ring\n");
988 /* Create DMA maps for TX buffers */
990 for (i = 0; i < RE_TX_DESC_CNT; i++) {
991 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
992 &sc->re_ldata.re_tx_dmamap[i]);
994 device_printf(dev, "can't create DMA map for TX\n");
1000 * Allocate map for RX descriptor list.
1002 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
1003 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1004 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1005 &sc->re_ldata.re_rx_list_tag);
1007 device_printf(dev, "could not allocate dma tag\n");
1011 /* Allocate DMA'able memory for the RX ring */
1013 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1014 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1015 &sc->re_ldata.re_rx_list_map);
1017 device_printf(dev, "could not allocate RX ring\n");
1021 /* Load the map for the RX ring. */
1023 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1024 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
1025 RE_RX_LIST_SZ, re_dma_map_addr,
1026 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
1028 device_printf(dev, "could not get address of RX ring\n");
1032 /* Create DMA maps for RX buffers */
1034 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1035 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1036 &sc->re_ldata.re_rx_dmamap[i]);
1038 device_printf(dev, "can't create DMA map for RX\n");
1047 * Attach the interface. Allocate softc structures, do ifmedia
1048 * setup and ethernet/BPF attach.
1051 re_attach(device_t dev)
1053 struct re_softc *sc = device_get_softc(dev);
1055 const struct re_hwrev *hw_rev;
1056 uint8_t eaddr[ETHER_ADDR_LEN];
1057 uint16_t as[ETHER_ADDR_LEN / 2];
1058 uint16_t re_did = 0;
1060 int error = 0, rid, i;
1062 callout_init(&sc->re_timer);
1067 RE_ENABLE_TX_MODERATION(sc);
1069 sysctl_ctx_init(&sc->re_sysctl_ctx);
1070 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1071 SYSCTL_STATIC_CHILDREN(_hw),
1073 device_get_nameunit(dev),
1075 if (sc->re_sysctl_tree == NULL) {
1076 device_printf(dev, "can't add sysctl node\n");
1080 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1081 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1082 OID_AUTO, "tx_moderation",
1083 CTLTYPE_INT | CTLFLAG_RW,
1084 sc, 0, re_sysctl_tx_moderation, "I",
1085 "Enable/Disable TX moderation");
1087 #ifndef BURN_BRIDGES
1089 * Handle power management nonsense.
1092 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1093 uint32_t membase, irq;
1095 /* Save important PCI config data. */
1096 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1097 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1099 /* Reset the power state. */
1100 device_printf(dev, "chip is in D%d power mode "
1101 "-- setting to D0\n", pci_get_powerstate(dev));
1103 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1105 /* Restore PCI config data. */
1106 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1107 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1111 * Map control/status registers.
1113 pci_enable_busmaster(dev);
1116 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1119 if (sc->re_res == NULL) {
1120 device_printf(dev, "couldn't map ports\n");
1125 sc->re_btag = rman_get_bustag(sc->re_res);
1126 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1128 /* Allocate interrupt */
1130 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1131 RF_SHAREABLE | RF_ACTIVE);
1133 if (sc->re_irq == NULL) {
1134 device_printf(dev, "couldn't map interrupt\n");
1139 /* Reset the adapter. */
1142 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1143 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1144 if (hw_rev->re_rev == hwrev) {
1145 sc->re_type = hw_rev->re_type;
1146 sc->re_flags = hw_rev->re_flags;
1152 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1153 if (re_did != 0x8129)
1157 * Get station address from the EEPROM.
1159 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
1160 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1161 as[i] = le16toh(as[i]);
1162 bcopy(as, eaddr, sizeof(eaddr));
1164 if (sc->re_type == RE_8169) {
1165 /* Set RX length mask */
1166 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1167 sc->re_txstart = RE_GTXSTART;
1169 /* Set RX length mask */
1170 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1171 sc->re_txstart = RE_TXSTART;
1175 * Allocate the parent bus DMA tag appropriate for PCI.
1177 #define RE_NSEG_NEW 32
1178 error = bus_dma_tag_create(NULL, /* parent */
1179 1, 0, /* alignment, boundary */
1180 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1181 BUS_SPACE_MAXADDR, /* highaddr */
1182 NULL, NULL, /* filter, filterarg */
1183 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1184 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1185 BUS_DMA_ALLOCNOW, /* flags */
1186 &sc->re_parent_tag);
1190 error = re_allocmem(dev, sc);
1196 if (mii_phy_probe(dev, &sc->re_miibus,
1197 re_ifmedia_upd, re_ifmedia_sts)) {
1198 device_printf(dev, "MII without any phy!\n");
1203 ifp = &sc->arpcom.ac_if;
1205 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1206 ifp->if_mtu = ETHERMTU;
1207 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1208 ifp->if_ioctl = re_ioctl;
1209 ifp->if_capabilities = IFCAP_VLAN_MTU;
1210 ifp->if_start = re_start;
1211 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1212 #ifdef DEVICE_POLLING
1213 ifp->if_poll = re_poll;
1215 ifp->if_watchdog = re_watchdog;
1216 ifp->if_init = re_init;
1217 if (sc->re_type == RE_8169)
1218 ifp->if_baudrate = 1000000000;
1220 ifp->if_baudrate = 100000000;
1221 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1222 ifq_set_ready(&ifp->if_snd);
1224 #ifdef RE_DISABLE_HWCSUM
1225 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1226 ifp->if_hwassist = 0;
1228 ifp->if_capenable = ifp->if_capabilities;
1229 ifp->if_hwassist = RE_CSUM_FEATURES;
1230 #endif /* RE_DISABLE_HWCSUM */
1233 * Call MI attach routine.
1235 ether_ifattach(ifp, eaddr, NULL);
1239 * Perform hardware diagnostic on the original RTL8169.
1240 * Some 32-bit cards were incorrectly wired and would
1241 * malfunction if plugged into a 64-bit slot.
1243 if (hwrev == RE_HWREV_8169) {
1244 lwkt_serialize_enter(ifp->if_serializer);
1245 error = re_diag(sc);
1246 lwkt_serialize_exit(ifp->if_serializer);
1249 device_printf(dev, "hardware diagnostic failure\n");
1250 ether_ifdetach(ifp);
1254 #endif /* RE_DIAG */
1256 /* Hook interrupt last to avoid having to lock softc */
1257 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc,
1258 &sc->re_intrhand, ifp->if_serializer);
1261 device_printf(dev, "couldn't set up irq\n");
1262 ether_ifdetach(ifp);
1274 * Shutdown hardware and free up resources. This can be called any
1275 * time after the mutex has been initialized. It is called in both
1276 * the error case in attach and the normal detach case so it needs
1277 * to be careful about only freeing resources that have actually been
1281 re_detach(device_t dev)
1283 struct re_softc *sc = device_get_softc(dev);
1284 struct ifnet *ifp = &sc->arpcom.ac_if;
1287 /* These should only be active if attach succeeded */
1288 if (device_is_attached(dev)) {
1289 lwkt_serialize_enter(ifp->if_serializer);
1291 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1292 lwkt_serialize_exit(ifp->if_serializer);
1294 ether_ifdetach(ifp);
1297 device_delete_child(dev, sc->re_miibus);
1298 bus_generic_detach(dev);
1301 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1303 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1307 /* Unload and free the RX DMA ring memory and map */
1309 if (sc->re_ldata.re_rx_list_tag) {
1310 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1311 sc->re_ldata.re_rx_list_map);
1312 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1313 sc->re_ldata.re_rx_list,
1314 sc->re_ldata.re_rx_list_map);
1315 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1318 /* Unload and free the TX DMA ring memory and map */
1320 if (sc->re_ldata.re_tx_list_tag) {
1321 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1322 sc->re_ldata.re_tx_list_map);
1323 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1324 sc->re_ldata.re_tx_list,
1325 sc->re_ldata.re_tx_list_map);
1326 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1329 /* Destroy all the RX and TX buffer maps */
1331 if (sc->re_ldata.re_mtag) {
1332 for (i = 0; i < RE_TX_DESC_CNT; i++)
1333 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1334 sc->re_ldata.re_tx_dmamap[i]);
1335 for (i = 0; i < RE_RX_DESC_CNT; i++)
1336 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1337 sc->re_ldata.re_rx_dmamap[i]);
1338 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1341 /* Unload and free the stats buffer and map */
1343 if (sc->re_ldata.re_stag) {
1344 bus_dmamap_unload(sc->re_ldata.re_stag,
1345 sc->re_ldata.re_rx_list_map);
1346 bus_dmamem_free(sc->re_ldata.re_stag,
1347 sc->re_ldata.re_stats,
1348 sc->re_ldata.re_smap);
1349 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1352 if (sc->re_parent_tag)
1353 bus_dma_tag_destroy(sc->re_parent_tag);
1359 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1361 struct re_dmaload_arg arg;
1362 struct mbuf *n = NULL;
1366 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1371 m->m_data = m->m_ext.ext_buf;
1373 m->m_len = m->m_pkthdr.len = MCLBYTES;
1377 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1378 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1385 arg.re_ring = sc->re_ldata.re_rx_list;
1387 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1388 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1389 &arg, BUS_DMA_NOWAIT);
1390 if (error || arg.re_maxsegs != 1) {
1396 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1397 sc->re_ldata.re_rx_mbuf[idx] = m;
1399 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1400 BUS_DMASYNC_PREREAD);
1406 re_tx_list_init(struct re_softc *sc)
1408 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1409 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1411 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1412 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1413 sc->re_ldata.re_tx_prodidx = 0;
1414 sc->re_ldata.re_tx_considx = 0;
1415 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1421 re_rx_list_init(struct re_softc *sc)
1425 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1426 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1428 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1429 error = re_newbuf(sc, i, NULL);
1434 /* Flush the RX descriptors */
1436 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1437 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1439 sc->re_ldata.re_rx_prodidx = 0;
1440 sc->re_head = sc->re_tail = NULL;
1446 * RX handler for C+ and 8169. For the gigE chips, we support
1447 * the reception of jumbo frames that have been fragmented
1448 * across multiple 2K mbuf cluster buffers.
1451 re_rxeof(struct re_softc *sc)
1453 struct ifnet *ifp = &sc->arpcom.ac_if;
1455 struct re_desc *cur_rx;
1456 uint32_t rxstat, rxvlan;
1459 /* Invalidate the descriptor memory */
1461 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1462 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1464 for (i = sc->re_ldata.re_rx_prodidx;
1465 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1466 cur_rx = &sc->re_ldata.re_rx_list[i];
1467 m = sc->re_ldata.re_rx_mbuf[i];
1468 total_len = RE_RXBYTES(cur_rx);
1469 rxstat = le32toh(cur_rx->re_cmdstat);
1470 rxvlan = le32toh(cur_rx->re_vlanctl);
1472 /* Invalidate the RX mbuf and unload its map */
1474 bus_dmamap_sync(sc->re_ldata.re_mtag,
1475 sc->re_ldata.re_rx_dmamap[i],
1476 BUS_DMASYNC_POSTWRITE);
1477 bus_dmamap_unload(sc->re_ldata.re_mtag,
1478 sc->re_ldata.re_rx_dmamap[i]);
1480 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1481 m->m_len = MCLBYTES - ETHER_ALIGN;
1482 if (sc->re_head == NULL) {
1483 sc->re_head = sc->re_tail = m;
1485 sc->re_tail->m_next = m;
1488 re_newbuf(sc, i, NULL);
1493 * NOTE: for the 8139C+, the frame length field
1494 * is always 12 bits in size, but for the gigE chips,
1495 * it is 13 bits (since the max RX frame length is 16K).
1496 * Unfortunately, all 32 bits in the status word
1497 * were already used, so to make room for the extra
1498 * length bit, RealTek took out the 'frame alignment
1499 * error' bit and shifted the other status bits
1500 * over one slot. The OWN, EOR, FS and LS bits are
1501 * still in the same places. We have already extracted
1502 * the frame length and checked the OWN bit, so rather
1503 * than using an alternate bit mapping, we shift the
1504 * status bits one space to the right so we can evaluate
1505 * them using the 8169 status as though it was in the
1506 * same format as that of the 8139C+.
1508 if (sc->re_type == RE_8169)
1511 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1514 * If this is part of a multi-fragment packet,
1515 * discard all the pieces.
1517 if (sc->re_head != NULL) {
1518 m_freem(sc->re_head);
1519 sc->re_head = sc->re_tail = NULL;
1521 re_newbuf(sc, i, m);
1526 * If allocating a replacement mbuf fails,
1527 * reload the current one.
1530 if (re_newbuf(sc, i, NULL)) {
1532 if (sc->re_head != NULL) {
1533 m_freem(sc->re_head);
1534 sc->re_head = sc->re_tail = NULL;
1536 re_newbuf(sc, i, m);
1540 if (sc->re_head != NULL) {
1541 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1543 * Special case: if there's 4 bytes or less
1544 * in this buffer, the mbuf can be discarded:
1545 * the last 4 bytes is the CRC, which we don't
1546 * care about anyway.
1548 if (m->m_len <= ETHER_CRC_LEN) {
1549 sc->re_tail->m_len -=
1550 (ETHER_CRC_LEN - m->m_len);
1553 m->m_len -= ETHER_CRC_LEN;
1554 sc->re_tail->m_next = m;
1557 sc->re_head = sc->re_tail = NULL;
1558 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1560 m->m_pkthdr.len = m->m_len =
1561 (total_len - ETHER_CRC_LEN);
1564 m->m_pkthdr.rcvif = ifp;
1566 /* Do RX checksumming if enabled */
1568 if (ifp->if_capenable & IFCAP_RXCSUM) {
1570 /* Check IP header checksum */
1571 if (rxstat & RE_RDESC_STAT_PROTOID)
1572 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1573 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1574 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1576 /* Check TCP/UDP checksum */
1577 if ((RE_TCPPKT(rxstat) &&
1578 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1579 (RE_UDPPKT(rxstat) &&
1580 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1581 m->m_pkthdr.csum_flags |=
1582 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1583 m->m_pkthdr.csum_data = 0xffff;
1587 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1589 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1591 ifp->if_input(ifp, m);
1595 /* Flush the RX DMA ring */
1597 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1598 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1600 sc->re_ldata.re_rx_prodidx = i;
1604 re_txeof(struct re_softc *sc)
1606 struct ifnet *ifp = &sc->arpcom.ac_if;
1610 /* Invalidate the TX descriptor list */
1612 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1613 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
1615 for (idx = sc->re_ldata.re_tx_considx;
1616 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) {
1617 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1618 if (txstat & RE_TDESC_CMD_OWN)
1621 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
1624 * We only stash mbufs in the last descriptor
1625 * in a fragment chain, which also happens to
1626 * be the only place where the TX status bits
1629 if (txstat & RE_TDESC_CMD_EOF) {
1630 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1631 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1632 bus_dmamap_unload(sc->re_ldata.re_mtag,
1633 sc->re_ldata.re_tx_dmamap[idx]);
1634 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1635 RE_TDESC_STAT_COLCNT))
1636 ifp->if_collisions++;
1637 if (txstat & RE_TDESC_STAT_TXERRSUM)
1642 sc->re_ldata.re_tx_free++;
1645 /* No changes made to the TX ring, so no flush needed */
1646 if (sc->re_ldata.re_tx_free) {
1647 sc->re_ldata.re_tx_considx = idx;
1648 ifp->if_flags &= ~IFF_OACTIVE;
1653 * Some chips will ignore a second TX request issued while an
1654 * existing transmission is in progress. If the transmitter goes
1655 * idle but there are still packets waiting to be sent, we need
1656 * to restart the channel here to flush them out. This only seems
1657 * to be required with the PCIe devices.
1659 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1660 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
1663 * If not all descriptors have been released reaped yet,
1664 * reload the timer so that we will eventually get another
1665 * interrupt that will cause us to re-enter this routine.
1666 * This is done in case the transmitter has gone idle.
1668 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
1669 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1670 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1676 struct re_softc *sc = xsc;
1678 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1679 re_tick_serialized(xsc);
1680 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1684 re_tick_serialized(void *xsc)
1686 struct re_softc *sc = xsc;
1687 struct ifnet *ifp = &sc->arpcom.ac_if;
1688 struct mii_data *mii;
1690 mii = device_get_softc(sc->re_miibus);
1693 if (!(mii->mii_media_status & IFM_ACTIVE))
1696 if (mii->mii_media_status & IFM_ACTIVE &&
1697 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1699 if (!ifq_is_empty(&ifp->if_snd))
1704 callout_reset(&sc->re_timer, hz, re_tick, sc);
1707 #ifdef DEVICE_POLLING
1710 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1712 struct re_softc *sc = ifp->if_softc;
1716 /* disable interrupts */
1717 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1719 case POLL_DEREGISTER:
1720 /* enable interrupts */
1721 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1724 sc->rxcycles = count;
1728 if (!ifq_is_empty(&ifp->if_snd))
1729 (*ifp->if_start)(ifp);
1731 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1734 status = CSR_READ_2(sc, RE_ISR);
1735 if (status == 0xffff)
1738 CSR_WRITE_2(sc, RE_ISR, status);
1741 * XXX check behaviour on receiver stalls.
1744 if (status & RE_ISR_SYSTEM_ERR) {
1752 #endif /* DEVICE_POLLING */
1757 struct re_softc *sc = arg;
1758 struct ifnet *ifp = &sc->arpcom.ac_if;
1761 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1765 status = CSR_READ_2(sc, RE_ISR);
1766 /* If the card has gone away the read returns 0xffff. */
1767 if (status == 0xffff)
1770 CSR_WRITE_2(sc, RE_ISR, status);
1772 if ((status & sc->re_intrs) == 0)
1775 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW))
1778 if ((status & sc->re_tx_ack) ||
1779 (status & RE_ISR_TX_ERR) ||
1780 (status & RE_ISR_TX_DESC_UNAVAIL))
1783 if (status & RE_ISR_SYSTEM_ERR) {
1788 if (status & RE_ISR_LINKCHG) {
1789 callout_stop(&sc->re_timer);
1790 re_tick_serialized(sc);
1794 if (!ifq_is_empty(&ifp->if_snd))
1795 (*ifp->if_start)(ifp);
1799 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1801 struct ifnet *ifp = &sc->arpcom.ac_if;
1802 struct mbuf *m, *m_new = NULL;
1803 struct re_dmaload_arg arg;
1808 if (sc->re_ldata.re_tx_free <= 4)
1814 * Set up checksum offload. Note: checksum offload bits must
1815 * appear in all descriptors of a multi-descriptor transmit
1816 * attempt. (This is according to testing done with an 8169
1817 * chip. I'm not sure if this is a requirement or a bug.)
1822 if (m->m_pkthdr.csum_flags & CSUM_IP)
1823 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1824 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1825 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1826 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1827 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1831 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1832 if (arg.re_maxsegs > 4)
1833 arg.re_maxsegs -= 4;
1834 arg.re_ring = sc->re_ldata.re_tx_list;
1836 map = sc->re_ldata.re_tx_dmamap[*idx];
1839 * With some of the RealTek chips, using the checksum offload
1840 * support in conjunction with the autopadding feature results
1841 * in the transmission of corrupt frames. For example, if we
1842 * need to send a really small IP fragment that's less than 60
1843 * bytes in size, and IP header checksumming is enabled, the
1844 * resulting ethernet frame that appears on the wire will
1845 * have garbled payload. To work around this, if TX checksum
1846 * offload is enabled, we always manually pad short frames out
1847 * to the minimum ethernet frame size. We do this by pretending
1848 * the mbuf chain has too many fragments so the coalescing code
1849 * below can assemble the packet into a single buffer that's
1850 * padded out to the mininum frame size.
1852 * Note: this appears unnecessary for TCP, and doing it for TCP
1853 * with PCIe adapters seems to result in bad checksums.
1855 if (arg.re_flags && !(arg.re_flags & RE_TDESC_CMD_TCPCSUM) &&
1856 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
1859 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1860 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1863 if (error && error != EFBIG) {
1864 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1868 /* Too many segments to map, coalesce into a single mbuf */
1870 if (error || arg.re_maxsegs == 0) {
1871 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1872 if (m_new == NULL) {
1880 * Manually pad short frames, and zero the pad space
1881 * to avoid leaking data.
1883 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) {
1884 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
1885 RE_MIN_FRAMELEN - m_new->m_pkthdr.len);
1886 m_new->m_pkthdr.len += RE_MIN_FRAMELEN -
1887 m_new->m_pkthdr.len;
1888 m_new->m_len = m_new->m_pkthdr.len;
1894 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1895 arg.re_ring = sc->re_ldata.re_tx_list;
1897 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1898 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1901 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1907 * Insure that the map for this transmission
1908 * is placed at the array index of the last descriptor
1911 sc->re_ldata.re_tx_dmamap[*idx] =
1912 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1913 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1915 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1916 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1919 * Set up hardware VLAN tagging. Note: vlan tag info must
1920 * appear in the first descriptor of a multi-descriptor
1921 * transmission attempt.
1924 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1925 m->m_pkthdr.rcvif != NULL &&
1926 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1928 ifv = m->m_pkthdr.rcvif->if_softc;
1930 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1931 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1934 /* Transfer ownership of packet to the chip. */
1936 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1937 htole32(RE_TDESC_CMD_OWN);
1938 if (*idx != arg.re_idx)
1939 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1940 htole32(RE_TDESC_CMD_OWN);
1942 RE_DESC_INC(arg.re_idx);
1949 * Main transmit routine for C+ and gigE NICs.
1953 re_start(struct ifnet *ifp)
1955 struct re_softc *sc = ifp->if_softc;
1956 struct mbuf *m_head;
1957 struct mbuf *m_head2;
1958 int called_defrag, idx, need_trans;
1960 if (!sc->re_link || (ifp->if_flags & IFF_OACTIVE))
1963 idx = sc->re_ldata.re_tx_prodidx;
1966 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1967 m_head = ifq_poll(&ifp->if_snd);
1971 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
1973 * If we could not encapsulate the defragged packet,
1974 * the returned m_head2 is garbage and we must dequeue
1975 * and throw away the original packet.
1977 if (called_defrag) {
1978 ifq_dequeue(&ifp->if_snd, m_head);
1981 ifp->if_flags |= IFF_OACTIVE;
1986 * Clean out the packet we encapsulated. If we defragged
1987 * the packet the m_head2 is the one that got encapsulated
1988 * and the original must be thrown away. Otherwise m_head2
1989 * *IS* the original.
1991 ifq_dequeue(&ifp->if_snd, m_head);
1997 * If there's a BPF listener, bounce a copy of this frame
2000 BPF_MTAP(ifp, m_head2);
2004 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
2005 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
2006 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2010 /* Flush the TX descriptors */
2011 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2012 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2014 sc->re_ldata.re_tx_prodidx = idx;
2017 * RealTek put the TX poll request register in a different
2018 * location on the 8169 gigE chip. I don't know why.
2020 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2022 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2024 * Use the countdown timer for interrupt moderation.
2025 * 'TX done' interrupts are disabled. Instead, we reset the
2026 * countdown timer, which will begin counting until it hits
2027 * the value in the TIMERINT register, and then trigger an
2028 * interrupt. Each time we write to the TIMERCNT register,
2029 * the timer count is reset to 0.
2031 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2035 * Set a timeout in case the chip goes out to lunch.
2043 struct re_softc *sc = xsc;
2044 struct ifnet *ifp = &sc->arpcom.ac_if;
2045 struct mii_data *mii;
2048 mii = device_get_softc(sc->re_miibus);
2051 * Cancel pending I/O and free all RX/TX buffers.
2056 * Enable C+ RX and TX mode, as well as VLAN stripping and
2057 * RX checksum offload. We must configure the C+ register
2058 * before all others.
2060 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2061 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
2062 (ifp->if_capenable & IFCAP_RXCSUM ?
2063 RE_CPLUSCMD_RXCSUM_ENB : 0));
2066 * Init our MAC address. Even though the chipset
2067 * documentation doesn't mention it, we need to enter "Config
2068 * register write enable" mode to modify the ID registers.
2070 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2071 CSR_WRITE_4(sc, RE_IDR0,
2072 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2073 CSR_WRITE_2(sc, RE_IDR4,
2074 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2075 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2078 * For C+ mode, initialize the RX descriptors and mbufs.
2080 re_rx_list_init(sc);
2081 re_tx_list_init(sc);
2084 * Load the addresses of the RX and TX lists into the chip.
2086 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2087 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2088 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2089 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2091 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2092 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2093 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2094 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2097 * Enable transmit and receive.
2099 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2102 * Set the initial TX and RX configuration.
2104 if (sc->re_testmode) {
2105 if (sc->re_type == RE_8169)
2106 CSR_WRITE_4(sc, RE_TXCFG,
2107 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2109 CSR_WRITE_4(sc, RE_TXCFG,
2110 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2112 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2114 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2116 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2118 /* Set the individual bit to receive frames for this host only. */
2119 rxcfg = CSR_READ_4(sc, RE_RXCFG);
2120 rxcfg |= RE_RXCFG_RX_INDIV;
2122 /* If we want promiscuous mode, set the allframes bit. */
2123 if (ifp->if_flags & IFF_PROMISC) {
2124 rxcfg |= RE_RXCFG_RX_ALLPHYS;
2125 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2127 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
2128 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2132 * Set capture broadcast bit to capture broadcast frames.
2134 if (ifp->if_flags & IFF_BROADCAST) {
2135 rxcfg |= RE_RXCFG_RX_BROAD;
2136 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2138 rxcfg &= ~RE_RXCFG_RX_BROAD;
2139 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2143 * Program the multicast filter, if necessary.
2147 #ifdef DEVICE_POLLING
2149 * Disable interrupts if we are polling.
2151 if (ifp->if_flags & IFF_POLLING)
2152 CSR_WRITE_2(sc, RE_IMR, 0);
2153 else /* otherwise ... */
2154 #endif /* DEVICE_POLLING */
2156 * Enable interrupts.
2158 if (sc->re_testmode)
2159 CSR_WRITE_2(sc, RE_IMR, 0);
2161 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2162 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2164 /* Set initial TX threshold */
2165 sc->re_txthresh = RE_TX_THRESH_INIT;
2167 /* Start RX/TX process. */
2168 if (sc->re_flags & RE_F_HASMPC)
2169 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2171 /* Enable receiver and transmitter. */
2172 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2175 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2177 * Initialize the timer interrupt register so that
2178 * a timer interrupt will be generated once the timer
2179 * reaches a certain number of ticks. The timer is
2180 * reloaded on each transmit. This gives us TX interrupt
2181 * moderation, which dramatically improves TX frame rate.
2183 if (sc->re_type == RE_8169)
2184 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2186 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2190 * For 8169 gigE NICs, set the max allowed RX packet
2191 * size so we can receive jumbo frames.
2193 if (sc->re_type == RE_8169)
2194 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2196 if (sc->re_testmode) {
2202 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2204 ifp->if_flags |= IFF_RUNNING;
2205 ifp->if_flags &= ~IFF_OACTIVE;
2208 callout_reset(&sc->re_timer, hz, re_tick, sc);
2212 * Set media options.
2215 re_ifmedia_upd(struct ifnet *ifp)
2217 struct re_softc *sc = ifp->if_softc;
2218 struct mii_data *mii;
2220 mii = device_get_softc(sc->re_miibus);
2227 * Report current media status.
2230 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2232 struct re_softc *sc = ifp->if_softc;
2233 struct mii_data *mii;
2235 mii = device_get_softc(sc->re_miibus);
2238 ifmr->ifm_active = mii->mii_media_active;
2239 ifmr->ifm_status = mii->mii_media_status;
2243 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2245 struct re_softc *sc = ifp->if_softc;
2246 struct ifreq *ifr = (struct ifreq *) data;
2247 struct mii_data *mii;
2252 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2254 ifp->if_mtu = ifr->ifr_mtu;
2257 if (ifp->if_flags & IFF_UP)
2259 else if (ifp->if_flags & IFF_RUNNING)
2269 mii = device_get_softc(sc->re_miibus);
2270 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2273 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2274 ifp->if_capenable |=
2275 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2276 if (ifp->if_capenable & IFCAP_TXCSUM)
2277 ifp->if_hwassist = RE_CSUM_FEATURES;
2279 ifp->if_hwassist = 0;
2280 if (ifp->if_flags & IFF_RUNNING)
2284 error = ether_ioctl(ifp, command, data);
2291 re_watchdog(struct ifnet *ifp)
2293 struct re_softc *sc = ifp->if_softc;
2295 if_printf(ifp, "watchdog timeout\n");
2304 if (!ifq_is_empty(&ifp->if_snd))
2309 * Stop the adapter and free any mbufs allocated to the
2313 re_stop(struct re_softc *sc)
2315 struct ifnet *ifp = &sc->arpcom.ac_if;
2319 callout_stop(&sc->re_timer);
2321 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2323 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2324 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2325 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2327 if (sc->re_head != NULL) {
2328 m_freem(sc->re_head);
2329 sc->re_head = sc->re_tail = NULL;
2332 /* Free the TX list buffers. */
2333 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2334 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2335 bus_dmamap_unload(sc->re_ldata.re_mtag,
2336 sc->re_ldata.re_tx_dmamap[i]);
2337 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2338 sc->re_ldata.re_tx_mbuf[i] = NULL;
2342 /* Free the RX list buffers. */
2343 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2344 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2345 bus_dmamap_unload(sc->re_ldata.re_mtag,
2346 sc->re_ldata.re_rx_dmamap[i]);
2347 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2348 sc->re_ldata.re_rx_mbuf[i] = NULL;
2354 * Device suspend routine. Stop the interface and save some PCI
2355 * settings in case the BIOS doesn't restore them properly on
2359 re_suspend(device_t dev)
2361 #ifndef BURN_BRIDGES
2364 struct re_softc *sc = device_get_softc(dev);
2368 #ifndef BURN_BRIDGES
2369 for (i = 0; i < 5; i++)
2370 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2371 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2372 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2373 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2374 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2383 * Device resume routine. Restore some PCI settings in case the BIOS
2384 * doesn't, re-enable busmastering, and restart the interface if
2388 re_resume(device_t dev)
2390 struct re_softc *sc = device_get_softc(dev);
2391 struct ifnet *ifp = &sc->arpcom.ac_if;
2392 #ifndef BURN_BRIDGES
2396 #ifndef BURN_BRIDGES
2397 /* better way to do this? */
2398 for (i = 0; i < 5; i++)
2399 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2400 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2401 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2402 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2403 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2405 /* reenable busmastering */
2406 pci_enable_busmaster(dev);
2407 pci_enable_io(dev, SYS_RES_IOPORT);
2410 /* reinitialize interface if necessary */
2411 if (ifp->if_flags & IFF_UP)
2420 * Stop all chip I/O so that the kernel's probe routines don't
2421 * get confused by errant DMAs when rebooting.
2424 re_shutdown(device_t dev)
2426 struct re_softc *sc = device_get_softc(dev);
2427 struct ifnet *ifp = &sc->arpcom.ac_if;
2429 lwkt_serialize_enter(ifp->if_serializer);
2431 lwkt_serialize_exit(ifp->if_serializer);
2435 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS)
2437 struct re_softc *sc = arg1;
2438 struct ifnet *ifp = &sc->arpcom.ac_if;
2439 int error = 0, mod, mod_old;
2441 lwkt_serialize_enter(ifp->if_serializer);
2443 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc);
2445 error = sysctl_handle_int(oidp, &mod, 0, req);
2446 if (error || req->newptr == NULL || mod == mod_old)
2448 if (mod != 0 && mod != 1) {
2454 RE_ENABLE_TX_MODERATION(sc);
2456 RE_DISABLE_TX_MODERATION(sc);
2458 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP))
2461 lwkt_serialize_exit(ifp->if_serializer);