3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.51 2008/09/29 20:27:38 dillon Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
118 #include <sys/endian.h>
119 #include <sys/kernel.h>
120 #include <sys/interrupt.h>
121 #include <sys/malloc.h>
122 #include <sys/mbuf.h>
123 #include <sys/rman.h>
124 #include <sys/serialize.h>
125 #include <sys/socket.h>
126 #include <sys/sockio.h>
127 #include <sys/sysctl.h>
130 #include <net/ethernet.h>
132 #include <net/ifq_var.h>
133 #include <net/if_arp.h>
134 #include <net/if_dl.h>
135 #include <net/if_media.h>
136 #include <net/if_types.h>
137 #include <net/vlan/if_vlan_var.h>
138 #include <net/vlan/if_vlan_ether.h>
140 #include <dev/netif/mii_layer/mii.h>
141 #include <dev/netif/mii_layer/miivar.h>
143 #include <bus/pci/pcidevs.h>
144 #include <bus/pci/pcireg.h>
145 #include <bus/pci/pcivar.h>
147 /* "device miibus" required. See GENERIC if you get errors here. */
148 #include "miibus_if.h"
150 #include <dev/netif/re/if_rereg.h>
151 #include <dev/netif/re/if_revar.h>
153 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
155 #define RE_DISABLE_HWCSUM
159 * Various supported device vendors/types and their names.
161 static const struct re_type re_devs[] = {
162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
163 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
164 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
165 "RealTek 8139C+ 10/100BaseTX" },
166 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E,
167 "RealTek 8101E PCIe 10/100baseTX" },
168 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8102EL,
169 "RealTek 8102EL PCIe 10/100baseTX" },
170 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1,
171 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
172 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2,
173 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN3,
175 "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
176 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168C,
177 "RealTek 8168C/8111C PCIe Gigabit Ethernet" },
178 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
179 "RealTek 8169 Gigabit Ethernet" },
180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
181 "RealTek 8169S Single-chip Gigabit Ethernet" },
182 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB,
183 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
184 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC,
185 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
186 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC,
187 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
188 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
189 "RealTek 8110S Single-chip Gigabit Ethernet" },
190 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S,
191 "Corega CG-LAPCIGT Gigabit Ethernet" },
192 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S,
193 "Linksys EG1032 Gigabit Ethernet" },
194 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S,
195 "US Robotics 997902 Gigabit Ethernet" },
199 static const struct re_hwrev re_hwrevs[] = {
200 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" },
201 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" },
202 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" },
203 { RE_HWREV_8168_SPIN3, RE_8169, RE_F_PCIE, "8168" },
204 { RE_HWREV_8168C, RE_8169, RE_F_PCIE, "8168C" },
205 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" },
206 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" },
207 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" },
208 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" },
209 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" },
210 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" },
211 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" },
212 { RE_HWREV_8102EL, RE_8169, RE_F_PCIE, "8102EL" },
216 static int re_probe(device_t);
217 static int re_attach(device_t);
218 static int re_detach(device_t);
219 static int re_suspend(device_t);
220 static int re_resume(device_t);
221 static void re_shutdown(device_t);
223 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
225 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
226 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
228 static int re_allocmem(device_t, struct re_softc *);
229 static int re_newbuf(struct re_softc *, int, struct mbuf *);
230 static int re_rx_list_init(struct re_softc *);
231 static int re_tx_list_init(struct re_softc *);
232 static void re_rxeof(struct re_softc *);
233 static void re_txeof(struct re_softc *);
234 static void re_intr(void *);
235 static void re_tick(void *);
236 static void re_tick_serialized(void *);
238 static void re_start(struct ifnet *);
239 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
240 static void re_init(void *);
241 static void re_stop(struct re_softc *);
242 static void re_watchdog(struct ifnet *);
243 static int re_ifmedia_upd(struct ifnet *);
244 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
246 static void re_eeprom_putbyte(struct re_softc *, int);
247 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
248 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
249 static int re_gmii_readreg(device_t, int, int);
250 static int re_gmii_writereg(device_t, int, int, int);
252 static int re_miibus_readreg(device_t, int, int);
253 static int re_miibus_writereg(device_t, int, int, int);
254 static void re_miibus_statchg(device_t);
256 static void re_setmulti(struct re_softc *);
257 static void re_reset(struct re_softc *);
260 static int re_diag(struct re_softc *);
263 #ifdef DEVICE_POLLING
264 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
267 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS);
269 static device_method_t re_methods[] = {
270 /* Device interface */
271 DEVMETHOD(device_probe, re_probe),
272 DEVMETHOD(device_attach, re_attach),
273 DEVMETHOD(device_detach, re_detach),
274 DEVMETHOD(device_suspend, re_suspend),
275 DEVMETHOD(device_resume, re_resume),
276 DEVMETHOD(device_shutdown, re_shutdown),
279 DEVMETHOD(bus_print_child, bus_generic_print_child),
280 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
283 DEVMETHOD(miibus_readreg, re_miibus_readreg),
284 DEVMETHOD(miibus_writereg, re_miibus_writereg),
285 DEVMETHOD(miibus_statchg, re_miibus_statchg),
290 static driver_t re_driver = {
293 sizeof(struct re_softc)
296 static devclass_t re_devclass;
298 DECLARE_DUMMY_MODULE(if_re);
299 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
300 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
301 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
304 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
307 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
310 * Send a read command and address to the EEPROM, check for ACK.
313 re_eeprom_putbyte(struct re_softc *sc, int addr)
317 d = addr | (RE_9346_READ << sc->re_eewidth);
320 * Feed in each bit and strobe the clock.
322 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
324 EE_SET(RE_EE_DATAIN);
326 EE_CLR(RE_EE_DATAIN);
336 * Read a word of data stored in the EEPROM at address 'addr.'
339 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
345 * Send address of word we want to read.
347 re_eeprom_putbyte(sc, addr);
350 * Start reading bits from EEPROM.
352 for (i = 0x8000; i != 0; i >>= 1) {
355 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
365 * Read a sequence of words from the EEPROM.
368 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
371 uint16_t word = 0, *ptr;
373 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
376 for (i = 0; i < cnt; i++) {
377 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
378 re_eeprom_getword(sc, off + i, &word);
379 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
380 ptr = (uint16_t *)(dest + (i * 2));
384 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
388 re_gmii_readreg(device_t dev, int phy, int reg)
390 struct re_softc *sc = device_get_softc(dev);
397 /* Let the rgephy driver read the GMEDIASTAT register */
399 if (reg == RE_GMEDIASTAT)
400 return(CSR_READ_1(sc, RE_GMEDIASTAT));
402 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
405 for (i = 0; i < RE_TIMEOUT; i++) {
406 rval = CSR_READ_4(sc, RE_PHYAR);
407 if (rval & RE_PHYAR_BUSY)
412 if (i == RE_TIMEOUT) {
413 device_printf(dev, "PHY read failed\n");
417 return(rval & RE_PHYAR_PHYDATA);
421 re_gmii_writereg(device_t dev, int phy, int reg, int data)
423 struct re_softc *sc = device_get_softc(dev);
427 CSR_WRITE_4(sc, RE_PHYAR,
428 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
431 for (i = 0; i < RE_TIMEOUT; i++) {
432 rval = CSR_READ_4(sc, RE_PHYAR);
433 if ((rval & RE_PHYAR_BUSY) == 0)
439 device_printf(dev, "PHY write failed\n");
445 re_miibus_readreg(device_t dev, int phy, int reg)
447 struct re_softc *sc = device_get_softc(dev);
449 uint16_t re8139_reg = 0;
451 if (sc->re_type == RE_8169) {
452 rval = re_gmii_readreg(dev, phy, reg);
456 /* Pretend the internal PHY is only at address 0 */
462 re8139_reg = RE_BMCR;
465 re8139_reg = RE_BMSR;
468 re8139_reg = RE_ANAR;
471 re8139_reg = RE_ANER;
474 re8139_reg = RE_LPAR;
480 * Allow the rlphy driver to read the media status
481 * register. If we have a link partner which does not
482 * support NWAY, this is the register which will tell
483 * us the results of parallel detection.
486 return(CSR_READ_1(sc, RE_MEDIASTAT));
488 device_printf(dev, "bad phy register\n");
491 rval = CSR_READ_2(sc, re8139_reg);
492 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) {
493 /* 8139C+ has different bit layout. */
494 rval &= ~(BMCR_LOOP | BMCR_ISO);
500 re_miibus_writereg(device_t dev, int phy, int reg, int data)
502 struct re_softc *sc= device_get_softc(dev);
503 u_int16_t re8139_reg = 0;
505 if (sc->re_type == RE_8169)
506 return(re_gmii_writereg(dev, phy, reg, data));
508 /* Pretend the internal PHY is only at address 0 */
514 re8139_reg = RE_BMCR;
515 if (sc->re_type == RE_8139CPLUS) {
516 /* 8139C+ has different bit layout. */
517 data &= ~(BMCR_LOOP | BMCR_ISO);
521 re8139_reg = RE_BMSR;
524 re8139_reg = RE_ANAR;
527 re8139_reg = RE_ANER;
530 re8139_reg = RE_LPAR;
536 device_printf(dev, "bad phy register\n");
539 CSR_WRITE_2(sc, re8139_reg, data);
544 re_miibus_statchg(device_t dev)
549 * Program the 64-bit multicast hash filter.
552 re_setmulti(struct re_softc *sc)
554 struct ifnet *ifp = &sc->arpcom.ac_if;
556 uint32_t hashes[2] = { 0, 0 };
557 struct ifmultiaddr *ifma;
561 rxfilt = CSR_READ_4(sc, RE_RXCFG);
563 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
564 rxfilt |= RE_RXCFG_RX_MULTI;
565 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
566 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
567 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
571 /* first, zot all the existing hash bits */
572 CSR_WRITE_4(sc, RE_MAR0, 0);
573 CSR_WRITE_4(sc, RE_MAR4, 0);
575 /* now program new ones */
576 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
577 if (ifma->ifma_addr->sa_family != AF_LINK)
579 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
580 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
582 hashes[0] |= (1 << h);
584 hashes[1] |= (1 << (h - 32));
589 rxfilt |= RE_RXCFG_RX_MULTI;
591 rxfilt &= ~RE_RXCFG_RX_MULTI;
593 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
596 * For some unfathomable reason, RealTek decided to reverse
597 * the order of the multicast hash registers in the PCI Express
598 * parts. This means we have to write the hash pattern in reverse
599 * order for those devices.
601 if (sc->re_flags & RE_F_PCIE) {
602 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0]));
603 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1]));
605 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
606 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
611 re_reset(struct re_softc *sc)
615 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
617 for (i = 0; i < RE_TIMEOUT; i++) {
619 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
623 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
625 CSR_WRITE_1(sc, 0x82, 1);
630 * The following routine is designed to test for a defect on some
631 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
632 * lines connected to the bus, however for a 32-bit only card, they
633 * should be pulled high. The result of this defect is that the
634 * NIC will not work right if you plug it into a 64-bit slot: DMA
635 * operations will be done with 64-bit transfers, which will fail
636 * because the 64-bit data lines aren't connected.
638 * There's no way to work around this (short of talking a soldering
639 * iron to the board), however we can detect it. The method we use
640 * here is to put the NIC into digital loopback mode, set the receiver
641 * to promiscuous mode, and then try to send a frame. We then compare
642 * the frame data we sent to what was received. If the data matches,
643 * then the NIC is working correctly, otherwise we know the user has
644 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
645 * slot. In the latter case, there's no way the NIC can work correctly,
646 * so we print out a message on the console and abort the device attach.
650 re_diag(struct re_softc *sc)
652 struct ifnet *ifp = &sc->arpcom.ac_if;
654 struct ether_header *eh;
655 struct re_desc *cur_rx;
658 int total_len, i, error = 0, phyaddr;
659 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
660 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
662 /* Allocate a single mbuf */
664 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
669 * Initialize the NIC in test mode. This sets the chip up
670 * so that it can send and receive frames, but performs the
671 * following special functions:
672 * - Puts receiver in promiscuous mode
673 * - Enables digital loopback mode
674 * - Leaves interrupts turned off
677 ifp->if_flags |= IFF_PROMISC;
682 if (sc->re_type == RE_8169)
687 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
688 for (i = 0; i < RE_TIMEOUT; i++) {
689 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
690 if (!(status & BMCR_RESET))
694 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
695 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
699 /* Put some data in the mbuf */
701 eh = mtod(m0, struct ether_header *);
702 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
703 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
704 eh->ether_type = htons(ETHERTYPE_IP);
705 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
708 * Queue the packet, start transmission.
709 * Note: ifq_handoff() ultimately calls re_start() for us.
712 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
713 error = ifq_handoff(ifp, m0, NULL);
720 /* Wait for it to propagate through the chip */
723 for (i = 0; i < RE_TIMEOUT; i++) {
724 status = CSR_READ_2(sc, RE_ISR);
725 CSR_WRITE_2(sc, RE_ISR, status);
726 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
727 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
732 if (i == RE_TIMEOUT) {
733 if_printf(ifp, "diagnostic failed to receive packet "
734 "in loopback mode\n");
740 * The packet should have been dumped into the first
741 * entry in the RX DMA ring. Grab it from there.
744 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
745 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
746 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
747 BUS_DMASYNC_POSTWRITE);
748 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
750 m0 = sc->re_ldata.re_rx_mbuf[0];
751 sc->re_ldata.re_rx_mbuf[0] = NULL;
752 eh = mtod(m0, struct ether_header *);
754 cur_rx = &sc->re_ldata.re_rx_list[0];
755 total_len = RE_RXBYTES(cur_rx);
756 rxstat = le32toh(cur_rx->re_cmdstat);
758 if (total_len != ETHER_MIN_LEN) {
759 if_printf(ifp, "diagnostic failed, received short packet\n");
764 /* Test that the received packet data matches what we sent. */
766 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
767 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
768 be16toh(eh->ether_type) != ETHERTYPE_IP) {
769 if_printf(ifp, "WARNING, DMA FAILURE!\n");
770 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
771 dst, ":", src, ":", ETHERTYPE_IP);
772 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
773 eh->ether_dhost, ":", eh->ether_shost, ":",
774 ntohs(eh->ether_type));
775 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
776 "into a 64-bit PCI slot.\n");
777 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
778 "for proper operation.\n");
779 if_printf(ifp, "Read the re(4) man page for more details.\n");
784 /* Turn interface off, release resources */
788 ifp->if_flags &= ~IFF_PROMISC;
798 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
799 * IDs against our list and return a device name if we find a match.
802 re_probe(device_t dev)
804 const struct re_type *t;
808 uint16_t vendor, product;
810 vendor = pci_get_vendor(dev);
811 product = pci_get_device(dev);
814 * Only attach to rev.3 of the Linksys EG1032 adapter.
815 * Rev.2 is supported by sk(4).
817 if (vendor == PCI_VENDOR_LINKSYS &&
818 product == PCI_PRODUCT_LINKSYS_EG1032 &&
819 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
822 for (t = re_devs; t->re_name != NULL; t++) {
823 if (product == t->re_did && vendor == t->re_vid)
828 * Check if we found a RealTek device.
830 if (t->re_name == NULL)
834 * Temporarily map the I/O space so we can read the chip ID register.
836 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
838 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
840 if (sc->re_res == NULL) {
841 device_printf(dev, "couldn't map ports/memory\n");
846 sc->re_btag = rman_get_bustag(sc->re_res);
847 sc->re_bhandle = rman_get_bushandle(sc->re_res);
849 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
850 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
854 * and continue matching for the specific chip...
856 for (; t->re_name != NULL; t++) {
857 if (product == t->re_did && vendor == t->re_vid &&
858 t->re_basetype == hwrev) {
859 device_set_desc(dev, t->re_name);
865 kprintf("re: unknown hwrev %#x\n", hwrev);
870 * This routine takes the segment list provided as the result of
871 * a bus_dma_map_load() operation and assigns the addresses/lengths
872 * to RealTek DMA descriptors. This can be called either by the RX
873 * code or the TX code. In the RX case, we'll probably wind up mapping
874 * at most one segment. For the TX case, there could be any number of
875 * segments since TX packets may span multiple mbufs. In either case,
876 * if the number of segments is larger than the re_maxsegs limit
877 * specified by the caller, we abort the mapping operation. Sadly,
878 * whoever designed the buffer mapping API did not provide a way to
879 * return an error from here, so we have to fake it a bit.
883 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
884 bus_size_t mapsize, int error)
886 struct re_dmaload_arg *ctx;
887 struct re_desc *d = NULL;
896 /* Signal error to caller if there's too many segments */
897 if (nseg > ctx->re_maxsegs) {
903 * Map the segment array into descriptors. Note that we set the
904 * start-of-frame and end-of-frame markers for either TX or RX, but
905 * they really only have meaning in the TX case. (In the RX case,
906 * it's the chip that tells us where packets begin and end.)
907 * We also keep track of the end of the ring and set the
908 * end-of-ring bits as needed, and we set the ownership bits
909 * in all except the very first descriptor. (The caller will
910 * set this descriptor later when it start transmission or
915 d = &ctx->re_ring[idx];
916 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
920 cmdstat = segs[i].ds_len;
921 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
922 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
924 cmdstat |= RE_TDESC_CMD_SOF;
926 cmdstat |= RE_TDESC_CMD_OWN;
927 if (idx == (RE_RX_DESC_CNT - 1))
928 cmdstat |= RE_TDESC_CMD_EOR;
929 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
936 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
937 ctx->re_maxsegs = nseg;
942 * Map a single buffer address.
946 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
953 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
955 *addr = segs->ds_addr;
959 re_allocmem(device_t dev, struct re_softc *sc)
964 * Allocate map for RX mbufs.
967 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
968 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
969 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
970 &sc->re_ldata.re_mtag);
972 device_printf(dev, "could not allocate dma tag\n");
977 * Allocate map for TX descriptor list.
979 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
980 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
981 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
982 &sc->re_ldata.re_tx_list_tag);
984 device_printf(dev, "could not allocate dma tag\n");
988 /* Allocate DMA'able memory for the TX ring */
990 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
991 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
992 &sc->re_ldata.re_tx_list_map);
994 device_printf(dev, "could not allocate TX ring\n");
998 /* Load the map for the TX ring. */
1000 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
1001 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
1002 RE_TX_LIST_SZ, re_dma_map_addr,
1003 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
1005 device_printf(dev, "could not get address of TX ring\n");
1009 /* Create DMA maps for TX buffers */
1011 for (i = 0; i < RE_TX_DESC_CNT; i++) {
1012 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1013 &sc->re_ldata.re_tx_dmamap[i]);
1015 device_printf(dev, "can't create DMA map for TX\n");
1021 * Allocate map for RX descriptor list.
1023 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
1024 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1025 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1026 &sc->re_ldata.re_rx_list_tag);
1028 device_printf(dev, "could not allocate dma tag\n");
1032 /* Allocate DMA'able memory for the RX ring */
1034 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1035 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1036 &sc->re_ldata.re_rx_list_map);
1038 device_printf(dev, "could not allocate RX ring\n");
1042 /* Load the map for the RX ring. */
1044 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1045 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
1046 RE_RX_LIST_SZ, re_dma_map_addr,
1047 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
1049 device_printf(dev, "could not get address of RX ring\n");
1053 /* Create DMA maps for RX buffers */
1055 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1056 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1057 &sc->re_ldata.re_rx_dmamap[i]);
1059 device_printf(dev, "can't create DMA map for RX\n");
1068 * Attach the interface. Allocate softc structures, do ifmedia
1069 * setup and ethernet/BPF attach.
1072 re_attach(device_t dev)
1074 struct re_softc *sc = device_get_softc(dev);
1076 const struct re_hwrev *hw_rev;
1077 uint8_t eaddr[ETHER_ADDR_LEN];
1078 uint16_t as[ETHER_ADDR_LEN / 2];
1079 uint16_t re_did = 0;
1081 int error = 0, rid, i;
1083 callout_init(&sc->re_timer);
1088 RE_ENABLE_TX_MODERATION(sc);
1090 sysctl_ctx_init(&sc->re_sysctl_ctx);
1091 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1092 SYSCTL_STATIC_CHILDREN(_hw),
1094 device_get_nameunit(dev),
1096 if (sc->re_sysctl_tree == NULL) {
1097 device_printf(dev, "can't add sysctl node\n");
1101 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1102 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1103 OID_AUTO, "tx_moderation",
1104 CTLTYPE_INT | CTLFLAG_RW,
1105 sc, 0, re_sysctl_tx_moderation, "I",
1106 "Enable/Disable TX moderation");
1108 #ifndef BURN_BRIDGES
1110 * Handle power management nonsense.
1113 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1114 uint32_t membase, irq;
1116 /* Save important PCI config data. */
1117 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1118 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1120 /* Reset the power state. */
1121 device_printf(dev, "chip is in D%d power mode "
1122 "-- setting to D0\n", pci_get_powerstate(dev));
1124 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1126 /* Restore PCI config data. */
1127 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1128 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1132 * Map control/status registers.
1134 pci_enable_busmaster(dev);
1137 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1140 if (sc->re_res == NULL) {
1141 device_printf(dev, "couldn't map ports\n");
1146 sc->re_btag = rman_get_bustag(sc->re_res);
1147 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1149 /* Allocate interrupt */
1151 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1152 RF_SHAREABLE | RF_ACTIVE);
1154 if (sc->re_irq == NULL) {
1155 device_printf(dev, "couldn't map interrupt\n");
1160 /* Reset the adapter. */
1163 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1164 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1165 if (hw_rev->re_rev == hwrev) {
1166 sc->re_type = hw_rev->re_type;
1167 sc->re_flags = hw_rev->re_flags;
1173 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1174 if (re_did != 0x8129)
1178 * Get station address from the EEPROM.
1180 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
1181 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1182 as[i] = le16toh(as[i]);
1183 bcopy(as, eaddr, sizeof(eaddr));
1185 if (sc->re_type == RE_8169) {
1186 /* Set RX length mask */
1187 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1188 sc->re_txstart = RE_GTXSTART;
1190 /* Set RX length mask */
1191 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1192 sc->re_txstart = RE_TXSTART;
1196 * Allocate the parent bus DMA tag appropriate for PCI.
1198 #define RE_NSEG_NEW 32
1199 error = bus_dma_tag_create(NULL, /* parent */
1200 1, 0, /* alignment, boundary */
1201 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1202 BUS_SPACE_MAXADDR, /* highaddr */
1203 NULL, NULL, /* filter, filterarg */
1204 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1205 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1206 BUS_DMA_ALLOCNOW, /* flags */
1207 &sc->re_parent_tag);
1211 error = re_allocmem(dev, sc);
1217 if (mii_phy_probe(dev, &sc->re_miibus,
1218 re_ifmedia_upd, re_ifmedia_sts)) {
1219 device_printf(dev, "MII without any phy!\n");
1224 ifp = &sc->arpcom.ac_if;
1226 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1227 ifp->if_mtu = ETHERMTU;
1228 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1229 ifp->if_ioctl = re_ioctl;
1230 ifp->if_start = re_start;
1231 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1234 case RE_HWREV_8168C:
1235 case RE_HWREV_8102EL:
1237 * XXX Hardware checksum does not work yet on 8168C
1238 * and 8102EL. Disble it.
1240 ifp->if_capabilities &= ~IFCAP_HWCSUM;
1243 ifp->if_capabilities |= IFCAP_HWCSUM;
1246 #ifdef DEVICE_POLLING
1247 ifp->if_poll = re_poll;
1249 ifp->if_watchdog = re_watchdog;
1250 ifp->if_init = re_init;
1251 if (sc->re_type == RE_8169)
1252 ifp->if_baudrate = 1000000000;
1254 ifp->if_baudrate = 100000000;
1255 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1256 ifq_set_ready(&ifp->if_snd);
1258 #ifdef RE_DISABLE_HWCSUM
1259 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1260 ifp->if_hwassist = 0;
1262 ifp->if_capenable = ifp->if_capabilities;
1263 if (ifp->if_capabilities & IFCAP_HWCSUM)
1264 ifp->if_hwassist = RE_CSUM_FEATURES;
1266 ifp->if_hwassist = 0;
1267 #endif /* RE_DISABLE_HWCSUM */
1270 * Call MI attach routine.
1272 ether_ifattach(ifp, eaddr, NULL);
1276 * Perform hardware diagnostic on the original RTL8169.
1277 * Some 32-bit cards were incorrectly wired and would
1278 * malfunction if plugged into a 64-bit slot.
1280 if (hwrev == RE_HWREV_8169) {
1281 lwkt_serialize_enter(ifp->if_serializer);
1282 error = re_diag(sc);
1283 lwkt_serialize_exit(ifp->if_serializer);
1286 device_printf(dev, "hardware diagnostic failure\n");
1287 ether_ifdetach(ifp);
1291 #endif /* RE_DIAG */
1293 /* Hook interrupt last to avoid having to lock softc */
1294 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1295 &sc->re_intrhand, ifp->if_serializer);
1298 device_printf(dev, "couldn't set up irq\n");
1299 ether_ifdetach(ifp);
1303 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq));
1304 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1314 * Shutdown hardware and free up resources. This can be called any
1315 * time after the mutex has been initialized. It is called in both
1316 * the error case in attach and the normal detach case so it needs
1317 * to be careful about only freeing resources that have actually been
1321 re_detach(device_t dev)
1323 struct re_softc *sc = device_get_softc(dev);
1324 struct ifnet *ifp = &sc->arpcom.ac_if;
1327 /* These should only be active if attach succeeded */
1328 if (device_is_attached(dev)) {
1329 lwkt_serialize_enter(ifp->if_serializer);
1331 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1332 lwkt_serialize_exit(ifp->if_serializer);
1334 ether_ifdetach(ifp);
1337 device_delete_child(dev, sc->re_miibus);
1338 bus_generic_detach(dev);
1341 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1343 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1347 /* Unload and free the RX DMA ring memory and map */
1349 if (sc->re_ldata.re_rx_list_tag) {
1350 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1351 sc->re_ldata.re_rx_list_map);
1352 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1353 sc->re_ldata.re_rx_list,
1354 sc->re_ldata.re_rx_list_map);
1355 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1358 /* Unload and free the TX DMA ring memory and map */
1360 if (sc->re_ldata.re_tx_list_tag) {
1361 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1362 sc->re_ldata.re_tx_list_map);
1363 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1364 sc->re_ldata.re_tx_list,
1365 sc->re_ldata.re_tx_list_map);
1366 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1369 /* Destroy all the RX and TX buffer maps */
1371 if (sc->re_ldata.re_mtag) {
1372 for (i = 0; i < RE_TX_DESC_CNT; i++)
1373 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1374 sc->re_ldata.re_tx_dmamap[i]);
1375 for (i = 0; i < RE_RX_DESC_CNT; i++)
1376 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1377 sc->re_ldata.re_rx_dmamap[i]);
1378 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1381 /* Unload and free the stats buffer and map */
1383 if (sc->re_ldata.re_stag) {
1384 bus_dmamap_unload(sc->re_ldata.re_stag,
1385 sc->re_ldata.re_rx_list_map);
1386 bus_dmamem_free(sc->re_ldata.re_stag,
1387 sc->re_ldata.re_stats,
1388 sc->re_ldata.re_smap);
1389 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1392 if (sc->re_parent_tag)
1393 bus_dma_tag_destroy(sc->re_parent_tag);
1399 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1401 struct re_dmaload_arg arg;
1402 struct mbuf *n = NULL;
1406 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1411 m->m_data = m->m_ext.ext_buf;
1413 m->m_len = m->m_pkthdr.len = MCLBYTES;
1417 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1418 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1425 arg.re_ring = sc->re_ldata.re_rx_list;
1427 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1428 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1429 &arg, BUS_DMA_NOWAIT);
1430 if (error || arg.re_maxsegs != 1) {
1436 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1437 sc->re_ldata.re_rx_mbuf[idx] = m;
1439 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1440 BUS_DMASYNC_PREREAD);
1446 re_tx_list_init(struct re_softc *sc)
1448 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1449 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1451 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1452 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1453 sc->re_ldata.re_tx_prodidx = 0;
1454 sc->re_ldata.re_tx_considx = 0;
1455 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1461 re_rx_list_init(struct re_softc *sc)
1465 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1466 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1468 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1469 error = re_newbuf(sc, i, NULL);
1474 /* Flush the RX descriptors */
1476 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1477 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1479 sc->re_ldata.re_rx_prodidx = 0;
1480 sc->re_head = sc->re_tail = NULL;
1486 * RX handler for C+ and 8169. For the gigE chips, we support
1487 * the reception of jumbo frames that have been fragmented
1488 * across multiple 2K mbuf cluster buffers.
1491 re_rxeof(struct re_softc *sc)
1493 struct ifnet *ifp = &sc->arpcom.ac_if;
1495 struct re_desc *cur_rx;
1496 uint32_t rxstat, rxvlan;
1498 struct mbuf_chain chain[MAXCPU];
1500 /* Invalidate the descriptor memory */
1502 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1503 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1505 ether_input_chain_init(chain);
1507 for (i = sc->re_ldata.re_rx_prodidx;
1508 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1509 cur_rx = &sc->re_ldata.re_rx_list[i];
1510 m = sc->re_ldata.re_rx_mbuf[i];
1511 total_len = RE_RXBYTES(cur_rx);
1512 rxstat = le32toh(cur_rx->re_cmdstat);
1513 rxvlan = le32toh(cur_rx->re_vlanctl);
1515 /* Invalidate the RX mbuf and unload its map */
1517 bus_dmamap_sync(sc->re_ldata.re_mtag,
1518 sc->re_ldata.re_rx_dmamap[i],
1519 BUS_DMASYNC_POSTWRITE);
1520 bus_dmamap_unload(sc->re_ldata.re_mtag,
1521 sc->re_ldata.re_rx_dmamap[i]);
1523 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1524 m->m_len = MCLBYTES - ETHER_ALIGN;
1525 if (sc->re_head == NULL) {
1526 sc->re_head = sc->re_tail = m;
1528 sc->re_tail->m_next = m;
1531 re_newbuf(sc, i, NULL);
1536 * NOTE: for the 8139C+, the frame length field
1537 * is always 12 bits in size, but for the gigE chips,
1538 * it is 13 bits (since the max RX frame length is 16K).
1539 * Unfortunately, all 32 bits in the status word
1540 * were already used, so to make room for the extra
1541 * length bit, RealTek took out the 'frame alignment
1542 * error' bit and shifted the other status bits
1543 * over one slot. The OWN, EOR, FS and LS bits are
1544 * still in the same places. We have already extracted
1545 * the frame length and checked the OWN bit, so rather
1546 * than using an alternate bit mapping, we shift the
1547 * status bits one space to the right so we can evaluate
1548 * them using the 8169 status as though it was in the
1549 * same format as that of the 8139C+.
1551 if (sc->re_type == RE_8169)
1554 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1557 * If this is part of a multi-fragment packet,
1558 * discard all the pieces.
1560 if (sc->re_head != NULL) {
1561 m_freem(sc->re_head);
1562 sc->re_head = sc->re_tail = NULL;
1564 re_newbuf(sc, i, m);
1569 * If allocating a replacement mbuf fails,
1570 * reload the current one.
1573 if (re_newbuf(sc, i, NULL)) {
1575 if (sc->re_head != NULL) {
1576 m_freem(sc->re_head);
1577 sc->re_head = sc->re_tail = NULL;
1579 re_newbuf(sc, i, m);
1583 if (sc->re_head != NULL) {
1584 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1586 * Special case: if there's 4 bytes or less
1587 * in this buffer, the mbuf can be discarded:
1588 * the last 4 bytes is the CRC, which we don't
1589 * care about anyway.
1591 if (m->m_len <= ETHER_CRC_LEN) {
1592 sc->re_tail->m_len -=
1593 (ETHER_CRC_LEN - m->m_len);
1596 m->m_len -= ETHER_CRC_LEN;
1597 sc->re_tail->m_next = m;
1600 sc->re_head = sc->re_tail = NULL;
1601 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1603 m->m_pkthdr.len = m->m_len =
1604 (total_len - ETHER_CRC_LEN);
1607 m->m_pkthdr.rcvif = ifp;
1609 /* Do RX checksumming if enabled */
1611 if (ifp->if_capenable & IFCAP_RXCSUM) {
1613 /* Check IP header checksum */
1614 if (rxstat & RE_RDESC_STAT_PROTOID)
1615 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1616 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1617 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1619 /* Check TCP/UDP checksum */
1620 if ((RE_TCPPKT(rxstat) &&
1621 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1622 (RE_UDPPKT(rxstat) &&
1623 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1624 m->m_pkthdr.csum_flags |=
1625 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1626 CSUM_FRAG_NOT_CHECKED;
1627 m->m_pkthdr.csum_data = 0xffff;
1631 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1632 m->m_flags |= M_VLANTAG;
1633 m->m_pkthdr.ether_vlantag =
1634 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA));
1636 ether_input_chain(ifp, m, chain);
1639 ether_input_dispatch(chain);
1641 /* Flush the RX DMA ring */
1643 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1644 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1646 sc->re_ldata.re_rx_prodidx = i;
1650 re_txeof(struct re_softc *sc)
1652 struct ifnet *ifp = &sc->arpcom.ac_if;
1656 /* Invalidate the TX descriptor list */
1658 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1659 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
1661 for (idx = sc->re_ldata.re_tx_considx;
1662 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) {
1663 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1664 if (txstat & RE_TDESC_CMD_OWN)
1667 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
1670 * We only stash mbufs in the last descriptor
1671 * in a fragment chain, which also happens to
1672 * be the only place where the TX status bits
1675 if (txstat & RE_TDESC_CMD_EOF) {
1676 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1677 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1678 bus_dmamap_unload(sc->re_ldata.re_mtag,
1679 sc->re_ldata.re_tx_dmamap[idx]);
1680 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1681 RE_TDESC_STAT_COLCNT))
1682 ifp->if_collisions++;
1683 if (txstat & RE_TDESC_STAT_TXERRSUM)
1688 sc->re_ldata.re_tx_free++;
1691 /* No changes made to the TX ring, so no flush needed */
1692 if (sc->re_ldata.re_tx_free) {
1693 sc->re_ldata.re_tx_considx = idx;
1694 ifp->if_flags &= ~IFF_OACTIVE;
1699 * Some chips will ignore a second TX request issued while an
1700 * existing transmission is in progress. If the transmitter goes
1701 * idle but there are still packets waiting to be sent, we need
1702 * to restart the channel here to flush them out. This only seems
1703 * to be required with the PCIe devices.
1705 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1706 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
1709 * If not all descriptors have been released reaped yet,
1710 * reload the timer so that we will eventually get another
1711 * interrupt that will cause us to re-enter this routine.
1712 * This is done in case the transmitter has gone idle.
1714 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
1715 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1716 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1722 struct re_softc *sc = xsc;
1724 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1725 re_tick_serialized(xsc);
1726 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1730 re_tick_serialized(void *xsc)
1732 struct re_softc *sc = xsc;
1733 struct ifnet *ifp = &sc->arpcom.ac_if;
1734 struct mii_data *mii;
1736 ASSERT_SERIALIZED(ifp->if_serializer);
1738 mii = device_get_softc(sc->re_miibus);
1741 if (!(mii->mii_media_status & IFM_ACTIVE))
1744 if (mii->mii_media_status & IFM_ACTIVE &&
1745 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1747 if (!ifq_is_empty(&ifp->if_snd))
1752 callout_reset(&sc->re_timer, hz, re_tick, sc);
1755 #ifdef DEVICE_POLLING
1758 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1760 struct re_softc *sc = ifp->if_softc;
1762 ASSERT_SERIALIZED(ifp->if_serializer);
1766 /* disable interrupts */
1767 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1769 case POLL_DEREGISTER:
1770 /* enable interrupts */
1771 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1774 sc->rxcycles = count;
1778 if (!ifq_is_empty(&ifp->if_snd))
1781 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1784 status = CSR_READ_2(sc, RE_ISR);
1785 if (status == 0xffff)
1788 CSR_WRITE_2(sc, RE_ISR, status);
1791 * XXX check behaviour on receiver stalls.
1794 if (status & RE_ISR_SYSTEM_ERR) {
1802 #endif /* DEVICE_POLLING */
1807 struct re_softc *sc = arg;
1808 struct ifnet *ifp = &sc->arpcom.ac_if;
1811 ASSERT_SERIALIZED(ifp->if_serializer);
1813 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1817 status = CSR_READ_2(sc, RE_ISR);
1818 /* If the card has gone away the read returns 0xffff. */
1819 if (status == 0xffff)
1822 CSR_WRITE_2(sc, RE_ISR, status);
1824 if ((status & sc->re_intrs) == 0)
1827 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW))
1830 if ((status & sc->re_tx_ack) ||
1831 (status & RE_ISR_TX_ERR) ||
1832 (status & RE_ISR_TX_DESC_UNAVAIL))
1835 if (status & RE_ISR_SYSTEM_ERR) {
1840 if (status & RE_ISR_LINKCHG) {
1841 callout_stop(&sc->re_timer);
1842 re_tick_serialized(sc);
1846 if (!ifq_is_empty(&ifp->if_snd))
1851 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1853 struct ifnet *ifp = &sc->arpcom.ac_if;
1854 struct mbuf *m, *m_new = NULL;
1855 struct re_dmaload_arg arg;
1859 KASSERT(sc->re_ldata.re_tx_free > 4, ("not enough free TX desc\n"));
1865 * Set up checksum offload. Note: checksum offload bits must
1866 * appear in all descriptors of a multi-descriptor transmit
1867 * attempt. (This is according to testing done with an 8169
1868 * chip. I'm not sure if this is a requirement or a bug.)
1873 if (m->m_pkthdr.csum_flags & CSUM_IP)
1874 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1875 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1876 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1877 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1878 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1882 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1883 if (arg.re_maxsegs > 4)
1884 arg.re_maxsegs -= 4;
1885 arg.re_ring = sc->re_ldata.re_tx_list;
1887 map = sc->re_ldata.re_tx_dmamap[*idx];
1890 * With some of the RealTek chips, using the checksum offload
1891 * support in conjunction with the autopadding feature results
1892 * in the transmission of corrupt frames. For example, if we
1893 * need to send a really small IP fragment that's less than 60
1894 * bytes in size, and IP header checksumming is enabled, the
1895 * resulting ethernet frame that appears on the wire will
1896 * have garbled payload. To work around this, if TX checksum
1897 * offload is enabled, we always manually pad short frames out
1898 * to the minimum ethernet frame size. We do this by pretending
1899 * the mbuf chain has too many fragments so the coalescing code
1900 * below can assemble the packet into a single buffer that's
1901 * padded out to the mininum frame size.
1903 * Note: this appears unnecessary for TCP, and doing it for TCP
1904 * with PCIe adapters seems to result in bad checksums.
1906 if (arg.re_flags && !(arg.re_flags & RE_TDESC_CMD_TCPCSUM) &&
1907 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
1910 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1911 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1914 if (error && error != EFBIG) {
1915 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1919 /* Too many segments to map, coalesce into a single mbuf */
1921 if (error || arg.re_maxsegs == 0) {
1922 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1923 if (m_new == NULL) {
1931 * Manually pad short frames, and zero the pad space
1932 * to avoid leaking data.
1934 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) {
1935 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
1936 RE_MIN_FRAMELEN - m_new->m_pkthdr.len);
1937 m_new->m_pkthdr.len += RE_MIN_FRAMELEN -
1938 m_new->m_pkthdr.len;
1939 m_new->m_len = m_new->m_pkthdr.len;
1945 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1946 arg.re_ring = sc->re_ldata.re_tx_list;
1948 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1949 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1952 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1958 * Insure that the map for this transmission
1959 * is placed at the array index of the last descriptor
1962 sc->re_ldata.re_tx_dmamap[*idx] =
1963 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1964 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1966 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1967 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1970 * Set up hardware VLAN tagging. Note: vlan tag info must
1971 * appear in the first descriptor of a multi-descriptor
1972 * transmission attempt.
1975 if (m->m_flags & M_VLANTAG) {
1976 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1977 htole32(htobe16(m->m_pkthdr.ether_vlantag) |
1978 RE_TDESC_VLANCTL_TAG);
1981 /* Transfer ownership of packet to the chip. */
1983 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1984 htole32(RE_TDESC_CMD_OWN);
1985 if (*idx != arg.re_idx)
1986 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1987 htole32(RE_TDESC_CMD_OWN);
1989 RE_DESC_INC(arg.re_idx);
1996 * Main transmit routine for C+ and gigE NICs.
2000 re_start(struct ifnet *ifp)
2002 struct re_softc *sc = ifp->if_softc;
2003 struct mbuf *m_head;
2004 struct mbuf *m_head2;
2005 int called_defrag, idx, need_trans;
2007 ASSERT_SERIALIZED(ifp->if_serializer);
2010 ifq_purge(&ifp->if_snd);
2014 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2017 idx = sc->re_ldata.re_tx_prodidx;
2020 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2021 if (sc->re_ldata.re_tx_free <= 4) {
2022 ifp->if_flags |= IFF_OACTIVE;
2026 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2031 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
2033 * If we could not encapsulate the defragged packet,
2034 * the returned m_head2 is garbage and we must dequeue
2035 * and throw away the original packet.
2039 ifp->if_flags |= IFF_OACTIVE;
2044 * Clean out the packet we encapsulated. If we defragged
2045 * the packet the m_head2 is the one that got encapsulated
2046 * and the original must be thrown away. Otherwise m_head2
2047 * *IS* the original.
2054 * If there's a BPF listener, bounce a copy of this frame
2057 ETHER_BPF_MTAP(ifp, m_head2);
2061 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
2062 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
2063 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2067 /* Flush the TX descriptors */
2068 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2069 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2071 sc->re_ldata.re_tx_prodidx = idx;
2074 * RealTek put the TX poll request register in a different
2075 * location on the 8169 gigE chip. I don't know why.
2077 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2079 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2081 * Use the countdown timer for interrupt moderation.
2082 * 'TX done' interrupts are disabled. Instead, we reset the
2083 * countdown timer, which will begin counting until it hits
2084 * the value in the TIMERINT register, and then trigger an
2085 * interrupt. Each time we write to the TIMERCNT register,
2086 * the timer count is reset to 0.
2088 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2092 * Set a timeout in case the chip goes out to lunch.
2100 struct re_softc *sc = xsc;
2101 struct ifnet *ifp = &sc->arpcom.ac_if;
2102 struct mii_data *mii;
2105 ASSERT_SERIALIZED(ifp->if_serializer);
2107 mii = device_get_softc(sc->re_miibus);
2110 * Cancel pending I/O and free all RX/TX buffers.
2115 * Enable C+ RX and TX mode, as well as VLAN stripping and
2116 * RX checksum offload. We must configure the C+ register
2117 * before all others.
2119 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2120 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
2121 (ifp->if_capenable & IFCAP_RXCSUM ?
2122 RE_CPLUSCMD_RXCSUM_ENB : 0));
2125 * Init our MAC address. Even though the chipset
2126 * documentation doesn't mention it, we need to enter "Config
2127 * register write enable" mode to modify the ID registers.
2129 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2130 CSR_WRITE_4(sc, RE_IDR0,
2131 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2132 CSR_WRITE_2(sc, RE_IDR4,
2133 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2134 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2137 * For C+ mode, initialize the RX descriptors and mbufs.
2139 re_rx_list_init(sc);
2140 re_tx_list_init(sc);
2143 * Load the addresses of the RX and TX lists into the chip.
2145 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2146 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2147 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2148 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2150 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2151 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2152 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2153 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2156 * Enable transmit and receive.
2158 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2161 * Set the initial TX and RX configuration.
2163 if (sc->re_testmode) {
2164 if (sc->re_type == RE_8169)
2165 CSR_WRITE_4(sc, RE_TXCFG,
2166 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2168 CSR_WRITE_4(sc, RE_TXCFG,
2169 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2171 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2173 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2175 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2177 /* Set the individual bit to receive frames for this host only. */
2178 rxcfg = CSR_READ_4(sc, RE_RXCFG);
2179 rxcfg |= RE_RXCFG_RX_INDIV;
2181 /* If we want promiscuous mode, set the allframes bit. */
2182 if (ifp->if_flags & IFF_PROMISC) {
2183 rxcfg |= RE_RXCFG_RX_ALLPHYS;
2184 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2186 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
2187 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2191 * Set capture broadcast bit to capture broadcast frames.
2193 if (ifp->if_flags & IFF_BROADCAST) {
2194 rxcfg |= RE_RXCFG_RX_BROAD;
2195 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2197 rxcfg &= ~RE_RXCFG_RX_BROAD;
2198 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2202 * Program the multicast filter, if necessary.
2206 #ifdef DEVICE_POLLING
2208 * Disable interrupts if we are polling.
2210 if (ifp->if_flags & IFF_POLLING)
2211 CSR_WRITE_2(sc, RE_IMR, 0);
2212 else /* otherwise ... */
2213 #endif /* DEVICE_POLLING */
2215 * Enable interrupts.
2217 if (sc->re_testmode)
2218 CSR_WRITE_2(sc, RE_IMR, 0);
2220 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2221 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2223 /* Set initial TX threshold */
2224 sc->re_txthresh = RE_TX_THRESH_INIT;
2226 /* Start RX/TX process. */
2227 if (sc->re_flags & RE_F_HASMPC)
2228 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2230 /* Enable receiver and transmitter. */
2231 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2234 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2236 * Initialize the timer interrupt register so that
2237 * a timer interrupt will be generated once the timer
2238 * reaches a certain number of ticks. The timer is
2239 * reloaded on each transmit. This gives us TX interrupt
2240 * moderation, which dramatically improves TX frame rate.
2242 if (sc->re_type == RE_8169)
2243 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2245 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2249 * For 8169 gigE NICs, set the max allowed RX packet
2250 * size so we can receive jumbo frames.
2252 if (sc->re_type == RE_8169)
2253 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2255 if (sc->re_testmode) {
2261 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2263 ifp->if_flags |= IFF_RUNNING;
2264 ifp->if_flags &= ~IFF_OACTIVE;
2267 callout_reset(&sc->re_timer, hz, re_tick, sc);
2271 * Set media options.
2274 re_ifmedia_upd(struct ifnet *ifp)
2276 struct re_softc *sc = ifp->if_softc;
2277 struct mii_data *mii;
2279 ASSERT_SERIALIZED(ifp->if_serializer);
2281 mii = device_get_softc(sc->re_miibus);
2288 * Report current media status.
2291 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2293 struct re_softc *sc = ifp->if_softc;
2294 struct mii_data *mii;
2296 ASSERT_SERIALIZED(ifp->if_serializer);
2298 mii = device_get_softc(sc->re_miibus);
2301 ifmr->ifm_active = mii->mii_media_active;
2302 ifmr->ifm_status = mii->mii_media_status;
2306 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2308 struct re_softc *sc = ifp->if_softc;
2309 struct ifreq *ifr = (struct ifreq *) data;
2310 struct mii_data *mii;
2313 ASSERT_SERIALIZED(ifp->if_serializer);
2317 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2319 ifp->if_mtu = ifr->ifr_mtu;
2322 if (ifp->if_flags & IFF_UP)
2324 else if (ifp->if_flags & IFF_RUNNING)
2334 mii = device_get_softc(sc->re_miibus);
2335 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2338 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2339 ifp->if_capenable |=
2340 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2341 if (ifp->if_capenable & IFCAP_TXCSUM)
2342 ifp->if_hwassist = RE_CSUM_FEATURES;
2344 ifp->if_hwassist = 0;
2345 if (ifp->if_flags & IFF_RUNNING)
2349 error = ether_ioctl(ifp, command, data);
2356 re_watchdog(struct ifnet *ifp)
2358 struct re_softc *sc = ifp->if_softc;
2360 ASSERT_SERIALIZED(ifp->if_serializer);
2362 if_printf(ifp, "watchdog timeout\n");
2371 if (!ifq_is_empty(&ifp->if_snd))
2376 * Stop the adapter and free any mbufs allocated to the
2380 re_stop(struct re_softc *sc)
2382 struct ifnet *ifp = &sc->arpcom.ac_if;
2385 ASSERT_SERIALIZED(ifp->if_serializer);
2388 callout_stop(&sc->re_timer);
2390 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2392 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2393 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2394 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2396 if (sc->re_head != NULL) {
2397 m_freem(sc->re_head);
2398 sc->re_head = sc->re_tail = NULL;
2401 /* Free the TX list buffers. */
2402 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2403 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2404 bus_dmamap_unload(sc->re_ldata.re_mtag,
2405 sc->re_ldata.re_tx_dmamap[i]);
2406 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2407 sc->re_ldata.re_tx_mbuf[i] = NULL;
2411 /* Free the RX list buffers. */
2412 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2413 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2414 bus_dmamap_unload(sc->re_ldata.re_mtag,
2415 sc->re_ldata.re_rx_dmamap[i]);
2416 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2417 sc->re_ldata.re_rx_mbuf[i] = NULL;
2423 * Device suspend routine. Stop the interface and save some PCI
2424 * settings in case the BIOS doesn't restore them properly on
2428 re_suspend(device_t dev)
2430 #ifndef BURN_BRIDGES
2433 struct re_softc *sc = device_get_softc(dev);
2434 struct ifnet *ifp = &sc->arpcom.ac_if;
2436 lwkt_serialize_enter(ifp->if_serializer);
2440 #ifndef BURN_BRIDGES
2441 for (i = 0; i < 5; i++)
2442 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2443 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2444 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2445 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2446 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2451 lwkt_serialize_exit(ifp->if_serializer);
2457 * Device resume routine. Restore some PCI settings in case the BIOS
2458 * doesn't, re-enable busmastering, and restart the interface if
2462 re_resume(device_t dev)
2464 struct re_softc *sc = device_get_softc(dev);
2465 struct ifnet *ifp = &sc->arpcom.ac_if;
2466 #ifndef BURN_BRIDGES
2470 lwkt_serialize_enter(ifp->if_serializer);
2472 #ifndef BURN_BRIDGES
2473 /* better way to do this? */
2474 for (i = 0; i < 5; i++)
2475 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2476 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2477 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2478 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2479 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2481 /* reenable busmastering */
2482 pci_enable_busmaster(dev);
2483 pci_enable_io(dev, SYS_RES_IOPORT);
2486 /* reinitialize interface if necessary */
2487 if (ifp->if_flags & IFF_UP)
2492 lwkt_serialize_exit(ifp->if_serializer);
2498 * Stop all chip I/O so that the kernel's probe routines don't
2499 * get confused by errant DMAs when rebooting.
2502 re_shutdown(device_t dev)
2504 struct re_softc *sc = device_get_softc(dev);
2505 struct ifnet *ifp = &sc->arpcom.ac_if;
2507 lwkt_serialize_enter(ifp->if_serializer);
2509 lwkt_serialize_exit(ifp->if_serializer);
2513 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS)
2515 struct re_softc *sc = arg1;
2516 struct ifnet *ifp = &sc->arpcom.ac_if;
2517 int error = 0, mod, mod_old;
2519 lwkt_serialize_enter(ifp->if_serializer);
2521 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc);
2523 error = sysctl_handle_int(oidp, &mod, 0, req);
2524 if (error || req->newptr == NULL || mod == mod_old)
2526 if (mod != 0 && mod != 1) {
2532 RE_ENABLE_TX_MODERATION(sc);
2534 RE_DISABLE_TX_MODERATION(sc);
2536 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP))
2539 lwkt_serialize_exit(ifp->if_serializer);