1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.28 2008/06/27 17:03:40 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
59 #include "opt_ethernet.h"
61 #include <sys/param.h>
62 #include <sys/endian.h>
63 #include <sys/kernel.h>
65 #include <sys/interrupt.h>
68 #include <sys/serialize.h>
69 #include <sys/socket.h>
70 #include <sys/sockio.h>
71 #include <sys/sysctl.h>
73 #include <net/ethernet.h>
76 #include <net/if_arp.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/ifq_var.h>
80 #include <net/if_types.h>
81 #include <net/if_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include "miibus_if.h"
94 #include <dev/netif/nfe/if_nfereg.h>
95 #include <dev/netif/nfe/if_nfevar.h>
98 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
100 static int nfe_probe(device_t);
101 static int nfe_attach(device_t);
102 static int nfe_detach(device_t);
103 static void nfe_shutdown(device_t);
104 static int nfe_resume(device_t);
105 static int nfe_suspend(device_t);
107 static int nfe_miibus_readreg(device_t, int, int);
108 static void nfe_miibus_writereg(device_t, int, int, int);
109 static void nfe_miibus_statchg(device_t);
111 #ifdef DEVICE_POLLING
112 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static void nfe_rxeof(struct nfe_softc *);
117 static void nfe_txeof(struct nfe_softc *);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_powerup(device_t);
143 static void nfe_mac_reset(struct nfe_softc *);
144 static void nfe_tick(void *);
145 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
146 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
148 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
150 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
152 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
154 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
157 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
162 static int nfe_debug = 0;
163 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
164 static int nfe_imtime = -1;
166 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
167 TUNABLE_INT("hw.nfe.imtime", &nfe_imtime);
168 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
170 #define DPRINTF(sc, fmt, ...) do { \
171 if ((sc)->sc_debug) { \
172 if_printf(&(sc)->arpcom.ac_if, \
177 #define DPRINTFN(sc, lv, fmt, ...) do { \
178 if ((sc)->sc_debug >= (lv)) { \
179 if_printf(&(sc)->arpcom.ac_if, \
184 #else /* !NFE_DEBUG */
186 #define DPRINTF(sc, fmt, ...)
187 #define DPRINTFN(sc, lv, fmt, ...)
189 #endif /* NFE_DEBUG */
193 bus_dma_segment_t *segs;
196 static const struct nfe_dev {
201 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
202 "NVIDIA nForce Fast Ethernet" },
204 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
205 "NVIDIA nForce2 Fast Ethernet" },
207 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
208 "NVIDIA nForce3 Gigabit Ethernet" },
210 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
211 chipset, and possibly also the 400R; it might be both nForce2- and
212 nForce3-based boards can use the same MCPs (= southbridges) */
213 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
214 "NVIDIA nForce3 Gigabit Ethernet" },
216 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
217 "NVIDIA nForce3 Gigabit Ethernet" },
219 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
220 "NVIDIA nForce3 Gigabit Ethernet" },
222 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
223 "NVIDIA nForce3 Gigabit Ethernet" },
225 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
226 "NVIDIA CK804 Gigabit Ethernet" },
228 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
229 "NVIDIA CK804 Gigabit Ethernet" },
231 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
232 "NVIDIA MCP04 Gigabit Ethernet" },
234 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
235 "NVIDIA MCP04 Gigabit Ethernet" },
237 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
238 "NVIDIA MCP51 Gigabit Ethernet" },
240 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
241 "NVIDIA MCP51 Gigabit Ethernet" },
243 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
244 "NVIDIA MCP55 Gigabit Ethernet" },
246 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
247 "NVIDIA MCP55 Gigabit Ethernet" },
249 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
250 "NVIDIA MCP61 Gigabit Ethernet" },
252 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
253 "NVIDIA MCP61 Gigabit Ethernet" },
255 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
256 "NVIDIA MCP61 Gigabit Ethernet" },
258 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
259 "NVIDIA MCP61 Gigabit Ethernet" },
261 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
262 "NVIDIA MCP65 Gigabit Ethernet" },
264 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
265 "NVIDIA MCP65 Gigabit Ethernet" },
267 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
268 "NVIDIA MCP65 Gigabit Ethernet" },
270 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
271 "NVIDIA MCP65 Gigabit Ethernet" },
273 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
274 "NVIDIA MCP67 Gigabit Ethernet" },
276 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
277 "NVIDIA MCP67 Gigabit Ethernet" },
279 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
280 "NVIDIA MCP67 Gigabit Ethernet" },
282 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
283 "NVIDIA MCP67 Gigabit Ethernet" },
285 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
286 "NVIDIA MCP73 Gigabit Ethernet" },
288 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
289 "NVIDIA MCP73 Gigabit Ethernet" },
291 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
292 "NVIDIA MCP73 Gigabit Ethernet" },
294 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
295 "NVIDIA MCP73 Gigabit Ethernet" },
297 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
298 "NVIDIA MCP77 Gigabit Ethernet" },
300 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
301 "NVIDIA MCP77 Gigabit Ethernet" },
303 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
304 "NVIDIA MCP77 Gigabit Ethernet" },
306 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
307 "NVIDIA MCP77 Gigabit Ethernet" },
309 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
310 "NVIDIA MCP79 Gigabit Ethernet" },
312 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
313 "NVIDIA MCP79 Gigabit Ethernet" },
315 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
316 "NVIDIA MCP79 Gigabit Ethernet" },
318 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
319 "NVIDIA MCP79 Gigabit Ethernet" },
324 static device_method_t nfe_methods[] = {
325 /* Device interface */
326 DEVMETHOD(device_probe, nfe_probe),
327 DEVMETHOD(device_attach, nfe_attach),
328 DEVMETHOD(device_detach, nfe_detach),
329 DEVMETHOD(device_suspend, nfe_suspend),
330 DEVMETHOD(device_resume, nfe_resume),
331 DEVMETHOD(device_shutdown, nfe_shutdown),
334 DEVMETHOD(bus_print_child, bus_generic_print_child),
335 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
338 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
339 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
340 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
345 static driver_t nfe_driver = {
348 sizeof(struct nfe_softc)
351 static devclass_t nfe_devclass;
353 DECLARE_DUMMY_MODULE(if_nfe);
354 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
355 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
356 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
359 nfe_probe(device_t dev)
361 const struct nfe_dev *n;
364 vid = pci_get_vendor(dev);
365 did = pci_get_device(dev);
366 for (n = nfe_devices; n->desc != NULL; ++n) {
367 if (vid == n->vid && did == n->did) {
368 struct nfe_softc *sc = device_get_softc(dev);
371 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
372 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
373 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
374 sc->sc_flags = NFE_NO_PWRCTL;
376 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
377 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
378 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
379 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
380 sc->sc_flags = NFE_JUMBO_SUP |
384 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
385 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
386 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
387 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
388 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
389 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
390 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
391 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
392 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
393 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
394 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
395 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
396 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
397 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
398 sc->sc_flags = NFE_40BIT_ADDR;
400 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
401 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
402 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
403 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
404 sc->sc_flags = NFE_JUMBO_SUP |
409 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
410 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
411 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
412 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
413 sc->sc_flags = NFE_JUMBO_SUP |
416 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
417 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
418 sc->sc_flags = NFE_JUMBO_SUP |
423 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
424 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
425 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
426 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
427 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
428 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
429 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
430 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
431 sc->sc_flags = NFE_40BIT_ADDR |
436 device_set_desc(dev, n->desc);
437 device_set_async_attach(dev, TRUE);
445 nfe_attach(device_t dev)
447 struct nfe_softc *sc = device_get_softc(dev);
448 struct ifnet *ifp = &sc->arpcom.ac_if;
449 uint8_t eaddr[ETHER_ADDR_LEN];
452 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
453 lwkt_serialize_init(&sc->sc_jbuf_serializer);
456 * Initialize sysctl variables
458 sc->sc_imtime = nfe_imtime;
459 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
460 sc->sc_rx_ring_count = nfe_rx_ring_count;
461 sc->sc_debug = nfe_debug;
463 sc->sc_mem_rid = PCIR_BAR(0);
465 if (sc->sc_flags & NFE_40BIT_ADDR)
466 sc->rxtxctl_desc = NFE_RXTX_DESC_V3;
467 else if (sc->sc_flags & NFE_JUMBO_SUP)
468 sc->rxtxctl_desc = NFE_RXTX_DESC_V2;
471 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
474 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
475 irq = pci_read_config(dev, PCIR_INTLINE, 4);
477 device_printf(dev, "chip is in D%d power mode "
478 "-- setting to D0\n", pci_get_powerstate(dev));
480 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
482 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
483 pci_write_config(dev, PCIR_INTLINE, irq, 4);
485 #endif /* !BURN_BRIDGE */
487 /* Enable bus mastering */
488 pci_enable_busmaster(dev);
490 /* Allocate IO memory */
491 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
492 &sc->sc_mem_rid, RF_ACTIVE);
493 if (sc->sc_mem_res == NULL) {
494 device_printf(dev, "cound not allocate io memory\n");
497 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
498 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
502 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
504 RF_SHAREABLE | RF_ACTIVE);
505 if (sc->sc_irq_res == NULL) {
506 device_printf(dev, "could not allocate irq\n");
512 NFE_WRITE(sc, NFE_WOL_CTL, 0);
514 if ((sc->sc_flags & NFE_NO_PWRCTL) == 0)
517 nfe_get_macaddr(sc, eaddr);
520 * Allocate Tx and Rx rings.
522 error = nfe_alloc_tx_ring(sc, &sc->txq);
524 device_printf(dev, "could not allocate Tx ring\n");
528 error = nfe_alloc_rx_ring(sc, &sc->rxq);
530 device_printf(dev, "could not allocate Rx ring\n");
537 sysctl_ctx_init(&sc->sc_sysctl_ctx);
538 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
539 SYSCTL_STATIC_CHILDREN(_hw),
541 device_get_nameunit(dev),
543 if (sc->sc_sysctl_tree == NULL) {
544 device_printf(dev, "can't add sysctl node\n");
548 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
549 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
550 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
551 sc, 0, nfe_sysctl_imtime, "I",
552 "Interrupt moderation time (usec). "
553 "-1 to disable interrupt moderation.");
554 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
555 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
557 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
558 "debug", CTLFLAG_RW, &sc->sc_debug,
559 0, "control debugging printfs");
561 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
564 device_printf(dev, "MII without any phy\n");
569 ifp->if_mtu = ETHERMTU;
570 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
571 ifp->if_ioctl = nfe_ioctl;
572 ifp->if_start = nfe_start;
573 #ifdef DEVICE_POLLING
574 ifp->if_poll = nfe_poll;
576 ifp->if_watchdog = nfe_watchdog;
577 ifp->if_init = nfe_init;
578 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
579 ifq_set_ready(&ifp->if_snd);
581 ifp->if_capabilities = IFCAP_VLAN_MTU;
583 if (sc->sc_flags & NFE_HW_VLAN)
584 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
587 if (sc->sc_flags & NFE_HW_CSUM) {
588 ifp->if_capabilities |= IFCAP_HWCSUM;
589 ifp->if_hwassist = NFE_CSUM_FEATURES;
592 sc->sc_flags &= ~NFE_HW_CSUM;
594 ifp->if_capenable = ifp->if_capabilities;
596 callout_init(&sc->sc_tick_ch);
598 ether_ifattach(ifp, eaddr, NULL);
600 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
601 &sc->sc_ih, ifp->if_serializer);
603 device_printf(dev, "could not setup intr\n");
608 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
609 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
618 nfe_detach(device_t dev)
620 struct nfe_softc *sc = device_get_softc(dev);
622 if (device_is_attached(dev)) {
623 struct ifnet *ifp = &sc->arpcom.ac_if;
625 lwkt_serialize_enter(ifp->if_serializer);
627 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
628 lwkt_serialize_exit(ifp->if_serializer);
633 if (sc->sc_miibus != NULL)
634 device_delete_child(dev, sc->sc_miibus);
635 bus_generic_detach(dev);
637 if (sc->sc_sysctl_tree != NULL)
638 sysctl_ctx_free(&sc->sc_sysctl_ctx);
640 if (sc->sc_irq_res != NULL) {
641 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
645 if (sc->sc_mem_res != NULL) {
646 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
650 nfe_free_tx_ring(sc, &sc->txq);
651 nfe_free_rx_ring(sc, &sc->rxq);
657 nfe_shutdown(device_t dev)
659 struct nfe_softc *sc = device_get_softc(dev);
660 struct ifnet *ifp = &sc->arpcom.ac_if;
662 lwkt_serialize_enter(ifp->if_serializer);
664 lwkt_serialize_exit(ifp->if_serializer);
668 nfe_suspend(device_t dev)
670 struct nfe_softc *sc = device_get_softc(dev);
671 struct ifnet *ifp = &sc->arpcom.ac_if;
673 lwkt_serialize_enter(ifp->if_serializer);
675 lwkt_serialize_exit(ifp->if_serializer);
681 nfe_resume(device_t dev)
683 struct nfe_softc *sc = device_get_softc(dev);
684 struct ifnet *ifp = &sc->arpcom.ac_if;
686 lwkt_serialize_enter(ifp->if_serializer);
687 if (ifp->if_flags & IFF_UP)
689 lwkt_serialize_exit(ifp->if_serializer);
695 nfe_miibus_statchg(device_t dev)
697 struct nfe_softc *sc = device_get_softc(dev);
698 struct mii_data *mii = device_get_softc(sc->sc_miibus);
699 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
701 phy = NFE_READ(sc, NFE_PHY_IFACE);
702 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
704 seed = NFE_READ(sc, NFE_RNDSEED);
705 seed &= ~NFE_SEED_MASK;
707 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
708 phy |= NFE_PHY_HDX; /* half-duplex */
709 misc |= NFE_MISC1_HDX;
712 switch (IFM_SUBTYPE(mii->mii_media_active)) {
713 case IFM_1000_T: /* full-duplex only */
714 link |= NFE_MEDIA_1000T;
715 seed |= NFE_SEED_1000T;
716 phy |= NFE_PHY_1000T;
719 link |= NFE_MEDIA_100TX;
720 seed |= NFE_SEED_100TX;
721 phy |= NFE_PHY_100TX;
724 link |= NFE_MEDIA_10T;
725 seed |= NFE_SEED_10T;
729 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
731 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
732 NFE_WRITE(sc, NFE_MISC1, misc);
733 NFE_WRITE(sc, NFE_LINKSPEED, link);
737 nfe_miibus_readreg(device_t dev, int phy, int reg)
739 struct nfe_softc *sc = device_get_softc(dev);
743 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
745 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
746 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
750 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
752 for (ntries = 0; ntries < 1000; ntries++) {
754 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
757 if (ntries == 1000) {
758 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
762 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
763 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
767 val = NFE_READ(sc, NFE_PHY_DATA);
768 if (val != 0xffffffff && val != 0)
769 sc->mii_phyaddr = phy;
771 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
777 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
779 struct nfe_softc *sc = device_get_softc(dev);
783 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
785 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
786 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
790 NFE_WRITE(sc, NFE_PHY_DATA, val);
791 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
792 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
794 for (ntries = 0; ntries < 1000; ntries++) {
796 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
802 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
806 #ifdef DEVICE_POLLING
809 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
811 struct nfe_softc *sc = ifp->if_softc;
813 ASSERT_SERIALIZED(ifp->if_serializer);
817 /* Disable interrupts */
818 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
820 case POLL_DEREGISTER:
821 /* enable interrupts */
822 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
824 case POLL_AND_CHECK_STATUS:
827 if (ifp->if_flags & IFF_RUNNING) {
840 struct nfe_softc *sc = arg;
841 struct ifnet *ifp = &sc->arpcom.ac_if;
844 r = NFE_READ(sc, NFE_IRQ_STATUS);
846 return; /* not for us */
847 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
849 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
851 if (r & NFE_IRQ_LINK) {
852 NFE_READ(sc, NFE_PHY_STATUS);
853 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
854 DPRINTF(sc, "link state changed %s\n", "");
857 if (ifp->if_flags & IFF_RUNNING) {
867 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
869 struct nfe_softc *sc = ifp->if_softc;
870 struct ifreq *ifr = (struct ifreq *)data;
871 struct mii_data *mii;
876 if (((sc->sc_flags & NFE_JUMBO_SUP) &&
877 ifr->ifr_mtu > NFE_JUMBO_MTU) ||
878 ((sc->sc_flags & NFE_JUMBO_SUP) == 0 &&
879 ifr->ifr_mtu > ETHERMTU)) {
881 } else if (ifp->if_mtu != ifr->ifr_mtu) {
882 ifp->if_mtu = ifr->ifr_mtu;
887 if (ifp->if_flags & IFF_UP) {
889 * If only the PROMISC or ALLMULTI flag changes, then
890 * don't do a full re-init of the chip, just update
893 if ((ifp->if_flags & IFF_RUNNING) &&
894 ((ifp->if_flags ^ sc->sc_if_flags) &
895 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
898 if (!(ifp->if_flags & IFF_RUNNING))
902 if (ifp->if_flags & IFF_RUNNING)
905 sc->sc_if_flags = ifp->if_flags;
909 if (ifp->if_flags & IFF_RUNNING)
914 mii = device_get_softc(sc->sc_miibus);
915 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
918 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
919 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
920 ifp->if_capenable ^= mask;
921 if (IFCAP_TXCSUM & ifp->if_capenable)
922 ifp->if_hwassist = NFE_CSUM_FEATURES;
924 ifp->if_hwassist = 0;
926 if (ifp->if_flags & IFF_RUNNING)
931 error = ether_ioctl(ifp, cmd, data);
938 nfe_rxeof(struct nfe_softc *sc)
940 struct ifnet *ifp = &sc->arpcom.ac_if;
941 struct nfe_rx_ring *ring = &sc->rxq;
943 #ifdef ETHER_INPUT_CHAIN
944 struct mbuf_chain chain[MAXCPU];
948 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
950 #ifdef ETHER_INPUT_CHAIN
951 ether_input_chain_init(chain);
955 struct nfe_rx_data *data = &ring->data[ring->cur];
960 if (sc->sc_flags & NFE_40BIT_ADDR) {
961 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
963 flags = le16toh(desc64->flags);
964 len = le16toh(desc64->length) & 0x3fff;
966 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
968 flags = le16toh(desc32->flags);
969 len = le16toh(desc32->length) & 0x3fff;
972 if (flags & NFE_RX_READY)
977 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
978 if (!(flags & NFE_RX_VALID_V1))
981 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
982 flags &= ~NFE_RX_ERROR;
983 len--; /* fix buffer length */
986 if (!(flags & NFE_RX_VALID_V2))
989 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
990 flags &= ~NFE_RX_ERROR;
991 len--; /* fix buffer length */
995 if (flags & NFE_RX_ERROR) {
1002 if (sc->sc_flags & NFE_USE_JUMBO)
1003 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
1005 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1012 m->m_pkthdr.len = m->m_len = len;
1013 m->m_pkthdr.rcvif = ifp;
1015 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1016 (flags & NFE_RX_CSUMOK)) {
1017 if (flags & NFE_RX_IP_CSUMOK_V2) {
1018 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1023 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1024 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1026 CSUM_FRAG_NOT_CHECKED;
1027 m->m_pkthdr.csum_data = 0xffff;
1032 #ifdef ETHER_INPUT_CHAIN
1034 ether_input_chain2(ifp, m, chain);
1036 ether_input_chain(ifp, m, chain);
1039 ifp->if_input(ifp, m);
1042 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1043 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1047 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1048 #ifdef ETHER_INPUT_CHAIN
1049 ether_input_dispatch(chain);
1055 nfe_txeof(struct nfe_softc *sc)
1057 struct ifnet *ifp = &sc->arpcom.ac_if;
1058 struct nfe_tx_ring *ring = &sc->txq;
1059 struct nfe_tx_data *data = NULL;
1061 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
1062 while (ring->next != ring->cur) {
1065 if (sc->sc_flags & NFE_40BIT_ADDR)
1066 flags = le16toh(ring->desc64[ring->next].flags);
1068 flags = le16toh(ring->desc32[ring->next].flags);
1070 if (flags & NFE_TX_VALID)
1073 data = &ring->data[ring->next];
1075 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1076 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1079 if ((flags & NFE_TX_ERROR_V1) != 0) {
1080 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1087 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1090 if ((flags & NFE_TX_ERROR_V2) != 0) {
1091 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1099 if (data->m == NULL) { /* should not get there */
1101 "last fragment bit w/o associated mbuf!\n");
1105 /* last fragment of the mbuf chain transmitted */
1106 bus_dmamap_sync(ring->data_tag, data->map,
1107 BUS_DMASYNC_POSTWRITE);
1108 bus_dmamap_unload(ring->data_tag, data->map);
1115 KKASSERT(ring->queued >= 0);
1116 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1119 if (data != NULL) { /* at least one slot freed */
1120 ifp->if_flags &= ~IFF_OACTIVE;
1126 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1128 struct nfe_dma_ctx ctx;
1129 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1130 struct nfe_tx_data *data, *data_map;
1132 struct nfe_desc64 *desc64 = NULL;
1133 struct nfe_desc32 *desc32 = NULL;
1138 data = &ring->data[ring->cur];
1140 data_map = data; /* Remember who owns the DMA map */
1142 ctx.nsegs = NFE_MAX_SCATTER;
1144 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1145 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1146 if (error && error != EFBIG) {
1147 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1151 if (error) { /* error == EFBIG */
1154 m_new = m_defrag(m0, MB_DONTWAIT);
1155 if (m_new == NULL) {
1156 if_printf(&sc->arpcom.ac_if,
1157 "could not defrag TX mbuf\n");
1164 ctx.nsegs = NFE_MAX_SCATTER;
1166 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1167 nfe_buf_dma_addr, &ctx,
1170 if_printf(&sc->arpcom.ac_if,
1171 "could not map defraged TX mbuf\n");
1178 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1179 bus_dmamap_unload(ring->data_tag, map);
1184 /* setup h/w VLAN tagging */
1185 if (m0->m_flags & M_VLANTAG)
1186 vtag = m0->m_pkthdr.ether_vlantag;
1188 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1189 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1190 flags |= NFE_TX_IP_CSUM;
1191 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1192 flags |= NFE_TX_TCP_CSUM;
1196 * XXX urm. somebody is unaware of how hardware works. You
1197 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1198 * the ring until the entire chain is actually *VALID*. Otherwise
1199 * the hardware may encounter a partially initialized chain that
1200 * is marked as being ready to go when it in fact is not ready to
1204 for (i = 0; i < ctx.nsegs; i++) {
1205 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1206 data = &ring->data[j];
1208 if (sc->sc_flags & NFE_40BIT_ADDR) {
1209 desc64 = &ring->desc64[j];
1210 #if defined(__LP64__)
1211 desc64->physaddr[0] =
1212 htole32(segs[i].ds_addr >> 32);
1214 desc64->physaddr[1] =
1215 htole32(segs[i].ds_addr & 0xffffffff);
1216 desc64->length = htole16(segs[i].ds_len - 1);
1217 desc64->vtag = htole32(vtag);
1218 desc64->flags = htole16(flags);
1220 desc32 = &ring->desc32[j];
1221 desc32->physaddr = htole32(segs[i].ds_addr);
1222 desc32->length = htole16(segs[i].ds_len - 1);
1223 desc32->flags = htole16(flags);
1226 /* csum flags and vtag belong to the first fragment only */
1227 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1231 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1234 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1235 if (sc->sc_flags & NFE_40BIT_ADDR) {
1236 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1238 if (sc->sc_flags & NFE_JUMBO_SUP)
1239 flags = NFE_TX_LASTFRAG_V2;
1241 flags = NFE_TX_LASTFRAG_V1;
1242 desc32->flags |= htole16(flags);
1246 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1247 * whole mess until the first descriptor in the map is flagged.
1249 for (i = ctx.nsegs - 1; i >= 0; --i) {
1250 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1251 if (sc->sc_flags & NFE_40BIT_ADDR) {
1252 desc64 = &ring->desc64[j];
1253 desc64->flags |= htole16(NFE_TX_VALID);
1255 desc32 = &ring->desc32[j];
1256 desc32->flags |= htole16(NFE_TX_VALID);
1259 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1261 /* Exchange DMA map */
1262 data_map->map = data->map;
1266 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1274 nfe_start(struct ifnet *ifp)
1276 struct nfe_softc *sc = ifp->if_softc;
1277 struct nfe_tx_ring *ring = &sc->txq;
1281 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1285 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1289 ETHER_BPF_MTAP(ifp, m0);
1291 if (nfe_encap(sc, ring, m0) != 0) {
1292 ifp->if_flags |= IFF_OACTIVE;
1299 * `m0' may be freed in nfe_encap(), so
1300 * it should not be touched any more.
1303 if (count == 0) /* nothing sent */
1306 /* Sync TX descriptor ring */
1307 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1310 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1313 * Set a timeout in case the chip goes out to lunch.
1319 nfe_watchdog(struct ifnet *ifp)
1321 struct nfe_softc *sc = ifp->if_softc;
1323 if (ifp->if_flags & IFF_RUNNING) {
1324 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1329 if_printf(ifp, "watchdog timeout\n");
1331 nfe_init(ifp->if_softc);
1339 struct nfe_softc *sc = xsc;
1340 struct ifnet *ifp = &sc->arpcom.ac_if;
1346 if ((sc->sc_flags & NFE_NO_PWRCTL) == 0)
1351 * Switching between jumbo frames and normal frames should
1352 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1354 if (ifp->if_mtu > ETHERMTU) {
1355 sc->sc_flags |= NFE_USE_JUMBO;
1356 sc->rxq.bufsz = NFE_JBYTES;
1358 if_printf(ifp, "use jumbo frames\n");
1360 sc->sc_flags &= ~NFE_USE_JUMBO;
1361 sc->rxq.bufsz = MCLBYTES;
1363 if_printf(ifp, "use non-jumbo frames\n");
1366 error = nfe_init_tx_ring(sc, &sc->txq);
1372 error = nfe_init_rx_ring(sc, &sc->rxq);
1378 NFE_WRITE(sc, NFE_TX_POLL, 0);
1379 NFE_WRITE(sc, NFE_STATUS, 0);
1381 sc->rxtxctl = NFE_RXTX_BIT2 | sc->rxtxctl_desc;
1383 if (ifp->if_capenable & IFCAP_RXCSUM)
1384 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1387 * Although the adapter is capable of stripping VLAN tags from received
1388 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1389 * purpose. This will be done in software by our network stack.
1391 if (sc->sc_flags & NFE_HW_VLAN)
1392 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1394 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1396 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1398 if (sc->sc_flags & NFE_HW_VLAN)
1399 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1401 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1403 /* set MAC address */
1404 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1406 /* tell MAC where rings are in memory */
1408 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1410 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1412 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1414 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1416 NFE_WRITE(sc, NFE_RING_SIZE,
1417 (sc->sc_rx_ring_count - 1) << 16 |
1418 (NFE_TX_RING_COUNT - 1));
1420 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1422 /* force MAC to wakeup */
1423 tmp = NFE_READ(sc, NFE_PWR_STATE);
1424 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1426 tmp = NFE_READ(sc, NFE_PWR_STATE);
1427 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1430 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
1431 * It is unclear how wide the timer is. Base programming does
1432 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
1433 * we don't get any interrupt moderation. TX moderation is
1434 * possible by using the timer interrupt instead of TX_DONE.
1436 * It is unclear whether there are other bits that can be
1437 * set to make the NFE device actually do interrupt moderation
1440 * For now set a 128uS interval as a placemark, but don't use
1443 if (sc->sc_imtime < 0)
1444 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
1446 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
1448 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1449 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1450 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1452 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1453 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1455 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1457 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1458 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1460 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1465 nfe_ifmedia_upd(ifp);
1468 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1471 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1473 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1475 #ifdef DEVICE_POLLING
1476 if ((ifp->if_flags & IFF_POLLING) == 0)
1478 /* enable interrupts */
1479 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
1481 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1483 ifp->if_flags |= IFF_RUNNING;
1484 ifp->if_flags &= ~IFF_OACTIVE;
1487 * If we had stuff in the tx ring before its all cleaned out now
1488 * so we are not going to get an interrupt, jump-start any pending
1495 nfe_stop(struct nfe_softc *sc)
1497 struct ifnet *ifp = &sc->arpcom.ac_if;
1498 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
1501 callout_stop(&sc->sc_tick_ch);
1504 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1506 #define WAITMAX 50000
1511 NFE_WRITE(sc, NFE_TX_CTL, 0);
1512 for (i = 0; i < WAITMAX; ++i) {
1514 if ((NFE_READ(sc, NFE_TX_STATUS) & NFE_TX_STATUS_BUSY) == 0)
1518 if_printf(ifp, "can't stop TX\n");
1524 NFE_WRITE(sc, NFE_RX_CTL, 0);
1525 for (i = 0; i < WAITMAX; ++i) {
1527 if ((NFE_READ(sc, NFE_RX_STATUS) & NFE_RX_STATUS_BUSY) == 0)
1531 if_printf(ifp, "can't stop RX\n");
1536 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
1538 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
1540 /* Disable interrupts */
1541 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1543 /* Reset Tx and Rx rings */
1544 nfe_reset_tx_ring(sc, &sc->txq);
1545 nfe_reset_rx_ring(sc, &sc->rxq);
1549 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1551 int i, j, error, descsize;
1554 if (sc->sc_flags & NFE_40BIT_ADDR) {
1555 desc = (void **)&ring->desc64;
1556 descsize = sizeof(struct nfe_desc64);
1558 desc = (void **)&ring->desc32;
1559 descsize = sizeof(struct nfe_desc32);
1562 ring->jbuf = kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT,
1563 M_DEVBUF, M_WAITOK | M_ZERO);
1564 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1565 M_DEVBUF, M_WAITOK | M_ZERO);
1567 ring->bufsz = MCLBYTES;
1568 ring->cur = ring->next = 0;
1570 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1571 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1573 sc->sc_rx_ring_count * descsize, 1,
1574 sc->sc_rx_ring_count * descsize,
1577 if_printf(&sc->arpcom.ac_if,
1578 "could not create desc RX DMA tag\n");
1582 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1585 if_printf(&sc->arpcom.ac_if,
1586 "could not allocate RX desc DMA memory\n");
1587 bus_dma_tag_destroy(ring->tag);
1592 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1593 sc->sc_rx_ring_count * descsize,
1594 nfe_ring_dma_addr, &ring->physaddr,
1597 if_printf(&sc->arpcom.ac_if,
1598 "could not load RX desc DMA map\n");
1599 bus_dmamem_free(ring->tag, *desc, ring->map);
1600 bus_dma_tag_destroy(ring->tag);
1605 if (sc->sc_flags & NFE_JUMBO_SUP) {
1606 error = nfe_jpool_alloc(sc, ring);
1608 if_printf(&sc->arpcom.ac_if,
1609 "could not allocate jumbo frames\n");
1614 error = bus_dma_tag_create(NULL, 1, 0,
1615 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1617 MCLBYTES, 1, MCLBYTES,
1618 0, &ring->data_tag);
1620 if_printf(&sc->arpcom.ac_if,
1621 "could not create RX mbuf DMA tag\n");
1625 /* Create a spare RX mbuf DMA map */
1626 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1628 if_printf(&sc->arpcom.ac_if,
1629 "could not create spare RX mbuf DMA map\n");
1630 bus_dma_tag_destroy(ring->data_tag);
1631 ring->data_tag = NULL;
1635 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1636 error = bus_dmamap_create(ring->data_tag, 0,
1637 &ring->data[i].map);
1639 if_printf(&sc->arpcom.ac_if,
1640 "could not create %dth RX mbuf DMA mapn", i);
1646 for (j = 0; j < i; ++j)
1647 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1648 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1649 bus_dma_tag_destroy(ring->data_tag);
1650 ring->data_tag = NULL;
1655 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1659 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1660 struct nfe_rx_data *data = &ring->data[i];
1662 if (data->m != NULL) {
1663 if ((sc->sc_flags & NFE_USE_JUMBO) == 0)
1664 bus_dmamap_unload(ring->data_tag, data->map);
1669 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1671 ring->cur = ring->next = 0;
1675 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1679 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1682 /* XXX should use a function pointer */
1683 if (sc->sc_flags & NFE_USE_JUMBO)
1684 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1686 error = nfe_newbuf_std(sc, ring, i, 1);
1688 if_printf(&sc->arpcom.ac_if,
1689 "could not allocate RX buffer\n");
1693 nfe_set_ready_rxdesc(sc, ring, i);
1695 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1701 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1703 if (ring->data_tag != NULL) {
1704 struct nfe_rx_data *data;
1707 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1708 data = &ring->data[i];
1710 if (data->m != NULL) {
1711 bus_dmamap_unload(ring->data_tag, data->map);
1714 bus_dmamap_destroy(ring->data_tag, data->map);
1716 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1717 bus_dma_tag_destroy(ring->data_tag);
1720 nfe_jpool_free(sc, ring);
1722 if (ring->jbuf != NULL)
1723 kfree(ring->jbuf, M_DEVBUF);
1724 if (ring->data != NULL)
1725 kfree(ring->data, M_DEVBUF);
1727 if (ring->tag != NULL) {
1730 if (sc->sc_flags & NFE_40BIT_ADDR)
1731 desc = ring->desc64;
1733 desc = ring->desc32;
1735 bus_dmamap_unload(ring->tag, ring->map);
1736 bus_dmamem_free(ring->tag, desc, ring->map);
1737 bus_dma_tag_destroy(ring->tag);
1741 static struct nfe_jbuf *
1742 nfe_jalloc(struct nfe_softc *sc)
1744 struct ifnet *ifp = &sc->arpcom.ac_if;
1745 struct nfe_jbuf *jbuf;
1747 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1749 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1751 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1754 if_printf(ifp, "no free jumbo buffer\n");
1757 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1763 nfe_jfree(void *arg)
1765 struct nfe_jbuf *jbuf = arg;
1766 struct nfe_softc *sc = jbuf->sc;
1767 struct nfe_rx_ring *ring = jbuf->ring;
1769 if (&ring->jbuf[jbuf->slot] != jbuf)
1770 panic("%s: free wrong jumbo buffer\n", __func__);
1771 else if (jbuf->inuse == 0)
1772 panic("%s: jumbo buffer already freed\n", __func__);
1774 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1775 atomic_subtract_int(&jbuf->inuse, 1);
1776 if (jbuf->inuse == 0)
1777 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1778 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1784 struct nfe_jbuf *jbuf = arg;
1785 struct nfe_rx_ring *ring = jbuf->ring;
1787 if (&ring->jbuf[jbuf->slot] != jbuf)
1788 panic("%s: ref wrong jumbo buffer\n", __func__);
1789 else if (jbuf->inuse == 0)
1790 panic("%s: jumbo buffer already freed\n", __func__);
1792 atomic_add_int(&jbuf->inuse, 1);
1796 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1798 struct nfe_jbuf *jbuf;
1799 bus_addr_t physaddr;
1804 * Allocate a big chunk of DMA'able memory.
1806 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1807 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1809 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1812 if_printf(&sc->arpcom.ac_if,
1813 "could not create jumbo DMA tag\n");
1817 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1818 BUS_DMA_WAITOK, &ring->jmap);
1820 if_printf(&sc->arpcom.ac_if,
1821 "could not allocate jumbo DMA memory\n");
1822 bus_dma_tag_destroy(ring->jtag);
1827 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1828 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1831 if_printf(&sc->arpcom.ac_if,
1832 "could not load jumbo DMA map\n");
1833 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1834 bus_dma_tag_destroy(ring->jtag);
1839 /* ..and split it into 9KB chunks */
1840 SLIST_INIT(&ring->jfreelist);
1843 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1844 jbuf = &ring->jbuf[i];
1851 jbuf->physaddr = physaddr;
1853 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1856 physaddr += NFE_JBYTES;
1863 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1865 if (ring->jtag != NULL) {
1866 bus_dmamap_unload(ring->jtag, ring->jmap);
1867 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1868 bus_dma_tag_destroy(ring->jtag);
1873 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1875 int i, j, error, descsize;
1878 if (sc->sc_flags & NFE_40BIT_ADDR) {
1879 desc = (void **)&ring->desc64;
1880 descsize = sizeof(struct nfe_desc64);
1882 desc = (void **)&ring->desc32;
1883 descsize = sizeof(struct nfe_desc32);
1887 ring->cur = ring->next = 0;
1889 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1890 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1892 NFE_TX_RING_COUNT * descsize, 1,
1893 NFE_TX_RING_COUNT * descsize,
1896 if_printf(&sc->arpcom.ac_if,
1897 "could not create TX desc DMA map\n");
1901 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1904 if_printf(&sc->arpcom.ac_if,
1905 "could not allocate TX desc DMA memory\n");
1906 bus_dma_tag_destroy(ring->tag);
1911 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1912 NFE_TX_RING_COUNT * descsize,
1913 nfe_ring_dma_addr, &ring->physaddr,
1916 if_printf(&sc->arpcom.ac_if,
1917 "could not load TX desc DMA map\n");
1918 bus_dmamem_free(ring->tag, *desc, ring->map);
1919 bus_dma_tag_destroy(ring->tag);
1924 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1925 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1927 NFE_JBYTES * NFE_MAX_SCATTER,
1928 NFE_MAX_SCATTER, NFE_JBYTES,
1929 0, &ring->data_tag);
1931 if_printf(&sc->arpcom.ac_if,
1932 "could not create TX buf DMA tag\n");
1936 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1937 error = bus_dmamap_create(ring->data_tag, 0,
1938 &ring->data[i].map);
1940 if_printf(&sc->arpcom.ac_if,
1941 "could not create %dth TX buf DMA map\n", i);
1948 for (j = 0; j < i; ++j)
1949 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1950 bus_dma_tag_destroy(ring->data_tag);
1951 ring->data_tag = NULL;
1956 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1960 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1961 struct nfe_tx_data *data = &ring->data[i];
1963 if (sc->sc_flags & NFE_40BIT_ADDR)
1964 ring->desc64[i].flags = 0;
1966 ring->desc32[i].flags = 0;
1968 if (data->m != NULL) {
1969 bus_dmamap_sync(ring->data_tag, data->map,
1970 BUS_DMASYNC_POSTWRITE);
1971 bus_dmamap_unload(ring->data_tag, data->map);
1976 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1979 ring->cur = ring->next = 0;
1983 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1984 struct nfe_tx_ring *ring __unused)
1990 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1992 if (ring->data_tag != NULL) {
1993 struct nfe_tx_data *data;
1996 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
1997 data = &ring->data[i];
1999 if (data->m != NULL) {
2000 bus_dmamap_unload(ring->data_tag, data->map);
2003 bus_dmamap_destroy(ring->data_tag, data->map);
2006 bus_dma_tag_destroy(ring->data_tag);
2009 if (ring->tag != NULL) {
2012 if (sc->sc_flags & NFE_40BIT_ADDR)
2013 desc = ring->desc64;
2015 desc = ring->desc32;
2017 bus_dmamap_unload(ring->tag, ring->map);
2018 bus_dmamem_free(ring->tag, desc, ring->map);
2019 bus_dma_tag_destroy(ring->tag);
2024 nfe_ifmedia_upd(struct ifnet *ifp)
2026 struct nfe_softc *sc = ifp->if_softc;
2027 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2029 if (mii->mii_instance != 0) {
2030 struct mii_softc *miisc;
2032 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2033 mii_phy_reset(miisc);
2041 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2043 struct nfe_softc *sc = ifp->if_softc;
2044 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2047 ifmr->ifm_status = mii->mii_media_status;
2048 ifmr->ifm_active = mii->mii_media_active;
2052 nfe_setmulti(struct nfe_softc *sc)
2054 struct ifnet *ifp = &sc->arpcom.ac_if;
2055 struct ifmultiaddr *ifma;
2056 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2057 uint32_t filter = NFE_RXFILTER_MAGIC;
2060 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2061 bzero(addr, ETHER_ADDR_LEN);
2062 bzero(mask, ETHER_ADDR_LEN);
2066 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2067 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2069 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2072 if (ifma->ifma_addr->sa_family != AF_LINK)
2075 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2076 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2077 addr[i] &= maddr[i];
2078 mask[i] &= ~maddr[i];
2082 for (i = 0; i < ETHER_ADDR_LEN; i++)
2086 addr[0] |= 0x01; /* make sure multicast bit is set */
2088 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2089 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2090 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2091 addr[5] << 8 | addr[4]);
2092 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2093 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2094 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2095 mask[5] << 8 | mask[4]);
2097 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2098 NFE_WRITE(sc, NFE_RXFILTER, filter);
2102 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2106 tmp = NFE_READ(sc, NFE_MACADDR_LO);
2107 addr[0] = (tmp >> 8) & 0xff;
2108 addr[1] = (tmp & 0xff);
2110 tmp = NFE_READ(sc, NFE_MACADDR_HI);
2111 addr[2] = (tmp >> 24) & 0xff;
2112 addr[3] = (tmp >> 16) & 0xff;
2113 addr[4] = (tmp >> 8) & 0xff;
2114 addr[5] = (tmp & 0xff);
2118 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2120 NFE_WRITE(sc, NFE_MACADDR_LO,
2121 addr[5] << 8 | addr[4]);
2122 NFE_WRITE(sc, NFE_MACADDR_HI,
2123 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2129 struct nfe_softc *sc = arg;
2130 struct ifnet *ifp = &sc->arpcom.ac_if;
2131 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2133 lwkt_serialize_enter(ifp->if_serializer);
2136 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2138 lwkt_serialize_exit(ifp->if_serializer);
2142 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2147 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2149 *((uint32_t *)arg) = seg->ds_addr;
2153 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2154 bus_size_t mapsz __unused, int error)
2156 struct nfe_dma_ctx *ctx = arg;
2162 KASSERT(nsegs <= ctx->nsegs,
2163 ("too many segments(%d), should be <= %d\n",
2164 nsegs, ctx->nsegs));
2167 for (i = 0; i < nsegs; ++i)
2168 ctx->segs[i] = segs[i];
2172 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2175 struct nfe_rx_data *data = &ring->data[idx];
2176 struct nfe_dma_ctx ctx;
2177 bus_dma_segment_t seg;
2182 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2185 m->m_len = m->m_pkthdr.len = MCLBYTES;
2189 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2190 m, nfe_buf_dma_addr, &ctx,
2191 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2194 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2198 /* Unload originally mapped mbuf */
2199 bus_dmamap_unload(ring->data_tag, data->map);
2201 /* Swap this DMA map with tmp DMA map */
2203 data->map = ring->data_tmpmap;
2204 ring->data_tmpmap = map;
2206 /* Caller is assumed to have collected the old mbuf */
2209 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2211 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2216 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2219 struct nfe_rx_data *data = &ring->data[idx];
2220 struct nfe_jbuf *jbuf;
2223 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2227 jbuf = nfe_jalloc(sc);
2230 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2231 "-- packet dropped!\n");
2235 m->m_ext.ext_arg = jbuf;
2236 m->m_ext.ext_buf = jbuf->buf;
2237 m->m_ext.ext_free = nfe_jfree;
2238 m->m_ext.ext_ref = nfe_jref;
2239 m->m_ext.ext_size = NFE_JBYTES;
2241 m->m_data = m->m_ext.ext_buf;
2242 m->m_flags |= M_EXT;
2243 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2245 /* Caller is assumed to have collected the old mbuf */
2248 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2250 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2255 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2256 bus_addr_t physaddr)
2258 if (sc->sc_flags & NFE_40BIT_ADDR) {
2259 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2261 #if defined(__LP64__)
2262 desc64->physaddr[0] = htole32(physaddr >> 32);
2264 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2266 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2268 desc32->physaddr = htole32(physaddr);
2273 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2275 if (sc->sc_flags & NFE_40BIT_ADDR) {
2276 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2278 desc64->length = htole16(ring->bufsz);
2279 desc64->flags = htole16(NFE_RX_READY);
2281 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2283 desc32->length = htole16(ring->bufsz);
2284 desc32->flags = htole16(NFE_RX_READY);
2289 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2291 struct nfe_softc *sc = arg1;
2292 struct ifnet *ifp = &sc->arpcom.ac_if;
2295 lwkt_serialize_enter(ifp->if_serializer);
2298 error = sysctl_handle_int(oidp, &v, 0, req);
2299 if (error || req->newptr == NULL)
2306 if (sc->sc_imtime != v) {
2307 int old_imtime = sc->sc_imtime;
2310 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2312 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2314 if (old_imtime > 0 && sc->sc_imtime > 0) {
2315 NFE_WRITE(sc, NFE_IMTIMER,
2316 NFE_IMTIME(sc->sc_imtime));
2317 } else if ((old_imtime * sc->sc_imtime) < 0) {
2323 lwkt_serialize_exit(ifp->if_serializer);
2328 nfe_powerup(device_t dev)
2330 struct nfe_softc *sc = device_get_softc(dev);
2335 * Bring MAC and PHY out of low power state
2338 pwr_state = NFE_READ(sc, NFE_PWR_STATE2) & ~NFE_PWRUP_MASK;
2340 did = pci_get_device(dev);
2341 if ((did == PCI_PRODUCT_NVIDIA_MCP51_LAN1 ||
2342 did == PCI_PRODUCT_NVIDIA_MCP51_LAN2) &&
2343 pci_get_revid(dev) >= 0xa3)
2344 pwr_state |= NFE_PWRUP_REV_A3;
2346 NFE_WRITE(sc, NFE_PWR_STATE2, pwr_state);
2350 nfe_mac_reset(struct nfe_softc *sc)
2352 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
2353 uint32_t macaddr_hi, macaddr_lo, tx_poll;
2355 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
2357 /* Save several registers for later restoration */
2358 macaddr_hi = NFE_READ(sc, NFE_MACADDR_HI);
2359 macaddr_lo = NFE_READ(sc, NFE_MACADDR_LO);
2360 tx_poll = NFE_READ(sc, NFE_TX_POLL);
2362 NFE_WRITE(sc, NFE_MAC_RESET, NFE_RESET_ASSERT);
2365 NFE_WRITE(sc, NFE_MAC_RESET, 0);
2368 /* Restore saved registers */
2369 NFE_WRITE(sc, NFE_MACADDR_HI, macaddr_hi);
2370 NFE_WRITE(sc, NFE_MACADDR_LO, macaddr_lo);
2371 NFE_WRITE(sc, NFE_TX_POLL, tx_poll);
2373 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);