1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.46 2008/10/28 07:30:49 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
60 #include <sys/param.h>
61 #include <sys/endian.h>
62 #include <sys/kernel.h>
64 #include <sys/interrupt.h>
67 #include <sys/serialize.h>
68 #include <sys/socket.h>
69 #include <sys/sockio.h>
70 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
75 #include <net/if_arp.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/ifq_var.h>
79 #include <net/if_types.h>
80 #include <net/if_var.h>
81 #include <net/vlan/if_vlan_var.h>
82 #include <net/vlan/if_vlan_ether.h>
84 #include <bus/pci/pcireg.h>
85 #include <bus/pci/pcivar.h>
86 #include <bus/pci/pcidevs.h>
88 #include <dev/netif/mii_layer/mii.h>
89 #include <dev/netif/mii_layer/miivar.h>
91 #include "miibus_if.h"
93 #include <dev/netif/nfe/if_nfereg.h>
94 #include <dev/netif/nfe/if_nfevar.h>
97 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
99 static int nfe_probe(device_t);
100 static int nfe_attach(device_t);
101 static int nfe_detach(device_t);
102 static void nfe_shutdown(device_t);
103 static int nfe_resume(device_t);
104 static int nfe_suspend(device_t);
106 static int nfe_miibus_readreg(device_t, int, int);
107 static void nfe_miibus_writereg(device_t, int, int, int);
108 static void nfe_miibus_statchg(device_t);
110 #ifdef DEVICE_POLLING
111 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
113 static void nfe_intr(void *);
114 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
115 static int nfe_rxeof(struct nfe_softc *);
116 static int nfe_txeof(struct nfe_softc *, int);
117 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
119 static void nfe_start(struct ifnet *);
120 static void nfe_watchdog(struct ifnet *);
121 static void nfe_init(void *);
122 static void nfe_stop(struct nfe_softc *);
123 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
124 static void nfe_jfree(void *);
125 static void nfe_jref(void *);
126 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
127 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
128 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
129 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
133 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static int nfe_ifmedia_upd(struct ifnet *);
137 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
138 static void nfe_setmulti(struct nfe_softc *);
139 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
140 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
141 static void nfe_powerup(device_t);
142 static void nfe_mac_reset(struct nfe_softc *);
143 static void nfe_tick(void *);
144 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
146 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
148 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
150 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
152 static void nfe_enable_intrs(struct nfe_softc *);
153 static void nfe_disable_intrs(struct nfe_softc *);
155 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
160 static int nfe_debug = 0;
161 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
162 static int nfe_tx_ring_count = NFE_TX_RING_DEF_COUNT;
163 /* hw timer simulated interrupt moderation @8000Hz */
164 static int nfe_imtime = -125;
166 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
167 TUNABLE_INT("hw.nfe.tx_ring_count", &nfe_tx_ring_count);
168 TUNABLE_INT("hw.nfe.imtimer", &nfe_imtime);
169 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
171 #define DPRINTF(sc, fmt, ...) do { \
172 if ((sc)->sc_debug) { \
173 if_printf(&(sc)->arpcom.ac_if, \
178 #define DPRINTFN(sc, lv, fmt, ...) do { \
179 if ((sc)->sc_debug >= (lv)) { \
180 if_printf(&(sc)->arpcom.ac_if, \
185 #else /* !NFE_DEBUG */
187 #define DPRINTF(sc, fmt, ...)
188 #define DPRINTFN(sc, lv, fmt, ...)
190 #endif /* NFE_DEBUG */
192 static const struct nfe_dev {
197 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
198 "NVIDIA nForce Fast Ethernet" },
200 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
201 "NVIDIA nForce2 Fast Ethernet" },
203 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
204 "NVIDIA nForce3 Gigabit Ethernet" },
206 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
207 chipset, and possibly also the 400R; it might be both nForce2- and
208 nForce3-based boards can use the same MCPs (= southbridges) */
209 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
210 "NVIDIA nForce3 Gigabit Ethernet" },
212 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
213 "NVIDIA nForce3 Gigabit Ethernet" },
215 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
216 "NVIDIA nForce3 Gigabit Ethernet" },
218 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
219 "NVIDIA nForce3 Gigabit Ethernet" },
221 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
222 "NVIDIA CK804 Gigabit Ethernet" },
224 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
225 "NVIDIA CK804 Gigabit Ethernet" },
227 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
228 "NVIDIA MCP04 Gigabit Ethernet" },
230 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
231 "NVIDIA MCP04 Gigabit Ethernet" },
233 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
234 "NVIDIA MCP51 Gigabit Ethernet" },
236 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
237 "NVIDIA MCP51 Gigabit Ethernet" },
239 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
240 "NVIDIA MCP55 Gigabit Ethernet" },
242 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
243 "NVIDIA MCP55 Gigabit Ethernet" },
245 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
246 "NVIDIA MCP61 Gigabit Ethernet" },
248 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
249 "NVIDIA MCP61 Gigabit Ethernet" },
251 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
252 "NVIDIA MCP61 Gigabit Ethernet" },
254 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
255 "NVIDIA MCP61 Gigabit Ethernet" },
257 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
258 "NVIDIA MCP65 Gigabit Ethernet" },
260 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
261 "NVIDIA MCP65 Gigabit Ethernet" },
263 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
264 "NVIDIA MCP65 Gigabit Ethernet" },
266 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
267 "NVIDIA MCP65 Gigabit Ethernet" },
269 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
270 "NVIDIA MCP67 Gigabit Ethernet" },
272 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
273 "NVIDIA MCP67 Gigabit Ethernet" },
275 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
276 "NVIDIA MCP67 Gigabit Ethernet" },
278 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
279 "NVIDIA MCP67 Gigabit Ethernet" },
281 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
282 "NVIDIA MCP73 Gigabit Ethernet" },
284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
285 "NVIDIA MCP73 Gigabit Ethernet" },
287 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
288 "NVIDIA MCP73 Gigabit Ethernet" },
290 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
291 "NVIDIA MCP73 Gigabit Ethernet" },
293 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
294 "NVIDIA MCP77 Gigabit Ethernet" },
296 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
297 "NVIDIA MCP77 Gigabit Ethernet" },
299 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
300 "NVIDIA MCP77 Gigabit Ethernet" },
302 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
303 "NVIDIA MCP77 Gigabit Ethernet" },
305 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
306 "NVIDIA MCP79 Gigabit Ethernet" },
308 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
309 "NVIDIA MCP79 Gigabit Ethernet" },
311 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
312 "NVIDIA MCP79 Gigabit Ethernet" },
314 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
315 "NVIDIA MCP79 Gigabit Ethernet" },
320 static device_method_t nfe_methods[] = {
321 /* Device interface */
322 DEVMETHOD(device_probe, nfe_probe),
323 DEVMETHOD(device_attach, nfe_attach),
324 DEVMETHOD(device_detach, nfe_detach),
325 DEVMETHOD(device_suspend, nfe_suspend),
326 DEVMETHOD(device_resume, nfe_resume),
327 DEVMETHOD(device_shutdown, nfe_shutdown),
330 DEVMETHOD(bus_print_child, bus_generic_print_child),
331 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
334 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
335 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
336 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
341 static driver_t nfe_driver = {
344 sizeof(struct nfe_softc)
347 static devclass_t nfe_devclass;
349 DECLARE_DUMMY_MODULE(if_nfe);
350 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
351 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
352 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
355 nfe_probe(device_t dev)
357 const struct nfe_dev *n;
360 vid = pci_get_vendor(dev);
361 did = pci_get_device(dev);
362 for (n = nfe_devices; n->desc != NULL; ++n) {
363 if (vid == n->vid && did == n->did) {
364 struct nfe_softc *sc = device_get_softc(dev);
367 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
368 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
369 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
370 sc->sc_caps = NFE_NO_PWRCTL |
373 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
374 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
375 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
376 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
377 sc->sc_caps = NFE_JUMBO_SUP |
382 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
383 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
384 sc->sc_caps = NFE_FIX_EADDR;
386 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
387 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
388 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
389 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
390 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
391 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
392 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
393 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
394 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
395 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
396 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
397 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
398 sc->sc_caps |= NFE_40BIT_ADDR;
400 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
401 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
402 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
403 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
404 sc->sc_caps = NFE_JUMBO_SUP |
410 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
411 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
412 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
413 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
414 sc->sc_caps = NFE_JUMBO_SUP |
417 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
418 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
419 sc->sc_caps = NFE_JUMBO_SUP |
425 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
426 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
427 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
428 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
429 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
430 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
431 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
432 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
433 sc->sc_caps = NFE_40BIT_ADDR |
438 device_set_desc(dev, n->desc);
439 device_set_async_attach(dev, TRUE);
447 nfe_attach(device_t dev)
449 struct nfe_softc *sc = device_get_softc(dev);
450 struct ifnet *ifp = &sc->arpcom.ac_if;
451 uint8_t eaddr[ETHER_ADDR_LEN];
455 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
456 lwkt_serialize_init(&sc->sc_jbuf_serializer);
459 * Initialize sysctl variables
461 sc->sc_rx_ring_count = nfe_rx_ring_count;
462 sc->sc_tx_ring_count = nfe_tx_ring_count;
463 sc->sc_debug = nfe_debug;
464 if (nfe_imtime < 0) {
465 sc->sc_flags |= NFE_F_DYN_IM;
466 sc->sc_imtime = -nfe_imtime;
468 sc->sc_imtime = nfe_imtime;
470 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
472 sc->sc_mem_rid = PCIR_BAR(0);
474 if (sc->sc_caps & NFE_40BIT_ADDR)
475 sc->rxtxctl_desc = NFE_RXTX_DESC_V3;
476 else if (sc->sc_caps & NFE_JUMBO_SUP)
477 sc->rxtxctl_desc = NFE_RXTX_DESC_V2;
480 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
483 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
484 irq = pci_read_config(dev, PCIR_INTLINE, 4);
486 device_printf(dev, "chip is in D%d power mode "
487 "-- setting to D0\n", pci_get_powerstate(dev));
489 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
491 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
492 pci_write_config(dev, PCIR_INTLINE, irq, 4);
494 #endif /* !BURN_BRIDGE */
496 /* Enable bus mastering */
497 pci_enable_busmaster(dev);
499 /* Allocate IO memory */
500 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
501 &sc->sc_mem_rid, RF_ACTIVE);
502 if (sc->sc_mem_res == NULL) {
503 device_printf(dev, "could not allocate io memory\n");
506 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
507 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
511 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
513 RF_SHAREABLE | RF_ACTIVE);
514 if (sc->sc_irq_res == NULL) {
515 device_printf(dev, "could not allocate irq\n");
521 NFE_WRITE(sc, NFE_WOL_CTL, 0);
523 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
526 nfe_get_macaddr(sc, eaddr);
529 * Allocate top level DMA tag
531 if (sc->sc_caps & NFE_40BIT_ADDR)
532 lowaddr = NFE_BUS_SPACE_MAXADDR;
534 lowaddr = BUS_SPACE_MAXADDR_32BIT;
535 error = bus_dma_tag_create(NULL, /* parent */
536 1, 0, /* alignment, boundary */
537 lowaddr, /* lowaddr */
538 BUS_SPACE_MAXADDR, /* highaddr */
539 NULL, NULL, /* filter, filterarg */
540 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
542 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
546 device_printf(dev, "could not allocate parent dma tag\n");
551 * Allocate Tx and Rx rings.
553 error = nfe_alloc_tx_ring(sc, &sc->txq);
555 device_printf(dev, "could not allocate Tx ring\n");
559 error = nfe_alloc_rx_ring(sc, &sc->rxq);
561 device_printf(dev, "could not allocate Rx ring\n");
568 sysctl_ctx_init(&sc->sc_sysctl_ctx);
569 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
570 SYSCTL_STATIC_CHILDREN(_hw),
572 device_get_nameunit(dev),
574 if (sc->sc_sysctl_tree == NULL) {
575 device_printf(dev, "can't add sysctl node\n");
579 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
580 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
581 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
582 sc, 0, nfe_sysctl_imtime, "I",
583 "Interrupt moderation time (usec). "
584 "0 to disable interrupt moderation.");
585 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
586 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
587 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
589 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
590 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
591 "tx_ring_count", CTLFLAG_RD, &sc->sc_tx_ring_count,
593 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
594 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
595 "debug", CTLFLAG_RW, &sc->sc_debug,
596 0, "control debugging printfs");
598 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
601 device_printf(dev, "MII without any phy\n");
606 ifp->if_mtu = ETHERMTU;
607 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
608 ifp->if_ioctl = nfe_ioctl;
609 ifp->if_start = nfe_start;
610 #ifdef DEVICE_POLLING
611 ifp->if_poll = nfe_poll;
613 ifp->if_watchdog = nfe_watchdog;
614 ifp->if_init = nfe_init;
615 ifq_set_maxlen(&ifp->if_snd, sc->sc_tx_ring_count);
616 ifq_set_ready(&ifp->if_snd);
618 ifp->if_capabilities = IFCAP_VLAN_MTU;
620 if (sc->sc_caps & NFE_HW_VLAN)
621 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
624 if (sc->sc_caps & NFE_HW_CSUM) {
625 ifp->if_capabilities |= IFCAP_HWCSUM;
626 ifp->if_hwassist = NFE_CSUM_FEATURES;
629 sc->sc_caps &= ~NFE_HW_CSUM;
631 ifp->if_capenable = ifp->if_capabilities;
633 callout_init(&sc->sc_tick_ch);
635 ether_ifattach(ifp, eaddr, NULL);
637 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
638 &sc->sc_ih, ifp->if_serializer);
640 device_printf(dev, "could not setup intr\n");
645 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
646 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
655 nfe_detach(device_t dev)
657 struct nfe_softc *sc = device_get_softc(dev);
659 if (device_is_attached(dev)) {
660 struct ifnet *ifp = &sc->arpcom.ac_if;
662 lwkt_serialize_enter(ifp->if_serializer);
664 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
665 lwkt_serialize_exit(ifp->if_serializer);
670 if (sc->sc_miibus != NULL)
671 device_delete_child(dev, sc->sc_miibus);
672 bus_generic_detach(dev);
674 if (sc->sc_sysctl_tree != NULL)
675 sysctl_ctx_free(&sc->sc_sysctl_ctx);
677 if (sc->sc_irq_res != NULL) {
678 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
682 if (sc->sc_mem_res != NULL) {
683 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
687 nfe_free_tx_ring(sc, &sc->txq);
688 nfe_free_rx_ring(sc, &sc->rxq);
689 if (sc->sc_dtag != NULL)
690 bus_dma_tag_destroy(sc->sc_dtag);
696 nfe_shutdown(device_t dev)
698 struct nfe_softc *sc = device_get_softc(dev);
699 struct ifnet *ifp = &sc->arpcom.ac_if;
701 lwkt_serialize_enter(ifp->if_serializer);
703 lwkt_serialize_exit(ifp->if_serializer);
707 nfe_suspend(device_t dev)
709 struct nfe_softc *sc = device_get_softc(dev);
710 struct ifnet *ifp = &sc->arpcom.ac_if;
712 lwkt_serialize_enter(ifp->if_serializer);
714 lwkt_serialize_exit(ifp->if_serializer);
720 nfe_resume(device_t dev)
722 struct nfe_softc *sc = device_get_softc(dev);
723 struct ifnet *ifp = &sc->arpcom.ac_if;
725 lwkt_serialize_enter(ifp->if_serializer);
726 if (ifp->if_flags & IFF_UP)
728 lwkt_serialize_exit(ifp->if_serializer);
734 nfe_miibus_statchg(device_t dev)
736 struct nfe_softc *sc = device_get_softc(dev);
737 struct mii_data *mii = device_get_softc(sc->sc_miibus);
738 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
740 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
742 phy = NFE_READ(sc, NFE_PHY_IFACE);
743 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
745 seed = NFE_READ(sc, NFE_RNDSEED);
746 seed &= ~NFE_SEED_MASK;
748 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
749 phy |= NFE_PHY_HDX; /* half-duplex */
750 misc |= NFE_MISC1_HDX;
753 switch (IFM_SUBTYPE(mii->mii_media_active)) {
754 case IFM_1000_T: /* full-duplex only */
755 link |= NFE_MEDIA_1000T;
756 seed |= NFE_SEED_1000T;
757 phy |= NFE_PHY_1000T;
760 link |= NFE_MEDIA_100TX;
761 seed |= NFE_SEED_100TX;
762 phy |= NFE_PHY_100TX;
765 link |= NFE_MEDIA_10T;
766 seed |= NFE_SEED_10T;
770 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
772 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
773 NFE_WRITE(sc, NFE_MISC1, misc);
774 NFE_WRITE(sc, NFE_LINKSPEED, link);
778 nfe_miibus_readreg(device_t dev, int phy, int reg)
780 struct nfe_softc *sc = device_get_softc(dev);
784 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
786 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
787 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
791 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
793 for (ntries = 0; ntries < 1000; ntries++) {
795 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
798 if (ntries == 1000) {
799 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
803 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
804 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
808 val = NFE_READ(sc, NFE_PHY_DATA);
809 if (val != 0xffffffff && val != 0)
810 sc->mii_phyaddr = phy;
812 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
818 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
820 struct nfe_softc *sc = device_get_softc(dev);
824 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
826 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
827 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
831 NFE_WRITE(sc, NFE_PHY_DATA, val);
832 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
833 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
835 for (ntries = 0; ntries < 1000; ntries++) {
837 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
843 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
847 #ifdef DEVICE_POLLING
850 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
852 struct nfe_softc *sc = ifp->if_softc;
854 ASSERT_SERIALIZED(ifp->if_serializer);
858 nfe_disable_intrs(sc);
861 case POLL_DEREGISTER:
862 nfe_enable_intrs(sc);
865 case POLL_AND_CHECK_STATUS:
868 if (ifp->if_flags & IFF_RUNNING) {
881 struct nfe_softc *sc = arg;
882 struct ifnet *ifp = &sc->arpcom.ac_if;
885 r = NFE_READ(sc, NFE_IRQ_STATUS);
887 return; /* not for us */
888 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
890 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
892 if (r & NFE_IRQ_LINK) {
893 NFE_READ(sc, NFE_PHY_STATUS);
894 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
895 DPRINTF(sc, "link state changed %s\n", "");
898 if (ifp->if_flags & IFF_RUNNING) {
905 ret |= nfe_txeof(sc, 1);
907 if (sc->sc_flags & NFE_F_DYN_IM) {
908 if (ret && (sc->sc_flags & NFE_F_IRQ_TIMER) == 0) {
910 * Assume that using hardware timer could reduce
911 * the interrupt rate.
913 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_IMTIMER);
914 sc->sc_flags |= NFE_F_IRQ_TIMER;
915 } else if (!ret && (sc->sc_flags & NFE_F_IRQ_TIMER)) {
917 * Nothing needs to be processed, fall back to
918 * use TX/RX interrupts.
920 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_NOIMTIMER);
921 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
924 * Recollect, mainly to avoid the possible race
925 * introduced by changing interrupt masks.
935 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
937 struct nfe_softc *sc = ifp->if_softc;
938 struct ifreq *ifr = (struct ifreq *)data;
939 struct mii_data *mii;
940 int error = 0, mask, jumbo_cap;
942 ASSERT_SERIALIZED(ifp->if_serializer);
946 if ((sc->sc_caps & NFE_JUMBO_SUP) && sc->rxq.jbuf != NULL)
951 if ((jumbo_cap && ifr->ifr_mtu > NFE_JUMBO_MTU) ||
952 (!jumbo_cap && ifr->ifr_mtu > ETHERMTU)) {
954 } else if (ifp->if_mtu != ifr->ifr_mtu) {
955 ifp->if_mtu = ifr->ifr_mtu;
956 if (ifp->if_flags & IFF_RUNNING)
961 if (ifp->if_flags & IFF_UP) {
963 * If only the PROMISC or ALLMULTI flag changes, then
964 * don't do a full re-init of the chip, just update
967 if ((ifp->if_flags & IFF_RUNNING) &&
968 ((ifp->if_flags ^ sc->sc_if_flags) &
969 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
972 if (!(ifp->if_flags & IFF_RUNNING))
976 if (ifp->if_flags & IFF_RUNNING)
979 sc->sc_if_flags = ifp->if_flags;
983 if (ifp->if_flags & IFF_RUNNING)
988 mii = device_get_softc(sc->sc_miibus);
989 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
992 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
993 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
994 ifp->if_capenable ^= mask;
995 if (IFCAP_TXCSUM & ifp->if_capenable)
996 ifp->if_hwassist = NFE_CSUM_FEATURES;
998 ifp->if_hwassist = 0;
1000 if (ifp->if_flags & IFF_RUNNING)
1005 error = ether_ioctl(ifp, cmd, data);
1012 nfe_rxeof(struct nfe_softc *sc)
1014 struct ifnet *ifp = &sc->arpcom.ac_if;
1015 struct nfe_rx_ring *ring = &sc->rxq;
1017 struct mbuf_chain chain[MAXCPU];
1020 ether_input_chain_init(chain);
1023 struct nfe_rx_data *data = &ring->data[ring->cur];
1028 if (sc->sc_caps & NFE_40BIT_ADDR) {
1029 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
1031 flags = le16toh(desc64->flags);
1032 len = le16toh(desc64->length) & 0x3fff;
1034 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
1036 flags = le16toh(desc32->flags);
1037 len = le16toh(desc32->length) & 0x3fff;
1040 if (flags & NFE_RX_READY)
1045 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1046 if (!(flags & NFE_RX_VALID_V1))
1049 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
1050 flags &= ~NFE_RX_ERROR;
1051 len--; /* fix buffer length */
1054 if (!(flags & NFE_RX_VALID_V2))
1057 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
1058 flags &= ~NFE_RX_ERROR;
1059 len--; /* fix buffer length */
1063 if (flags & NFE_RX_ERROR) {
1070 if (sc->sc_flags & NFE_F_USE_JUMBO)
1071 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
1073 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1080 m->m_pkthdr.len = m->m_len = len;
1081 m->m_pkthdr.rcvif = ifp;
1083 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1084 (flags & NFE_RX_CSUMOK)) {
1085 if (flags & NFE_RX_IP_CSUMOK_V2) {
1086 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1091 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1092 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1094 CSUM_FRAG_NOT_CHECKED;
1095 m->m_pkthdr.csum_data = 0xffff;
1100 ether_input_chain(ifp, m, NULL, chain);
1102 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1103 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1107 ether_input_dispatch(chain);
1112 nfe_txeof(struct nfe_softc *sc, int start)
1114 struct ifnet *ifp = &sc->arpcom.ac_if;
1115 struct nfe_tx_ring *ring = &sc->txq;
1116 struct nfe_tx_data *data = NULL;
1118 while (ring->next != ring->cur) {
1121 if (sc->sc_caps & NFE_40BIT_ADDR)
1122 flags = le16toh(ring->desc64[ring->next].flags);
1124 flags = le16toh(ring->desc32[ring->next].flags);
1126 if (flags & NFE_TX_VALID)
1129 data = &ring->data[ring->next];
1131 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1132 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1135 if ((flags & NFE_TX_ERROR_V1) != 0) {
1136 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1143 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1146 if ((flags & NFE_TX_ERROR_V2) != 0) {
1147 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1155 if (data->m == NULL) { /* should not get there */
1157 "last fragment bit w/o associated mbuf!\n");
1161 /* last fragment of the mbuf chain transmitted */
1162 bus_dmamap_unload(ring->data_tag, data->map);
1167 KKASSERT(ring->queued >= 0);
1168 ring->next = (ring->next + 1) % sc->sc_tx_ring_count;
1171 if (sc->sc_tx_ring_count - ring->queued >=
1172 sc->sc_tx_spare + NFE_NSEG_RSVD)
1173 ifp->if_flags &= ~IFF_OACTIVE;
1175 if (ring->queued == 0)
1178 if (start && !ifq_is_empty(&ifp->if_snd))
1188 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1190 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1191 struct nfe_tx_data *data, *data_map;
1193 struct nfe_desc64 *desc64 = NULL;
1194 struct nfe_desc32 *desc32 = NULL;
1197 int error, i, j, maxsegs, nsegs;
1199 data = &ring->data[ring->cur];
1201 data_map = data; /* Remember who owns the DMA map */
1203 maxsegs = (sc->sc_tx_ring_count - ring->queued) - NFE_NSEG_RSVD;
1204 if (maxsegs > NFE_MAX_SCATTER)
1205 maxsegs = NFE_MAX_SCATTER;
1206 KASSERT(maxsegs >= sc->sc_tx_spare,
1207 ("no enough segments %d,%d\n", maxsegs, sc->sc_tx_spare));
1209 error = bus_dmamap_load_mbuf_defrag(ring->data_tag, map, &m0,
1210 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1213 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1217 /* setup h/w VLAN tagging */
1218 if (m0->m_flags & M_VLANTAG)
1219 vtag = m0->m_pkthdr.ether_vlantag;
1221 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1222 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1223 flags |= NFE_TX_IP_CSUM;
1224 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1225 flags |= NFE_TX_TCP_CSUM;
1229 * XXX urm. somebody is unaware of how hardware works. You
1230 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1231 * the ring until the entire chain is actually *VALID*. Otherwise
1232 * the hardware may encounter a partially initialized chain that
1233 * is marked as being ready to go when it in fact is not ready to
1237 for (i = 0; i < nsegs; i++) {
1238 j = (ring->cur + i) % sc->sc_tx_ring_count;
1239 data = &ring->data[j];
1241 if (sc->sc_caps & NFE_40BIT_ADDR) {
1242 desc64 = &ring->desc64[j];
1243 desc64->physaddr[0] =
1244 htole32(NFE_ADDR_HI(segs[i].ds_addr));
1245 desc64->physaddr[1] =
1246 htole32(NFE_ADDR_LO(segs[i].ds_addr));
1247 desc64->length = htole16(segs[i].ds_len - 1);
1248 desc64->vtag = htole32(vtag);
1249 desc64->flags = htole16(flags);
1251 desc32 = &ring->desc32[j];
1252 desc32->physaddr = htole32(segs[i].ds_addr);
1253 desc32->length = htole16(segs[i].ds_len - 1);
1254 desc32->flags = htole16(flags);
1257 /* csum flags and vtag belong to the first fragment only */
1258 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1262 KKASSERT(ring->queued <= sc->sc_tx_ring_count);
1265 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1266 if (sc->sc_caps & NFE_40BIT_ADDR) {
1267 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1269 if (sc->sc_caps & NFE_JUMBO_SUP)
1270 flags = NFE_TX_LASTFRAG_V2;
1272 flags = NFE_TX_LASTFRAG_V1;
1273 desc32->flags |= htole16(flags);
1277 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1278 * whole mess until the first descriptor in the map is flagged.
1280 for (i = nsegs - 1; i >= 0; --i) {
1281 j = (ring->cur + i) % sc->sc_tx_ring_count;
1282 if (sc->sc_caps & NFE_40BIT_ADDR) {
1283 desc64 = &ring->desc64[j];
1284 desc64->flags |= htole16(NFE_TX_VALID);
1286 desc32 = &ring->desc32[j];
1287 desc32->flags |= htole16(NFE_TX_VALID);
1290 ring->cur = (ring->cur + nsegs) % sc->sc_tx_ring_count;
1292 /* Exchange DMA map */
1293 data_map->map = data->map;
1303 nfe_start(struct ifnet *ifp)
1305 struct nfe_softc *sc = ifp->if_softc;
1306 struct nfe_tx_ring *ring = &sc->txq;
1307 int count = 0, oactive = 0;
1310 ASSERT_SERIALIZED(ifp->if_serializer);
1312 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1318 if (sc->sc_tx_ring_count - ring->queued <
1319 sc->sc_tx_spare + NFE_NSEG_RSVD) {
1321 ifp->if_flags |= IFF_OACTIVE;
1330 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1334 ETHER_BPF_MTAP(ifp, m0);
1336 error = nfe_encap(sc, ring, m0);
1339 if (error == EFBIG) {
1341 ifp->if_flags |= IFF_OACTIVE;
1355 * `m0' may be freed in nfe_encap(), so
1356 * it should not be touched any more.
1360 if (count == 0) /* nothing sent */
1364 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1367 * Set a timeout in case the chip goes out to lunch.
1373 nfe_watchdog(struct ifnet *ifp)
1375 struct nfe_softc *sc = ifp->if_softc;
1377 ASSERT_SERIALIZED(ifp->if_serializer);
1379 if (ifp->if_flags & IFF_RUNNING) {
1380 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1385 if_printf(ifp, "watchdog timeout\n");
1387 nfe_init(ifp->if_softc);
1395 struct nfe_softc *sc = xsc;
1396 struct ifnet *ifp = &sc->arpcom.ac_if;
1400 ASSERT_SERIALIZED(ifp->if_serializer);
1404 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
1409 * Switching between jumbo frames and normal frames should
1410 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1412 if (ifp->if_mtu > ETHERMTU) {
1413 sc->sc_flags |= NFE_F_USE_JUMBO;
1414 sc->rxq.bufsz = NFE_JBYTES;
1415 sc->sc_tx_spare = NFE_NSEG_SPARE_JUMBO;
1417 if_printf(ifp, "use jumbo frames\n");
1419 sc->sc_flags &= ~NFE_F_USE_JUMBO;
1420 sc->rxq.bufsz = MCLBYTES;
1421 sc->sc_tx_spare = NFE_NSEG_SPARE;
1423 if_printf(ifp, "use non-jumbo frames\n");
1426 error = nfe_init_tx_ring(sc, &sc->txq);
1432 error = nfe_init_rx_ring(sc, &sc->rxq);
1438 NFE_WRITE(sc, NFE_TX_POLL, 0);
1439 NFE_WRITE(sc, NFE_STATUS, 0);
1441 sc->rxtxctl = NFE_RXTX_BIT2 | sc->rxtxctl_desc;
1443 if (ifp->if_capenable & IFCAP_RXCSUM)
1444 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1447 * Although the adapter is capable of stripping VLAN tags from received
1448 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1449 * purpose. This will be done in software by our network stack.
1451 if (sc->sc_caps & NFE_HW_VLAN)
1452 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1454 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1456 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1458 if (sc->sc_caps & NFE_HW_VLAN)
1459 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1461 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1463 /* set MAC address */
1464 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1466 /* tell MAC where rings are in memory */
1467 if (sc->sc_caps & NFE_40BIT_ADDR) {
1468 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
1469 NFE_ADDR_HI(sc->rxq.physaddr));
1471 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, NFE_ADDR_LO(sc->rxq.physaddr));
1473 if (sc->sc_caps & NFE_40BIT_ADDR) {
1474 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI,
1475 NFE_ADDR_HI(sc->txq.physaddr));
1477 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr));
1479 NFE_WRITE(sc, NFE_RING_SIZE,
1480 (sc->sc_rx_ring_count - 1) << 16 |
1481 (sc->sc_tx_ring_count - 1));
1483 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1485 /* force MAC to wakeup */
1486 tmp = NFE_READ(sc, NFE_PWR_STATE);
1487 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1489 tmp = NFE_READ(sc, NFE_PWR_STATE);
1490 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1492 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1493 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1494 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1496 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1497 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1499 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1501 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1502 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1504 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1509 nfe_ifmedia_upd(ifp);
1512 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1515 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1517 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1519 #ifdef DEVICE_POLLING
1520 if ((ifp->if_flags & IFF_POLLING))
1521 nfe_disable_intrs(sc);
1524 nfe_enable_intrs(sc);
1526 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1528 ifp->if_flags |= IFF_RUNNING;
1529 ifp->if_flags &= ~IFF_OACTIVE;
1532 * If we had stuff in the tx ring before its all cleaned out now
1533 * so we are not going to get an interrupt, jump-start any pending
1536 if (!ifq_is_empty(&ifp->if_snd))
1541 nfe_stop(struct nfe_softc *sc)
1543 struct ifnet *ifp = &sc->arpcom.ac_if;
1544 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
1547 ASSERT_SERIALIZED(ifp->if_serializer);
1549 callout_stop(&sc->sc_tick_ch);
1552 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1553 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
1555 #define WAITMAX 50000
1560 NFE_WRITE(sc, NFE_TX_CTL, 0);
1561 for (i = 0; i < WAITMAX; ++i) {
1563 if ((NFE_READ(sc, NFE_TX_STATUS) & NFE_TX_STATUS_BUSY) == 0)
1567 if_printf(ifp, "can't stop TX\n");
1573 NFE_WRITE(sc, NFE_RX_CTL, 0);
1574 for (i = 0; i < WAITMAX; ++i) {
1576 if ((NFE_READ(sc, NFE_RX_STATUS) & NFE_RX_STATUS_BUSY) == 0)
1580 if_printf(ifp, "can't stop RX\n");
1585 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
1587 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
1589 /* Disable interrupts */
1590 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1592 /* Reset Tx and Rx rings */
1593 nfe_reset_tx_ring(sc, &sc->txq);
1594 nfe_reset_rx_ring(sc, &sc->rxq);
1598 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1600 int i, j, error, descsize;
1604 if (sc->sc_caps & NFE_40BIT_ADDR) {
1605 desc = (void **)&ring->desc64;
1606 descsize = sizeof(struct nfe_desc64);
1608 desc = (void **)&ring->desc32;
1609 descsize = sizeof(struct nfe_desc32);
1612 ring->bufsz = MCLBYTES;
1613 ring->cur = ring->next = 0;
1615 error = bus_dmamem_coherent(sc->sc_dtag, PAGE_SIZE, 0,
1616 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1617 sc->sc_rx_ring_count * descsize,
1618 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1620 if_printf(&sc->arpcom.ac_if,
1621 "could not create RX desc ring\n");
1624 ring->tag = dmem.dmem_tag;
1625 ring->map = dmem.dmem_map;
1626 *desc = dmem.dmem_addr;
1627 ring->physaddr = dmem.dmem_busaddr;
1629 if (sc->sc_caps & NFE_JUMBO_SUP) {
1631 kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT(sc),
1632 M_DEVBUF, M_WAITOK | M_ZERO);
1634 error = nfe_jpool_alloc(sc, ring);
1636 if_printf(&sc->arpcom.ac_if,
1637 "could not allocate jumbo frames\n");
1638 kfree(ring->jbuf, M_DEVBUF);
1640 /* Allow jumbo frame allocation to fail */
1644 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1645 M_DEVBUF, M_WAITOK | M_ZERO);
1647 error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
1648 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1650 MCLBYTES, 1, MCLBYTES,
1651 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
1654 if_printf(&sc->arpcom.ac_if,
1655 "could not create RX mbuf DMA tag\n");
1659 /* Create a spare RX mbuf DMA map */
1660 error = bus_dmamap_create(ring->data_tag, BUS_DMA_WAITOK,
1661 &ring->data_tmpmap);
1663 if_printf(&sc->arpcom.ac_if,
1664 "could not create spare RX mbuf DMA map\n");
1665 bus_dma_tag_destroy(ring->data_tag);
1666 ring->data_tag = NULL;
1670 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1671 error = bus_dmamap_create(ring->data_tag, BUS_DMA_WAITOK,
1672 &ring->data[i].map);
1674 if_printf(&sc->arpcom.ac_if,
1675 "could not create %dth RX mbuf DMA mapn", i);
1681 for (j = 0; j < i; ++j)
1682 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1683 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1684 bus_dma_tag_destroy(ring->data_tag);
1685 ring->data_tag = NULL;
1690 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1694 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1695 struct nfe_rx_data *data = &ring->data[i];
1697 if (data->m != NULL) {
1698 if ((sc->sc_flags & NFE_F_USE_JUMBO) == 0)
1699 bus_dmamap_unload(ring->data_tag, data->map);
1705 ring->cur = ring->next = 0;
1709 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1713 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1716 /* XXX should use a function pointer */
1717 if (sc->sc_flags & NFE_F_USE_JUMBO)
1718 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1720 error = nfe_newbuf_std(sc, ring, i, 1);
1722 if_printf(&sc->arpcom.ac_if,
1723 "could not allocate RX buffer\n");
1726 nfe_set_ready_rxdesc(sc, ring, i);
1732 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1734 if (ring->data_tag != NULL) {
1735 struct nfe_rx_data *data;
1738 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1739 data = &ring->data[i];
1741 if (data->m != NULL) {
1742 bus_dmamap_unload(ring->data_tag, data->map);
1745 bus_dmamap_destroy(ring->data_tag, data->map);
1747 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1748 bus_dma_tag_destroy(ring->data_tag);
1751 nfe_jpool_free(sc, ring);
1753 if (ring->jbuf != NULL)
1754 kfree(ring->jbuf, M_DEVBUF);
1755 if (ring->data != NULL)
1756 kfree(ring->data, M_DEVBUF);
1758 if (ring->tag != NULL) {
1761 if (sc->sc_caps & NFE_40BIT_ADDR)
1762 desc = ring->desc64;
1764 desc = ring->desc32;
1766 bus_dmamap_unload(ring->tag, ring->map);
1767 bus_dmamem_free(ring->tag, desc, ring->map);
1768 bus_dma_tag_destroy(ring->tag);
1772 static struct nfe_jbuf *
1773 nfe_jalloc(struct nfe_softc *sc)
1775 struct ifnet *ifp = &sc->arpcom.ac_if;
1776 struct nfe_jbuf *jbuf;
1778 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1780 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1782 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1785 if_printf(ifp, "no free jumbo buffer\n");
1788 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1794 nfe_jfree(void *arg)
1796 struct nfe_jbuf *jbuf = arg;
1797 struct nfe_softc *sc = jbuf->sc;
1798 struct nfe_rx_ring *ring = jbuf->ring;
1800 if (&ring->jbuf[jbuf->slot] != jbuf)
1801 panic("%s: free wrong jumbo buffer\n", __func__);
1802 else if (jbuf->inuse == 0)
1803 panic("%s: jumbo buffer already freed\n", __func__);
1805 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1806 atomic_subtract_int(&jbuf->inuse, 1);
1807 if (jbuf->inuse == 0)
1808 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1809 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1815 struct nfe_jbuf *jbuf = arg;
1816 struct nfe_rx_ring *ring = jbuf->ring;
1818 if (&ring->jbuf[jbuf->slot] != jbuf)
1819 panic("%s: ref wrong jumbo buffer\n", __func__);
1820 else if (jbuf->inuse == 0)
1821 panic("%s: jumbo buffer already freed\n", __func__);
1823 atomic_add_int(&jbuf->inuse, 1);
1827 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1829 struct nfe_jbuf *jbuf;
1831 bus_addr_t physaddr;
1836 * Allocate a big chunk of DMA'able memory.
1838 error = bus_dmamem_coherent(sc->sc_dtag, PAGE_SIZE, 0,
1839 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1841 BUS_DMA_WAITOK, &dmem);
1843 if_printf(&sc->arpcom.ac_if,
1844 "could not create jumbo buffer\n");
1847 ring->jtag = dmem.dmem_tag;
1848 ring->jmap = dmem.dmem_map;
1849 ring->jpool = dmem.dmem_addr;
1850 physaddr = dmem.dmem_busaddr;
1852 /* ..and split it into 9KB chunks */
1853 SLIST_INIT(&ring->jfreelist);
1856 for (i = 0; i < NFE_JPOOL_COUNT(sc); i++) {
1857 jbuf = &ring->jbuf[i];
1864 jbuf->physaddr = physaddr;
1866 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1869 physaddr += NFE_JBYTES;
1876 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1878 if (ring->jtag != NULL) {
1879 bus_dmamap_unload(ring->jtag, ring->jmap);
1880 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1881 bus_dma_tag_destroy(ring->jtag);
1886 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1888 int i, j, error, descsize;
1892 if (sc->sc_caps & NFE_40BIT_ADDR) {
1893 desc = (void **)&ring->desc64;
1894 descsize = sizeof(struct nfe_desc64);
1896 desc = (void **)&ring->desc32;
1897 descsize = sizeof(struct nfe_desc32);
1901 ring->cur = ring->next = 0;
1903 error = bus_dmamem_coherent(sc->sc_dtag, PAGE_SIZE, 0,
1904 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1905 sc->sc_tx_ring_count * descsize,
1906 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1908 if_printf(&sc->arpcom.ac_if,
1909 "could not create TX desc ring\n");
1912 ring->tag = dmem.dmem_tag;
1913 ring->map = dmem.dmem_map;
1914 *desc = dmem.dmem_addr;
1915 ring->physaddr = dmem.dmem_busaddr;
1917 ring->data = kmalloc(sizeof(struct nfe_tx_data) * sc->sc_tx_ring_count,
1918 M_DEVBUF, M_WAITOK | M_ZERO);
1920 error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
1921 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1923 NFE_JBYTES, NFE_MAX_SCATTER, MCLBYTES,
1924 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1927 if_printf(&sc->arpcom.ac_if,
1928 "could not create TX buf DMA tag\n");
1932 for (i = 0; i < sc->sc_tx_ring_count; i++) {
1933 error = bus_dmamap_create(ring->data_tag,
1934 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1935 &ring->data[i].map);
1937 if_printf(&sc->arpcom.ac_if,
1938 "could not create %dth TX buf DMA map\n", i);
1945 for (j = 0; j < i; ++j)
1946 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1947 bus_dma_tag_destroy(ring->data_tag);
1948 ring->data_tag = NULL;
1953 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1957 for (i = 0; i < sc->sc_tx_ring_count; i++) {
1958 struct nfe_tx_data *data = &ring->data[i];
1960 if (sc->sc_caps & NFE_40BIT_ADDR)
1961 ring->desc64[i].flags = 0;
1963 ring->desc32[i].flags = 0;
1965 if (data->m != NULL) {
1966 bus_dmamap_unload(ring->data_tag, data->map);
1973 ring->cur = ring->next = 0;
1977 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1978 struct nfe_tx_ring *ring __unused)
1984 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1986 if (ring->data_tag != NULL) {
1987 struct nfe_tx_data *data;
1990 for (i = 0; i < sc->sc_tx_ring_count; ++i) {
1991 data = &ring->data[i];
1993 if (data->m != NULL) {
1994 bus_dmamap_unload(ring->data_tag, data->map);
1997 bus_dmamap_destroy(ring->data_tag, data->map);
2000 bus_dma_tag_destroy(ring->data_tag);
2003 if (ring->data != NULL)
2004 kfree(ring->data, M_DEVBUF);
2006 if (ring->tag != NULL) {
2009 if (sc->sc_caps & NFE_40BIT_ADDR)
2010 desc = ring->desc64;
2012 desc = ring->desc32;
2014 bus_dmamap_unload(ring->tag, ring->map);
2015 bus_dmamem_free(ring->tag, desc, ring->map);
2016 bus_dma_tag_destroy(ring->tag);
2021 nfe_ifmedia_upd(struct ifnet *ifp)
2023 struct nfe_softc *sc = ifp->if_softc;
2024 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2026 ASSERT_SERIALIZED(ifp->if_serializer);
2028 if (mii->mii_instance != 0) {
2029 struct mii_softc *miisc;
2031 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2032 mii_phy_reset(miisc);
2040 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2042 struct nfe_softc *sc = ifp->if_softc;
2043 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2045 ASSERT_SERIALIZED(ifp->if_serializer);
2048 ifmr->ifm_status = mii->mii_media_status;
2049 ifmr->ifm_active = mii->mii_media_active;
2053 nfe_setmulti(struct nfe_softc *sc)
2055 struct ifnet *ifp = &sc->arpcom.ac_if;
2056 struct ifmultiaddr *ifma;
2057 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2058 uint32_t filter = NFE_RXFILTER_MAGIC;
2061 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2062 bzero(addr, ETHER_ADDR_LEN);
2063 bzero(mask, ETHER_ADDR_LEN);
2067 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2068 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2070 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2073 if (ifma->ifma_addr->sa_family != AF_LINK)
2076 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2077 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2078 addr[i] &= maddr[i];
2079 mask[i] &= ~maddr[i];
2083 for (i = 0; i < ETHER_ADDR_LEN; i++)
2087 addr[0] |= 0x01; /* make sure multicast bit is set */
2089 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2090 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2091 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2092 addr[5] << 8 | addr[4]);
2093 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2094 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2095 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2096 mask[5] << 8 | mask[4]);
2098 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2099 NFE_WRITE(sc, NFE_RXFILTER, filter);
2103 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2107 lo = NFE_READ(sc, NFE_MACADDR_LO);
2108 hi = NFE_READ(sc, NFE_MACADDR_HI);
2109 if (sc->sc_caps & NFE_FIX_EADDR) {
2110 addr[0] = (lo >> 8) & 0xff;
2111 addr[1] = (lo & 0xff);
2113 addr[2] = (hi >> 24) & 0xff;
2114 addr[3] = (hi >> 16) & 0xff;
2115 addr[4] = (hi >> 8) & 0xff;
2116 addr[5] = (hi & 0xff);
2118 addr[0] = (hi & 0xff);
2119 addr[1] = (hi >> 8) & 0xff;
2120 addr[2] = (hi >> 16) & 0xff;
2121 addr[3] = (hi >> 24) & 0xff;
2123 addr[4] = (lo & 0xff);
2124 addr[5] = (lo >> 8) & 0xff;
2129 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2131 NFE_WRITE(sc, NFE_MACADDR_LO,
2132 addr[5] << 8 | addr[4]);
2133 NFE_WRITE(sc, NFE_MACADDR_HI,
2134 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2140 struct nfe_softc *sc = arg;
2141 struct ifnet *ifp = &sc->arpcom.ac_if;
2142 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2144 lwkt_serialize_enter(ifp->if_serializer);
2147 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2149 lwkt_serialize_exit(ifp->if_serializer);
2153 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2156 struct nfe_rx_data *data = &ring->data[idx];
2157 bus_dma_segment_t seg;
2162 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2165 m->m_len = m->m_pkthdr.len = MCLBYTES;
2167 error = bus_dmamap_load_mbuf_segment(ring->data_tag, ring->data_tmpmap,
2168 m, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
2172 if_printf(&sc->arpcom.ac_if,
2173 "could map RX mbuf %d\n", error);
2178 if (data->m != NULL) {
2179 /* Sync and unload originally mapped mbuf */
2180 bus_dmamap_sync(ring->data_tag, data->map,
2181 BUS_DMASYNC_POSTREAD);
2182 bus_dmamap_unload(ring->data_tag, data->map);
2185 /* Swap this DMA map with tmp DMA map */
2187 data->map = ring->data_tmpmap;
2188 ring->data_tmpmap = map;
2190 /* Caller is assumed to have collected the old mbuf */
2193 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2198 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2201 struct nfe_rx_data *data = &ring->data[idx];
2202 struct nfe_jbuf *jbuf;
2205 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2209 jbuf = nfe_jalloc(sc);
2212 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2213 "-- packet dropped!\n");
2217 m->m_ext.ext_arg = jbuf;
2218 m->m_ext.ext_buf = jbuf->buf;
2219 m->m_ext.ext_free = nfe_jfree;
2220 m->m_ext.ext_ref = nfe_jref;
2221 m->m_ext.ext_size = NFE_JBYTES;
2223 m->m_data = m->m_ext.ext_buf;
2224 m->m_flags |= M_EXT;
2225 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2227 /* Caller is assumed to have collected the old mbuf */
2230 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2235 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2236 bus_addr_t physaddr)
2238 if (sc->sc_caps & NFE_40BIT_ADDR) {
2239 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2241 desc64->physaddr[0] = htole32(NFE_ADDR_HI(physaddr));
2242 desc64->physaddr[1] = htole32(NFE_ADDR_LO(physaddr));
2244 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2246 desc32->physaddr = htole32(physaddr);
2251 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2253 if (sc->sc_caps & NFE_40BIT_ADDR) {
2254 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2256 desc64->length = htole16(ring->bufsz);
2257 desc64->flags = htole16(NFE_RX_READY);
2259 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2261 desc32->length = htole16(ring->bufsz);
2262 desc32->flags = htole16(NFE_RX_READY);
2267 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2269 struct nfe_softc *sc = arg1;
2270 struct ifnet *ifp = &sc->arpcom.ac_if;
2274 lwkt_serialize_enter(ifp->if_serializer);
2276 flags = sc->sc_flags & ~NFE_F_DYN_IM;
2278 if (sc->sc_flags & NFE_F_DYN_IM)
2281 error = sysctl_handle_int(oidp, &v, 0, req);
2282 if (error || req->newptr == NULL)
2286 flags |= NFE_F_DYN_IM;
2290 if (v != sc->sc_imtime || (flags ^ sc->sc_flags)) {
2291 int old_imtime = sc->sc_imtime;
2292 uint32_t old_flags = sc->sc_flags;
2295 sc->sc_flags = flags;
2296 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2298 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2300 if (old_imtime * sc->sc_imtime == 0 ||
2301 (old_flags ^ sc->sc_flags)) {
2304 NFE_WRITE(sc, NFE_IMTIMER,
2305 NFE_IMTIME(sc->sc_imtime));
2310 lwkt_serialize_exit(ifp->if_serializer);
2315 nfe_powerup(device_t dev)
2317 struct nfe_softc *sc = device_get_softc(dev);
2322 * Bring MAC and PHY out of low power state
2325 pwr_state = NFE_READ(sc, NFE_PWR_STATE2) & ~NFE_PWRUP_MASK;
2327 did = pci_get_device(dev);
2328 if ((did == PCI_PRODUCT_NVIDIA_MCP51_LAN1 ||
2329 did == PCI_PRODUCT_NVIDIA_MCP51_LAN2) &&
2330 pci_get_revid(dev) >= 0xa3)
2331 pwr_state |= NFE_PWRUP_REV_A3;
2333 NFE_WRITE(sc, NFE_PWR_STATE2, pwr_state);
2337 nfe_mac_reset(struct nfe_softc *sc)
2339 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
2340 uint32_t macaddr_hi, macaddr_lo, tx_poll;
2342 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
2344 /* Save several registers for later restoration */
2345 macaddr_hi = NFE_READ(sc, NFE_MACADDR_HI);
2346 macaddr_lo = NFE_READ(sc, NFE_MACADDR_LO);
2347 tx_poll = NFE_READ(sc, NFE_TX_POLL);
2349 NFE_WRITE(sc, NFE_MAC_RESET, NFE_RESET_ASSERT);
2352 NFE_WRITE(sc, NFE_MAC_RESET, 0);
2355 /* Restore saved registers */
2356 NFE_WRITE(sc, NFE_MACADDR_HI, macaddr_hi);
2357 NFE_WRITE(sc, NFE_MACADDR_LO, macaddr_lo);
2358 NFE_WRITE(sc, NFE_TX_POLL, tx_poll);
2360 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
2364 nfe_enable_intrs(struct nfe_softc *sc)
2367 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
2368 * It is unclear how wide the timer is. Base programming does
2369 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
2370 * we don't get any interrupt moderation. TX moderation is
2371 * possible by using the timer interrupt instead of TX_DONE.
2373 * It is unclear whether there are other bits that can be
2374 * set to make the NFE device actually do interrupt moderation
2377 * For now set a 128uS interval as a placemark, but don't use
2380 if (sc->sc_imtime == 0)
2381 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
2383 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
2385 /* Enable interrupts */
2386 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
2388 if (sc->sc_irq_enable & NFE_IRQ_TIMER)
2389 sc->sc_flags |= NFE_F_IRQ_TIMER;
2391 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
2395 nfe_disable_intrs(struct nfe_softc *sc)
2397 /* Disable interrupts */
2398 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
2399 sc->sc_flags &= ~NFE_F_IRQ_TIMER;