2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/i386/i386/initcpu.c,v 1.19.2.9 2003/04/05 13:47:19 dwmalone Exp $
30 * $DragonFly: src/sys/platform/pc32/i386/initcpu.c,v 1.10 2006/12/23 00:27:03 swildner Exp $
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
44 void initializecpu(void);
45 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
46 void enable_K5_wt_alloc(void);
47 void enable_K6_wt_alloc(void);
48 void enable_K6_2_wt_alloc(void);
52 static void init_5x86(void);
53 static void init_bluelightning(void);
54 static void init_486dlc(void);
55 static void init_cy486dx(void);
56 #ifdef CPU_I486_ON_386
57 static void init_i486_on_386(void);
59 static void init_6x86(void);
63 static void init_6x86MX(void);
64 static void init_ppro(void);
65 static void init_mendocino(void);
68 static int hw_instruction_sse;
69 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
70 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
72 #ifndef CPU_DISABLE_SSE
73 u_int cpu_fxsr; /* SSE enabled */
81 init_bluelightning(void)
85 eflags = read_eflags();
88 load_cr0(rcr0() | CR0_CD | CR0_NW);
91 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
92 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
94 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
96 /* Enables 13MB and 0-640KB cache. */
97 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
98 #ifdef CPU_BLUELIGHTNING_3X
99 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
101 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
104 /* Enable caching in CR0. */
105 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
107 write_eflags(eflags);
111 * Cyrix 486SLC/DLC/SR/DR series
119 eflags = read_eflags();
123 ccr0 = read_cyrix_reg(CCR0);
124 #ifndef CYRIX_CACHE_WORKS
125 ccr0 |= CCR0_NC1 | CCR0_BARB;
126 write_cyrix_reg(CCR0, ccr0);
130 #ifndef CYRIX_CACHE_REALLY_WORKS
131 ccr0 |= CCR0_NC1 | CCR0_BARB;
135 #ifdef CPU_DIRECT_MAPPED_CACHE
136 ccr0 |= CCR0_CO; /* Direct mapped mode. */
138 write_cyrix_reg(CCR0, ccr0);
140 /* Clear non-cacheable region. */
141 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
142 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
143 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
144 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
146 write_cyrix_reg(0, 0); /* dummy write */
148 /* Enable caching in CR0. */
149 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
151 #endif /* !CYRIX_CACHE_WORKS */
152 write_eflags(eflags);
157 * Cyrix 486S/DX series
165 eflags = read_eflags();
169 ccr2 = read_cyrix_reg(CCR2);
171 ccr2 |= CCR2_SUSP_HLT;
174 write_cyrix_reg(CCR2, ccr2);
175 write_eflags(eflags);
186 u_char ccr2, ccr3, ccr4, pcr0;
188 eflags = read_eflags();
191 load_cr0(rcr0() | CR0_CD | CR0_NW);
194 read_cyrix_reg(CCR3); /* dummy */
196 /* Initialize CCR2. */
197 ccr2 = read_cyrix_reg(CCR2);
200 ccr2 |= CCR2_SUSP_HLT;
202 ccr2 &= ~CCR2_SUSP_HLT;
205 write_cyrix_reg(CCR2, ccr2);
207 /* Initialize CCR4. */
208 ccr3 = read_cyrix_reg(CCR3);
209 write_cyrix_reg(CCR3, CCR3_MAPEN0);
211 ccr4 = read_cyrix_reg(CCR4);
214 #ifdef CPU_FASTER_5X86_FPU
215 ccr4 |= CCR4_FASTFPE;
217 ccr4 &= ~CCR4_FASTFPE;
219 ccr4 &= ~CCR4_IOMASK;
220 /********************************************************************
221 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
222 * should be 0 for errata fix.
223 ********************************************************************/
225 ccr4 |= CPU_IORT & CCR4_IOMASK;
227 write_cyrix_reg(CCR4, ccr4);
229 /* Initialize PCR0. */
230 /****************************************************************
231 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
232 * BTB_EN might make your system unstable.
233 ****************************************************************/
234 pcr0 = read_cyrix_reg(PCR0);
251 /****************************************************************
252 * WARNING: if you use a memory mapped I/O device, don't use
253 * DISABLE_5X86_LSSER option, which may reorder memory mapped
255 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
256 ****************************************************************/
257 #ifdef CPU_DISABLE_5X86_LSSER
262 write_cyrix_reg(PCR0, pcr0);
265 write_cyrix_reg(CCR3, ccr3);
267 read_cyrix_reg(0x80); /* dummy */
269 /* Unlock NW bit in CR0. */
270 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
271 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
272 /* Lock NW bit in CR0. */
273 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
275 write_eflags(eflags);
278 #ifdef CPU_I486_ON_386
280 * There are i486 based upgrade products for i386 machines.
281 * In this case, BIOS doesn't enables CPU cache.
284 init_i486_on_386(void)
288 eflags = read_eflags();
291 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
293 write_eflags(eflags);
300 * XXX - What should I do here? Please let me know.
308 eflags = read_eflags();
311 load_cr0(rcr0() | CR0_CD | CR0_NW);
314 /* Initialize CCR0. */
315 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
317 /* Initialize CCR1. */
318 #ifdef CPU_CYRIX_NO_LOCK
319 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
321 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
324 /* Initialize CCR2. */
326 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
328 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
331 ccr3 = read_cyrix_reg(CCR3);
332 write_cyrix_reg(CCR3, CCR3_MAPEN0);
334 /* Initialize CCR4. */
335 ccr4 = read_cyrix_reg(CCR4);
337 ccr4 &= ~CCR4_IOMASK;
339 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
341 write_cyrix_reg(CCR4, ccr4 | 7);
344 /* Initialize CCR5. */
346 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
350 write_cyrix_reg(CCR3, ccr3);
352 /* Unlock NW bit in CR0. */
353 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
356 * Earlier revision of the 6x86 CPU could crash the system if
357 * L1 cache is in write-back mode.
359 if ((cyrix_did & 0xff00) > 0x1600)
360 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
362 /* Revision 2.6 and lower. */
363 #ifdef CYRIX_CACHE_REALLY_WORKS
364 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
366 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
370 /* Lock NW bit in CR0. */
371 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
373 write_eflags(eflags);
375 #endif /* I486_CPU */
379 * Cyrix 6x86MX (code-named M2)
381 * XXX - What should I do here? Please let me know.
389 eflags = read_eflags();
392 load_cr0(rcr0() | CR0_CD | CR0_NW);
395 /* Initialize CCR0. */
396 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
398 /* Initialize CCR1. */
399 #ifdef CPU_CYRIX_NO_LOCK
400 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
402 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
405 /* Initialize CCR2. */
407 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
409 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
412 ccr3 = read_cyrix_reg(CCR3);
413 write_cyrix_reg(CCR3, CCR3_MAPEN0);
415 /* Initialize CCR4. */
416 ccr4 = read_cyrix_reg(CCR4);
417 ccr4 &= ~CCR4_IOMASK;
419 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
421 write_cyrix_reg(CCR4, ccr4 | 7);
424 /* Initialize CCR5. */
426 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
430 write_cyrix_reg(CCR3, ccr3);
432 /* Unlock NW bit in CR0. */
433 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
435 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
437 /* Lock NW bit in CR0. */
438 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
440 write_eflags(eflags);
450 * Local APIC should be diabled in UP kernel.
452 apicbase = rdmsr(0x1b);
453 apicbase &= ~0x800LL;
454 wrmsr(0x1b, apicbase);
459 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
465 #ifdef CPU_PPRO2CELERON
467 u_int64_t bbl_cr_ctl3;
469 eflags = read_eflags();
472 load_cr0(rcr0() | CR0_CD | CR0_NW);
475 bbl_cr_ctl3 = rdmsr(0x11e);
477 /* If the L2 cache is configured, do nothing. */
478 if (!(bbl_cr_ctl3 & 1)) {
479 bbl_cr_ctl3 = 0x134052bLL;
481 /* Set L2 Cache Latency (Default: 5). */
482 #ifdef CPU_CELERON_L2_LATENCY
483 #if CPU_L2_LATENCY > 15
484 #error invalid CPU_L2_LATENCY.
486 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
488 bbl_cr_ctl3 |= 5 << 1;
490 wrmsr(0x11e, bbl_cr_ctl3);
493 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
494 write_eflags(eflags);
495 #endif /* CPU_PPRO2CELERON */
498 #endif /* I686_CPU */
501 * Initialize CR4 (Control register 4) to enable SSE instructions.
506 #ifndef CPU_DISABLE_SSE
507 if ((cpu_feature & CPUID_SSE) && (cpu_feature & CPUID_FXSR)) {
508 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
509 cpu_fxsr = hw_instruction_sse = 1;
518 #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
520 * Sometimes the BIOS doesn't enable SSE instructions.
521 * According to AMD document 20734, the mobile
522 * Duron, the (mobile) Athlon 4 and the Athlon MP
523 * support SSE. These correspond to cpu_id 0x66X
526 if ((cpu_feature & CPUID_XMM) == 0 &&
527 ((cpu_id & ~0xf) == 0x660 ||
528 (cpu_id & ~0xf) == 0x670 ||
529 (cpu_id & ~0xf) == 0x680)) {
531 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
533 cpu_feature = regs[3];
536 #if defined(I686_CPU) && defined(CPU_AMD64X2_INTR_SPAM)
538 * Set the LINTEN bit in the HyperTransport Transaction
541 * This will cause EXTINT and NMI interrupts routed over the
542 * hypertransport bus to be fed into the LAPIC LINT0/LINT1. If
543 * the bit isn't set, the interrupts will go to the general cpu
544 * INTR/NMI pins. On a dual-core cpu the interrupt winds up
545 * going to BOTH cpus. The first cpu that does the interrupt ack
546 * cycle will get the correct interrupt. The second cpu that does
547 * it will get a spurious interrupt vector (typically IRQ 7).
549 if ((cpu_id & 0xff0) == 0xf30) {
552 (1 << 31) | /* enable */
553 (0 << 16) | /* bus */
554 (24 << 11) | /* dev (cpu + 24) */
555 (0 << 8) | /* func */
559 if ((tcr & 0x00010000) == 0) {
560 outl(0xcfc, tcr|0x00010000);
561 additional_cpu_info("AMD: Rerouting HyperTransport "
562 "EXTINT/NMI to APIC");
575 init_bluelightning();
586 #ifdef CPU_I486_ON_386
594 #endif /* I486_CPU */
600 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
601 switch (cpu_id & 0xff0) {
609 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
620 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
622 * Enable write allocate feature of AMD processors.
623 * Following two functions require the Maxmem variable being set.
626 enable_K5_wt_alloc(void)
631 * Write allocate is supported only on models 1, 2, and 3, with
632 * a stepping of 4 or greater.
634 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
636 msr = rdmsr(0x83); /* HWCR */
637 wrmsr(0x83, msr & !(0x10));
640 * We have to tell the chip where the top of memory is,
641 * since video cards could have frame bufferes there,
642 * memory-mapped I/O could be there, etc.
648 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
651 * There is no way to know wheter 15-16M hole exists or not.
652 * Therefore, we disable write allocate for this range.
654 wrmsr(0x86, 0x0ff00f0);
655 msr |= AMD_WT_ALLOC_PRE;
659 wrmsr(0x83, msr|0x10); /* enable write allocate */
666 enable_K6_wt_alloc(void)
672 eflags = read_eflags();
676 #ifdef CPU_DISABLE_CACHE
678 * Certain K6-2 box becomes unstable when write allocation is
682 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
683 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
684 * All other bits in TR12 have no effect on the processer's operation.
685 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
688 wrmsr(0x0000000e, (u_int64_t)0x0008);
690 /* Don't assume that memory size is aligned with 4M. */
692 size = ((Maxmem >> 8) + 3) >> 2;
696 /* Limit is 508M bytes. */
699 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
701 #if defined(NO_MEMORY_HOLE)
702 if (whcr & (0x7fLL << 1))
706 * There is no way to know wheter 15-16M hole exists or not.
707 * Therefore, we disable write allocate for this range.
711 wrmsr(0x0c0000082, whcr);
713 write_eflags(eflags);
717 enable_K6_2_wt_alloc(void)
723 eflags = read_eflags();
727 #ifdef CPU_DISABLE_CACHE
729 * Certain K6-2 box becomes unstable when write allocation is
733 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
734 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
735 * All other bits in TR12 have no effect on the processer's operation.
736 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
739 wrmsr(0x0000000e, (u_int64_t)0x0008);
741 /* Don't assume that memory size is aligned with 4M. */
743 size = ((Maxmem >> 8) + 3) >> 2;
747 /* Limit is 4092M bytes. */
750 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
752 #if defined(NO_MEMORY_HOLE)
753 if (whcr & (0x3ffLL << 22))
757 * There is no way to know wheter 15-16M hole exists or not.
758 * Therefore, we disable write allocate for this range.
760 whcr &= ~(1LL << 16);
762 wrmsr(0x0c0000082, whcr);
764 write_eflags(eflags);
766 #endif /* I585_CPU && CPU_WT_ALLOC */
772 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
776 u_char ccr1, ccr2, ccr3;
777 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
780 if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
781 eflags = read_eflags();
785 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
786 ccr0 = read_cyrix_reg(CCR0);
788 ccr1 = read_cyrix_reg(CCR1);
789 ccr2 = read_cyrix_reg(CCR2);
790 ccr3 = read_cyrix_reg(CCR3);
791 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
792 write_cyrix_reg(CCR3, CCR3_MAPEN0);
793 ccr4 = read_cyrix_reg(CCR4);
794 if ((cpu == CPU_M1) || (cpu == CPU_M2))
795 ccr5 = read_cyrix_reg(CCR5);
797 pcr0 = read_cyrix_reg(PCR0);
798 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
800 write_eflags(eflags);
802 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
803 kprintf("CCR0=%x, ", (u_int)ccr0);
805 kprintf("CCR1=%x, CCR2=%x, CCR3=%x",
806 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
807 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
808 kprintf(", CCR4=%x, ", (u_int)ccr4);
810 kprintf("PCR0=%x\n", pcr0);
812 kprintf("CCR5=%x\n", ccr5);
815 kprintf("CR0=%x\n", cr0);