2 * Hardware structure definitions for the Adaptec 174X CAM SCSI device driver.
4 * Copyright (c) 1998 Justin T. Gibbs
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice immediately at the beginning of the file, without modification,
12 * this list of conditions, and the following disclaimer.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/ahb/ahbreg.h,v 1.2 1999/08/28 00:43:37 peter Exp $
29 * $DragonFly: src/sys/dev/disk/ahb/ahbreg.h,v 1.2 2003/06/17 04:28:21 dillon Exp $
32 /* Resource Constatns */
36 /* AHA1740 EISA ID, IO port range size, and offset from slot base */
37 #define EISA_DEVICE_ID_ADAPTEC_1740 0x04900000
38 #define AHB_EISA_IOSIZE 0x100
39 #define AHB_EISA_SLOT_OFFSET 0xc00
41 /* AHA1740 EISA board control registers (Offset from slot base) */
46 * AHA1740 EISA board mode registers (Offset from slot base)
48 #define PORTADDR 0x0C0
49 #define PORTADDR_ENHANCED 0x80
51 #define BIOSADDR 0x0C1
64 #define HSCSIID 0x0F /* our SCSI ID */
68 #define B0uS 0x00 /* give up bus immediatly */
69 #define B4uS 0x01 /* delay 4uSec. */
70 #define B8uS 0x02 /* delay 8uSec. */
75 #define EXTENDED_TRANS 0x01
80 * AHA1740 ENHANCED mode mailbox control regs (Offset from slot base)
82 #define MBOXOUT0 0x0D0
83 #define MBOXOUT1 0x0D1
84 #define MBOXOUT2 0x0D2
85 #define MBOXOUT3 0x0D3
88 #define ATTN_TARGMASK 0x0F
89 #define ATTN_IMMED 0x10
90 #define ATTN_STARTECB 0x40
91 #define ATTN_ABORTECB 0x50
92 #define ATTN_TARG_RESET 0x80
95 #define CNTRL_SET_HRDY 0x20
96 #define CNTRL_CLRINT 0x40
97 #define CNTRL_HARD_RST 0x80
100 #define INTSTAT_TARGET_MASK 0x0F
101 #define INTSTAT_MASK 0xF0
102 #define INTSTAT_ECB_OK 0x10 /* ECB Completed w/out error */
103 #define INTSTAT_ECB_CMPWRETRY 0x50 /* ECB Completed w/retries */
104 #define INTSTAT_HW_ERR 0x70 /* Adapter Hardware Failure */
105 #define INTSTAT_IMMED_OK 0xA0 /* Immediate command complete */
106 #define INTSTAT_ECB_CMPWERR 0xC0 /* ECB Completed w/error */
107 #define INTSTAT_AEN_OCCURED 0xD0 /* Async Event Notification */
108 #define INTSTAT_IMMED_ERR 0xE0 /* Immediate command failed */
110 #define HOSTSTAT 0x0D7
111 #define HOSTSTAT_MBOX_EMPTY 0x04
112 #define HOSTSTAT_INTPEND 0x02
113 #define HOSTSTAT_BUSY 0x01
116 #define MBOXIN0 0x0D8
117 #define MBOXIN1 0x0D9
118 #define MBOXIN2 0x0DA
119 #define MBOXIN3 0x0DB
121 #define STATUS2 0x0DC
122 #define STATUS2_HOST_READY 0x01
125 IMMED_RESET = 0x000080,
126 IMMED_DEVICE_CLEAR_QUEUE = 0x000480,
127 IMMED_ADAPTER_CLEAR_QUEUE = 0x000880,
128 IMMED_RESUME = 0x200090
133 u_int16_t no_error :1, /* Completed with no error */
141 status_avail :1, /* status bytes 14-31 are valid */
151 u_int8_t scsi_status;
153 u_int32_t resid_addr;
154 u_int16_t addit_status;
162 HS_CMD_ABORTED_HOST = 0x04,
163 HS_CMD_ABORTED_ADAPTER = 0x05,
164 HS_FIRMWARE_LOAD_REQ = 0x08,
165 HS_TARGET_NOT_ASSIGNED = 0x0A,
166 HS_SEL_TIMEOUT = 0x11,
167 HS_DATA_RUN_ERR = 0x12,
168 HS_UNEXPECTED_BUSFREE = 0x13,
169 HS_INVALID_PHASE = 0x14,
170 HS_INVALID_OPCODE = 0x16,
171 HS_INVALID_CMD_LINK = 0x17,
172 HS_INVALID_ECB_PARAM = 0x18,
173 HS_DUP_TCB_RECEIVED = 0x19,
174 HS_REQUEST_SENSE_FAILED = 0x1A,
175 HS_TAG_MSG_REJECTED = 0x1C,
176 HS_HARDWARE_ERR = 0x20,
177 HS_ATN_TARGET_FAILED = 0x21,
178 HS_SCSI_RESET_ADAPTER = 0x22,
179 HS_SCSI_RESET_INCOMING = 0x23,
180 HS_PROGRAM_CKSUM_ERROR = 0x80
185 ECBOP_INITIATOR_SCSI_CMD = 0x01,
186 ECBOP_RUN_DIAGNOSTICS = 0x05,
187 ECBOP_INITIALIZE_SCSI = 0x06, /* Set syncrate/disc/parity */
188 ECBOP_READ_SENSE = 0x08,
189 ECBOP_DOWNLOAD_FIRMWARE = 0x09,
190 ECBOP_READ_HA_INQDATA = 0x0a,
191 ECBOP_TARGET_SCSI_CMD = 0x10
194 struct ha_inquiry_data {
195 struct scsi_inquiry_data scsi_data;
196 u_int8_t release_date[8];
197 u_int8_t release_time[8];
198 u_int16_t firmware_cksum;
200 u_int16_t target_data[16];
203 struct hardware_ecb {
205 u_int16_t flag_word1;
206 #define FW1_LINKED_CMD 0x0001
207 #define FW1_DISABLE_INTR 0x0080
208 #define FW1_SUPPRESS_URUN_ERR 0x0400
209 #define FW1_SG_ECB 0x1000
210 #define FW1_ERR_STATUS_BLK_ONLY 0x4000
211 #define FW1_AUTO_REQUEST_SENSE 0x8000
212 u_int16_t flag_word2;
213 #define FW2_LUN_MASK 0x0007
214 #define FW2_TAG_ENB 0x0008
215 #define FW2_TAG_TYPE 0x0030
216 #define FW2_TAG_TYPE_SHIFT 4
217 #define FW2_DISABLE_DISC 0x0040
218 #define FW2_CHECK_DATA_DIR 0x0100
219 #define FW2_DATA_DIR_IN 0x0200
220 #define FW2_SUPRESS_TRANSFER 0x0400
221 #define FW2_CALC_CKSUM 0x0800
222 #define FW2_RECOVERY_ECB 0x4000
223 #define FW2_NO_RETRY_ON_BUSY 0x8000
227 u_int32_t status_ptr;
245 ECB_DEVICE_RESET = 0x2,
246 ECB_SCSIBUS_RESET = 0x4,
247 ECB_RELEASE_SIMQ = 0x8
251 struct hardware_ecb hecb;
252 struct ecb_status status;
253 struct scsi_sense_data sense;
254 ahb_sg_t sg_list[AHB_NSEG];
255 SLIST_ENTRY(ecb) links;
263 bus_space_handle_t bsh;
265 struct cam_path *path;
266 SLIST_HEAD(,ecb) free_ecbs;
267 LIST_HEAD(,ccb_hdr) pending_ccbs;
268 struct ecb *ecb_array;
269 u_int32_t ecb_physbase;
270 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
271 bus_dma_tag_t ecb_dmat; /* dmat for our ecb array */
272 bus_dmamap_t ecb_dmamap;
273 volatile u_int32_t immed_cmd;
274 struct ecb *immed_ecb;
275 struct ha_inquiry_data *ha_inq_data;
276 u_int32_t ha_inq_physbase;
281 u_int extended_trans;
282 u_int8_t disc_permitted;
283 u_int8_t tags_permitted;