3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.30 2007/01/15 12:53:26 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
118 #include <sys/endian.h>
119 #include <sys/kernel.h>
120 #include <sys/malloc.h>
121 #include <sys/mbuf.h>
122 /* #include <sys/module.h> */
123 #include <sys/rman.h>
124 #include <sys/serialize.h>
125 #include <sys/socket.h>
126 #include <sys/sockio.h>
127 #include <sys/sysctl.h>
130 #include <net/ethernet.h>
132 #include <net/ifq_var.h>
133 #include <net/if_arp.h>
134 #include <net/if_dl.h>
135 #include <net/if_media.h>
136 #include <net/if_types.h>
137 #include <net/vlan/if_vlan_var.h>
139 #include <dev/netif/mii_layer/mii.h>
140 #include <dev/netif/mii_layer/miivar.h>
142 #include <bus/pci/pcidevs.h>
143 #include <bus/pci/pcireg.h>
144 #include <bus/pci/pcivar.h>
146 /* "device miibus" required. See GENERIC if you get errors here. */
147 #include "miibus_if.h"
149 #include <dev/netif/re/if_rereg.h>
150 #include <dev/netif/re/if_revar.h>
152 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
154 #define RE_DISABLE_HWCSUM
158 * Various supported device vendors/types and their names.
160 static const struct re_type re_devs[] = {
161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
162 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
163 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
164 "RealTek 8139C+ 10/100BaseTX" },
165 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E,
166 "RealTek 8101E PCIe 10/100baseTX" },
167 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1,
168 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2,
170 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
172 "RealTek 8169 Gigabit Ethernet" },
173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
174 "RealTek 8169S Single-chip Gigabit Ethernet" },
175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB,
176 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC,
178 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
180 "RealTek 8110S Single-chip Gigabit Ethernet" },
181 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S,
182 "Corega CG-LAPCIGT Gigabit Ethernet" },
183 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S,
184 "Linksys EG1032 Gigabit Ethernet" },
185 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S,
186 "US Robotics 997902 Gigabit Ethernet" },
190 static const struct re_hwrev re_hwrevs[] = {
191 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" },
192 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" },
193 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" },
194 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" },
195 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" },
196 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" },
197 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" },
198 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" },
199 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" },
200 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" },
204 static int re_probe(device_t);
205 static int re_attach(device_t);
206 static int re_detach(device_t);
208 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
210 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
211 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
213 static int re_allocmem(device_t, struct re_softc *);
214 static int re_newbuf(struct re_softc *, int, struct mbuf *);
215 static int re_rx_list_init(struct re_softc *);
216 static int re_tx_list_init(struct re_softc *);
217 static void re_rxeof(struct re_softc *);
218 static void re_txeof(struct re_softc *);
219 static void re_intr(void *);
220 static void re_tick(void *);
221 static void re_tick_serialized(void *);
222 static void re_start(struct ifnet *);
223 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
224 static void re_init(void *);
225 static void re_stop(struct re_softc *);
226 static void re_watchdog(struct ifnet *);
227 static int re_suspend(device_t);
228 static int re_resume(device_t);
229 static void re_shutdown(device_t);
230 static int re_ifmedia_upd(struct ifnet *);
231 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
233 static void re_eeprom_putbyte(struct re_softc *, int);
234 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
235 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
236 static int re_gmii_readreg(device_t, int, int);
237 static int re_gmii_writereg(device_t, int, int, int);
239 static int re_miibus_readreg(device_t, int, int);
240 static int re_miibus_writereg(device_t, int, int, int);
241 static void re_miibus_statchg(device_t);
243 static void re_setmulti(struct re_softc *);
244 static void re_reset(struct re_softc *);
247 static int re_diag(struct re_softc *);
250 #ifdef DEVICE_POLLING
251 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
254 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS);
256 static device_method_t re_methods[] = {
257 /* Device interface */
258 DEVMETHOD(device_probe, re_probe),
259 DEVMETHOD(device_attach, re_attach),
260 DEVMETHOD(device_detach, re_detach),
261 DEVMETHOD(device_suspend, re_suspend),
262 DEVMETHOD(device_resume, re_resume),
263 DEVMETHOD(device_shutdown, re_shutdown),
266 DEVMETHOD(bus_print_child, bus_generic_print_child),
267 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
270 DEVMETHOD(miibus_readreg, re_miibus_readreg),
271 DEVMETHOD(miibus_writereg, re_miibus_writereg),
272 DEVMETHOD(miibus_statchg, re_miibus_statchg),
277 static driver_t re_driver = {
280 sizeof(struct re_softc)
283 static devclass_t re_devclass;
285 DECLARE_DUMMY_MODULE(if_re);
286 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
287 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
288 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
291 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
294 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
297 * Send a read command and address to the EEPROM, check for ACK.
300 re_eeprom_putbyte(struct re_softc *sc, int addr)
304 d = addr | (RE_9346_READ << sc->re_eewidth);
307 * Feed in each bit and strobe the clock.
309 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
311 EE_SET(RE_EE_DATAIN);
313 EE_CLR(RE_EE_DATAIN);
323 * Read a word of data stored in the EEPROM at address 'addr.'
326 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
332 * Send address of word we want to read.
334 re_eeprom_putbyte(sc, addr);
337 * Start reading bits from EEPROM.
339 for (i = 0x8000; i != 0; i >>= 1) {
342 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
352 * Read a sequence of words from the EEPROM.
355 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
358 uint16_t word = 0, *ptr;
360 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
363 for (i = 0; i < cnt; i++) {
364 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
365 re_eeprom_getword(sc, off + i, &word);
366 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
367 ptr = (uint16_t *)(dest + (i * 2));
371 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
375 re_gmii_readreg(device_t dev, int phy, int reg)
377 struct re_softc *sc = device_get_softc(dev);
384 /* Let the rgephy driver read the GMEDIASTAT register */
386 if (reg == RE_GMEDIASTAT)
387 return(CSR_READ_1(sc, RE_GMEDIASTAT));
389 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
392 for (i = 0; i < RE_TIMEOUT; i++) {
393 rval = CSR_READ_4(sc, RE_PHYAR);
394 if (rval & RE_PHYAR_BUSY)
399 if (i == RE_TIMEOUT) {
400 device_printf(dev, "PHY read failed\n");
404 return(rval & RE_PHYAR_PHYDATA);
408 re_gmii_writereg(device_t dev, int phy, int reg, int data)
410 struct re_softc *sc = device_get_softc(dev);
414 CSR_WRITE_4(sc, RE_PHYAR,
415 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
418 for (i = 0; i < RE_TIMEOUT; i++) {
419 rval = CSR_READ_4(sc, RE_PHYAR);
420 if ((rval & RE_PHYAR_BUSY) == 0)
426 device_printf(dev, "PHY write failed\n");
432 re_miibus_readreg(device_t dev, int phy, int reg)
434 struct re_softc *sc = device_get_softc(dev);
436 uint16_t re8139_reg = 0;
438 if (sc->re_type == RE_8169) {
439 rval = re_gmii_readreg(dev, phy, reg);
443 /* Pretend the internal PHY is only at address 0 */
449 re8139_reg = RE_BMCR;
452 re8139_reg = RE_BMSR;
455 re8139_reg = RE_ANAR;
458 re8139_reg = RE_ANER;
461 re8139_reg = RE_LPAR;
467 * Allow the rlphy driver to read the media status
468 * register. If we have a link partner which does not
469 * support NWAY, this is the register which will tell
470 * us the results of parallel detection.
473 return(CSR_READ_1(sc, RE_MEDIASTAT));
475 device_printf(dev, "bad phy register\n");
478 rval = CSR_READ_2(sc, re8139_reg);
479 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) {
480 /* 8139C+ has different bit layout. */
481 rval &= ~(BMCR_LOOP | BMCR_ISO);
487 re_miibus_writereg(device_t dev, int phy, int reg, int data)
489 struct re_softc *sc= device_get_softc(dev);
490 u_int16_t re8139_reg = 0;
492 if (sc->re_type == RE_8169)
493 return(re_gmii_writereg(dev, phy, reg, data));
495 /* Pretend the internal PHY is only at address 0 */
501 re8139_reg = RE_BMCR;
502 if (sc->re_type == RE_8139CPLUS) {
503 /* 8139C+ has different bit layout. */
504 data &= ~(BMCR_LOOP | BMCR_ISO);
508 re8139_reg = RE_BMSR;
511 re8139_reg = RE_ANAR;
514 re8139_reg = RE_ANER;
517 re8139_reg = RE_LPAR;
523 device_printf(dev, "bad phy register\n");
526 CSR_WRITE_2(sc, re8139_reg, data);
531 re_miibus_statchg(device_t dev)
536 * Program the 64-bit multicast hash filter.
539 re_setmulti(struct re_softc *sc)
541 struct ifnet *ifp = &sc->arpcom.ac_if;
543 uint32_t hashes[2] = { 0, 0 };
544 struct ifmultiaddr *ifma;
548 rxfilt = CSR_READ_4(sc, RE_RXCFG);
550 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
551 rxfilt |= RE_RXCFG_RX_MULTI;
552 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
553 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
554 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
558 /* first, zot all the existing hash bits */
559 CSR_WRITE_4(sc, RE_MAR0, 0);
560 CSR_WRITE_4(sc, RE_MAR4, 0);
562 /* now program new ones */
563 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
564 if (ifma->ifma_addr->sa_family != AF_LINK)
566 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
567 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
569 hashes[0] |= (1 << h);
571 hashes[1] |= (1 << (h - 32));
576 rxfilt |= RE_RXCFG_RX_MULTI;
578 rxfilt &= ~RE_RXCFG_RX_MULTI;
580 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
581 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
582 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
586 re_reset(struct re_softc *sc)
590 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
592 for (i = 0; i < RE_TIMEOUT; i++) {
594 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
598 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
600 CSR_WRITE_1(sc, 0x82, 1);
605 * The following routine is designed to test for a defect on some
606 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
607 * lines connected to the bus, however for a 32-bit only card, they
608 * should be pulled high. The result of this defect is that the
609 * NIC will not work right if you plug it into a 64-bit slot: DMA
610 * operations will be done with 64-bit transfers, which will fail
611 * because the 64-bit data lines aren't connected.
613 * There's no way to work around this (short of talking a soldering
614 * iron to the board), however we can detect it. The method we use
615 * here is to put the NIC into digital loopback mode, set the receiver
616 * to promiscuous mode, and then try to send a frame. We then compare
617 * the frame data we sent to what was received. If the data matches,
618 * then the NIC is working correctly, otherwise we know the user has
619 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
620 * slot. In the latter case, there's no way the NIC can work correctly,
621 * so we print out a message on the console and abort the device attach.
625 re_diag(struct re_softc *sc)
627 struct ifnet *ifp = &sc->arpcom.ac_if;
629 struct ether_header *eh;
630 struct re_desc *cur_rx;
633 int total_len, i, error = 0, phyaddr;
634 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
635 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
637 /* Allocate a single mbuf */
639 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
644 * Initialize the NIC in test mode. This sets the chip up
645 * so that it can send and receive frames, but performs the
646 * following special functions:
647 * - Puts receiver in promiscuous mode
648 * - Enables digital loopback mode
649 * - Leaves interrupts turned off
652 ifp->if_flags |= IFF_PROMISC;
657 if (sc->re_type == RE_8169)
662 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
663 for (i = 0; i < RE_TIMEOUT; i++) {
664 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
665 if (!(status & BMCR_RESET))
669 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
670 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
674 /* Put some data in the mbuf */
676 eh = mtod(m0, struct ether_header *);
677 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
678 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
679 eh->ether_type = htons(ETHERTYPE_IP);
680 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
683 * Queue the packet, start transmission.
684 * Note: ifq_handoff() ultimately calls re_start() for us.
687 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
688 error = ifq_handoff(ifp, m0, NULL);
695 /* Wait for it to propagate through the chip */
698 for (i = 0; i < RE_TIMEOUT; i++) {
699 status = CSR_READ_2(sc, RE_ISR);
700 CSR_WRITE_2(sc, RE_ISR, status);
701 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
702 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
707 if (i == RE_TIMEOUT) {
708 if_printf(ifp, "diagnostic failed to receive packet "
709 "in loopback mode\n");
715 * The packet should have been dumped into the first
716 * entry in the RX DMA ring. Grab it from there.
719 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
720 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
721 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
722 BUS_DMASYNC_POSTWRITE);
723 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
725 m0 = sc->re_ldata.re_rx_mbuf[0];
726 sc->re_ldata.re_rx_mbuf[0] = NULL;
727 eh = mtod(m0, struct ether_header *);
729 cur_rx = &sc->re_ldata.re_rx_list[0];
730 total_len = RE_RXBYTES(cur_rx);
731 rxstat = le32toh(cur_rx->re_cmdstat);
733 if (total_len != ETHER_MIN_LEN) {
734 if_printf(ifp, "diagnostic failed, received short packet\n");
739 /* Test that the received packet data matches what we sent. */
741 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
742 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
743 be16toh(eh->ether_type) != ETHERTYPE_IP) {
744 if_printf(ifp, "WARNING, DMA FAILURE!\n");
745 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
746 dst, ":", src, ":", ETHERTYPE_IP);
747 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
748 eh->ether_dhost, ":", eh->ether_shost, ":",
749 ntohs(eh->ether_type));
750 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
751 "into a 64-bit PCI slot.\n");
752 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
753 "for proper operation.\n");
754 if_printf(ifp, "Read the re(4) man page for more details.\n");
759 /* Turn interface off, release resources */
763 ifp->if_flags &= ~IFF_PROMISC;
773 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
774 * IDs against our list and return a device name if we find a match.
777 re_probe(device_t dev)
779 const struct re_type *t;
783 uint16_t vendor, product;
787 vendor = pci_get_vendor(dev);
788 product = pci_get_device(dev);
791 * Only attach to rev.3 of the Linksys EG1032 adapter.
792 * Rev.2 is supported by sk(4).
794 if (vendor == PCI_VENDOR_LINKSYS &&
795 product == PCI_PRODUCT_LINKSYS_EG1032 &&
796 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
799 for (t = re_devs; t->re_name != NULL; t++) {
800 if (product == t->re_did && vendor == t->re_vid)
805 * Check if we found a RealTek device.
807 if (t->re_name == NULL)
811 * Temporarily map the I/O space so we can read the chip ID register.
813 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
815 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
817 if (sc->re_res == NULL) {
818 device_printf(dev, "couldn't map ports/memory\n");
823 sc->re_btag = rman_get_bustag(sc->re_res);
824 sc->re_bhandle = rman_get_bushandle(sc->re_res);
826 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
827 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
831 * and continue matching for the specific chip...
833 for (; t->re_name != NULL; t++) {
834 if (product == t->re_did && vendor == t->re_vid &&
835 t->re_basetype == hwrev) {
836 device_set_desc(dev, t->re_name);
844 * This routine takes the segment list provided as the result of
845 * a bus_dma_map_load() operation and assigns the addresses/lengths
846 * to RealTek DMA descriptors. This can be called either by the RX
847 * code or the TX code. In the RX case, we'll probably wind up mapping
848 * at most one segment. For the TX case, there could be any number of
849 * segments since TX packets may span multiple mbufs. In either case,
850 * if the number of segments is larger than the re_maxsegs limit
851 * specified by the caller, we abort the mapping operation. Sadly,
852 * whoever designed the buffer mapping API did not provide a way to
853 * return an error from here, so we have to fake it a bit.
857 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
858 bus_size_t mapsize, int error)
860 struct re_dmaload_arg *ctx;
861 struct re_desc *d = NULL;
870 /* Signal error to caller if there's too many segments */
871 if (nseg > ctx->re_maxsegs) {
877 * Map the segment array into descriptors. Note that we set the
878 * start-of-frame and end-of-frame markers for either TX or RX, but
879 * they really only have meaning in the TX case. (In the RX case,
880 * it's the chip that tells us where packets begin and end.)
881 * We also keep track of the end of the ring and set the
882 * end-of-ring bits as needed, and we set the ownership bits
883 * in all except the very first descriptor. (The caller will
884 * set this descriptor later when it start transmission or
889 d = &ctx->re_ring[idx];
890 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
894 cmdstat = segs[i].ds_len;
895 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
896 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
898 cmdstat |= RE_TDESC_CMD_SOF;
900 cmdstat |= RE_TDESC_CMD_OWN;
901 if (idx == (RE_RX_DESC_CNT - 1))
902 cmdstat |= RE_TDESC_CMD_EOR;
903 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
910 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
911 ctx->re_maxsegs = nseg;
916 * Map a single buffer address.
920 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
927 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
929 *addr = segs->ds_addr;
933 re_allocmem(device_t dev, struct re_softc *sc)
938 * Allocate map for RX mbufs.
941 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
942 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
943 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
944 &sc->re_ldata.re_mtag);
946 device_printf(dev, "could not allocate dma tag\n");
951 * Allocate map for TX descriptor list.
953 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
954 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
955 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
956 &sc->re_ldata.re_tx_list_tag);
958 device_printf(dev, "could not allocate dma tag\n");
962 /* Allocate DMA'able memory for the TX ring */
964 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
965 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
966 &sc->re_ldata.re_tx_list_map);
968 device_printf(dev, "could not allocate TX ring\n");
972 /* Load the map for the TX ring. */
974 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
975 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
976 RE_TX_LIST_SZ, re_dma_map_addr,
977 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
979 device_printf(dev, "could not get addres of TX ring\n");
983 /* Create DMA maps for TX buffers */
985 for (i = 0; i < RE_TX_DESC_CNT; i++) {
986 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
987 &sc->re_ldata.re_tx_dmamap[i]);
989 device_printf(dev, "can't create DMA map for TX\n");
995 * Allocate map for RX descriptor list.
997 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
998 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
999 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1000 &sc->re_ldata.re_rx_list_tag);
1002 device_printf(dev, "could not allocate dma tag\n");
1006 /* Allocate DMA'able memory for the RX ring */
1008 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1009 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1010 &sc->re_ldata.re_rx_list_map);
1012 device_printf(dev, "could not allocate RX ring\n");
1016 /* Load the map for the RX ring. */
1018 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1019 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
1020 RE_RX_LIST_SZ, re_dma_map_addr,
1021 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
1023 device_printf(dev, "could not get address of RX ring\n");
1027 /* Create DMA maps for RX buffers */
1029 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1030 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1031 &sc->re_ldata.re_rx_dmamap[i]);
1033 device_printf(dev, "can't create DMA map for RX\n");
1042 * Attach the interface. Allocate softc structures, do ifmedia
1043 * setup and ethernet/BPF attach.
1046 re_attach(device_t dev)
1048 struct re_softc *sc = device_get_softc(dev);
1050 const struct re_hwrev *hw_rev;
1051 uint8_t eaddr[ETHER_ADDR_LEN];
1052 uint16_t as[ETHER_ADDR_LEN / 2];
1053 uint16_t re_did = 0;
1055 int error = 0, rid, i;
1057 callout_init(&sc->re_timer);
1062 RE_ENABLE_TX_MODERATION(sc);
1064 sysctl_ctx_init(&sc->re_sysctl_ctx);
1065 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1066 SYSCTL_STATIC_CHILDREN(_hw),
1068 device_get_nameunit(dev),
1070 if (sc->re_sysctl_tree == NULL) {
1071 device_printf(dev, "can't add sysctl node\n");
1075 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1076 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1077 OID_AUTO, "tx_moderation",
1078 CTLTYPE_INT | CTLFLAG_RW,
1079 sc, 0, re_sysctl_tx_moderation, "I",
1080 "Enable/Disable TX moderation");
1082 #ifndef BURN_BRIDGES
1084 * Handle power management nonsense.
1087 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1088 uint32_t membase, irq;
1090 /* Save important PCI config data. */
1091 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1092 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1094 /* Reset the power state. */
1095 device_printf(dev, "chip is is in D%d power mode "
1096 "-- setting to D0\n", pci_get_powerstate(dev));
1098 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1100 /* Restore PCI config data. */
1101 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1102 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1106 * Map control/status registers.
1108 pci_enable_busmaster(dev);
1111 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1114 if (sc->re_res == NULL) {
1115 device_printf(dev, "couldn't map ports\n");
1120 sc->re_btag = rman_get_bustag(sc->re_res);
1121 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1123 /* Allocate interrupt */
1125 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1126 RF_SHAREABLE | RF_ACTIVE);
1128 if (sc->re_irq == NULL) {
1129 device_printf(dev, "couldn't map interrupt\n");
1134 /* Reset the adapter. */
1137 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1138 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1139 if (hw_rev->re_rev == hwrev) {
1140 sc->re_type = hw_rev->re_type;
1141 sc->re_flags = hw_rev->re_flags;
1147 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1148 if (re_did != 0x8129)
1152 * Get station address from the EEPROM.
1154 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
1155 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1156 as[i] = le16toh(as[i]);
1157 bcopy(as, eaddr, sizeof(eaddr));
1159 if (sc->re_type == RE_8169) {
1160 /* Set RX length mask */
1161 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1162 sc->re_txstart = RE_GTXSTART;
1164 /* Set RX length mask */
1165 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1166 sc->re_txstart = RE_TXSTART;
1170 * Allocate the parent bus DMA tag appropriate for PCI.
1172 #define RE_NSEG_NEW 32
1173 error = bus_dma_tag_create(NULL, /* parent */
1174 1, 0, /* alignment, boundary */
1175 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1176 BUS_SPACE_MAXADDR, /* highaddr */
1177 NULL, NULL, /* filter, filterarg */
1178 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1179 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1180 BUS_DMA_ALLOCNOW, /* flags */
1181 &sc->re_parent_tag);
1185 error = re_allocmem(dev, sc);
1191 if (mii_phy_probe(dev, &sc->re_miibus,
1192 re_ifmedia_upd, re_ifmedia_sts)) {
1193 device_printf(dev, "MII without any phy!\n");
1198 ifp = &sc->arpcom.ac_if;
1200 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1201 ifp->if_mtu = ETHERMTU;
1202 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1203 ifp->if_ioctl = re_ioctl;
1204 ifp->if_capabilities = IFCAP_VLAN_MTU;
1205 ifp->if_start = re_start;
1206 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1207 #ifdef DEVICE_POLLING
1208 ifp->if_poll = re_poll;
1210 ifp->if_watchdog = re_watchdog;
1211 ifp->if_init = re_init;
1212 if (sc->re_type == RE_8169)
1213 ifp->if_baudrate = 1000000000;
1215 ifp->if_baudrate = 100000000;
1216 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1217 ifq_set_ready(&ifp->if_snd);
1219 #ifdef RE_DISABLE_HWCSUM
1220 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1221 ifp->if_hwassist = 0;
1223 if (sc->re_flags & RE_F_PCIE) {
1225 * The hardware supports checksumming but, as usual, PCIe
1226 * chipsets screw it all up and produce bogus packets, so
1227 * we don't enable it by default.
1229 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1230 ifp->if_hwassist = 0;
1232 ifp->if_capenable = ifp->if_capabilities;
1233 ifp->if_hwassist = RE_CSUM_FEATURES;
1235 #endif /* RE_DISABLE_HWCSUM */
1238 * Call MI attach routine.
1240 ether_ifattach(ifp, eaddr, NULL);
1244 * Perform hardware diagnostic on the original RTL8169.
1245 * Some 32-bit cards were incorrectly wired and would
1246 * malfunction if plugged into a 64-bit slot.
1248 if (hwrev == RE_HWREV_8169) {
1249 lwkt_serialize_enter(ifp->if_serializer);
1250 error = re_diag(sc);
1251 lwkt_serialize_exit(ifp->if_serializer);
1254 device_printf(dev, "hardware diagnostic failure\n");
1255 ether_ifdetach(ifp);
1259 #endif /* RE_DIAG */
1261 /* Hook interrupt last to avoid having to lock softc */
1262 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc,
1263 &sc->re_intrhand, ifp->if_serializer);
1266 device_printf(dev, "couldn't set up irq\n");
1267 ether_ifdetach(ifp);
1279 * Shutdown hardware and free up resources. This can be called any
1280 * time after the mutex has been initialized. It is called in both
1281 * the error case in attach and the normal detach case so it needs
1282 * to be careful about only freeing resources that have actually been
1286 re_detach(device_t dev)
1288 struct re_softc *sc = device_get_softc(dev);
1289 struct ifnet *ifp = &sc->arpcom.ac_if;
1292 /* These should only be active if attach succeeded */
1293 if (device_is_attached(dev)) {
1294 lwkt_serialize_enter(ifp->if_serializer);
1296 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1297 lwkt_serialize_exit(ifp->if_serializer);
1299 ether_ifdetach(ifp);
1302 device_delete_child(dev, sc->re_miibus);
1303 bus_generic_detach(dev);
1306 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1308 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1312 /* Unload and free the RX DMA ring memory and map */
1314 if (sc->re_ldata.re_rx_list_tag) {
1315 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1316 sc->re_ldata.re_rx_list_map);
1317 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1318 sc->re_ldata.re_rx_list,
1319 sc->re_ldata.re_rx_list_map);
1320 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1323 /* Unload and free the TX DMA ring memory and map */
1325 if (sc->re_ldata.re_tx_list_tag) {
1326 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1327 sc->re_ldata.re_tx_list_map);
1328 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1329 sc->re_ldata.re_tx_list,
1330 sc->re_ldata.re_tx_list_map);
1331 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1334 /* Destroy all the RX and TX buffer maps */
1336 if (sc->re_ldata.re_mtag) {
1337 for (i = 0; i < RE_TX_DESC_CNT; i++)
1338 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1339 sc->re_ldata.re_tx_dmamap[i]);
1340 for (i = 0; i < RE_RX_DESC_CNT; i++)
1341 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1342 sc->re_ldata.re_rx_dmamap[i]);
1343 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1346 /* Unload and free the stats buffer and map */
1348 if (sc->re_ldata.re_stag) {
1349 bus_dmamap_unload(sc->re_ldata.re_stag,
1350 sc->re_ldata.re_rx_list_map);
1351 bus_dmamem_free(sc->re_ldata.re_stag,
1352 sc->re_ldata.re_stats,
1353 sc->re_ldata.re_smap);
1354 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1357 if (sc->re_parent_tag)
1358 bus_dma_tag_destroy(sc->re_parent_tag);
1364 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1366 struct re_dmaload_arg arg;
1367 struct mbuf *n = NULL;
1371 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1376 m->m_data = m->m_ext.ext_buf;
1378 m->m_len = m->m_pkthdr.len = MCLBYTES;
1382 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1383 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1390 arg.re_ring = sc->re_ldata.re_rx_list;
1392 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1393 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1394 &arg, BUS_DMA_NOWAIT);
1395 if (error || arg.re_maxsegs != 1) {
1401 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1402 sc->re_ldata.re_rx_mbuf[idx] = m;
1404 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1405 BUS_DMASYNC_PREREAD);
1411 re_tx_list_init(struct re_softc *sc)
1413 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1414 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1416 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1417 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1418 sc->re_ldata.re_tx_prodidx = 0;
1419 sc->re_ldata.re_tx_considx = 0;
1420 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1426 re_rx_list_init(struct re_softc *sc)
1430 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1431 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1433 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1434 error = re_newbuf(sc, i, NULL);
1439 /* Flush the RX descriptors */
1441 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1442 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1444 sc->re_ldata.re_rx_prodidx = 0;
1445 sc->re_head = sc->re_tail = NULL;
1451 * RX handler for C+ and 8169. For the gigE chips, we support
1452 * the reception of jumbo frames that have been fragmented
1453 * across multiple 2K mbuf cluster buffers.
1456 re_rxeof(struct re_softc *sc)
1458 struct ifnet *ifp = &sc->arpcom.ac_if;
1460 struct re_desc *cur_rx;
1461 uint32_t rxstat, rxvlan;
1464 /* Invalidate the descriptor memory */
1466 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1467 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1469 for (i = sc->re_ldata.re_rx_prodidx;
1470 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1471 cur_rx = &sc->re_ldata.re_rx_list[i];
1472 m = sc->re_ldata.re_rx_mbuf[i];
1473 total_len = RE_RXBYTES(cur_rx);
1474 rxstat = le32toh(cur_rx->re_cmdstat);
1475 rxvlan = le32toh(cur_rx->re_vlanctl);
1477 /* Invalidate the RX mbuf and unload its map */
1479 bus_dmamap_sync(sc->re_ldata.re_mtag,
1480 sc->re_ldata.re_rx_dmamap[i],
1481 BUS_DMASYNC_POSTWRITE);
1482 bus_dmamap_unload(sc->re_ldata.re_mtag,
1483 sc->re_ldata.re_rx_dmamap[i]);
1485 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1486 m->m_len = MCLBYTES - ETHER_ALIGN;
1487 if (sc->re_head == NULL) {
1488 sc->re_head = sc->re_tail = m;
1490 sc->re_tail->m_next = m;
1493 re_newbuf(sc, i, NULL);
1498 * NOTE: for the 8139C+, the frame length field
1499 * is always 12 bits in size, but for the gigE chips,
1500 * it is 13 bits (since the max RX frame length is 16K).
1501 * Unfortunately, all 32 bits in the status word
1502 * were already used, so to make room for the extra
1503 * length bit, RealTek took out the 'frame alignment
1504 * error' bit and shifted the other status bits
1505 * over one slot. The OWN, EOR, FS and LS bits are
1506 * still in the same places. We have already extracted
1507 * the frame length and checked the OWN bit, so rather
1508 * than using an alternate bit mapping, we shift the
1509 * status bits one space to the right so we can evaluate
1510 * them using the 8169 status as though it was in the
1511 * same format as that of the 8139C+.
1513 if (sc->re_type == RE_8169)
1516 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1519 * If this is part of a multi-fragment packet,
1520 * discard all the pieces.
1522 if (sc->re_head != NULL) {
1523 m_freem(sc->re_head);
1524 sc->re_head = sc->re_tail = NULL;
1526 re_newbuf(sc, i, m);
1531 * If allocating a replacement mbuf fails,
1532 * reload the current one.
1535 if (re_newbuf(sc, i, NULL)) {
1537 if (sc->re_head != NULL) {
1538 m_freem(sc->re_head);
1539 sc->re_head = sc->re_tail = NULL;
1541 re_newbuf(sc, i, m);
1545 if (sc->re_head != NULL) {
1546 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1548 * Special case: if there's 4 bytes or less
1549 * in this buffer, the mbuf can be discarded:
1550 * the last 4 bytes is the CRC, which we don't
1551 * care about anyway.
1553 if (m->m_len <= ETHER_CRC_LEN) {
1554 sc->re_tail->m_len -=
1555 (ETHER_CRC_LEN - m->m_len);
1558 m->m_len -= ETHER_CRC_LEN;
1559 sc->re_tail->m_next = m;
1562 sc->re_head = sc->re_tail = NULL;
1563 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1565 m->m_pkthdr.len = m->m_len =
1566 (total_len - ETHER_CRC_LEN);
1569 m->m_pkthdr.rcvif = ifp;
1571 /* Do RX checksumming if enabled */
1573 if (ifp->if_capenable & IFCAP_RXCSUM) {
1575 /* Check IP header checksum */
1576 if (rxstat & RE_RDESC_STAT_PROTOID)
1577 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1578 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1579 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1581 /* Check TCP/UDP checksum */
1582 if ((RE_TCPPKT(rxstat) &&
1583 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1584 (RE_UDPPKT(rxstat) &&
1585 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1586 m->m_pkthdr.csum_flags |=
1587 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1588 m->m_pkthdr.csum_data = 0xffff;
1592 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1594 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1596 ifp->if_input(ifp, m);
1600 /* Flush the RX DMA ring */
1602 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1603 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1605 sc->re_ldata.re_rx_prodidx = i;
1609 re_txeof(struct re_softc *sc)
1611 struct ifnet *ifp = &sc->arpcom.ac_if;
1615 /* Invalidate the TX descriptor list */
1617 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1618 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
1620 for (idx = sc->re_ldata.re_tx_considx;
1621 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) {
1622 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1623 if (txstat & RE_TDESC_CMD_OWN)
1626 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
1629 * We only stash mbufs in the last descriptor
1630 * in a fragment chain, which also happens to
1631 * be the only place where the TX status bits
1634 if (txstat & RE_TDESC_CMD_EOF) {
1635 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1636 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1637 bus_dmamap_unload(sc->re_ldata.re_mtag,
1638 sc->re_ldata.re_tx_dmamap[idx]);
1639 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1640 RE_TDESC_STAT_COLCNT))
1641 ifp->if_collisions++;
1642 if (txstat & RE_TDESC_STAT_TXERRSUM)
1647 sc->re_ldata.re_tx_free++;
1650 /* No changes made to the TX ring, so no flush needed */
1651 if (sc->re_ldata.re_tx_free) {
1652 sc->re_ldata.re_tx_considx = idx;
1653 ifp->if_flags &= ~IFF_OACTIVE;
1658 * Some chips will ignore a second TX request issued while an
1659 * existing transmission is in progress. If the transmitter goes
1660 * idle but there are still packets waiting to be sent, we need
1661 * to restart the channel here to flush them out. This only seems
1662 * to be required with the PCIe devices.
1664 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1665 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
1668 * If not all descriptors have been released reaped yet,
1669 * reload the timer so that we will eventually get another
1670 * interrupt that will cause us to re-enter this routine.
1671 * This is done in case the transmitter has gone idle.
1673 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
1674 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1675 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1681 struct re_softc *sc = xsc;
1683 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1684 re_tick_serialized(xsc);
1685 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1689 re_tick_serialized(void *xsc)
1691 struct re_softc *sc = xsc;
1692 struct ifnet *ifp = &sc->arpcom.ac_if;
1693 struct mii_data *mii;
1695 mii = device_get_softc(sc->re_miibus);
1698 if (!(mii->mii_media_status & IFM_ACTIVE))
1701 if (mii->mii_media_status & IFM_ACTIVE &&
1702 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1704 if (!ifq_is_empty(&ifp->if_snd))
1709 callout_reset(&sc->re_timer, hz, re_tick, sc);
1712 #ifdef DEVICE_POLLING
1715 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1717 struct re_softc *sc = ifp->if_softc;
1721 /* disable interrupts */
1722 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1724 case POLL_DEREGISTER:
1725 /* enable interrupts */
1726 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1729 sc->rxcycles = count;
1733 if (!ifq_is_empty(&ifp->if_snd))
1734 (*ifp->if_start)(ifp);
1736 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1739 status = CSR_READ_2(sc, RE_ISR);
1740 if (status == 0xffff)
1743 CSR_WRITE_2(sc, RE_ISR, status);
1746 * XXX check behaviour on receiver stalls.
1749 if (status & RE_ISR_SYSTEM_ERR) {
1757 #endif /* DEVICE_POLLING */
1762 struct re_softc *sc = arg;
1763 struct ifnet *ifp = &sc->arpcom.ac_if;
1766 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1770 status = CSR_READ_2(sc, RE_ISR);
1771 /* If the card has gone away the read returns 0xffff. */
1772 if (status == 0xffff)
1775 CSR_WRITE_2(sc, RE_ISR, status);
1777 if ((status & sc->re_intrs) == 0)
1780 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW))
1783 if ((status & sc->re_tx_ack) ||
1784 (status & RE_ISR_TX_ERR) ||
1785 (status & RE_ISR_TX_DESC_UNAVAIL))
1788 if (status & RE_ISR_SYSTEM_ERR) {
1793 if (status & RE_ISR_LINKCHG) {
1794 callout_stop(&sc->re_timer);
1795 re_tick_serialized(sc);
1799 if (!ifq_is_empty(&ifp->if_snd))
1800 (*ifp->if_start)(ifp);
1804 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1806 struct ifnet *ifp = &sc->arpcom.ac_if;
1807 struct mbuf *m, *m_new = NULL;
1808 struct re_dmaload_arg arg;
1813 if (sc->re_ldata.re_tx_free <= 4)
1819 * Set up checksum offload. Note: checksum offload bits must
1820 * appear in all descriptors of a multi-descriptor transmit
1821 * attempt. (This is according to testing done with an 8169
1822 * chip. I'm not sure if this is a requirement or a bug.)
1827 if (m->m_pkthdr.csum_flags & CSUM_IP)
1828 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1829 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1830 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1831 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1832 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1836 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1837 if (arg.re_maxsegs > 4)
1838 arg.re_maxsegs -= 4;
1839 arg.re_ring = sc->re_ldata.re_tx_list;
1841 map = sc->re_ldata.re_tx_dmamap[*idx];
1844 * With some of the RealTek chips, using the checksum offload
1845 * support in conjunction with the autopadding feature results
1846 * in the transmission of corrupt frames. For example, if we
1847 * need to send a really small IP fragment that's less than 60
1848 * bytes in size, and IP header checksumming is enabled, the
1849 * resulting ethernet frame that appears on the wire will
1850 * have garbled payload. To work around this, if TX checksum
1851 * offload is enabled, we always manually pad short frames out
1852 * to the minimum ethernet frame size. We do this by pretending
1853 * the mbuf chain has too many fragments so the coalescing code
1854 * below can assemble the packet into a single buffer that's
1855 * padded out to the mininum frame size.
1857 if (arg.re_flags && m->m_pkthdr.len < RE_MIN_FRAMELEN) {
1860 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1861 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1864 if (error && error != EFBIG) {
1865 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1869 /* Too many segments to map, coalesce into a single mbuf */
1871 if (error || arg.re_maxsegs == 0) {
1872 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1881 * Manually pad short frames, and zero the pad space
1882 * to avoid leaking data.
1884 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) {
1885 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
1886 RE_MIN_FRAMELEN - m_new->m_pkthdr.len);
1887 m_new->m_pkthdr.len += RE_MIN_FRAMELEN -
1888 m_new->m_pkthdr.len;
1889 m_new->m_len = m_new->m_pkthdr.len;
1895 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1896 arg.re_ring = sc->re_ldata.re_tx_list;
1898 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1899 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1902 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1908 * Insure that the map for this transmission
1909 * is placed at the array index of the last descriptor
1912 sc->re_ldata.re_tx_dmamap[*idx] =
1913 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1914 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1916 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1917 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1920 * Set up hardware VLAN tagging. Note: vlan tag info must
1921 * appear in the first descriptor of a multi-descriptor
1922 * transmission attempt.
1925 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1926 m->m_pkthdr.rcvif != NULL &&
1927 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1929 ifv = m->m_pkthdr.rcvif->if_softc;
1931 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1932 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1935 /* Transfer ownership of packet to the chip. */
1937 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1938 htole32(RE_TDESC_CMD_OWN);
1939 if (*idx != arg.re_idx)
1940 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1941 htole32(RE_TDESC_CMD_OWN);
1943 RE_DESC_INC(arg.re_idx);
1950 * Main transmit routine for C+ and gigE NICs.
1954 re_start(struct ifnet *ifp)
1956 struct re_softc *sc = ifp->if_softc;
1957 struct mbuf *m_head;
1958 struct mbuf *m_head2;
1959 int called_defrag, idx, need_trans;
1961 if (!sc->re_link || (ifp->if_flags & IFF_OACTIVE))
1964 idx = sc->re_ldata.re_tx_prodidx;
1967 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1968 m_head = ifq_poll(&ifp->if_snd);
1972 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
1974 * If we could not encapsulate the defragged packet,
1975 * the returned m_head2 is garbage and we must dequeue
1976 * and throw away the original packet.
1978 if (called_defrag) {
1979 ifq_dequeue(&ifp->if_snd, m_head);
1982 ifp->if_flags |= IFF_OACTIVE;
1987 * Clean out the packet we encapsulated. If we defragged
1988 * the packet the m_head2 is the one that got encapsulated
1989 * and the original must be thrown away. Otherwise m_head2
1990 * *IS* the original.
1992 ifq_dequeue(&ifp->if_snd, m_head);
1998 * If there's a BPF listener, bounce a copy of this frame
2001 BPF_MTAP(ifp, m_head2);
2005 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
2006 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
2007 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2011 /* Flush the TX descriptors */
2012 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2013 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2015 sc->re_ldata.re_tx_prodidx = idx;
2018 * RealTek put the TX poll request register in a different
2019 * location on the 8169 gigE chip. I don't know why.
2021 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2023 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2025 * Use the countdown timer for interrupt moderation.
2026 * 'TX done' interrupts are disabled. Instead, we reset the
2027 * countdown timer, which will begin counting until it hits
2028 * the value in the TIMERINT register, and then trigger an
2029 * interrupt. Each time we write to the TIMERCNT register,
2030 * the timer count is reset to 0.
2032 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2036 * Set a timeout in case the chip goes out to lunch.
2044 struct re_softc *sc = xsc;
2045 struct ifnet *ifp = &sc->arpcom.ac_if;
2046 struct mii_data *mii;
2049 mii = device_get_softc(sc->re_miibus);
2052 * Cancel pending I/O and free all RX/TX buffers.
2057 * Enable C+ RX and TX mode, as well as VLAN stripping and
2058 * RX checksum offload. We must configure the C+ register
2059 * before all others.
2061 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2062 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
2063 (ifp->if_capenable & IFCAP_RXCSUM ?
2064 RE_CPLUSCMD_RXCSUM_ENB : 0));
2067 * Init our MAC address. Even though the chipset
2068 * documentation doesn't mention it, we need to enter "Config
2069 * register write enable" mode to modify the ID registers.
2071 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2072 CSR_WRITE_4(sc, RE_IDR0,
2073 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2074 CSR_WRITE_2(sc, RE_IDR4,
2075 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2076 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2079 * For C+ mode, initialize the RX descriptors and mbufs.
2081 re_rx_list_init(sc);
2082 re_tx_list_init(sc);
2085 * Load the addresses of the RX and TX lists into the chip.
2087 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2088 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2089 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2090 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2092 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2093 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2094 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2095 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2098 * Enable transmit and receive.
2100 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2103 * Set the initial TX and RX configuration.
2105 if (sc->re_testmode) {
2106 if (sc->re_type == RE_8169)
2107 CSR_WRITE_4(sc, RE_TXCFG,
2108 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2110 CSR_WRITE_4(sc, RE_TXCFG,
2111 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2113 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2115 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2117 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2119 /* Set the individual bit to receive frames for this host only. */
2120 rxcfg = CSR_READ_4(sc, RE_RXCFG);
2121 rxcfg |= RE_RXCFG_RX_INDIV;
2123 /* If we want promiscuous mode, set the allframes bit. */
2124 if (ifp->if_flags & IFF_PROMISC) {
2125 rxcfg |= RE_RXCFG_RX_ALLPHYS;
2126 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2128 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
2129 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2133 * Set capture broadcast bit to capture broadcast frames.
2135 if (ifp->if_flags & IFF_BROADCAST) {
2136 rxcfg |= RE_RXCFG_RX_BROAD;
2137 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2139 rxcfg &= ~RE_RXCFG_RX_BROAD;
2140 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2144 * Program the multicast filter, if necessary.
2148 #ifdef DEVICE_POLLING
2150 * Disable interrupts if we are polling.
2152 if (ifp->if_flags & IFF_POLLING)
2153 CSR_WRITE_2(sc, RE_IMR, 0);
2154 else /* otherwise ... */
2155 #endif /* DEVICE_POLLING */
2157 * Enable interrupts.
2159 if (sc->re_testmode)
2160 CSR_WRITE_2(sc, RE_IMR, 0);
2162 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2163 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2165 /* Set initial TX threshold */
2166 sc->re_txthresh = RE_TX_THRESH_INIT;
2168 /* Start RX/TX process. */
2169 if (sc->re_flags & RE_F_HASMPC)
2170 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2172 /* Enable receiver and transmitter. */
2173 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2176 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2178 * Initialize the timer interrupt register so that
2179 * a timer interrupt will be generated once the timer
2180 * reaches a certain number of ticks. The timer is
2181 * reloaded on each transmit. This gives us TX interrupt
2182 * moderation, which dramatically improves TX frame rate.
2184 if (sc->re_type == RE_8169)
2185 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2187 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2191 * For 8169 gigE NICs, set the max allowed RX packet
2192 * size so we can receive jumbo frames.
2194 if (sc->re_type == RE_8169)
2195 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2197 if (sc->re_testmode) {
2203 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2205 ifp->if_flags |= IFF_RUNNING;
2206 ifp->if_flags &= ~IFF_OACTIVE;
2209 callout_reset(&sc->re_timer, hz, re_tick, sc);
2213 * Set media options.
2216 re_ifmedia_upd(struct ifnet *ifp)
2218 struct re_softc *sc = ifp->if_softc;
2219 struct mii_data *mii;
2221 mii = device_get_softc(sc->re_miibus);
2228 * Report current media status.
2231 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2233 struct re_softc *sc = ifp->if_softc;
2234 struct mii_data *mii;
2236 mii = device_get_softc(sc->re_miibus);
2239 ifmr->ifm_active = mii->mii_media_active;
2240 ifmr->ifm_status = mii->mii_media_status;
2244 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2246 struct re_softc *sc = ifp->if_softc;
2247 struct ifreq *ifr = (struct ifreq *) data;
2248 struct mii_data *mii;
2253 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2255 ifp->if_mtu = ifr->ifr_mtu;
2258 if (ifp->if_flags & IFF_UP)
2260 else if (ifp->if_flags & IFF_RUNNING)
2270 mii = device_get_softc(sc->re_miibus);
2271 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2274 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2275 ifp->if_capenable |=
2276 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2277 if (ifp->if_capenable & IFCAP_TXCSUM)
2278 ifp->if_hwassist = RE_CSUM_FEATURES;
2280 ifp->if_hwassist = 0;
2281 if (ifp->if_flags & IFF_RUNNING)
2285 error = ether_ioctl(ifp, command, data);
2292 re_watchdog(struct ifnet *ifp)
2294 struct re_softc *sc = ifp->if_softc;
2296 if_printf(ifp, "watchdog timeout\n");
2305 if (!ifq_is_empty(&ifp->if_snd))
2310 * Stop the adapter and free any mbufs allocated to the
2314 re_stop(struct re_softc *sc)
2316 struct ifnet *ifp = &sc->arpcom.ac_if;
2320 callout_stop(&sc->re_timer);
2322 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2324 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2325 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2326 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2328 if (sc->re_head != NULL) {
2329 m_freem(sc->re_head);
2330 sc->re_head = sc->re_tail = NULL;
2333 /* Free the TX list buffers. */
2334 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2335 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2336 bus_dmamap_unload(sc->re_ldata.re_mtag,
2337 sc->re_ldata.re_tx_dmamap[i]);
2338 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2339 sc->re_ldata.re_tx_mbuf[i] = NULL;
2343 /* Free the RX list buffers. */
2344 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2345 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2346 bus_dmamap_unload(sc->re_ldata.re_mtag,
2347 sc->re_ldata.re_rx_dmamap[i]);
2348 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2349 sc->re_ldata.re_rx_mbuf[i] = NULL;
2355 * Device suspend routine. Stop the interface and save some PCI
2356 * settings in case the BIOS doesn't restore them properly on
2360 re_suspend(device_t dev)
2362 #ifndef BURN_BRIDGES
2365 struct re_softc *sc = device_get_softc(dev);
2369 #ifndef BURN_BRIDGES
2370 for (i = 0; i < 5; i++)
2371 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2372 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2373 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2374 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2375 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2384 * Device resume routine. Restore some PCI settings in case the BIOS
2385 * doesn't, re-enable busmastering, and restart the interface if
2389 re_resume(device_t dev)
2391 struct re_softc *sc = device_get_softc(dev);
2392 struct ifnet *ifp = &sc->arpcom.ac_if;
2393 #ifndef BURN_BRIDGES
2397 #ifndef BURN_BRIDGES
2398 /* better way to do this? */
2399 for (i = 0; i < 5; i++)
2400 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2401 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2402 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2403 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2404 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2406 /* reenable busmastering */
2407 pci_enable_busmaster(dev);
2408 pci_enable_io(dev, SYS_RES_IOPORT);
2411 /* reinitialize interface if necessary */
2412 if (ifp->if_flags & IFF_UP)
2421 * Stop all chip I/O so that the kernel's probe routines don't
2422 * get confused by errant DMAs when rebooting.
2425 re_shutdown(device_t dev)
2427 struct re_softc *sc = device_get_softc(dev);
2428 struct ifnet *ifp = &sc->arpcom.ac_if;
2430 lwkt_serialize_enter(ifp->if_serializer);
2432 lwkt_serialize_exit(ifp->if_serializer);
2436 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS)
2438 struct re_softc *sc = arg1;
2439 struct ifnet *ifp = &sc->arpcom.ac_if;
2440 int error = 0, mod, mod_old;
2442 lwkt_serialize_enter(ifp->if_serializer);
2444 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc);
2446 error = sysctl_handle_int(oidp, &mod, 0, req);
2447 if (error || req->newptr == NULL || mod == mod_old)
2449 if (mod != 0 && mod != 1) {
2455 RE_ENABLE_TX_MODERATION(sc);
2457 RE_DISABLE_TX_MODERATION(sc);
2459 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP))
2462 lwkt_serialize_exit(ifp->if_serializer);