2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.36 2008/07/27 10:06:55 sephe Exp $
34 #include "opt_ethernet.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/sockio.h>
40 #include <sys/malloc.h>
41 #include <sys/interrupt.h>
42 #include <sys/kernel.h>
43 #include <sys/socket.h>
44 #include <sys/queue.h>
47 #include <sys/thread2.h>
50 #include <net/ifq_var.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
58 #include <net/if_types.h>
59 #include <net/vlan/if_vlan_var.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/in.h>
63 #include <netinet/ip.h>
65 #include <bus/pci/pcireg.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcidevs.h>
69 #include <dev/netif/mii_layer/mii.h>
70 #include <dev/netif/mii_layer/miivar.h>
72 #include <dev/netif/bfe/if_bfereg.h>
74 MODULE_DEPEND(bfe, pci, 1, 1, 1);
75 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
77 /* "controller miibus0" required. See GENERIC if you get errors here. */
78 #include "miibus_if.h"
80 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
82 static struct bfe_type bfe_devs[] = {
83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
84 "Broadcom BCM4401 Fast Ethernet" },
85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
86 "Broadcom BCM4401-B0 Fast Ethernet" },
87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
88 "Broadcom BCM4402 Fast Ethernet" },
92 static int bfe_probe(device_t);
93 static int bfe_attach(device_t);
94 static int bfe_detach(device_t);
95 static void bfe_intr(void *);
96 static void bfe_start(struct ifnet *);
97 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
98 static void bfe_init(void *);
99 static void bfe_stop(struct bfe_softc *);
100 static void bfe_watchdog(struct ifnet *);
101 static void bfe_shutdown(device_t);
102 static void bfe_tick(void *);
103 static void bfe_txeof(struct bfe_softc *);
104 static void bfe_rxeof(struct bfe_softc *);
105 static void bfe_set_rx_mode(struct bfe_softc *);
106 static int bfe_list_rx_init(struct bfe_softc *);
107 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
108 static void bfe_rx_ring_free(struct bfe_softc *);
110 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
111 static int bfe_ifmedia_upd(struct ifnet *);
112 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
113 static int bfe_miibus_readreg(device_t, int, int);
114 static int bfe_miibus_writereg(device_t, int, int, int);
115 static void bfe_miibus_statchg(device_t);
116 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
118 static void bfe_get_config(struct bfe_softc *sc);
119 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
120 static void bfe_stats_update(struct bfe_softc *);
121 static void bfe_clear_stats (struct bfe_softc *);
122 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
123 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
124 static int bfe_resetphy(struct bfe_softc *);
125 static int bfe_setupphy(struct bfe_softc *);
126 static void bfe_chip_reset(struct bfe_softc *);
127 static void bfe_chip_halt(struct bfe_softc *);
128 static void bfe_core_reset(struct bfe_softc *);
129 static void bfe_core_disable(struct bfe_softc *);
130 static int bfe_dma_alloc(device_t);
131 static void bfe_dma_free(struct bfe_softc *);
132 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
133 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
134 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
136 static device_method_t bfe_methods[] = {
137 /* Device interface */
138 DEVMETHOD(device_probe, bfe_probe),
139 DEVMETHOD(device_attach, bfe_attach),
140 DEVMETHOD(device_detach, bfe_detach),
141 DEVMETHOD(device_shutdown, bfe_shutdown),
144 DEVMETHOD(bus_print_child, bus_generic_print_child),
145 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
148 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
149 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
150 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
155 static driver_t bfe_driver = {
158 sizeof(struct bfe_softc)
161 static devclass_t bfe_devclass;
163 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
164 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
167 * Probe for a Broadcom 4401 chip.
170 bfe_probe(device_t dev)
173 uint16_t vendor, product;
175 vendor = pci_get_vendor(dev);
176 product = pci_get_device(dev);
178 for (t = bfe_devs; t->bfe_name != NULL; t++) {
179 if (vendor == t->bfe_vid && product == t->bfe_did) {
180 device_set_desc(dev, t->bfe_name);
189 bfe_dma_alloc(device_t dev)
191 struct bfe_softc *sc = device_get_softc(dev);
192 int error, i, tx_pos, rx_pos;
195 * parent tag. Apparently the chip cannot handle any DMA address
198 error = bus_dma_tag_create(NULL, /* parent */
199 4096, 0, /* alignment, boundary */
200 0x3FFFFFFF, /* lowaddr */
201 BUS_SPACE_MAXADDR, /* highaddr */
202 NULL, NULL, /* filter, filterarg */
203 MAXBSIZE, /* maxsize */
204 BUS_SPACE_UNRESTRICTED, /* num of segments */
205 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
207 &sc->bfe_parent_tag);
209 device_printf(dev, "could not allocate parent dma tag\n");
213 /* tag for TX ring */
214 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0,
215 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
218 BUS_SPACE_MAXSIZE_32BIT,
221 device_printf(dev, "could not allocate dma tag for TX list\n");
225 /* tag for RX ring */
226 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0,
227 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
230 BUS_SPACE_MAXSIZE_32BIT,
233 device_printf(dev, "could not allocate dma tag for RX list\n");
238 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
239 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
241 MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT,
242 BUS_DMA_ALLOCNOW, &sc->bfe_tag);
244 device_printf(dev, "could not allocate dma tag for mbufs\n");
250 /* pre allocate dmamaps for RX list */
251 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
252 error = bus_dmamap_create(sc->bfe_tag, 0,
253 &sc->bfe_rx_ring[i].bfe_map);
256 device_printf(dev, "cannot create DMA map for RX\n");
260 rx_pos = BFE_RX_LIST_CNT;
262 /* pre allocate dmamaps for TX list */
263 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
264 error = bus_dmamap_create(sc->bfe_tag, 0,
265 &sc->bfe_tx_ring[i].bfe_map);
268 device_printf(dev, "cannot create DMA map for TX\n");
273 /* Alloc dma for rx ring */
274 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
275 BUS_DMA_WAITOK | BUS_DMA_ZERO,
278 device_printf(dev, "cannot allocate DMA mem for RX\n");
282 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
283 sc->bfe_rx_list, sizeof(struct bfe_desc),
284 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK);
286 device_printf(dev, "cannot load DMA map for RX\n");
290 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
292 /* Alloc dma for tx ring */
293 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
294 BUS_DMA_WAITOK | BUS_DMA_ZERO,
297 device_printf(dev, "cannot allocate DMA mem for TX\n");
301 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
302 sc->bfe_tx_list, sizeof(struct bfe_desc),
303 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK);
305 device_printf(dev, "cannot load DMA map for TX\n");
309 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
314 for (i = 0; i < rx_pos; ++i)
315 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map);
316 for (i = 0; i < tx_pos; ++i)
317 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map);
319 bus_dma_tag_destroy(sc->bfe_tag);
325 bfe_attach(device_t dev)
328 struct bfe_softc *sc;
331 sc = device_get_softc(dev);
334 callout_init(&sc->bfe_stat_timer);
338 * Handle power management nonsense.
340 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
341 uint32_t membase, irq;
343 /* Save important PCI config data. */
344 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
345 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
347 /* Reset the power state. */
348 device_printf(dev, "chip is in D%d power mode"
349 " -- setting to D0\n", pci_get_powerstate(dev));
351 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
353 /* Restore PCI config data. */
354 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
355 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
357 #endif /* !BURN_BRIDGE */
360 * Map control/status registers.
362 pci_enable_busmaster(dev);
365 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
367 if (sc->bfe_res == NULL) {
368 device_printf(dev, "couldn't map memory\n");
372 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
373 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
375 /* Allocate interrupt */
378 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
379 RF_SHAREABLE | RF_ACTIVE);
380 if (sc->bfe_irq == NULL) {
381 device_printf(dev, "couldn't map interrupt\n");
386 error = bfe_dma_alloc(dev);
388 device_printf(dev, "failed to allocate DMA resources\n");
392 /* Set up ifnet structure */
393 ifp = &sc->arpcom.ac_if;
395 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
396 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
397 ifp->if_ioctl = bfe_ioctl;
398 ifp->if_start = bfe_start;
399 ifp->if_watchdog = bfe_watchdog;
400 ifp->if_init = bfe_init;
401 ifp->if_mtu = ETHERMTU;
402 ifp->if_baudrate = 100000000;
403 ifp->if_capabilities |= IFCAP_VLAN_MTU;
404 ifp->if_capenable |= IFCAP_VLAN_MTU;
405 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
406 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
407 ifq_set_ready(&ifp->if_snd);
411 /* Reset the chip and turn on the PHY */
414 if (mii_phy_probe(dev, &sc->bfe_miibus,
415 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
416 device_printf(dev, "MII without any PHY!\n");
421 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
424 * Hook interrupt last to avoid having to lock softc
426 error = bus_setup_intr(dev, sc->bfe_irq, INTR_NETSAFE,
427 bfe_intr, sc, &sc->bfe_intrhand,
428 sc->arpcom.ac_if.if_serializer);
432 device_printf(dev, "couldn't set up irq\n");
436 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq));
437 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
445 bfe_detach(device_t dev)
447 struct bfe_softc *sc = device_get_softc(dev);
448 struct ifnet *ifp = &sc->arpcom.ac_if;
450 if (device_is_attached(dev)) {
451 lwkt_serialize_enter(ifp->if_serializer);
454 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
455 lwkt_serialize_exit(ifp->if_serializer);
459 if (sc->bfe_miibus != NULL)
460 device_delete_child(dev, sc->bfe_miibus);
461 bus_generic_detach(dev);
463 if (sc->bfe_irq != NULL)
464 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
466 if (sc->bfe_res != NULL) {
467 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
476 * Stop all chip I/O so that the kernel's probe routines don't
477 * get confused by errant DMAs when rebooting.
480 bfe_shutdown(device_t dev)
482 struct bfe_softc *sc = device_get_softc(dev);
483 struct ifnet *ifp = &sc->arpcom.ac_if;
485 lwkt_serialize_enter(ifp->if_serializer);
487 lwkt_serialize_exit(ifp->if_serializer);
491 bfe_miibus_readreg(device_t dev, int phy, int reg)
493 struct bfe_softc *sc;
496 sc = device_get_softc(dev);
497 if (phy != sc->bfe_phyaddr)
499 bfe_readphy(sc, reg, &ret);
505 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
507 struct bfe_softc *sc;
509 sc = device_get_softc(dev);
510 if (phy != sc->bfe_phyaddr)
512 bfe_writephy(sc, reg, val);
518 bfe_miibus_statchg(device_t dev)
524 bfe_tx_ring_free(struct bfe_softc *sc)
528 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
529 bus_dmamap_unload(sc->bfe_tag,
530 sc->bfe_tx_ring[i].bfe_map);
531 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
532 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
533 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
536 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
537 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
541 bfe_rx_ring_free(struct bfe_softc *sc)
545 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
546 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
547 bus_dmamap_unload(sc->bfe_tag,
548 sc->bfe_rx_ring[i].bfe_map);
549 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
550 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
553 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
554 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
558 bfe_list_rx_init(struct bfe_softc *sc)
562 for (i = 0; i < BFE_RX_LIST_CNT; i++)
563 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
566 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
567 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
575 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
577 struct bfe_rxheader *rx_header;
582 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
586 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
589 m->m_len = m->m_pkthdr.len = MCLBYTES;
592 m->m_data = m->m_ext.ext_buf;
594 rx_header = mtod(m, struct bfe_rxheader *);
596 rx_header->flags = 0;
598 /* Map the mbuf into DMA */
600 d = &sc->bfe_rx_list[c];
601 r = &sc->bfe_rx_ring[c];
603 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
604 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT);
605 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
607 ctrl = ETHER_MAX_LEN + 32;
609 if(c == BFE_RX_LIST_CNT - 1)
610 ctrl |= BFE_DESC_EOT;
614 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
619 bfe_get_config(struct bfe_softc *sc)
623 bfe_read_eeprom(sc, eeprom);
625 sc->arpcom.ac_enaddr[0] = eeprom[79];
626 sc->arpcom.ac_enaddr[1] = eeprom[78];
627 sc->arpcom.ac_enaddr[2] = eeprom[81];
628 sc->arpcom.ac_enaddr[3] = eeprom[80];
629 sc->arpcom.ac_enaddr[4] = eeprom[83];
630 sc->arpcom.ac_enaddr[5] = eeprom[82];
632 sc->bfe_phyaddr = eeprom[90] & 0x1f;
633 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
635 sc->bfe_core_unit = 0;
636 sc->bfe_dma_offset = BFE_PCI_DMA;
640 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
642 uint32_t bar_orig, pci_rev, val;
644 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
645 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
646 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
648 val = CSR_READ_4(sc, BFE_SBINTVEC);
650 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
652 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
653 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
654 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
656 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
660 bfe_clear_stats(struct bfe_softc *sc)
664 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
665 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
667 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
672 bfe_resetphy(struct bfe_softc *sc)
676 bfe_writephy(sc, 0, BMCR_RESET);
678 bfe_readphy(sc, 0, &val);
679 if (val & BMCR_RESET) {
680 if_printf(&sc->arpcom.ac_if,
681 "PHY Reset would not complete.\n");
688 bfe_chip_halt(struct bfe_softc *sc)
690 /* disable interrupts - not that it actually does..*/
691 CSR_WRITE_4(sc, BFE_IMASK, 0);
692 CSR_READ_4(sc, BFE_IMASK);
694 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
695 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
697 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
698 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
703 bfe_chip_reset(struct bfe_softc *sc)
707 /* Set the interrupt vector for the enet core */
708 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
711 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
712 if (val == BFE_CLOCK) {
713 /* It is, so shut it down */
714 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
715 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
716 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
717 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
718 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
719 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
720 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
721 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
722 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
729 * We want the phy registers to be accessible even when
730 * the driver is "downed" so initialize MDC preamble, frequency,
731 * and whether internal or external phy here.
734 /* 4402 has 62.5Mhz SB clock and internal phy */
735 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
737 /* Internal or external PHY? */
738 val = CSR_READ_4(sc, BFE_DEVCTRL);
739 if (!(val & BFE_IPP))
740 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
741 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
742 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
746 /* Enable CRC32 generation and set proper LED modes */
747 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
749 /* Reset or clear powerdown control bit */
750 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
752 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
756 * We don't want lazy interrupts, so just send them at the end of a
759 BFE_OR(sc, BFE_RCV_LAZY, 0);
761 /* Set max lengths, accounting for VLAN tags */
762 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
763 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
765 /* Set watermark XXX - magic */
766 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
769 * Initialise DMA channels - not forgetting dma addresses need to be
770 * added to BFE_PCI_DMA
772 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
773 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
775 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
777 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
784 bfe_core_disable(struct bfe_softc *sc)
786 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
790 * Set reject, wait for it set, then wait for the core to stop being busy
791 * Then set reset and reject and enable the clocks
793 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
794 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
795 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
796 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
798 CSR_READ_4(sc, BFE_SBTMSLOW);
800 /* Leave reset and reject set */
801 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
806 bfe_core_reset(struct bfe_softc *sc)
810 /* Disable the core */
811 bfe_core_disable(sc);
813 /* and bring it back up */
814 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
815 CSR_READ_4(sc, BFE_SBTMSLOW);
818 /* Chip bug, clear SERR, IB and TO if they are set. */
819 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
820 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
821 val = CSR_READ_4(sc, BFE_SBIMSTATE);
822 if (val & (BFE_IBE | BFE_TO))
823 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
825 /* Clear reset and allow it to move through the core */
826 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
827 CSR_READ_4(sc, BFE_SBTMSLOW);
830 /* Leave the clock set */
831 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
832 CSR_READ_4(sc, BFE_SBTMSLOW);
837 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
841 val = ((uint32_t) data[2]) << 24;
842 val |= ((uint32_t) data[3]) << 16;
843 val |= ((uint32_t) data[4]) << 8;
844 val |= ((uint32_t) data[5]);
845 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
846 val = (BFE_CAM_HI_VALID |
847 (((uint32_t) data[0]) << 8) |
848 (((uint32_t) data[1])));
849 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
850 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
851 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
852 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
856 bfe_set_rx_mode(struct bfe_softc *sc)
858 struct ifnet *ifp = &sc->arpcom.ac_if;
859 struct ifmultiaddr *ifma;
863 val = CSR_READ_4(sc, BFE_RXCONF);
865 if (ifp->if_flags & IFF_PROMISC)
866 val |= BFE_RXCONF_PROMISC;
868 val &= ~BFE_RXCONF_PROMISC;
870 if (ifp->if_flags & IFF_BROADCAST)
871 val &= ~BFE_RXCONF_DBCAST;
873 val |= BFE_RXCONF_DBCAST;
876 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
877 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
879 if (ifp->if_flags & IFF_ALLMULTI) {
880 val |= BFE_RXCONF_ALLMULTI;
882 val &= ~BFE_RXCONF_ALLMULTI;
883 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
884 if (ifma->ifma_addr->sa_family != AF_LINK)
887 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
891 CSR_WRITE_4(sc, BFE_RXCONF, val);
892 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
896 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
901 *ptr = segs->ds_addr;
905 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
910 /* The chip needs all addresses to be added to BFE_PCI_DMA */
911 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
915 bfe_dma_free(struct bfe_softc *sc)
917 if (sc->bfe_tx_tag != NULL) {
918 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
919 if (sc->bfe_tx_list != NULL) {
920 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
922 sc->bfe_tx_list = NULL;
924 bus_dma_tag_destroy(sc->bfe_tx_tag);
925 sc->bfe_tx_tag = NULL;
928 if (sc->bfe_rx_tag != NULL) {
929 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
930 if (sc->bfe_rx_list != NULL) {
931 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
933 sc->bfe_rx_list = NULL;
935 bus_dma_tag_destroy(sc->bfe_rx_tag);
936 sc->bfe_rx_tag = NULL;
939 if (sc->bfe_tag != NULL) {
942 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
943 bus_dmamap_destroy(sc->bfe_tag,
944 sc->bfe_tx_ring[i].bfe_map);
946 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
947 bus_dmamap_destroy(sc->bfe_tag,
948 sc->bfe_rx_ring[i].bfe_map);
951 bus_dma_tag_destroy(sc->bfe_tag);
955 if (sc->bfe_parent_tag != NULL) {
956 bus_dma_tag_destroy(sc->bfe_parent_tag);
957 sc->bfe_parent_tag = NULL;
962 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
965 uint16_t *ptr = (uint16_t *)data;
967 for (i = 0; i < 128; i += 2)
968 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
972 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
973 u_long timeout, const int clear)
977 for (i = 0; i < timeout; i++) {
978 uint32_t val = CSR_READ_4(sc, reg);
980 if (clear && !(val & bit))
982 if (!clear && (val & bit))
987 if_printf(&sc->arpcom.ac_if,
988 "BUG! Timeout waiting for bit %08x of register "
989 "%x to %s.\n", bit, reg,
990 (clear ? "clear" : "set"));
997 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
1002 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1003 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1004 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1005 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1006 (reg << BFE_MDIO_RA_SHIFT) |
1007 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1008 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1009 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1014 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1018 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1019 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1020 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1021 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1022 (reg << BFE_MDIO_RA_SHIFT) |
1023 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1024 (val & BFE_MDIO_DATA_DATA)));
1025 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1031 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1035 bfe_setupphy(struct bfe_softc *sc)
1039 /* Enable activity LED */
1040 bfe_readphy(sc, 26, &val);
1041 bfe_writephy(sc, 26, val & 0x7fff);
1042 bfe_readphy(sc, 26, &val);
1044 /* Enable traffic meter LED mode */
1045 bfe_readphy(sc, 27, &val);
1046 bfe_writephy(sc, 27, val | (1 << 6));
1052 bfe_stats_update(struct bfe_softc *sc)
1057 val = &sc->bfe_hwstats.tx_good_octets;
1058 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1059 *val++ += CSR_READ_4(sc, reg);
1060 val = &sc->bfe_hwstats.rx_good_octets;
1061 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1062 *val++ += CSR_READ_4(sc, reg);
1066 bfe_txeof(struct bfe_softc *sc)
1068 struct ifnet *ifp = &sc->arpcom.ac_if;
1069 uint32_t i, chipidx;
1071 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1072 chipidx /= sizeof(struct bfe_desc);
1074 i = sc->bfe_tx_cons;
1075 /* Go through the mbufs and free those that have been transmitted */
1076 while (i != chipidx) {
1077 struct bfe_data *r = &sc->bfe_tx_ring[i];
1079 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1080 if (r->bfe_mbuf != NULL) {
1082 m_freem(r->bfe_mbuf);
1086 BFE_INC(i, BFE_TX_LIST_CNT);
1089 if (i != sc->bfe_tx_cons) {
1090 /* we freed up some mbufs */
1091 sc->bfe_tx_cons = i;
1092 ifp->if_flags &= ~IFF_OACTIVE;
1094 if (sc->bfe_tx_cnt == 0)
1100 /* Pass a received packet up the stack */
1102 bfe_rxeof(struct bfe_softc *sc)
1104 struct ifnet *ifp = &sc->arpcom.ac_if;
1106 struct bfe_rxheader *rxheader;
1108 uint32_t cons, status, current, len, flags;
1109 #ifdef ETHER_INPUT_CHAIN
1110 struct mbuf_chain chain[MAXCPU];
1113 cons = sc->bfe_rx_cons;
1114 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1115 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1117 #ifdef ETHER_INPUT_CHAIN
1118 ether_input_chain_init(chain);
1121 while (current != cons) {
1122 r = &sc->bfe_rx_ring[cons];
1124 rxheader = mtod(m, struct bfe_rxheader*);
1125 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD);
1126 len = rxheader->len;
1129 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1130 flags = rxheader->flags;
1132 len -= ETHER_CRC_LEN;
1134 /* flag an error and try again */
1135 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1137 if (flags & BFE_RX_FLAG_SERR)
1138 ifp->if_collisions++;
1139 bfe_list_newbuf(sc, cons, m);
1140 BFE_INC(cons, BFE_RX_LIST_CNT);
1144 /* Go past the rx header */
1145 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1146 bfe_list_newbuf(sc, cons, m);
1147 BFE_INC(cons, BFE_RX_LIST_CNT);
1152 m_adj(m, BFE_RX_OFFSET);
1153 m->m_len = m->m_pkthdr.len = len;
1156 m->m_pkthdr.rcvif = ifp;
1158 #ifdef ETHER_INPUT_CHAIN
1159 ether_input_chain2(ifp, m, chain);
1161 ifp->if_input(ifp, m);
1163 BFE_INC(cons, BFE_RX_LIST_CNT);
1166 #ifdef ETHER_INPUT_CHAIN
1167 ether_input_dispatch(chain);
1170 sc->bfe_rx_cons = cons;
1176 struct bfe_softc *sc = xsc;
1177 struct ifnet *ifp = &sc->arpcom.ac_if;
1178 uint32_t istat, imask, flag;
1180 istat = CSR_READ_4(sc, BFE_ISTAT);
1181 imask = CSR_READ_4(sc, BFE_IMASK);
1184 * Defer unsolicited interrupts - This is necessary because setting the
1185 * chips interrupt mask register to 0 doesn't actually stop the
1189 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1190 CSR_READ_4(sc, BFE_ISTAT);
1192 /* not expecting this interrupt, disregard it */
1197 if (istat & BFE_ISTAT_ERRORS) {
1198 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1199 if (flag & BFE_STAT_EMASK)
1202 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1203 if (flag & BFE_RX_FLAG_ERRORS)
1206 ifp->if_flags &= ~IFF_RUNNING;
1210 /* A packet was received */
1211 if (istat & BFE_ISTAT_RX)
1214 /* A packet was sent */
1215 if (istat & BFE_ISTAT_TX)
1218 /* We have packets pending, fire them out */
1219 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1224 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1226 struct bfe_desc *d = NULL;
1227 struct bfe_data *r = NULL;
1229 uint32_t frag, cur, cnt = 0;
1230 int error, chainlen = 0;
1232 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt));
1235 * Count the number of frags in this chain to see if
1236 * we need to m_defrag. Since the descriptor list is shared
1237 * by all packets, we'll m_defrag long chains so that they
1238 * do not use up the entire list, even if they would fit.
1240 for (m = *m_head; m != NULL; m = m->m_next)
1243 if (chainlen > (BFE_TX_LIST_CNT / 4) ||
1244 BFE_TX_LIST_CNT < (2 + chainlen + sc->bfe_tx_cnt)) {
1245 m = m_defrag(*m_head, MB_DONTWAIT);
1254 * Start packing the mbufs in this chain into
1255 * the fragment pointers. Stop when we run out
1256 * of fragments or hit the end of the mbuf chain.
1258 cur = frag = *txidx;
1261 for (m = *m_head; m != NULL; m = m->m_next) {
1262 if (m->m_len != 0) {
1263 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt + cnt));
1265 d = &sc->bfe_tx_list[cur];
1266 r = &sc->bfe_tx_ring[cur];
1267 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1268 /* always intterupt on completion */
1269 d->bfe_ctrl |= BFE_DESC_IOC;
1271 /* Set start of frame */
1272 d->bfe_ctrl |= BFE_DESC_SOF;
1274 if (cur == BFE_TX_LIST_CNT - 1) {
1276 * Tell the chip to wrap to the start of the
1279 d->bfe_ctrl |= BFE_DESC_EOT;
1282 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map,
1283 mtod(m, void *), m->m_len,
1284 bfe_dma_map_desc, d,
1287 /* XXX This should be a fatal error. */
1288 if_printf(&sc->arpcom.ac_if,
1289 "%s bus_dmamap_load failed: %d",
1295 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1296 BUS_DMASYNC_PREWRITE);
1299 BFE_INC(cur, BFE_TX_LIST_CNT);
1304 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1305 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head;
1306 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
1309 sc->bfe_tx_cnt += cnt;
1314 * Set up to transmit a packet
1317 bfe_start(struct ifnet *ifp)
1319 struct bfe_softc *sc = ifp->if_softc;
1320 struct mbuf *m_head = NULL;
1321 int idx, need_trans;
1324 * Not much point trying to send if the link is down
1325 * or we have nothing to send.
1327 if (!sc->bfe_link) {
1328 ifq_purge(&ifp->if_snd);
1332 if (ifp->if_flags & IFF_OACTIVE)
1335 idx = sc->bfe_tx_prod;
1338 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1339 if (BFE_TX_LIST_CNT < (2 + sc->bfe_tx_cnt)) {
1340 ifp->if_flags |= IFF_OACTIVE;
1344 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1349 * Pack the data into the tx ring. If we don't have
1350 * enough room, let the chip drain the ring.
1352 if (bfe_encap(sc, &m_head, &idx)) {
1353 ifp->if_flags |= IFF_OACTIVE;
1359 * If there's a BPF listener, bounce a copy of this frame
1362 BPF_MTAP(ifp, m_head);
1368 sc->bfe_tx_prod = idx;
1369 /* Transmit - twice due to apparent hardware bug */
1370 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1371 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1374 * Set a timeout in case the chip goes out to lunch.
1382 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1383 struct ifnet *ifp = &sc->arpcom.ac_if;
1385 if (ifp->if_flags & IFF_RUNNING)
1391 if (bfe_list_rx_init(sc) == ENOBUFS) {
1392 if_printf(ifp, "bfe_init failed. "
1393 " Not enough memory for list buffers\n");
1398 bfe_set_rx_mode(sc);
1400 /* Enable the chip and core */
1401 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1402 /* Enable interrupts */
1403 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1405 bfe_ifmedia_upd(ifp);
1406 ifp->if_flags |= IFF_RUNNING;
1407 ifp->if_flags &= ~IFF_OACTIVE;
1409 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1413 * Set media options.
1416 bfe_ifmedia_upd(struct ifnet *ifp)
1418 struct bfe_softc *sc = ifp->if_softc;
1419 struct mii_data *mii;
1421 mii = device_get_softc(sc->bfe_miibus);
1423 if (mii->mii_instance) {
1424 struct mii_softc *miisc;
1425 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1426 miisc = LIST_NEXT(miisc, mii_list))
1427 mii_phy_reset(miisc);
1437 * Report current media status.
1440 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1442 struct bfe_softc *sc = ifp->if_softc;
1443 struct mii_data *mii;
1445 mii = device_get_softc(sc->bfe_miibus);
1447 ifmr->ifm_active = mii->mii_media_active;
1448 ifmr->ifm_status = mii->mii_media_status;
1452 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1454 struct bfe_softc *sc = ifp->if_softc;
1455 struct ifreq *ifr = (struct ifreq *) data;
1456 struct mii_data *mii;
1461 if (ifp->if_flags & IFF_UP)
1462 if (ifp->if_flags & IFF_RUNNING)
1463 bfe_set_rx_mode(sc);
1466 else if (ifp->if_flags & IFF_RUNNING)
1471 if (ifp->if_flags & IFF_RUNNING)
1472 bfe_set_rx_mode(sc);
1476 mii = device_get_softc(sc->bfe_miibus);
1477 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1481 error = ether_ioctl(ifp, command, data);
1488 bfe_watchdog(struct ifnet *ifp)
1490 struct bfe_softc *sc = ifp->if_softc;
1492 if_printf(ifp, "watchdog timeout -- resetting\n");
1494 ifp->if_flags &= ~IFF_RUNNING;
1503 struct bfe_softc *sc = xsc;
1504 struct mii_data *mii;
1505 struct ifnet *ifp = &sc->arpcom.ac_if;
1507 mii = device_get_softc(sc->bfe_miibus);
1509 lwkt_serialize_enter(ifp->if_serializer);
1511 bfe_stats_update(sc);
1512 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1514 if (sc->bfe_link == 0) {
1516 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1517 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1523 lwkt_serialize_exit(ifp->if_serializer);
1527 * Stop the adapter and free any mbufs allocated to the
1531 bfe_stop(struct bfe_softc *sc)
1533 struct ifnet *ifp = &sc->arpcom.ac_if;
1535 callout_stop(&sc->bfe_stat_timer);
1538 bfe_tx_ring_free(sc);
1539 bfe_rx_ring_free(sc);
1541 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);