2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
5 * ISA-specific part separated from:
6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
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17 * must display the following acknowledgement:
18 * This product includes software developed by Comtrol Corporation.
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35 * $FreeBSD: src/sys/dev/rp/rp_isa.c,v 1.3.2.1 2002/06/18 03:11:46 obrien Exp $
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/fcntl.h>
41 #include <sys/malloc.h>
44 #include <sys/kernel.h>
52 #include <bus/isa/isavar.h>
54 /* ISA-specific part of CONTROLLER_t */
55 struct ISACONTROLLER_T {
56 int MBaseIO; /* rid of the Mudbac controller for this controller */
57 int MReg0IO; /* offset0 of the Mudbac controller for this controller */
58 int MReg1IO; /* offset1 of the Mudbac controller for this controller */
59 int MReg2IO; /* offset2 of the Mudbac controller for this controller */
60 int MReg3IO; /* offset3 of the Mudbac controller for this controller */
64 typedef struct ISACONTROLLER_T ISACONTROLLER_t;
66 #define ISACTL(ctlp) ((ISACONTROLLER_t *)((ctlp)->bus_ctlp))
68 /***************************************************************************
69 Function: sControllerEOI
70 Purpose: Strobe the MUDBAC's End Of Interrupt bit.
71 Call: sControllerEOI(MudbacCtlP,CtlP)
72 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
73 CONTROLLER_T *CtlP; Ptr to controller structure
75 #define sControllerEOI(MudbacCtlP,CtlP) \
76 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg2IO,ISACTL(CtlP)->MReg2 | INT_STROB)
78 /***************************************************************************
80 Purpose: Disable I/O access to an AIOP
81 Call: sDisAiop(MudbacCtlP,CtlP)
82 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
83 CONTROLLER_T *CtlP; Ptr to controller structure
84 int AiopNum; Number of AIOP on controller
86 #define sDisAiop(MudbacCtlP,CtlP,AIOPNUM) \
88 ISACTL(CtlP)->MReg3 &= rp_sBitMapClrTbl[AIOPNUM]; \
89 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3); \
92 /***************************************************************************
94 Purpose: Enable I/O access to an AIOP
95 Call: sEnAiop(MudbacCtlP,CtlP)
96 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
97 CONTROLLER_T *CtlP; Ptr to controller structure
98 int AiopNum; Number of AIOP on controller
100 #define sEnAiop(MudbacCtlP,CtlP,AIOPNUM) \
102 ISACTL(CtlP)->MReg3 |= rp_sBitMapSetTbl[AIOPNUM]; \
103 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3); \
106 /***************************************************************************
107 Function: sGetControllerIntStatus
108 Purpose: Get the controller interrupt status
109 Call: sGetControllerIntStatus(MudbacCtlP,CtlP)
110 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
111 CONTROLLER_T *CtlP; Ptr to controller structure
112 Return: Byte_t: The controller interrupt status in the lower 4
113 bits. Bits 0 through 3 represent AIOP's 0
114 through 3 respectively. If a bit is set that
115 AIOP is interrupting. Bits 4 through 7 will
118 #define sGetControllerIntStatus(MudbacCtlP,CtlP) \
119 (rp_readio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg1IO) & 0x0f)
121 static devclass_t rp_devclass;
122 static CONTROLLER_t *rp_controller;
123 static int rp_nisadevs;
125 static int rp_probe(device_t dev);
126 static int rp_attach(device_t dev);
127 static void rp_isareleaseresource(CONTROLLER_t *ctlp);
128 static int sInitController(CONTROLLER_T *CtlP,
129 CONTROLLER_T *MudbacCtlP,
134 static rp_aiop2rid_t rp_isa_aiop2rid;
135 static rp_aiop2off_t rp_isa_aiop2off;
136 static rp_ctlmask_t rp_isa_ctlmask;
139 rp_probe(device_t dev)
142 CONTROLLER_t *controller;
148 * We have no PnP RocketPort cards.
149 * (At least according to LINT)
151 if (isa_get_logicalid(dev) != 0)
154 /* We need IO port resource to configure an ISA device. */
155 if (bus_get_resource_count(dev, SYS_RES_IOPORT, 0) == 0)
158 unit = device_get_unit(dev);
160 device_printf(dev, "rpprobe: unit number %d invalid.\n", unit);
163 device_printf(dev, "probing for RocketPort(ISA) unit %d.\n", unit);
165 ctlp = device_get_softc(dev);
166 bzero(ctlp, sizeof(*ctlp));
168 ctlp->aiop2rid = rp_isa_aiop2rid;
169 ctlp->aiop2off = rp_isa_aiop2off;
170 ctlp->ctlmask = rp_isa_ctlmask;
172 /* The IO ports of AIOPs for an ISA controller are discrete. */
174 ctlp->io_rid = kmalloc(sizeof(*(ctlp->io_rid)) * MAX_AIOPS_PER_BOARD,
175 M_DEVBUF, M_WAITOK | M_ZERO);
176 ctlp->io = kmalloc(sizeof(*(ctlp->io)) * MAX_AIOPS_PER_BOARD,
177 M_DEVBUF, M_WAITOK | M_ZERO);
179 ctlp->bus_ctlp = kmalloc(sizeof(ISACONTROLLER_t) * 1,
180 M_DEVBUF, M_WAITOK | M_ZERO);
183 if (rp_controller != NULL) {
184 controller = rp_controller;
185 ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 0x40, RF_ACTIVE);
187 controller = rp_controller = ctlp;
188 ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 0x44, RF_ACTIVE);
190 if (ctlp->io[0] == NULL) {
191 device_printf(dev, "rp_attach: Resource not available.\n");
196 num_aiops = sInitController(ctlp,
198 MAX_AIOPS_PER_BOARD, 0,
200 if (num_aiops <= 0) {
201 device_printf(dev, "board%d init failed.\n", unit);
206 if (rp_controller == NULL)
207 rp_controller = controller;
210 device_set_desc(dev, "RocketPort ISA");
215 rp_isareleaseresource(ctlp);
221 rp_attach(device_t dev)
223 int num_ports, num_aiops;
228 ctlp = device_get_softc(dev);
231 num_aiops = sInitController(ctlp,
233 MAX_AIOPS_PER_BOARD, 0,
236 num_aiops = ctlp->NumAiop;
240 for(aiop=0; aiop < num_aiops; aiop++) {
241 sResetAiopByNum(ctlp, aiop);
242 sEnAiop(rp_controller, ctlp, aiop);
243 num_ports += sGetAiopNumChan(ctlp, aiop);
246 retval = rp_attachcommon(ctlp, num_aiops, num_ports);
253 rp_isareleaseresource(ctlp);
259 rp_isareleaseresource(CONTROLLER_t *ctlp)
263 rp_releaseresource(ctlp);
265 if (ctlp == rp_controller)
266 rp_controller = NULL;
267 if (ctlp->io != NULL) {
268 for (i = 0 ; i < MAX_AIOPS_PER_BOARD ; i++)
269 if (ctlp->io[i] != NULL)
270 bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[i], ctlp->io[i]);
271 kfree(ctlp->io, M_DEVBUF);
273 if (ctlp->io_rid != NULL)
274 kfree(ctlp->io_rid, M_DEVBUF);
275 if (rp_controller != NULL && rp_controller->io[ISACTL(ctlp)->MBaseIO] != NULL) {
276 bus_release_resource(rp_controller->dev, SYS_RES_IOPORT, rp_controller->io_rid[ISACTL(ctlp)->MBaseIO], rp_controller->io[ISACTL(ctlp)->MBaseIO]);
277 rp_controller->io[ISACTL(ctlp)->MBaseIO] = NULL;
278 rp_controller->io_rid[ISACTL(ctlp)->MBaseIO] = 0;
280 if (ctlp->bus_ctlp != NULL)
281 kfree(ctlp->bus_ctlp, M_DEVBUF);
284 /***************************************************************************
285 Function: sInitController
286 Purpose: Initialization of controller global registers and controller
288 Call: sInitController(CtlP,MudbacCtlP,AiopNum,
289 IRQNum,Frequency,PeriodicOnly)
290 CONTROLLER_T *CtlP; Ptr to controller structure
291 CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
292 int AiopNum; Number of Aiops
293 int IRQNum; Interrupt Request number. Can be any of the following:
294 0: Disable global interrupts
303 Byte_t Frequency: A flag identifying the frequency
304 of the periodic interrupt, can be any one of the following:
305 FREQ_DIS - periodic interrupt disabled
306 FREQ_137HZ - 137 Hertz
312 If IRQNum is set to 0 the Frequency parameter is
313 overidden, it is forced to a value of FREQ_DIS.
314 int PeriodicOnly: TRUE if all interrupts except the periodic
315 interrupt are to be blocked.
316 FALSE is both the periodic interrupt and
317 other channel interrupts are allowed.
318 If IRQNum is set to 0 the PeriodicOnly parameter is
319 overidden, it is forced to a value of FALSE.
320 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
321 initialization failed.
324 If periodic interrupts are to be disabled but AIOP interrupts
325 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE.
327 If interrupts are to be completely disabled set IRQNum to 0.
329 Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an
332 This function performs initialization of global interrupt modes,
333 but it does not actually enable global interrupts. To enable
334 and disable global interrupts use functions sEnGlobalInt() and
335 sDisGlobalInt(). Enabling of global interrupts is normally not
336 done until all other initializations are complete.
338 Even if interrupts are globally enabled, they must also be
339 individually enabled for each channel that is to generate
342 Warnings: No range checking on any of the parameters is done.
344 No context switches are allowed while executing this function.
346 After this function all AIOPs on the controller are disabled,
347 they can be enabled with sEnAiop().
350 sInitController( CONTROLLER_T *CtlP,
351 CONTROLLER_T *MudbacCtlP,
358 int ctl_base, aiop_base, aiop_size;
360 CtlP->CtlID = CTLID_0001; /* controller release 1 */
362 ISACTL(CtlP)->MBaseIO = rp_nisadevs;
363 if (MudbacCtlP->io[ISACTL(CtlP)->MBaseIO] != NULL) {
364 ISACTL(CtlP)->MReg0IO = 0x40 + 0;
365 ISACTL(CtlP)->MReg1IO = 0x40 + 1;
366 ISACTL(CtlP)->MReg2IO = 0x40 + 2;
367 ISACTL(CtlP)->MReg3IO = 0x40 + 3;
369 MudbacCtlP->io_rid[ISACTL(CtlP)->MBaseIO] = ISACTL(CtlP)->MBaseIO;
370 ctl_base = rman_get_start(MudbacCtlP->io[0]) + 0x40 + 0x400 * rp_nisadevs;
371 MudbacCtlP->io[ISACTL(CtlP)->MBaseIO] = bus_alloc_resource(MudbacCtlP->dev, SYS_RES_IOPORT, &CtlP->io_rid[ISACTL(CtlP)->MBaseIO], ctl_base, ctl_base + 3, 4, RF_ACTIVE);
372 ISACTL(CtlP)->MReg0IO = 0;
373 ISACTL(CtlP)->MReg1IO = 1;
374 ISACTL(CtlP)->MReg2IO = 2;
375 ISACTL(CtlP)->MReg3IO = 3;
378 ISACTL(CtlP)->MReg2 = 0; /* interrupt disable */
379 ISACTL(CtlP)->MReg3 = 0; /* no periodic interrupts */
381 if(sIRQMap[IRQNum] == 0) /* interrupts globally disabled */
383 ISACTL(CtlP)->MReg2 = 0; /* interrupt disable */
384 ISACTL(CtlP)->MReg3 = 0; /* no periodic interrupts */
388 ISACTL(CtlP)->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
389 ISACTL(CtlP)->MReg3 = Frequency; /* set frequency */
390 if(PeriodicOnly) /* periodic interrupt only */
392 ISACTL(CtlP)->MReg3 |= PERIODIC_ONLY;
396 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg2IO,ISACTL(CtlP)->MReg2);
397 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3);
398 sControllerEOI(MudbacCtlP,CtlP); /* clear EOI if warm init */
402 for(i=0; i < AiopNum; i++)
404 if (CtlP->io[i] == NULL) {
406 aiop_base = rman_get_start(CtlP->io[0]) + 0x400 * i;
407 if (rp_nisadevs == 0)
411 CtlP->io[i] = bus_alloc_resource(CtlP->dev, SYS_RES_IOPORT, &CtlP->io_rid[i], aiop_base, aiop_base + aiop_size - 1, aiop_size, RF_ACTIVE);
413 aiop_base = rman_get_start(CtlP->io[i]);
414 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,
415 ISACTL(CtlP)->MReg2IO,
416 ISACTL(CtlP)->MReg2 | (i & 0x03)); /* AIOP index */
417 rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,
418 ISACTL(CtlP)->MReg0IO,
419 (Byte_t)(aiop_base >> 6)); /* set up AIOP I/O in MUDBAC */
420 sEnAiop(MudbacCtlP,CtlP,i); /* enable the AIOP */
422 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
423 if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
425 sDisAiop(MudbacCtlP,CtlP,i); /* disable AIOP */
426 bus_release_resource(CtlP->dev, SYS_RES_IOPORT, CtlP->io_rid[i], CtlP->io[i]);
428 break; /* done looking for AIOPs */
431 CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i); /* num channels in AIOP */
432 rp_writeaiop2(CtlP,i,_INDX_ADDR,_CLK_PRE); /* clock prescaler */
433 rp_writeaiop1(CtlP,i,_INDX_DATA,CLOCK_PRESC);
434 CtlP->NumAiop++; /* bump count of AIOPs */
435 sDisAiop(MudbacCtlP,CtlP,i); /* disable AIOP */
438 if(CtlP->NumAiop == 0)
441 return(CtlP->NumAiop);
446 * Maps (aiop, offset) to rid.
449 rp_isa_aiop2rid(int aiop, int offset)
451 /* rid equals to aiop for an ISA controller. */
457 * Maps (aiop, offset) to the offset of resource.
460 rp_isa_aiop2off(int aiop, int offset)
462 /* Each aiop has its own resource. */
466 /* Read the int status for an ISA controller. */
468 rp_isa_ctlmask(CONTROLLER_t *ctlp)
470 return sGetControllerIntStatus(rp_controller,ctlp);
473 static device_method_t rp_methods[] = {
474 /* Device interface */
475 DEVMETHOD(device_probe, rp_probe),
476 DEVMETHOD(device_attach, rp_attach),
481 static driver_t rp_driver = {
484 sizeof(CONTROLLER_t),
488 * rp can be attached to an isa bus.
490 DRIVER_MODULE(rp, isa, rp_driver, rp_devclass, NULL, NULL);