2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $
33 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
37 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
39 * Permission to use, copy, modify, and distribute this software for any
40 * purpose with or without fee is hereby granted, provided that the above
41 * copyright notice and this permission notice appear in all copies.
43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
53 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
54 * the SK-984x series adapters, both single port and dual port.
56 * The XaQti XMAC II datasheet,
57 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
58 * The SysKonnect GEnesis manual, http://www.syskonnect.com
60 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
61 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
62 * convenience to others until Vitesse corrects this problem:
64 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
66 * Written by Bill Paul <wpaul@ee.columbia.edu>
67 * Department of Electrical Engineering
68 * Columbia University, New York City
72 * The SysKonnect gigabit ethernet adapters consist of two main
73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75 * components and a PHY while the GEnesis controller provides a PCI
76 * interface with DMA support. Each card may have between 512K and
77 * 2MB of SRAM on board depending on the configuration.
79 * The SysKonnect GEnesis controller can have either one or two XMAC
80 * chips connected to it, allowing single or dual port NIC configurations.
81 * SysKonnect has the distinction of being the only vendor on the market
82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84 * XMAC registers. This driver takes advantage of these features to allow
85 * both XMACs to operate as independent interfaces.
88 #include <sys/param.h>
90 #include <sys/endian.h>
91 #include <sys/in_cksum.h>
92 #include <sys/kernel.h>
93 #include <sys/interrupt.h>
95 #include <sys/malloc.h>
96 #include <sys/queue.h>
98 #include <sys/serialize.h>
99 #include <sys/socket.h>
100 #include <sys/sockio.h>
101 #include <sys/sysctl.h>
104 #include <net/ethernet.h>
106 #include <net/if_arp.h>
107 #include <net/if_dl.h>
108 #include <net/if_media.h>
109 #include <net/ifq_var.h>
110 #include <net/vlan/if_vlan_var.h>
112 #include <netinet/ip.h>
113 #include <netinet/udp.h>
115 #include <dev/netif/mii_layer/mii.h>
116 #include <dev/netif/mii_layer/miivar.h>
117 #include <dev/netif/mii_layer/brgphyreg.h>
119 #include <bus/pci/pcireg.h>
120 #include <bus/pci/pcivar.h>
121 #include <bus/pci/pcidevs.h>
123 #include <dev/netif/sk/if_skreg.h>
124 #include <dev/netif/sk/yukonreg.h>
125 #include <dev/netif/sk/xmaciireg.h>
126 #include <dev/netif/sk/if_skvar.h>
128 #include "miibus_if.h"
138 /* supported device vendors */
139 static const struct skc_type {
142 const char *skc_name;
144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940,
146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B,
149 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD,
152 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_A1,
153 "D-Link DGE-530T A1" },
154 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_B1,
155 "D-Link DGE-530T B1" },
157 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
158 "Linksys EG1032 v2" },
159 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064,
162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON,
163 "Marvell Yukon 88E8001/8003/8010" },
164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN,
167 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE,
168 "SysKonnect SK-NET" },
169 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2,
170 "SysKonnect SK9821 v2" },
175 static int skc_probe(device_t);
176 static int skc_attach(device_t);
177 static int skc_detach(device_t);
178 static void skc_shutdown(device_t);
179 static int skc_sysctl_imtime(SYSCTL_HANDLER_ARGS);
181 static int sk_probe(device_t);
182 static int sk_attach(device_t);
183 static int sk_detach(device_t);
184 static void sk_tick(void *);
185 static void sk_yukon_tick(void *);
186 static void sk_intr(void *);
187 static void sk_intr_bcom(struct sk_if_softc *);
188 static void sk_intr_xmac(struct sk_if_softc *);
189 static void sk_intr_yukon(struct sk_if_softc *);
190 static void sk_rxeof(struct sk_if_softc *);
191 static void sk_txeof(struct sk_if_softc *);
192 static int sk_encap(struct sk_if_softc *, struct mbuf **, uint32_t *);
193 static void sk_start(struct ifnet *, struct ifaltq_subque *);
194 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
195 static void sk_init(void *);
196 static void sk_init_xmac(struct sk_if_softc *);
197 static void sk_init_yukon(struct sk_if_softc *);
198 static void sk_stop(struct sk_if_softc *);
199 static void sk_watchdog(struct ifnet *);
200 static int sk_ifmedia_upd(struct ifnet *);
201 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
202 static void sk_reset(struct sk_softc *);
203 static int sk_newbuf_jumbo(struct sk_if_softc *, int, int);
204 static int sk_newbuf_std(struct sk_if_softc *, int, int);
205 static int sk_jpool_alloc(device_t);
206 static void sk_jpool_free(struct sk_if_softc *);
207 static struct sk_jpool_entry
208 *sk_jalloc(struct sk_if_softc *);
209 static void sk_jfree(void *);
210 static void sk_jref(void *);
211 static int sk_init_rx_ring(struct sk_if_softc *);
212 static int sk_init_tx_ring(struct sk_if_softc *);
214 static int sk_miibus_readreg(device_t, int, int);
215 static int sk_miibus_writereg(device_t, int, int, int);
216 static void sk_miibus_statchg(device_t);
218 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
219 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
220 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
222 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
223 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
224 static void sk_marv_miibus_statchg(struct sk_if_softc *);
226 static void sk_setfilt(struct sk_if_softc *, caddr_t, int);
227 static void sk_setmulti(struct sk_if_softc *);
228 static void sk_setpromisc(struct sk_if_softc *);
231 static void sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t,
234 static int sk_dma_alloc(device_t);
235 static void sk_dma_free(device_t);
238 #define DPRINTF(x) if (skdebug) kprintf x
239 #define DPRINTFN(n,x) if (skdebug >= (n)) kprintf x
240 static int skdebug = 2;
242 static void sk_dump_txdesc(struct sk_tx_desc *, int);
243 static void sk_dump_mbuf(struct mbuf *);
244 static void sk_dump_bytes(const char *, int);
247 #define DPRINTFN(n,x)
250 /* Interrupt moderation time. */
251 static int skc_imtime = SK_IMTIME_DEFAULT;
252 TUNABLE_INT("hw.skc.imtime", &skc_imtime);
255 * Note that we have newbus methods for both the GEnesis controller
256 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
257 * the miibus code is a child of the XMACs. We need to do it this way
258 * so that the miibus drivers can access the PHY registers on the
259 * right PHY. It's not quite what I had in mind, but it's the only
260 * design that achieves the desired effect.
262 static device_method_t skc_methods[] = {
263 /* Device interface */
264 DEVMETHOD(device_probe, skc_probe),
265 DEVMETHOD(device_attach, skc_attach),
266 DEVMETHOD(device_detach, skc_detach),
267 DEVMETHOD(device_shutdown, skc_shutdown),
270 DEVMETHOD(bus_print_child, bus_generic_print_child),
271 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
276 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
277 static devclass_t skc_devclass;
279 static device_method_t sk_methods[] = {
280 /* Device interface */
281 DEVMETHOD(device_probe, sk_probe),
282 DEVMETHOD(device_attach, sk_attach),
283 DEVMETHOD(device_detach, sk_detach),
284 DEVMETHOD(device_shutdown, bus_generic_shutdown),
287 DEVMETHOD(bus_print_child, bus_generic_print_child),
288 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
291 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
292 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
293 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
298 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
299 static devclass_t sk_devclass;
301 DECLARE_DUMMY_MODULE(if_sk);
302 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, NULL, NULL);
303 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, NULL, NULL);
304 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
306 static __inline uint32_t
307 sk_win_read_4(struct sk_softc *sc, uint32_t reg)
309 return CSR_READ_4(sc, reg);
312 static __inline uint16_t
313 sk_win_read_2(struct sk_softc *sc, uint32_t reg)
315 return CSR_READ_2(sc, reg);
318 static __inline uint8_t
319 sk_win_read_1(struct sk_softc *sc, uint32_t reg)
321 return CSR_READ_1(sc, reg);
325 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
327 CSR_WRITE_4(sc, reg, x);
331 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
333 CSR_WRITE_2(sc, reg, x);
337 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
339 CSR_WRITE_1(sc, reg, x);
343 sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait)
347 if (sc_if->sk_use_jumbo)
348 ret = sk_newbuf_jumbo(sc_if, idx, wait);
350 ret = sk_newbuf_std(sc_if, idx, wait);
355 sk_miibus_readreg(device_t dev, int phy, int reg)
357 struct sk_if_softc *sc_if = device_get_softc(dev);
359 if (SK_IS_GENESIS(sc_if->sk_softc))
360 return sk_xmac_miibus_readreg(sc_if, phy, reg);
362 return sk_marv_miibus_readreg(sc_if, phy, reg);
366 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
368 struct sk_if_softc *sc_if = device_get_softc(dev);
370 if (SK_IS_GENESIS(sc_if->sk_softc))
371 return sk_xmac_miibus_writereg(sc_if, phy, reg, val);
373 return sk_marv_miibus_writereg(sc_if, phy, reg, val);
377 sk_miibus_statchg(device_t dev)
379 struct sk_if_softc *sc_if = device_get_softc(dev);
381 if (SK_IS_GENESIS(sc_if->sk_softc))
382 sk_xmac_miibus_statchg(sc_if);
384 sk_marv_miibus_statchg(sc_if);
388 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
392 DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
394 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
397 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
398 SK_XM_READ_2(sc_if, XM_PHY_DATA);
399 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
400 for (i = 0; i < SK_TIMEOUT; i++) {
402 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
403 XM_MMUCMD_PHYDATARDY)
407 if (i == SK_TIMEOUT) {
408 if_printf(&sc_if->arpcom.ac_if,
409 "phy failed to come ready\n");
414 return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
418 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
422 DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
424 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
425 for (i = 0; i < SK_TIMEOUT; i++) {
426 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
430 if (i == SK_TIMEOUT) {
431 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
435 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
436 for (i = 0; i < SK_TIMEOUT; i++) {
438 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
443 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
448 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
450 struct mii_data *mii;
452 mii = device_get_softc(sc_if->sk_miibus);
453 DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
456 * If this is a GMII PHY, manually set the XMAC's
457 * duplex mode accordingly.
459 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
460 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
461 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
463 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
468 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
474 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
475 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
476 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
481 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
482 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
484 for (i = 0; i < SK_TIMEOUT; i++) {
486 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
487 if (val & YU_SMICR_READ_VALID)
491 if (i == SK_TIMEOUT) {
492 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
496 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
499 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
501 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
508 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
512 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
515 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
516 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
517 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
519 for (i = 0; i < SK_TIMEOUT; i++) {
521 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
526 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
532 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
534 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
535 SK_YU_READ_2(sc_if, YUKON_GPCR)));
541 sk_xmac_hash(caddr_t addr)
545 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
546 return (~crc & ((1 << HASH_BITS) - 1));
550 sk_yukon_hash(caddr_t addr)
554 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
555 return (crc & ((1 << HASH_BITS) - 1));
559 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
563 base = XM_RXFILT_ENTRY(slot);
565 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
566 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
567 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
571 sk_setmulti(struct sk_if_softc *sc_if)
573 struct sk_softc *sc = sc_if->sk_softc;
574 struct ifnet *ifp = &sc_if->arpcom.ac_if;
575 uint32_t hashes[2] = { 0, 0 };
577 struct ifmultiaddr *ifma;
578 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
580 /* First, zot all the existing filters. */
581 switch(sc->sk_type) {
583 for (i = 1; i < XM_RXFILT_MAX; i++)
584 sk_setfilt(sc_if, (caddr_t)&dummy, i);
586 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
587 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
592 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
593 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
594 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
595 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
599 /* Now program new ones. */
600 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
601 hashes[0] = 0xFFFFFFFF;
602 hashes[1] = 0xFFFFFFFF;
605 /* First find the tail of the list. */
606 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
610 if (ifma->ifma_addr->sa_family != AF_LINK)
613 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
616 * Program the first XM_RXFILT_MAX multicast groups
617 * into the perfect filter. For all others,
618 * use the hash table.
620 if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) {
621 sk_setfilt(sc_if, maddr, i);
626 switch(sc->sk_type) {
628 h = sk_xmac_hash(maddr);
634 h = sk_yukon_hash(maddr);
638 hashes[0] |= (1 << h);
640 hashes[1] |= (1 << (h - 32));
644 switch(sc->sk_type) {
646 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
647 XM_MODE_RX_USE_PERFECT);
648 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
649 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
654 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
655 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
656 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
657 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
663 sk_setpromisc(struct sk_if_softc *sc_if)
665 struct sk_softc *sc = sc_if->sk_softc;
666 struct ifnet *ifp = &sc_if->arpcom.ac_if;
668 switch(sc->sk_type) {
670 if (ifp->if_flags & IFF_PROMISC)
671 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
673 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
678 if (ifp->if_flags & IFF_PROMISC) {
679 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
680 YU_RCR_UFLEN | YU_RCR_MUFLEN);
682 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
683 YU_RCR_UFLEN | YU_RCR_MUFLEN);
690 sk_init_rx_ring(struct sk_if_softc *sc_if)
692 struct sk_chain_data *cd = &sc_if->sk_cdata;
693 struct sk_ring_data *rd = &sc_if->sk_rdata;
696 bzero(rd->sk_rx_ring, SK_RX_RING_SIZE);
698 for (i = 0; i < SK_RX_RING_CNT; i++) {
701 if (i == (SK_RX_RING_CNT - 1))
705 paddr = rd->sk_rx_ring_paddr +
706 (nexti * sizeof(struct sk_rx_desc));
708 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
709 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN);
710 rd->sk_rx_ring[i].sk_csum2_start =
711 htole16(ETHER_HDR_LEN + sizeof(struct ip));
713 error = sk_newbuf(sc_if, i, 1);
715 if_printf(&sc_if->arpcom.ac_if,
716 "failed alloc of %dth mbuf\n", i);
728 sk_init_tx_ring(struct sk_if_softc *sc_if)
730 struct sk_ring_data *rd = &sc_if->sk_rdata;
733 bzero(rd->sk_tx_ring, SK_TX_RING_SIZE);
735 for (i = 0; i < SK_TX_RING_CNT; i++) {
738 if (i == (SK_TX_RING_CNT - 1))
742 paddr = rd->sk_tx_ring_paddr +
743 (nexti * sizeof(struct sk_tx_desc));
745 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
748 sc_if->sk_cdata.sk_tx_prod = 0;
749 sc_if->sk_cdata.sk_tx_cons = 0;
750 sc_if->sk_cdata.sk_tx_cnt = 0;
756 sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait)
758 struct sk_jpool_entry *entry;
759 struct mbuf *m_new = NULL;
760 struct sk_rx_desc *r;
763 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
765 MGETHDR(m_new, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
769 /* Allocate the jumbo buffer */
770 entry = sk_jalloc(sc_if);
773 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
774 "dropped!\n", sc_if->arpcom.ac_if.if_xname));
778 m_new->m_ext.ext_arg = entry;
779 m_new->m_ext.ext_buf = entry->buf;
780 m_new->m_ext.ext_free = sk_jfree;
781 m_new->m_ext.ext_ref = sk_jref;
782 m_new->m_ext.ext_size = SK_JLEN;
784 m_new->m_flags |= M_EXT;
786 m_new->m_data = m_new->m_ext.ext_buf;
787 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
789 paddr = entry->paddr;
792 * Adjust alignment so packet payload begins on a
793 * longword boundary. Mandatory for Alpha, useful on
796 m_adj(m_new, ETHER_ALIGN);
797 paddr += ETHER_ALIGN;
799 sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new;
801 r = &sc_if->sk_rdata.sk_rx_ring[idx];
802 r->sk_data_lo = htole32(SK_ADDR_LO(paddr));
803 r->sk_data_hi = htole32(SK_ADDR_HI(paddr));
804 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
810 sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait)
812 struct mbuf *m_new = NULL;
813 struct sk_chain_data *cd = &sc_if->sk_cdata;
814 struct sk_rx_desc *r;
815 bus_dma_segment_t seg;
819 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
821 m_new = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
825 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
828 * Adjust alignment so packet payload begins on a
829 * longword boundary. Mandatory for Alpha, useful on
832 m_adj(m_new, ETHER_ALIGN);
834 error = bus_dmamap_load_mbuf_segment(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp,
835 m_new, &seg, 1, &nseg, BUS_DMA_NOWAIT);
839 if_printf(&sc_if->arpcom.ac_if,
840 "could not map RX mbuf\n");
845 /* Unload originally mapped mbuf */
846 if (cd->sk_rx_mbuf[idx] != NULL) {
847 bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[idx],
848 BUS_DMASYNC_POSTREAD);
849 bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]);
852 /* Switch DMA map with tmp DMA map */
853 map = cd->sk_rx_dmap_tmp;
854 cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx];
855 cd->sk_rx_dmap[idx] = map;
857 cd->sk_rx_mbuf[idx] = m_new;
859 r = &sc_if->sk_rdata.sk_rx_ring[idx];
860 r->sk_data_lo = htole32(SK_ADDR_LO(seg.ds_addr));
861 r->sk_data_hi = htole32(SK_ADDR_HI(seg.ds_addr));
862 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
868 * Allocate a jumbo buffer.
870 struct sk_jpool_entry *
871 sk_jalloc(struct sk_if_softc *sc_if)
873 struct sk_chain_data *cd = &sc_if->sk_cdata;
874 struct sk_jpool_entry *entry;
876 lwkt_serialize_enter(&cd->sk_jpool_serializer);
878 entry = SLIST_FIRST(&cd->sk_jpool_free_ent);
880 SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next);
883 DPRINTF(("no free jumbo buffer\n"));
886 lwkt_serialize_exit(&cd->sk_jpool_serializer);
891 * Release a jumbo buffer.
896 struct sk_jpool_entry *entry = arg;
897 struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
899 if (&cd->sk_jpool_ent[entry->slot] != entry)
900 panic("%s: free wrong jumbo buffer", __func__);
901 else if (entry->inuse == 0)
902 panic("%s: jumbo buffer already freed", __func__);
904 lwkt_serialize_enter(&cd->sk_jpool_serializer);
906 atomic_subtract_int(&entry->inuse, 1);
907 if (entry->inuse == 0)
908 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
910 lwkt_serialize_exit(&cd->sk_jpool_serializer);
916 struct sk_jpool_entry *entry = arg;
917 struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
919 if (&cd->sk_jpool_ent[entry->slot] != entry)
920 panic("%s: free wrong jumbo buffer", __func__);
921 else if (entry->inuse == 0)
922 panic("%s: jumbo buffer already freed", __func__);
924 atomic_add_int(&entry->inuse, 1);
931 sk_ifmedia_upd(struct ifnet *ifp)
933 struct sk_if_softc *sc_if = ifp->if_softc;
934 struct mii_data *mii;
936 mii = device_get_softc(sc_if->sk_miibus);
944 * Report current media status.
947 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
949 struct sk_if_softc *sc_if;
950 struct mii_data *mii;
952 sc_if = ifp->if_softc;
953 mii = device_get_softc(sc_if->sk_miibus);
956 ifmr->ifm_active = mii->mii_media_active;
957 ifmr->ifm_status = mii->mii_media_status;
961 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
963 struct sk_if_softc *sc_if = ifp->if_softc;
964 struct ifreq *ifr = (struct ifreq *)data;
965 struct mii_data *mii;
968 ASSERT_SERIALIZED(ifp->if_serializer);
972 if (ifr->ifr_mtu > SK_JUMBO_MTU)
975 ifp->if_mtu = ifr->ifr_mtu;
976 ifp->if_flags &= ~IFF_RUNNING;
981 if (ifp->if_flags & IFF_UP) {
982 if (ifp->if_flags & IFF_RUNNING) {
983 if ((ifp->if_flags ^ sc_if->sk_if_flags)
985 sk_setpromisc(sc_if);
991 if (ifp->if_flags & IFF_RUNNING)
994 sc_if->sk_if_flags = ifp->if_flags;
1002 mii = device_get_softc(sc_if->sk_miibus);
1003 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1006 error = ether_ioctl(ifp, command, data);
1014 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1015 * IDs against our list and return a device name if we find a match.
1018 skc_probe(device_t dev)
1020 const struct skc_type *t;
1023 vid = pci_get_vendor(dev);
1024 did = pci_get_device(dev);
1027 * Only attach to rev.2 of the Linksys EG1032 adapter.
1028 * Rev.3 is supported by re(4).
1030 if (vid == PCI_VENDOR_LINKSYS &&
1031 did == PCI_PRODUCT_LINKSYS_EG1032 &&
1032 pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2)
1035 for (t = skc_devs; t->skc_name != NULL; t++) {
1036 if (vid == t->skc_vid && did == t->skc_did) {
1037 device_set_desc(dev, t->skc_name);
1045 * Force the GEnesis into reset, then bring it out of reset.
1048 sk_reset(struct sk_softc *sc)
1050 DPRINTFN(2, ("sk_reset\n"));
1052 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1053 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1054 if (SK_IS_YUKON(sc))
1055 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1058 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1060 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1061 if (SK_IS_YUKON(sc))
1062 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1064 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
1065 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
1066 CSR_READ_2(sc, SK_LINK_CTRL)));
1068 if (SK_IS_GENESIS(sc)) {
1069 /* Configure packet arbiter */
1070 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1071 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1072 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1073 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1074 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1077 /* Enable RAM interface */
1078 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1081 * Configure interrupt moderation. The moderation timer
1082 * defers interrupts specified in the interrupt moderation
1083 * timer mask based on the timeout specified in the interrupt
1084 * moderation timer init register. Each bit in the timer
1085 * register represents one tick, so to specify a timeout in
1086 * microseconds, we have to multiply by the correct number of
1087 * ticks-per-microsecond.
1089 KKASSERT(sc->sk_imtimer_ticks != 0 && sc->sk_imtime != 0);
1090 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc, sc->sk_imtime));
1091 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1092 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1093 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1097 sk_probe(device_t dev)
1099 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1100 const char *revstr = "", *name = NULL;
1103 switch (sc->sk_type) {
1105 name = "SysKonnect GEnesis";
1108 name = "Marvell Yukon";
1111 name = "Marvell Yukon Lite";
1112 switch (sc->sk_rev) {
1113 case SK_YUKON_LITE_REV_A0:
1116 case SK_YUKON_LITE_REV_A1:
1119 case SK_YUKON_LITE_REV_A3:
1125 name = "Marvell Yukon LP";
1131 ksnprintf(devname, sizeof(devname), "%s%s (0x%x)",
1132 name, revstr, sc->sk_rev);
1133 device_set_desc_copy(dev, devname);
1138 * Each XMAC chip is attached as a separate logical IP interface.
1139 * Single port cards will have only one logical interface of course.
1142 sk_attach(device_t dev)
1144 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1145 struct sk_if_softc *sc_if = device_get_softc(dev);
1146 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1147 int i, error, if_attached = 0;
1149 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1151 sc_if->sk_port = *(int *)device_get_ivars(dev);
1152 KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B);
1154 sc_if->sk_softc = sc;
1155 sc->sk_if[sc_if->sk_port] = sc_if;
1157 kfree(device_get_ivars(dev), M_DEVBUF);
1158 device_set_ivars(dev, NULL);
1160 if (sc_if->sk_port == SK_PORT_A)
1161 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1162 if (sc_if->sk_port == SK_PORT_B)
1163 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1165 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1168 * Get station address for this interface. Note that
1169 * dual port cards actually come with three station
1170 * addresses: one for each port, plus an extra. The
1171 * extra one is used by the SysKonnect driver software
1172 * as a 'virtual' station address for when both ports
1173 * are operating in failover mode. Currently we don't
1174 * use this extra address.
1176 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1178 sc_if->arpcom.ac_enaddr[i] =
1179 sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i);
1183 * Set up RAM buffer addresses. The NIC will have a certain
1184 * amount of SRAM on it, somewhere between 512K and 2MB. We
1185 * need to divide this up a) between the transmitter and
1186 * receiver and b) between the two XMACs, if this is a
1187 * dual port NIC. Our algorithm is to divide up the memory
1188 * evenly so that everyone gets a fair share.
1190 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1191 uint32_t chunk, val;
1193 chunk = sc->sk_ramsize / 2;
1194 val = sc->sk_rboff / sizeof(uint64_t);
1195 sc_if->sk_rx_ramstart = val;
1196 val += (chunk / sizeof(uint64_t));
1197 sc_if->sk_rx_ramend = val - 1;
1198 sc_if->sk_tx_ramstart = val;
1199 val += (chunk / sizeof(uint64_t));
1200 sc_if->sk_tx_ramend = val - 1;
1202 uint32_t chunk, val;
1204 chunk = sc->sk_ramsize / 4;
1205 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1207 sc_if->sk_rx_ramstart = val;
1208 val += (chunk / sizeof(uint64_t));
1209 sc_if->sk_rx_ramend = val - 1;
1210 sc_if->sk_tx_ramstart = val;
1211 val += (chunk / sizeof(uint64_t));
1212 sc_if->sk_tx_ramend = val - 1;
1215 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1216 " tx_ramstart=%#x tx_ramend=%#x\n",
1217 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1218 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1220 /* Read and save PHY type */
1221 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1223 /* Set PHY address */
1224 if (SK_IS_GENESIS(sc)) {
1225 switch (sc_if->sk_phytype) {
1226 case SK_PHYTYPE_XMAC:
1227 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1229 case SK_PHYTYPE_BCOM:
1230 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1233 device_printf(dev, "unsupported PHY type: %d\n",
1240 if (SK_IS_YUKON(sc)) {
1241 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1242 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
1243 /* not initialized, punt */
1244 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1245 sc->sk_coppertype = 1;
1248 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1250 if (!(sc->sk_coppertype))
1251 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1254 error = sk_dma_alloc(dev);
1258 ifp->if_softc = sc_if;
1259 ifp->if_mtu = ETHERMTU;
1260 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1261 ifp->if_ioctl = sk_ioctl;
1262 ifp->if_start = sk_start;
1263 ifp->if_watchdog = sk_watchdog;
1264 ifp->if_init = sk_init;
1265 ifp->if_baudrate = 1000000000;
1266 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1267 ifq_set_ready(&ifp->if_snd);
1269 ifp->if_capabilities = IFCAP_VLAN_MTU;
1271 /* Don't use jumbo buffers by default */
1272 sc_if->sk_use_jumbo = 0;
1275 * Call MI attach routines.
1278 * This must be done before following sk_init_xxx(), in which
1279 * if_multiaddrs will be used.
1281 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer);
1287 switch (sc->sk_type) {
1289 sk_init_xmac(sc_if);
1294 sk_init_yukon(sc_if);
1297 device_printf(dev, "unknown device type %d\n", sc->sk_type);
1302 DPRINTFN(2, ("sk_attach: 1\n"));
1304 error = mii_phy_probe(dev, &sc_if->sk_miibus,
1305 sk_ifmedia_upd, sk_ifmedia_sts);
1307 device_printf(dev, "no PHY found!\n");
1311 callout_init(&sc_if->sk_tick_timer);
1313 DPRINTFN(2, ("sk_attach: end\n"));
1317 ether_ifdetach(ifp);
1319 sc->sk_if[sc_if->sk_port] = NULL;
1324 * Attach the interface. Allocate softc structures, do ifmedia
1325 * setup and ethernet/BPF attach.
1328 skc_attach(device_t dev)
1330 struct sk_softc *sc = device_get_softc(dev);
1335 DPRINTFN(2, ("begin skc_attach\n"));
1338 lwkt_serialize_init(&sc->sk_serializer);
1340 #ifndef BURN_BRIDGES
1342 * Handle power management nonsense.
1344 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1345 uint32_t iobase, membase, irq;
1347 /* Save important PCI config data. */
1348 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1349 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1350 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1352 /* Reset the power state. */
1353 device_printf(dev, "chip is in D%d power mode "
1354 "-- setting to D0\n", pci_get_powerstate(dev));
1356 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1358 /* Restore PCI config data. */
1359 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1360 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1361 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1363 #endif /* BURN_BRIDGES */
1366 * Map control/status registers.
1368 pci_enable_busmaster(dev);
1370 sc->sk_res_rid = SK_PCI_LOMEM;
1371 sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1372 &sc->sk_res_rid, RF_ACTIVE);
1373 if (sc->sk_res == NULL) {
1374 device_printf(dev, "couldn't map memory\n");
1378 sc->sk_btag = rman_get_bustag(sc->sk_res);
1379 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1381 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1382 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1384 /* Bail out here if chip is not recognized */
1385 if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) {
1386 device_printf(dev, "unknown chip type: %d\n", sc->sk_type);
1391 DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
1393 /* Allocate interrupt */
1395 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid,
1396 RF_SHAREABLE | RF_ACTIVE);
1397 if (sc->sk_irq == NULL) {
1398 device_printf(dev, "couldn't map interrupt\n");
1403 switch (sc->sk_type) {
1405 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
1408 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1411 sc->sk_imtime = skc_imtime;
1413 /* Reset the adapter. */
1416 skrs = sk_win_read_1(sc, SK_EPROM0);
1417 if (SK_IS_GENESIS(sc)) {
1418 /* Read and save RAM size and RAMbuffer offset */
1420 case SK_RAMSIZE_512K_64:
1421 sc->sk_ramsize = 0x80000;
1422 sc->sk_rboff = SK_RBOFF_0;
1424 case SK_RAMSIZE_1024K_64:
1425 sc->sk_ramsize = 0x100000;
1426 sc->sk_rboff = SK_RBOFF_80000;
1428 case SK_RAMSIZE_1024K_128:
1429 sc->sk_ramsize = 0x100000;
1430 sc->sk_rboff = SK_RBOFF_0;
1432 case SK_RAMSIZE_2048K_128:
1433 sc->sk_ramsize = 0x200000;
1434 sc->sk_rboff = SK_RBOFF_0;
1437 device_printf(dev, "unknown ram size: %d\n", skrs);
1443 sc->sk_ramsize = 0x20000;
1445 sc->sk_ramsize = skrs * (1<<12);
1446 sc->sk_rboff = SK_RBOFF_0;
1449 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
1450 sc->sk_ramsize, sc->sk_ramsize / 1024,
1453 /* Read and save physical media type */
1454 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1456 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1457 sc->sk_coppertype = 1;
1459 sc->sk_coppertype = 0;
1461 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1462 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1466 flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1468 /* Test Flash-Address Register */
1469 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1470 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1472 if (testbyte != 0) {
1473 /* This is a Yukon Lite Rev A0 */
1474 sc->sk_type = SK_YUKON_LITE;
1475 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1476 /* Restore Flash-Address Register */
1477 sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1482 * Create sysctl nodes.
1484 sysctl_ctx_init(&sc->sk_sysctl_ctx);
1485 sc->sk_sysctl_tree = SYSCTL_ADD_NODE(&sc->sk_sysctl_ctx,
1486 SYSCTL_STATIC_CHILDREN(_hw),
1488 device_get_nameunit(dev),
1490 if (sc->sk_sysctl_tree == NULL) {
1491 device_printf(dev, "can't add sysctl node\n");
1495 SYSCTL_ADD_PROC(&sc->sk_sysctl_ctx,
1496 SYSCTL_CHILDREN(sc->sk_sysctl_tree),
1497 OID_AUTO, "imtime", CTLTYPE_INT | CTLFLAG_RW,
1498 sc, 0, skc_sysctl_imtime, "I",
1499 "Interrupt moderation time (usec).");
1501 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1502 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1504 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1506 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1507 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1508 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1510 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1513 /* Turn on the 'driver is loaded' LED. */
1514 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1516 bus_generic_attach(dev);
1518 error = bus_setup_intr(dev, sc->sk_irq, INTR_MPSAFE, sk_intr, sc,
1519 &sc->sk_intrhand, &sc->sk_serializer);
1521 device_printf(dev, "couldn't set up irq\n");
1525 cpuid = rman_get_cpuid(sc->sk_irq);
1526 if (sc->sk_if[0] != NULL)
1527 ifq_set_cpuid(&sc->sk_if[0]->arpcom.ac_if.if_snd, cpuid);
1528 if (sc->sk_if[1] != NULL)
1529 ifq_set_cpuid(&sc->sk_if[1]->arpcom.ac_if.if_snd, cpuid);
1538 sk_detach(device_t dev)
1540 struct sk_if_softc *sc_if = device_get_softc(dev);
1542 if (device_is_attached(dev)) {
1543 struct sk_softc *sc = sc_if->sk_softc;
1544 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1546 lwkt_serialize_enter(ifp->if_serializer);
1548 if (sc->sk_intrhand != NULL) {
1549 if (sc->sk_if[SK_PORT_A] != NULL)
1550 sk_stop(sc->sk_if[SK_PORT_A]);
1551 if (sc->sk_if[SK_PORT_B] != NULL)
1552 sk_stop(sc->sk_if[SK_PORT_B]);
1554 bus_teardown_intr(sc->sk_dev, sc->sk_irq,
1556 sc->sk_intrhand = NULL;
1559 lwkt_serialize_exit(ifp->if_serializer);
1561 ether_ifdetach(ifp);
1564 if (sc_if->sk_miibus != NULL)
1565 device_delete_child(dev, sc_if->sk_miibus);
1572 skc_detach(device_t dev)
1574 struct sk_softc *sc = device_get_softc(dev);
1578 if (device_is_attached(dev)) {
1579 KASSERT(sc->sk_intrhand == NULL,
1580 ("intr has not been torn down yet"));
1584 if (sc->sk_devs[SK_PORT_A] != NULL) {
1585 port = device_get_ivars(sc->sk_devs[SK_PORT_A]);
1587 kfree(port, M_DEVBUF);
1588 device_set_ivars(sc->sk_devs[SK_PORT_A], NULL);
1590 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1592 if (sc->sk_devs[SK_PORT_B] != NULL) {
1593 port = device_get_ivars(sc->sk_devs[SK_PORT_B]);
1595 kfree(port, M_DEVBUF);
1596 device_set_ivars(sc->sk_devs[SK_PORT_B], NULL);
1598 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1601 if (sc->sk_irq != NULL) {
1602 bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid,
1605 if (sc->sk_res != NULL) {
1606 bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid,
1610 if (sc->sk_sysctl_tree != NULL)
1611 sysctl_ctx_free(&sc->sk_sysctl_ctx);
1617 sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head0, uint32_t *txidx)
1619 struct sk_chain_data *cd = &sc_if->sk_cdata;
1620 struct sk_ring_data *rd = &sc_if->sk_rdata;
1621 struct sk_tx_desc *f = NULL;
1622 uint32_t frag, cur, sk_ctl;
1623 bus_dma_segment_t segs[SK_NTXSEG];
1625 int i, error, maxsegs, nsegs;
1627 DPRINTFN(2, ("sk_encap\n"));
1629 maxsegs = SK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - SK_NDESC_RESERVE;
1630 KASSERT(maxsegs >= SK_NDESC_SPARE, ("not enough spare TX desc"));
1631 if (maxsegs > SK_NTXSEG)
1632 maxsegs = SK_NTXSEG;
1634 cur = frag = *txidx;
1638 sk_dump_mbuf(*m_head0);
1641 map = cd->sk_tx_dmap[*txidx];
1643 error = bus_dmamap_load_mbuf_defrag(cd->sk_tx_dtag, map, m_head0,
1644 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1651 DPRINTFN(2, ("sk_encap: nsegs=%d\n", nsegs));
1653 /* Sync the DMA map. */
1654 bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE);
1656 for (i = 0; i < nsegs; i++) {
1657 f = &rd->sk_tx_ring[frag];
1658 f->sk_data_lo = htole32(SK_ADDR_LO(segs[i].ds_addr));
1659 f->sk_data_hi = htole32(SK_ADDR_HI(segs[i].ds_addr));
1660 sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT;
1662 sk_ctl |= SK_TXCTL_FIRSTFRAG;
1664 sk_ctl |= SK_TXCTL_OWN;
1665 f->sk_ctl = htole32(sk_ctl);
1667 SK_INC(frag, SK_TX_RING_CNT);
1670 cd->sk_tx_mbuf[cur] = *m_head0;
1671 /* Switch DMA map */
1672 cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur];
1673 cd->sk_tx_dmap[cur] = map;
1675 rd->sk_tx_ring[cur].sk_ctl |=
1676 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
1677 rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN);
1679 sc_if->sk_cdata.sk_tx_cnt += nsegs;
1683 struct sk_tx_desc *desc;
1686 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1687 desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1688 sk_dump_txdesc(desc, idx);
1695 DPRINTFN(2, ("sk_encap: completed successfully\n"));
1701 sk_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1703 struct sk_if_softc *sc_if = ifp->if_softc;
1704 struct sk_softc *sc = sc_if->sk_softc;
1705 uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
1708 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1709 DPRINTFN(2, ("sk_start\n"));
1711 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1714 while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) {
1715 struct mbuf *m_head;
1717 if (SK_IS_OACTIVE(sc_if)) {
1718 ifq_set_oactive(&ifp->if_snd);
1722 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1727 * Pack the data into the transmit ring. If we
1728 * don't have room, set the OACTIVE flag and wait
1729 * for the NIC to drain the ring.
1731 if (sk_encap(sc_if, &m_head, &idx)) {
1732 if (sc_if->sk_cdata.sk_tx_cnt == 0) {
1735 ifq_set_oactive(&ifp->if_snd);
1741 BPF_MTAP(ifp, m_head);
1747 if (idx != sc_if->sk_cdata.sk_tx_prod) {
1748 sc_if->sk_cdata.sk_tx_prod = idx;
1749 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1751 /* Set a timeout in case the chip goes out to lunch. */
1757 sk_watchdog(struct ifnet *ifp)
1759 struct sk_if_softc *sc_if = ifp->if_softc;
1761 ASSERT_SERIALIZED(ifp->if_serializer);
1763 * Reclaim first as there is a possibility of losing Tx completion
1767 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1768 if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n");
1769 IFNET_STAT_INC(ifp, oerrors, 1);
1770 ifp->if_flags &= ~IFF_RUNNING;
1776 skc_shutdown(device_t dev)
1778 struct sk_softc *sc = device_get_softc(dev);
1780 DPRINTFN(2, ("sk_shutdown\n"));
1782 lwkt_serialize_enter(&sc->sk_serializer);
1784 /* Turn off the 'driver is loaded' LED. */
1785 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1788 * Reset the GEnesis controller. Doing this should also
1789 * assert the resets on the attached XMAC(s).
1793 lwkt_serialize_exit(&sc->sk_serializer);
1797 sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len)
1799 if (sc->sk_type == SK_GENESIS) {
1800 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
1801 XM_RXSTAT_BYTES(stat) != len)
1804 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1805 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1806 YU_RXSTAT_JABBER)) != 0 ||
1807 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1808 YU_RXSTAT_BYTES(stat) != len)
1816 sk_rxeof(struct sk_if_softc *sc_if)
1818 struct sk_softc *sc = sc_if->sk_softc;
1819 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1820 struct sk_chain_data *cd = &sc_if->sk_cdata;
1821 struct sk_ring_data *rd = &sc_if->sk_rdata;
1824 DPRINTFN(2, ("sk_rxeof\n"));
1828 if (sc_if->sk_use_jumbo)
1829 max_frmlen = SK_JUMBO_FRAMELEN;
1831 max_frmlen = ETHER_MAX_LEN;
1834 struct sk_rx_desc *cur_desc;
1835 uint32_t rxstat, sk_ctl;
1837 uint16_t csum1, csum2;
1843 cur_desc = &rd->sk_rx_ring[cur];
1845 sk_ctl = le32toh(cur_desc->sk_ctl);
1846 if (sk_ctl & SK_RXCTL_OWN) {
1847 /* Invalidate the descriptor -- it's not ready yet */
1848 cd->sk_rx_prod = cur;
1852 rxstat = le32toh(cur_desc->sk_xmac_rxstat);
1853 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl));
1856 csum1 = le16toh(cur_desc->sk_csum1);
1857 csum2 = le16toh(cur_desc->sk_csum2);
1860 m = cd->sk_rx_mbuf[cur];
1863 * Bump 'i' here, so we can keep going, even if the current
1864 * RX descriptor reaping fails later. 'i' shoult NOT be used
1865 * in the following processing any more.
1867 SK_INC(i, SK_RX_RING_CNT);
1869 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
1870 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
1871 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
1872 total_len < SK_MIN_FRAMELEN || total_len > max_frmlen ||
1873 sk_rxvalid(sc, rxstat, total_len) == 0) {
1874 IFNET_STAT_INC(ifp, ierrors, 1);
1875 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1880 * Try to allocate a new RX buffer. If that fails,
1881 * copy the packet to mbufs and put the RX buffer
1882 * back in the ring so it can be re-used. If
1883 * allocating mbufs fails, then we have to drop
1886 if (sk_newbuf(sc_if, cur, 0)) {
1887 IFNET_STAT_INC(ifp, ierrors, 1);
1888 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1891 m->m_pkthdr.rcvif = ifp;
1892 m->m_pkthdr.len = m->m_len = total_len;
1896 sk_rxcsum(ifp, m, csum1, csum2);
1899 IFNET_STAT_INC(ifp, ipackets, 1);
1900 ifp->if_input(ifp, m);
1906 sk_rxcsum(struct ifnet *ifp, struct mbuf *m,
1907 const uint16_t csum1, const uint16_t csum2)
1909 struct ether_header *eh;
1912 int hlen, len, plen;
1913 uint16_t iph_csum, ipo_csum, ipd_csum, csum;
1915 pp = mtod(m, uint8_t *);
1916 plen = m->m_pkthdr.len;
1917 if (plen < sizeof(*eh))
1919 eh = (struct ether_header *)pp;
1920 iph_csum = in_addword(csum1, (~csum2 & 0xffff));
1922 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1923 uint16_t *xp = (uint16_t *)pp;
1925 xp = (uint16_t *)pp;
1926 if (xp[1] != htons(ETHERTYPE_IP))
1928 iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff));
1929 iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff));
1930 xp = (uint16_t *)(pp + sizeof(struct ip));
1931 iph_csum = in_addword(iph_csum, xp[0]);
1932 iph_csum = in_addword(iph_csum, xp[1]);
1934 } else if (eh->ether_type != htons(ETHERTYPE_IP)) {
1939 plen -= sizeof(*eh);
1941 ip = (struct ip *)pp;
1943 if (ip->ip_v != IPVERSION)
1946 hlen = ip->ip_hl << 2;
1947 if (hlen < sizeof(struct ip))
1949 if (hlen > ntohs(ip->ip_len))
1952 /* Don't deal with truncated or padded packets. */
1953 if (plen != ntohs(ip->ip_len))
1956 len = hlen - sizeof(struct ip);
1960 p = (uint16_t *)(ip + 1);
1962 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++)
1963 ipo_csum = in_addword(ipo_csum, *p);
1964 iph_csum = in_addword(iph_csum, ipo_csum);
1965 ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff));
1970 if (iph_csum != 0xffff)
1972 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID;
1974 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1975 return; /* ip frag, we're done for now */
1979 /* Only know checksum protocol for udp/tcp */
1980 if (ip->ip_p == IPPROTO_UDP) {
1981 struct udphdr *uh = (struct udphdr *)pp;
1983 if (uh->uh_sum == 0) /* udp with no checksum */
1985 } else if (ip->ip_p != IPPROTO_TCP) {
1989 csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1990 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum);
1991 if (csum == 0xffff) {
1992 m->m_pkthdr.csum_data = csum;
1993 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1999 sk_txeof(struct sk_if_softc *sc_if)
2001 struct sk_chain_data *cd = &sc_if->sk_cdata;
2002 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2005 DPRINTFN(2, ("sk_txeof\n"));
2008 * Go through our tx ring and free mbufs for those
2009 * frames that have been sent.
2011 idx = cd->sk_tx_cons;
2012 while (idx != cd->sk_tx_prod) {
2013 struct sk_tx_desc *cur_tx;
2016 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2017 sk_ctl = le32toh(cur_tx->sk_ctl);
2020 sk_dump_txdesc(cur_tx, idx);
2022 if (sk_ctl & SK_TXCTL_OWN)
2024 if (sk_ctl & SK_TXCTL_LASTFRAG)
2025 IFNET_STAT_INC(ifp, opackets, 1);
2026 if (cd->sk_tx_mbuf[idx] != NULL) {
2027 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]);
2028 m_freem(cd->sk_tx_mbuf[idx]);
2029 cd->sk_tx_mbuf[idx] = NULL;
2031 sc_if->sk_cdata.sk_tx_cnt--;
2032 SK_INC(idx, SK_TX_RING_CNT);
2035 if (!SK_IS_OACTIVE(sc_if))
2036 ifq_clr_oactive(&ifp->if_snd);
2038 if (sc_if->sk_cdata.sk_tx_cnt == 0)
2041 sc_if->sk_cdata.sk_tx_cons = idx;
2045 sk_tick(void *xsc_if)
2047 struct sk_if_softc *sc_if = xsc_if;
2048 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2049 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2052 DPRINTFN(2, ("sk_tick\n"));
2054 lwkt_serialize_enter(ifp->if_serializer);
2056 if ((ifp->if_flags & IFF_UP) == 0) {
2057 lwkt_serialize_exit(ifp->if_serializer);
2061 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2062 sk_intr_bcom(sc_if);
2063 lwkt_serialize_exit(ifp->if_serializer);
2068 * According to SysKonnect, the correct way to verify that
2069 * the link has come back up is to poll bit 0 of the GPIO
2070 * register three times. This pin has the signal from the
2071 * link sync pin connected to it; if we read the same link
2072 * state 3 times in a row, we know the link is up.
2074 for (i = 0; i < 3; i++) {
2075 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2080 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
2081 lwkt_serialize_exit(ifp->if_serializer);
2085 /* Turn the GP0 interrupt back on. */
2086 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2087 SK_XM_READ_2(sc_if, XM_ISR);
2089 callout_stop(&sc_if->sk_tick_timer);
2090 lwkt_serialize_exit(ifp->if_serializer);
2094 sk_yukon_tick(void *xsc_if)
2096 struct sk_if_softc *sc_if = xsc_if;
2097 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2098 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2100 lwkt_serialize_enter(ifp->if_serializer);
2102 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2103 lwkt_serialize_exit(ifp->if_serializer);
2107 sk_intr_bcom(struct sk_if_softc *sc_if)
2109 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2110 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2113 DPRINTFN(2, ("sk_intr_bcom\n"));
2115 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2118 * Read the PHY interrupt register to make sure
2119 * we clear any pending interrupts.
2121 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2123 if ((ifp->if_flags & IFF_RUNNING) == 0) {
2124 sk_init_xmac(sc_if);
2128 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2131 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2134 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2136 /* Turn off the link LED. */
2137 SK_IF_WRITE_1(sc_if, 0,
2138 SK_LINKLED1_CTL, SK_LINKLED_OFF);
2140 } else if (status & BRGPHY_ISR_LNK_CHG) {
2141 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2142 BRGPHY_MII_IMR, 0xFF00);
2145 /* Turn on the link LED. */
2146 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2147 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2148 SK_LINKLED_BLINK_OFF);
2151 callout_reset(&sc_if->sk_tick_timer, hz,
2156 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2160 sk_intr_xmac(struct sk_if_softc *sc_if)
2164 status = SK_XM_READ_2(sc_if, XM_ISR);
2165 DPRINTFN(2, ("sk_intr_xmac\n"));
2167 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC &&
2168 (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) {
2169 if (status & XM_ISR_GP0_SET)
2170 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2172 callout_reset(&sc_if->sk_tick_timer, hz,
2176 if (status & XM_IMR_TX_UNDERRUN)
2177 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2179 if (status & XM_IMR_RX_OVERRUN)
2180 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2184 sk_intr_yukon(struct sk_if_softc *sc_if)
2188 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2190 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2191 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2192 SK_RFCTL_RX_FIFO_OVER);
2195 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2196 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2197 SK_TFCTL_TX_FIFO_UNDER);
2200 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
2206 struct sk_softc *sc = xsc;
2207 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2208 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
2209 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2212 ASSERT_SERIALIZED(&sc->sk_serializer);
2214 status = CSR_READ_4(sc, SK_ISSR);
2215 if (status == 0 || status == 0xffffffff)
2219 ifp0 = &sc_if0->arpcom.ac_if;
2221 ifp1 = &sc_if1->arpcom.ac_if;
2223 for (; (status &= sc->sk_intrmask) != 0;) {
2224 /* Handle receive interrupts first. */
2225 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
2227 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2228 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2230 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
2232 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2233 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2236 /* Then transmit interrupts. */
2237 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
2239 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2240 SK_TXBMU_CLR_IRQ_EOF);
2242 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
2244 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2245 SK_TXBMU_CLR_IRQ_EOF);
2248 /* Then MAC interrupts. */
2249 if (sc_if0 && (status & SK_ISR_MAC1) &&
2250 (ifp0->if_flags & IFF_RUNNING)) {
2251 if (SK_IS_GENESIS(sc))
2252 sk_intr_xmac(sc_if0);
2254 sk_intr_yukon(sc_if0);
2257 if (sc_if1 && (status & SK_ISR_MAC2) &&
2258 (ifp1->if_flags & IFF_RUNNING)) {
2259 if (SK_IS_GENESIS(sc))
2260 sk_intr_xmac(sc_if1);
2262 sk_intr_yukon(sc_if1);
2265 if (status & SK_ISR_EXTERNAL_REG) {
2266 if (sc_if0 != NULL &&
2267 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2268 sk_intr_bcom(sc_if0);
2270 if (sc_if1 != NULL &&
2271 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2272 sk_intr_bcom(sc_if1);
2274 status = CSR_READ_4(sc, SK_ISSR);
2277 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2279 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2281 if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd))
2286 sk_init_xmac(struct sk_if_softc *sc_if)
2288 struct sk_softc *sc = sc_if->sk_softc;
2289 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2290 static const struct sk_bcom_hack bhack[] = {
2291 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2292 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2293 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2296 DPRINTFN(2, ("sk_init_xmac\n"));
2298 /* Unreset the XMAC. */
2299 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2302 /* Reset the XMAC's internal state. */
2303 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2305 /* Save the XMAC II revision */
2306 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2309 * Perform additional initialization for external PHYs,
2310 * namely for the 1000baseT cards that use the XMAC's
2313 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2317 /* Take PHY out of reset. */
2318 val = sk_win_read_4(sc, SK_GPIO);
2319 if (sc_if->sk_port == SK_PORT_A)
2320 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2322 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2323 sk_win_write_4(sc, SK_GPIO, val);
2325 /* Enable GMII mode on the XMAC. */
2326 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2328 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2329 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2331 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2332 BRGPHY_MII_IMR, 0xFFF0);
2335 * Early versions of the BCM5400 apparently have
2336 * a bug that requires them to have their reserved
2337 * registers initialized to some magic values. I don't
2338 * know what the numbers do, I'm just the messenger.
2340 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2342 while(bhack[i].reg) {
2343 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2344 bhack[i].reg, bhack[i].val);
2350 /* Set station address */
2351 SK_XM_WRITE_2(sc_if, XM_PAR0,
2352 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2353 SK_XM_WRITE_2(sc_if, XM_PAR1,
2354 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2355 SK_XM_WRITE_2(sc_if, XM_PAR2,
2356 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2357 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2359 if (ifp->if_flags & IFF_BROADCAST)
2360 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2362 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2364 /* We don't need the FCS appended to the packet. */
2365 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2367 /* We want short frames padded to 60 bytes. */
2368 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2371 * Enable the reception of all error frames. This is
2372 * a necessary evil due to the design of the XMAC. The
2373 * XMAC's receive FIFO is only 8K in size, however jumbo
2374 * frames can be up to 9000 bytes in length. When bad
2375 * frame filtering is enabled, the XMAC's RX FIFO operates
2376 * in 'store and forward' mode. For this to work, the
2377 * entire frame has to fit into the FIFO, but that means
2378 * that jumbo frames larger than 8192 bytes will be
2379 * truncated. Disabling all bad frame filtering causes
2380 * the RX FIFO to operate in streaming mode, in which
2381 * case the XMAC will start transfering frames out of the
2382 * RX FIFO as soon as the FIFO threshold is reached.
2384 if (sc_if->sk_use_jumbo) {
2385 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2386 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2387 XM_MODE_RX_INRANGELEN);
2390 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2393 * Bump up the transmit threshold. This helps hold off transmit
2394 * underruns when we're blasting traffic from both ports at once.
2396 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2398 /* Set promiscuous mode */
2399 sk_setpromisc(sc_if);
2401 /* Set multicast filter */
2404 /* Clear and enable interrupts */
2405 SK_XM_READ_2(sc_if, XM_ISR);
2406 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2407 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2409 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2411 /* Configure MAC arbiter */
2412 switch(sc_if->sk_xmac_rev) {
2413 case XM_XMAC_REV_B2:
2414 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2415 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2416 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2417 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2418 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2419 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2420 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2421 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2422 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2424 case XM_XMAC_REV_C1:
2425 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2426 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2427 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2428 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2429 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2430 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2431 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2432 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2433 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2438 sk_win_write_2(sc, SK_MACARB_CTL,
2439 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2445 sk_init_yukon(struct sk_if_softc *sc_if)
2449 struct sk_softc *sc;
2452 sc = sc_if->sk_softc;
2454 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
2455 CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2457 if (sc->sk_type == SK_YUKON_LITE &&
2458 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2460 * Workaround code for COMA mode, set PHY reset.
2461 * Otherwise it will not correctly take chip out of
2464 v = sk_win_read_4(sc, SK_GPIO);
2465 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
2466 sk_win_write_4(sc, SK_GPIO, v);
2469 DPRINTFN(6, ("sk_init_yukon: 1\n"));
2471 /* GMAC and GPHY Reset */
2472 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2473 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2476 DPRINTFN(6, ("sk_init_yukon: 2\n"));
2478 if (sc->sk_type == SK_YUKON_LITE &&
2479 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2481 * Workaround code for COMA mode, clear PHY reset
2483 v = sk_win_read_4(sc, SK_GPIO);
2486 sk_win_write_4(sc, SK_GPIO, v);
2489 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2490 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2492 if (sc->sk_coppertype)
2493 phy |= SK_GPHY_COPPER;
2495 phy |= SK_GPHY_FIBER;
2497 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
2499 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2501 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2502 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2503 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2505 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2506 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2508 DPRINTFN(6, ("sk_init_yukon: 3\n"));
2510 /* unused read of the interrupt source register */
2511 DPRINTFN(6, ("sk_init_yukon: 4\n"));
2512 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2514 DPRINTFN(6, ("sk_init_yukon: 4a\n"));
2515 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2516 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2518 /* MIB Counter Clear Mode set */
2519 reg |= YU_PAR_MIB_CLR;
2520 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2521 DPRINTFN(6, ("sk_init_yukon: 4b\n"));
2522 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2524 /* MIB Counter Clear Mode clear */
2525 DPRINTFN(6, ("sk_init_yukon: 5\n"));
2526 reg &= ~YU_PAR_MIB_CLR;
2527 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2529 /* receive control reg */
2530 DPRINTFN(6, ("sk_init_yukon: 7\n"));
2531 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2533 /* transmit parameter register */
2534 DPRINTFN(6, ("sk_init_yukon: 8\n"));
2535 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2536 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2538 /* serial mode register */
2539 DPRINTFN(6, ("sk_init_yukon: 9\n"));
2540 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2541 if (sc_if->sk_use_jumbo)
2542 reg |= YU_SMR_MFL_JUMBO;
2543 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2545 DPRINTFN(6, ("sk_init_yukon: 10\n"));
2546 /* Setup Yukon's address */
2547 for (i = 0; i < 3; i++) {
2548 /* Write Source Address 1 (unicast filter) */
2549 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2550 sc_if->arpcom.ac_enaddr[i * 2] |
2551 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2554 for (i = 0; i < 3; i++) {
2555 reg = sk_win_read_2(sc_if->sk_softc,
2556 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2557 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2560 /* Set promiscuous mode */
2561 sk_setpromisc(sc_if);
2563 /* Set multicast filter */
2564 DPRINTFN(6, ("sk_init_yukon: 11\n"));
2567 /* enable interrupt mask for counter overflows */
2568 DPRINTFN(6, ("sk_init_yukon: 12\n"));
2569 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2570 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2571 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2573 /* Configure RX MAC FIFO Flush Mask */
2574 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2575 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2577 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2579 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
2580 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
2581 v = SK_TFCTL_OPERATION_ON;
2583 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
2584 /* Configure RX MAC FIFO */
2585 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2586 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2588 /* Increase flush threshould to 64 bytes */
2589 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2590 SK_RFCTL_FIFO_THRESHOLD + 1);
2592 /* Configure TX MAC FIFO */
2593 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2594 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2596 DPRINTFN(6, ("sk_init_yukon: end\n"));
2600 * Note that to properly initialize any part of the GEnesis chip,
2601 * you first have to take it out of reset mode.
2604 sk_init(void *xsc_if)
2606 struct sk_if_softc *sc_if = xsc_if;
2607 struct sk_softc *sc = sc_if->sk_softc;
2608 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2609 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2611 DPRINTFN(2, ("sk_init\n"));
2613 ASSERT_SERIALIZED(ifp->if_serializer);
2615 if (ifp->if_flags & IFF_RUNNING)
2618 /* Cancel pending I/O and free all RX/TX buffers. */
2622 * NOTE: Change sk_use_jumbo after sk_stop(),
2623 * but before real initialization.
2625 if (ifp->if_mtu > ETHER_MAX_LEN)
2626 sc_if->sk_use_jumbo = 1;
2628 sc_if->sk_use_jumbo = 0;
2629 DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO"));
2631 if (SK_IS_GENESIS(sc)) {
2632 /* Configure LINK_SYNC LED */
2633 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2634 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2635 SK_LINKLED_LINKSYNC_ON);
2637 /* Configure RX LED */
2638 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2639 SK_RXLEDCTL_COUNTER_START);
2641 /* Configure TX LED */
2642 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2643 SK_TXLEDCTL_COUNTER_START);
2647 * Configure descriptor poll timer
2649 * SK-NET GENESIS data sheet says that possibility of losing Start
2650 * transmit command due to CPU/cache related interim storage problems
2651 * under certain conditions. The document recommends a polling
2652 * mechanism to send a Start transmit command to initiate transfer
2653 * of ready descriptors regulary. To cope with this issue sk(4) now
2654 * enables descriptor poll timer to initiate descriptor processing
2655 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
2656 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
2657 * command instead of waiting for next descriptor polling time.
2658 * The same rule may apply to Rx side too but it seems that is not
2659 * needed at the moment.
2660 * Since sk(4) uses descriptor polling as a last resort there is no
2661 * need to set smaller polling time than maximum allowable one.
2663 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
2665 /* Configure I2C registers */
2667 /* Configure XMAC(s) */
2668 switch (sc->sk_type) {
2670 sk_init_xmac(sc_if);
2675 sk_init_yukon(sc_if);
2680 if (SK_IS_GENESIS(sc)) {
2681 /* Configure MAC FIFOs */
2682 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2683 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2684 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2686 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2687 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2688 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2691 /* Configure transmit arbiter(s) */
2692 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2693 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2695 /* Configure RAMbuffers */
2696 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2697 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2698 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2699 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2700 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2701 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2703 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2704 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2705 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2706 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2707 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2708 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2709 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2711 /* Configure BMUs */
2712 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2713 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2714 SK_ADDR_LO(sc_if->sk_rdata.sk_rx_ring_paddr));
2715 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
2716 SK_ADDR_HI(sc_if->sk_rdata.sk_rx_ring_paddr));
2718 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2719 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2720 SK_ADDR_LO(sc_if->sk_rdata.sk_tx_ring_paddr));
2721 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
2722 SK_ADDR_HI(sc_if->sk_rdata.sk_tx_ring_paddr));
2724 /* Init descriptors */
2725 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2726 if_printf(ifp, "initialization failed: "
2727 "no memory for rx buffers\n");
2732 if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2733 if_printf(ifp, "initialization failed: "
2734 "no memory for tx buffers\n");
2739 /* Configure interrupt handling */
2740 CSR_READ_4(sc, SK_ISSR);
2741 if (sc_if->sk_port == SK_PORT_A)
2742 sc->sk_intrmask |= SK_INTRS1;
2744 sc->sk_intrmask |= SK_INTRS2;
2746 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2748 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2751 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2753 if (SK_IS_GENESIS(sc)) {
2754 /* Enable XMACs TX and RX state machines */
2755 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2756 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2757 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2760 if (SK_IS_YUKON(sc)) {
2761 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2762 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2764 /* XXX disable 100Mbps and full duplex mode? */
2765 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
2767 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2770 /* Activate descriptor polling timer */
2771 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
2772 /* Start transfer of Tx descriptors */
2773 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2775 ifp->if_flags |= IFF_RUNNING;
2776 ifq_clr_oactive(&ifp->if_snd);
2778 if (SK_IS_YUKON(sc))
2779 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2783 sk_stop(struct sk_if_softc *sc_if)
2785 struct sk_softc *sc = sc_if->sk_softc;
2786 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2787 struct sk_chain_data *cd = &sc_if->sk_cdata;
2791 ASSERT_SERIALIZED(ifp->if_serializer);
2793 DPRINTFN(2, ("sk_stop\n"));
2795 callout_stop(&sc_if->sk_tick_timer);
2797 ifp->if_flags &= ~IFF_RUNNING;
2798 ifq_clr_oactive(&ifp->if_snd);
2800 /* Stop Tx descriptor polling timer */
2801 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
2803 /* Stop transfer of Tx descriptors */
2804 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
2805 for (i = 0; i < SK_TIMEOUT; i++) {
2806 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
2807 if (!(val & SK_TXBMU_TX_STOP))
2811 if (i == SK_TIMEOUT)
2812 if_printf(ifp, "cannot stop transfer of Tx descriptors\n");
2814 /* Stop transfer of Rx descriptors */
2815 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
2816 for (i = 0; i < SK_TIMEOUT; i++) {
2817 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
2818 if (!(val & SK_RXBMU_RX_STOP))
2822 if (i == SK_TIMEOUT)
2823 if_printf(ifp, "cannot stop transfer of Rx descriptors\n");
2825 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2826 /* Put PHY back into reset. */
2827 val = sk_win_read_4(sc, SK_GPIO);
2828 if (sc_if->sk_port == SK_PORT_A) {
2829 val |= SK_GPIO_DIR0;
2830 val &= ~SK_GPIO_DAT0;
2832 val |= SK_GPIO_DIR2;
2833 val &= ~SK_GPIO_DAT2;
2835 sk_win_write_4(sc, SK_GPIO, val);
2838 /* Turn off various components of this interface. */
2839 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2840 switch (sc->sk_type) {
2842 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2843 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2848 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2849 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2852 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2853 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2854 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2855 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2856 SK_RBCTL_RESET | SK_RBCTL_OFF);
2857 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2858 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2859 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2860 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2861 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2863 /* Disable interrupts */
2864 if (sc_if->sk_port == SK_PORT_A)
2865 sc->sk_intrmask &= ~SK_INTRS1;
2867 sc->sk_intrmask &= ~SK_INTRS2;
2868 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2870 SK_XM_READ_2(sc_if, XM_ISR);
2871 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2873 /* Free RX and TX mbufs still in the queues. */
2874 for (i = 0; i < SK_RX_RING_CNT; i++) {
2875 if (cd->sk_rx_mbuf[i] != NULL) {
2876 if (!sc_if->sk_use_jumbo) {
2877 bus_dmamap_unload(cd->sk_rx_dtag,
2880 m_freem(cd->sk_rx_mbuf[i]);
2881 cd->sk_rx_mbuf[i] = NULL;
2884 for (i = 0; i < SK_TX_RING_CNT; i++) {
2885 if (cd->sk_tx_mbuf[i] != NULL) {
2886 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
2887 m_freem(cd->sk_tx_mbuf[i]);
2888 cd->sk_tx_mbuf[i] = NULL;
2895 sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
2897 #define DESC_PRINT(X) \
2899 kprintf("txdesc[%d]." #X "=%#x\n", \
2902 DESC_PRINT(le32toh(desc->sk_ctl));
2903 DESC_PRINT(le32toh(desc->sk_next));
2904 DESC_PRINT(le32toh(desc->sk_data_lo));
2905 DESC_PRINT(le32toh(desc->sk_data_hi));
2906 DESC_PRINT(le32toh(desc->sk_xmac_txstat));
2907 DESC_PRINT(le16toh(desc->sk_rsvd0));
2908 DESC_PRINT(le16toh(desc->sk_csum_startval));
2909 DESC_PRINT(le16toh(desc->sk_csum_startpos));
2910 DESC_PRINT(le16toh(desc->sk_csum_writepos));
2911 DESC_PRINT(le16toh(desc->sk_rsvd1));
2916 sk_dump_bytes(const char *data, int len)
2920 for (i = 0; i < len; i += 16) {
2921 kprintf("%08x ", i);
2925 for (j = 0; j < c; j++) {
2926 kprintf("%02x ", data[i + j] & 0xff);
2927 if ((j & 0xf) == 7 && j > 0)
2935 for (j = 0; j < c; j++) {
2936 int ch = data[i + j] & 0xff;
2937 kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2948 sk_dump_mbuf(struct mbuf *m)
2950 int count = m->m_pkthdr.len;
2952 kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2954 while (count > 0 && m) {
2955 kprintf("m=%p, m->m_data=%p, m->m_len=%d\n",
2956 m, m->m_data, m->m_len);
2957 sk_dump_bytes(mtod(m, char *), m->m_len);
2966 * Allocate jumbo buffer storage. The SysKonnect adapters support
2967 * "jumbograms" (9K frames), although SysKonnect doesn't currently
2968 * use them in their drivers. In order for us to use them, we need
2969 * large 9K receive buffers, however standard mbuf clusters are only
2970 * 2048 bytes in size. Consequently, we need to allocate and manage
2971 * our own jumbo buffer pool. Fortunately, this does not require an
2972 * excessive amount of additional code.
2975 sk_jpool_alloc(device_t dev)
2977 struct sk_if_softc *sc_if = device_get_softc(dev);
2978 struct sk_chain_data *cd = &sc_if->sk_cdata;
2984 lwkt_serialize_init(&cd->sk_jpool_serializer);
2986 error = bus_dmamem_coherent(cd->sk_buf_dtag, PAGE_SIZE /* XXX */, 0,
2987 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2988 SK_JMEM, BUS_DMA_WAITOK, &dmem);
2990 device_printf(dev, "can't allocate jumbo frame pool\n");
2993 cd->sk_jpool_dtag = dmem.dmem_tag;
2994 cd->sk_jpool_dmap = dmem.dmem_map;
2995 cd->sk_jpool = dmem.dmem_addr;
2996 paddr = dmem.dmem_busaddr;
2998 SLIST_INIT(&cd->sk_jpool_free_ent);
3002 * Now divide it up into SK_JLEN pieces.
3004 for (i = 0; i < SK_JSLOTS; i++) {
3005 struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i];
3007 entry->sc_if = sc_if;
3011 entry->paddr = paddr;
3013 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
3022 sk_jpool_free(struct sk_if_softc *sc_if)
3024 struct sk_chain_data *cd = &sc_if->sk_cdata;
3026 if (cd->sk_jpool_dtag != NULL) {
3027 bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap);
3028 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
3030 bus_dma_tag_destroy(cd->sk_jpool_dtag);
3031 cd->sk_jpool_dtag = NULL;
3036 sk_dma_alloc(device_t dev)
3038 struct sk_if_softc *sc_if = device_get_softc(dev);
3039 struct sk_chain_data *cd = &sc_if->sk_cdata;
3040 struct sk_ring_data *rd = &sc_if->sk_rdata;
3044 /* Create parent DMA tag */
3045 error = bus_dma_tag_create(NULL, 1, 0,
3046 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3048 BUS_SPACE_MAXSIZE_32BIT, 0,
3049 BUS_SPACE_MAXSIZE_32BIT,
3050 0, &sc_if->sk_parent_dtag);
3052 device_printf(dev, "can't create parent DMA tag\n");
3056 /* Create top level ring DMA tag */
3057 error = bus_dma_tag_create(sc_if->sk_parent_dtag,
3058 1, SK_RING_BOUNDARY,
3059 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3061 BUS_SPACE_MAXSIZE_32BIT, 0,
3062 BUS_SPACE_MAXSIZE_32BIT,
3063 0, &rd->sk_ring_dtag);
3065 device_printf(dev, "can't create ring DMA tag\n");
3069 /* Create top level buffer DMA tag */
3070 error = bus_dma_tag_create(sc_if->sk_parent_dtag, 1, 0,
3071 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3073 BUS_SPACE_MAXSIZE_32BIT, 0,
3074 BUS_SPACE_MAXSIZE_32BIT,
3075 0, &cd->sk_buf_dtag);
3077 device_printf(dev, "can't create buf DMA tag\n");
3081 /* Allocate the TX descriptor queue. */
3082 error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3083 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3085 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3087 device_printf(dev, "can't allocate TX ring\n");
3090 rd->sk_tx_ring_dtag = dmem.dmem_tag;
3091 rd->sk_tx_ring_dmap = dmem.dmem_map;
3092 rd->sk_tx_ring = dmem.dmem_addr;
3093 rd->sk_tx_ring_paddr = dmem.dmem_busaddr;
3095 /* Allocate the RX descriptor queue. */
3096 error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3097 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3099 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3101 device_printf(dev, "can't allocate TX ring\n");
3104 rd->sk_rx_ring_dtag = dmem.dmem_tag;
3105 rd->sk_rx_ring_dmap = dmem.dmem_map;
3106 rd->sk_rx_ring = dmem.dmem_addr;
3107 rd->sk_rx_ring_paddr = dmem.dmem_busaddr;
3109 /* Try to allocate memory for jumbo buffers. */
3110 error = sk_jpool_alloc(dev);
3112 device_printf(dev, "jumbo buffer allocation failed\n");
3116 /* Create DMA tag for TX. */
3117 error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3118 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3120 SK_JLEN, SK_NTXSEG, SK_JLEN,
3121 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3125 device_printf(dev, "can't create TX DMA tag\n");
3129 /* Create DMA maps for TX. */
3130 for (i = 0; i < SK_TX_RING_CNT; i++) {
3131 error = bus_dmamap_create(cd->sk_tx_dtag,
3132 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3133 &cd->sk_tx_dmap[i]);
3135 device_printf(dev, "can't create %dth TX DMA map\n", i);
3137 for (j = 0; j < i; ++j) {
3138 bus_dmamap_destroy(cd->sk_tx_dtag,
3141 bus_dma_tag_destroy(cd->sk_tx_dtag);
3142 cd->sk_tx_dtag = NULL;
3147 /* Create DMA tag for RX. */
3148 error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3149 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3151 MCLBYTES, 1, MCLBYTES,
3152 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3155 device_printf(dev, "can't create RX DMA tag\n");
3159 /* Create a spare RX DMA map. */
3160 error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
3161 &cd->sk_rx_dmap_tmp);
3163 device_printf(dev, "can't create spare RX DMA map\n");
3164 bus_dma_tag_destroy(cd->sk_rx_dtag);
3165 cd->sk_rx_dtag = NULL;
3169 /* Create DMA maps for RX. */
3170 for (i = 0; i < SK_RX_RING_CNT; ++i) {
3171 error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
3172 &cd->sk_rx_dmap[i]);
3174 device_printf(dev, "can't create %dth RX DMA map\n", i);
3176 for (j = 0; j < i; ++j) {
3177 bus_dmamap_destroy(cd->sk_rx_dtag,
3180 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3181 bus_dma_tag_destroy(cd->sk_rx_dtag);
3182 cd->sk_rx_dtag = NULL;
3190 sk_dma_free(device_t dev)
3192 struct sk_if_softc *sc_if = device_get_softc(dev);
3193 struct sk_chain_data *cd = &sc_if->sk_cdata;
3194 struct sk_ring_data *rd = &sc_if->sk_rdata;
3197 if (cd->sk_tx_dtag != NULL) {
3198 for (i = 0; i < SK_TX_RING_CNT; ++i) {
3199 KASSERT(cd->sk_tx_mbuf[i] == NULL,
3200 ("sk_stop() is not called before %s()",
3202 bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
3204 bus_dma_tag_destroy(cd->sk_tx_dtag);
3207 if (cd->sk_rx_dtag != NULL) {
3208 for (i = 0; i < SK_RX_RING_CNT; ++i) {
3209 KASSERT(cd->sk_rx_mbuf[i] == NULL,
3210 ("sk_stop() is not called before %s()",
3212 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]);
3214 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3215 bus_dma_tag_destroy(cd->sk_rx_dtag);
3218 sk_jpool_free(sc_if);
3220 if (rd->sk_rx_ring_dtag != NULL) {
3221 bus_dmamap_unload(rd->sk_rx_ring_dtag, rd->sk_rx_ring_dmap);
3222 bus_dmamem_free(rd->sk_rx_ring_dtag, rd->sk_rx_ring,
3223 rd->sk_rx_ring_dmap);
3224 bus_dma_tag_destroy(rd->sk_rx_ring_dtag);
3227 if (rd->sk_tx_ring_dtag != NULL) {
3228 bus_dmamap_unload(rd->sk_tx_ring_dtag, rd->sk_tx_ring_dmap);
3229 bus_dmamem_free(rd->sk_tx_ring_dtag, rd->sk_tx_ring,
3230 rd->sk_tx_ring_dmap);
3231 bus_dma_tag_destroy(rd->sk_tx_ring_dtag);
3234 if (rd->sk_ring_dtag != NULL)
3235 bus_dma_tag_destroy(rd->sk_ring_dtag);
3236 if (cd->sk_buf_dtag != NULL)
3237 bus_dma_tag_destroy(cd->sk_buf_dtag);
3238 if (sc_if->sk_parent_dtag != NULL)
3239 bus_dma_tag_destroy(sc_if->sk_parent_dtag);
3243 skc_sysctl_imtime(SYSCTL_HANDLER_ARGS)
3245 struct sk_softc *sc = arg1;
3246 struct lwkt_serialize *slize = &sc->sk_serializer;
3249 lwkt_serialize_enter(slize);
3252 error = sysctl_handle_int(oidp, &v, 0, req);
3253 if (error || req->newptr == NULL)
3260 if (sc->sk_imtime != v) {
3262 sk_win_write_4(sc, SK_IMTIMERINIT,
3263 SK_IM_USECS(sc, sc->sk_imtime));
3266 * Force interrupt moderation timer to
3269 sk_win_write_4(sc, SK_IMTIMER, 0);
3272 lwkt_serialize_exit(slize);