2 * Copyright (c) 1996 - 2001 John Hay.
3 * Copyright (c) 1996 SDL Communications, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
34 * Programming assumptions and other issues.
36 * Only a 16K window will be used.
38 * The descriptors of a DMA channel will fit in a 16K memory window.
40 * The buffers of a transmit DMA channel will fit in a 16K memory window.
42 * When interface is going up, handshaking is set and it is only cleared
43 * when the interface is down'ed.
45 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
46 * internal/external clock, etc.....
50 #include "opt_netgraph.h"
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/kernel.h>
58 #include <sys/malloc.h>
60 #include <sys/sockio.h>
61 #include <sys/socket.h>
62 #include <sys/thread2.h>
67 #include <net/ifq_var.h>
69 #include <sys/syslog.h>
71 #include <net/if_arp.h>
72 #include <net/sppp/if_sppp.h>
77 #include <machine/md_var.h>
79 #include "../ic_layer/hd64570.h"
80 #include "if_srregs.h"
83 #include <netgraph/ng_message.h>
84 #include <netgraph/netgraph.h>
86 /* #define USE_MODEMCK */
93 #define PPP_HEADER_LEN 4
96 static int next_sc_unit = 0;
99 static int sr_watcher = 0;
101 #endif /* NETGRAPH */
104 * Define the software interface for the card... There is one for
105 * every channel (port).
109 struct sppp ifsppp; /* PPP service w/in system */
110 #endif /* NETGRAPH */
111 struct sr_hardc *hc; /* card-level information */
113 int unit; /* With regard to all sr devices */
114 int subunit; /* With regard to this card */
117 u_int txdesc; /* DPRAM offset */
118 u_int txstart;/* DPRAM offset */
119 u_int txend; /* DPRAM offset */
120 u_int txtail; /* # of 1st free gran */
121 u_int txmax; /* # of free grans */
122 u_int txeda; /* err descr addr */
123 } block[SR_TX_BLOCKS];
125 char xmit_busy; /* Transmitter is busy */
126 char txb_inuse; /* # of tx grans in use */
127 u_int txb_new; /* ndx to new buffer */
128 u_int txb_next_tx; /* ndx to next gran rdy tx */
130 u_int rxdesc; /* DPRAM offset */
131 u_int rxstart; /* DPRAM offset */
132 u_int rxend; /* DPRAM offset */
133 u_int rxhind; /* ndx to the hd of rx bufrs */
134 u_int rxmax; /* # of avail grans */
136 u_int clk_cfg; /* Clock configuration */
138 int scachan; /* channel # on card */
140 int running; /* something is attached so we are running */
141 int dcd; /* do we have dcd? */
142 /* ---netgraph bits --- */
143 char nodename[NG_NODESIZ]; /* store our node name */
144 int datahooks; /* number of data hooks attached */
145 node_p node; /* netgraph node */
146 hook_p hook; /* data hook */
148 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
149 struct ifqueue xmitq; /* transmit queue */
150 int flags; /* state */
151 #define SCF_RUNNING 0x01 /* board is active */
152 #define SCF_OACTIVE 0x02 /* output is active */
153 int out_dog; /* watchdog cycles output count-down */
154 struct callout sr_timer; /* timeout(9) handle */
155 u_long inbytes, outbytes; /* stats */
156 u_long lastinbytes, lastoutbytes; /* a second ago */
157 u_long inrate, outrate; /* highest rate seen */
158 u_long inlast; /* last input N secs ago */
159 u_long out_deficit; /* output since last input */
160 u_long oerrors, ierrors[6];
161 u_long opackets, ipackets;
162 #endif /* NETGRAPH */
166 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
167 #define QUITE_A_WHILE 300 /* 5 MINUTES */
168 #define LOTS_OF_PACKETS 100
169 #endif /* NETGRAPH */
172 * Baud Rate table for Sync Mode.
173 * Each entry consists of 3 elements:
174 * Baud Rate (x100) , TMC, BR
176 * Baud Rate = FCLK / TMC / 2^BR
177 * Baud table for Crystal freq. of 9.8304 Mhz
181 int target; /* target rate/100 */
182 int tmc_reg; /* TMC register value */
183 int br_reg; /* BR (BaudRateClk) selector */
185 /* Baudx100 TMC BR */
206 int sr_test_speed[] = {
212 SR_MCR_ETC0, /* ISA channel 0 */
213 SR_MCR_ETC1, /* ISA channel 1 */
214 SR_FECR_ETC0, /* PCI channel 0 */
215 SR_FECR_ETC1 /* PCI channel 1 */
219 devclass_t sr_devclass;
221 DECLARE_DUMMY_MODULE(if_sr);
222 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
224 MODULE_DEPEND(ng_sync_sr, netgraph, NG_ABI_VERSION, NG_ABI_VERSION, NG_ABI_VERSION);
227 static void srintr(void *arg);
228 static void sr_xmit(struct sr_softc *sc);
230 static void srstart(struct ifnet *ifp, struct ifaltq_subque *);
231 static int srioctl(struct ifnet *ifp, u_long cmd, caddr_t data,
233 static void srwatchdog(struct ifnet *ifp);
235 static void srstart(struct sr_softc *sc);
236 static void srwatchdog(struct sr_softc *sc);
237 #endif /* NETGRAPH */
238 static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
239 static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
240 static void sr_eat_packet(struct sr_softc *sc, int single);
241 static void sr_get_packets(struct sr_softc *sc);
243 static void sr_up(struct sr_softc *sc);
244 static void sr_down(struct sr_softc *sc);
245 static void src_init(struct sr_hardc *hc);
246 static void sr_init_sca(struct sr_hardc *hc);
247 static void sr_init_msci(struct sr_softc *sc);
248 static void sr_init_rx_dmac(struct sr_softc *sc);
249 static void sr_init_tx_dmac(struct sr_softc *sc);
250 static void sr_dmac_intr(struct sr_hardc *hc, u_char isr);
251 static void sr_msci_intr(struct sr_hardc *hc, u_char isr);
252 static void sr_timer_intr(struct sr_hardc *hc, u_char isr);
255 static void sr_modemck(void *x);
258 static void sr_modemck(struct sr_softc *x);
259 #endif /* NETGRAPH */
262 static void ngsr_watchdog_frame(void * arg);
263 static void ngsr_init(void* ignored);
265 static ng_constructor_t ngsr_constructor;
266 static ng_rcvmsg_t ngsr_rcvmsg;
267 static ng_shutdown_t ngsr_rmnode;
268 static ng_newhook_t ngsr_newhook;
269 /*static ng_findhook_t ngsr_findhook; */
270 static ng_connect_t ngsr_connect;
271 static ng_rcvdata_t ngsr_rcvdata;
272 static ng_disconnect_t ngsr_disconnect;
274 static struct ng_type typestruct = {
290 static int ngsr_done_init = 0;
291 #endif /* NETGRAPH */
294 * Register the ports on the adapter.
295 * Fill in the info for each port.
297 * Attach each port to sppp and bpf.
301 sr_attach(device_t device)
310 #endif /* NETGRAPH */
311 int unit; /* index: channel w/in card */
313 hc = (struct sr_hardc *)device_get_softc(device);
314 sc = kmalloc(hc->numports * sizeof(struct sr_softc), M_DEVBUF,
319 * Get the TX clock direction and configuration. The default is a
320 * single external clock which is used by RX and TX.
322 switch(hc->cardtype) {
324 flags = device_get_flags(device);
326 if (sr_test_speed[0] > 0)
327 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
330 if (flags & SR_FLAGS_0_CLK_MSK)
332 (flags & SR_FLAGS_0_CLK_MSK)
333 >> SR_FLAGS_CLK_SHFT;
335 if (hc->numports == 2)
337 if (sr_test_speed[1] > 0)
338 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
341 if (flags & SR_FLAGS_1_CLK_MSK)
342 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
343 >> (SR_FLAGS_CLK_SHFT +
344 SR_FLAGS_CLK_CHAN_SHFT);
347 fecrp = (u_int *)(hc->sca_base + SR_FECR);
349 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
352 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
356 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
360 if (sr_test_speed[pndx] > 0)
361 sc->clk_cfg = SR_FLAGS_INT_CLK;
373 sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
377 sc->clk_cfg = SR_FLAGS_EXT_CLK;
386 * Report Card configuration information before we start configuring
387 * each channel on the card...
389 kprintf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
390 hc->cunit, hc->memsize / 1024, hc->mempages,
391 (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
396 if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
398 &hc->intr_cookie, NULL, NULL) != 0)
402 * Now configure each port on the card.
404 for (unit = 0; unit < hc->numports; sc++, unit++) {
407 sc->unit = next_sc_unit;
409 sc->scachan = unit % NCHAN;
415 kprintf("sr%d: Adapter %d, port %d.\n",
416 sc->unit, hc->cunit, sc->subunit);
419 ifp = &sc->ifsppp.pp_if;
421 if_initname(ifp, "sr", sc->unit);
422 ifp->if_mtu = PP_MTU;
423 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
424 ifp->if_ioctl = srioctl;
425 ifp->if_start = srstart;
426 ifp->if_watchdog = srwatchdog;
428 sc->ifsppp.pp_flags = PP_KEEPALIVE;
429 sppp_attach((struct ifnet *)&sc->ifsppp);
430 if_attach(ifp, NULL);
432 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
435 * we have found a node, make sure our 'type' is availabe.
437 if (ngsr_done_init == 0) ngsr_init(NULL);
438 if (ng_make_node_common(&typestruct, &sc->node) != 0)
440 sc->node->private = sc;
441 callout_init(&sc->sr_timer);
442 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
443 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
444 ksprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
445 if (ng_name_node(sc->node, sc->nodename)) {
451 #endif /* NETGRAPH */
457 sr_deallocate_resources(device);
462 sr_detach(device_t device)
464 device_t parent = device_get_parent(device);
465 struct sr_hardc *hc = device_get_softc(device);
467 if (hc->intr_cookie != NULL) {
468 if (BUS_TEARDOWN_INTR(parent, device,
469 hc->res_irq, hc->intr_cookie) != 0) {
470 kprintf("intr teardown failed.. continuing\n");
472 hc->intr_cookie = NULL;
475 /* XXX Stop the DMA. */
478 * deallocate any system resources we may have
479 * allocated on behalf of this driver.
481 kfree(hc->sc, M_DEVBUF);
483 hc->mem_start = NULL;
484 return (sr_deallocate_resources(device));
488 sr_allocate_irq(device_t device, int rid, u_long size)
490 struct sr_hardc *hc = device_get_softc(device);
493 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
494 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
495 if (hc->res_irq == NULL) {
501 sr_deallocate_resources(device);
506 sr_allocate_memory(device_t device, int rid, u_long size)
508 struct sr_hardc *hc = device_get_softc(device);
510 hc->rid_memory = rid;
511 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
512 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
513 if (hc->res_memory == NULL) {
519 sr_deallocate_resources(device);
524 sr_allocate_plx_memory(device_t device, int rid, u_long size)
526 struct sr_hardc *hc = device_get_softc(device);
528 hc->rid_plx_memory = rid;
529 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
530 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
531 if (hc->res_plx_memory == NULL) {
537 sr_deallocate_resources(device);
542 sr_deallocate_resources(device_t device)
544 struct sr_hardc *hc = device_get_softc(device);
546 if (hc->res_irq != 0) {
547 bus_deactivate_resource(device, SYS_RES_IRQ,
548 hc->rid_irq, hc->res_irq);
549 bus_release_resource(device, SYS_RES_IRQ,
550 hc->rid_irq, hc->res_irq);
553 if (hc->res_memory != 0) {
554 bus_deactivate_resource(device, SYS_RES_MEMORY,
555 hc->rid_memory, hc->res_memory);
556 bus_release_resource(device, SYS_RES_MEMORY,
557 hc->rid_memory, hc->res_memory);
560 if (hc->res_plx_memory != 0) {
561 bus_deactivate_resource(device, SYS_RES_MEMORY,
562 hc->rid_plx_memory, hc->res_plx_memory);
563 bus_release_resource(device, SYS_RES_MEMORY,
564 hc->rid_plx_memory, hc->res_plx_memory);
565 hc->res_plx_memory = 0;
571 * N2 Interrupt Service Routine
573 * First figure out which SCA gave the interrupt.
575 * See if there is other interrupts pending.
576 * Repeat until there no interrupts remain.
581 struct sr_hardc *hc = (struct sr_hardc *)arg;
582 sca_regs *sca = hc->sca; /* MSCI register tree */
583 u_char isr0, isr1, isr2; /* interrupt statii captured */
586 kprintf("sr: srintr_hc(hc=%08x)\n", hc);
590 * Since multiple interfaces may share this interrupt, we must loop
591 * until no interrupts are still pending service.
595 * Read all three interrupt status registers from the N2
598 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
599 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
600 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
603 * If all three registers returned 0, we've finished
604 * processing interrupts from this device, so we can quit
607 if ((isr0 | isr1 | isr2) == 0)
611 kprintf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
613 unit, isr0, isr1, isr2);
615 hc->cunit, isr0, isr1, isr2);
616 #endif /* NETGRAPH */
620 * Now we can dispatch the interrupts. Since we don't expect
621 * either MSCI or timer interrupts, we'll test for DMA
622 * interrupts first...
624 if (isr1) /* DMA-initiated interrupt */
625 sr_dmac_intr(hc, isr1);
627 if (isr0) /* serial part IRQ? */
628 sr_msci_intr(hc, isr0);
630 if (isr2) /* timer-initiated interrupt */
631 sr_timer_intr(hc, isr2);
636 * This will only start the transmitter. It is assumed that the data
638 * It is normally called from srstart() or sr_dmac_intr().
641 sr_xmit(struct sr_softc *sc)
643 u_short cda_value; /* starting descriptor */
644 u_short eda_value; /* ending descriptor */
647 struct ifnet *ifp; /* O/S Network Services */
648 #endif /* NETGRAPH */
649 dmac_channel *dmac; /* DMA channel registers */
652 kprintf("sr: sr_xmit( sc=%08x)\n", sc);
657 ifp = &sc->ifsppp.pp_if;
658 #endif /* NETGRAPH */
659 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
662 * Get the starting and ending addresses of the chain to be
663 * transmitted and pass these on to the DMA engine on-chip.
665 cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
666 cda_value &= 0x00ffff;
667 eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
668 eda_value &= 0x00ffff;
670 SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
671 SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
674 * Now we'll let the DMA status register know about this change
676 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
678 sc->xmit_busy = 1; /* mark transmitter busy */
681 kprintf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n",
682 sc->unit, cda_value, eda_value,
683 sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
686 sc->txb_next_tx++; /* update next transmit seq# */
688 if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */
693 * Finally, we'll set a timout (which will start srwatchdog())
694 * within the O/S network services layer...
696 ifp->if_timer = 2; /* Value in seconds. */
699 * Don't time out for a while.
701 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
702 #endif /* NETGRAPH */
706 * This function will be called from the upper level when a user add a
707 * packet to be send, and from the interrupt handler after a finished
710 * This function only place the data in the oncard buffers. It does not
711 * start the transmition. sr_xmit() does that.
713 * Transmitter idle state is indicated by the OACTIVE flag.
714 * The function that clears that should ensure that the transmitter
715 * and its DMA is in a "good" idle state.
719 srstart(struct ifnet *ifp, struct ifaltq_subque *ifsq)
721 struct sr_softc *sc; /* channel control structure */
724 srstart(struct sr_softc *sc)
726 #endif /* NETGRAPH */
727 struct sr_hardc *hc; /* card control/config block */
728 int len; /* total length of a packet */
729 int pkts; /* packets placed in DPRAM */
730 int tlen; /* working length of pkt */
732 struct mbuf *mtx; /* message buffer from O/S */
733 u_char *txdata; /* buffer address in DPRAM */
734 sca_descriptor *txdesc; /* working descriptor pointr */
735 struct buf_block *blkp;
739 kprintf("sr: srstart( ifp=%08x)\n", ifp);
742 if ((ifp->if_flags & IFF_RUNNING) == 0)
744 #endif /* NETGRAPH */
747 * It is OK to set the memory window outside the loop because all tx
748 * buffers and descriptors are assumed to be in the same 16K window.
752 * Loop to place packets into DPRAM.
754 * We stay in this loop until there is nothing in
755 * the TX queue left or the tx buffers are full.
760 * See if we have space for more packets.
762 if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */
764 ifq_set_oactive(&ifp->if_snd); /* yes, mark active */
766 /*ifq_set_oactive(&ifp->if_snd);*/ /* yes, mark active */
767 #endif /* NETGRAPH */
770 kprintf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
771 sc->unit, sc->txb_inuse);
776 * OK, the card can take more traffic. Let's see if there's any
777 * pending from the system...
780 * The architecture of the networking interface doesn't
781 * actually call us like 'write()', providing an address. We get
782 * started, a lot like a disk strategy routine, and we actually call
783 * back out to the system to get traffic to send...
786 * If we were gonna run through another layer, we would use a
787 * dispatch table to select the service we're getting a packet
791 mtx = sppp_dequeue(ifp);
793 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
795 IF_DEQUEUE(&sc->xmitq, mtx);
797 #endif /* NETGRAPH */
802 * OK, we got a packet from the network services of the O/S. Now we
803 * can move it into the DPRAM (under control of the descriptors) and
807 i = 0; /* counts # of granules used */
809 blkp = &sc->block[sc->txb_new]; /* address of free granule */
810 txdesc = (sca_descriptor *)
811 (hc->mem_start + (blkp->txdesc & hc->winmsk));
813 txdata = (u_char *)(hc->mem_start
814 + (blkp->txstart & hc->winmsk));
817 * Now we'll try to install as many packets as possible into the
818 * card's DP RAM buffers.
820 for (;;) { /* perform actual copy of packet */
821 len = mtx->m_pkthdr.len; /* length of message */
824 kprintf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
832 #endif /* NETGRAPH */
835 * We can perform a straight copy because the tranmit
836 * buffers won't wrap.
838 m_copydata(mtx, 0, len, txdata);
841 * Now we know how big the message is gonna be. We must now
842 * construct the descriptors to drive this message out...
845 while (tlen > SR_BUF_SIZ) { /* loop for full granules */
846 txdesc->stat = 0; /* reset bits */
847 txdesc->len = SR_BUF_SIZ; /* size of granule */
850 txdesc++; /* move to next dscr */
851 txdata += SR_BUF_SIZ; /* adjust data addr */
856 * This section handles the setting of the final piece of a
859 txdesc->stat = SCA_DESC_EOM;
864 * prepare for subsequent packets (if any)
867 txdata += SR_BUF_SIZ; /* next mem granule */
868 i++; /* count of granules */
871 * OK, we've now placed the message into the DPRAM where it
872 * can be transmitted. We'll now release the message memory
873 * and update the statistics...
877 IFNET_STAT_INC(&sc->ifsppp.pp_if, opackets, 1);
880 #endif /* NETGRAPH */
883 * Check if we have space for another packet. XXX This is
884 * hardcoded. A packet can't be larger than 3 buffers (3 x
887 if ((i + 3) >= blkp->txmax) { /* enough remains? */
889 kprintf("sr%d.srstart: i=%d (%d pkts); card full.\n",
895 * We'll pull the next message to be sent (if any)
898 mtx = sppp_dequeue(ifp);
900 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
902 IF_DEQUEUE(&sc->xmitq, mtx);
904 #endif /* NETGRAPH */
905 if (!mtx) { /* no message? We're done! */
907 kprintf("sr%d.srstart: pending=0, pkts=%d\n",
914 blkp->txtail = i; /* record next free granule */
917 * Mark the last descriptor, so that the SCA know where to stop.
919 txdesc--; /* back up to last descriptor in list */
920 txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */
923 * Now we'll reset the transmit granule's descriptor address so we
924 * can record this in the structure and fire it off w/ the DMA
925 * processor of the serial chip...
927 txdesc = (sca_descriptor *)blkp->txdesc;
928 blkp->txeda = (u_short)((u_int)&txdesc[i]);
930 sc->txb_inuse++; /* update inuse status */
931 sc->txb_new++; /* new traffic wuz added */
933 if (sc->txb_new == SR_TX_BLOCKS)
937 * If the tranmitter wasn't marked as "busy" we will force it to be
940 if (sc->xmit_busy == 0) {
943 kprintf("sr%d.srstart: called sr_xmit()\n", sc->unit);
951 * Handle ioctl's at the device level, though we *will* call up
955 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
959 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
961 int error, was_up, should_be_up;
962 struct sr_softc *sc = ifp->if_softc;
965 kprintf("%s: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
966 ifp->if_xname, ifp, cmd, data);
969 was_up = ifp->if_flags & IFF_RUNNING;
971 error = sppp_ioctl(ifp, cmd, data);
974 kprintf("%s: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
975 ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
981 if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
983 if (bug_splats[sc->unit]++ < 2) {
984 kprintf("sr(%d).if_addrheads = %08x\n",
985 sc->unit, ifp->if_addrheads);
986 kprintf("sr(%d).if_bpf = %08x\n",
987 sc->unit, ifp->if_bpf);
988 kprintf("sr(%d).if_init = %08x\n",
989 sc->unit, ifp->if_init);
990 kprintf("sr(%d).if_output = %08x\n",
991 sc->unit, ifp->if_output);
992 kprintf("sr(%d).if_start = %08x\n",
993 sc->unit, ifp->if_start);
994 kprintf("sr(%d).if_done = %08x\n",
995 sc->unit, ifp->if_done);
996 kprintf("sr(%d).if_ioctl = %08x\n",
997 sc->unit, ifp->if_ioctl);
998 kprintf("sr(%d).if_reset = %08x\n",
999 sc->unit, ifp->if_reset);
1000 kprintf("sr(%d).if_watchdog = %08x\n",
1001 sc->unit, ifp->if_watchdog);
1009 should_be_up = ifp->if_flags & IFF_RUNNING;
1011 if (!was_up && should_be_up) {
1013 * Interface should be up -- start it.
1016 srstart(ifp, ifq_get_subq_default(&ifp->if_snd));
1019 * XXX Clear the IFF_UP flag so that the link will only go
1020 * up after sppp lcp and ipcp negotiation.
1022 /* ifp->if_flags &= ~IFF_UP; */
1023 } else if (was_up && !should_be_up) {
1025 * Interface should be down -- stop it.
1035 #endif /* NETGRAPH */
1038 * This is to catch lost tx interrupts.
1042 srwatchdog(struct ifnet *ifp)
1044 srwatchdog(struct sr_softc *sc)
1045 #endif /* NETGRAPH */
1047 int got_st0, got_st1, got_st3, got_dsr;
1049 struct sr_softc *sc = ifp->if_softc;
1050 #endif /* NETGRAPH */
1051 struct sr_hardc *hc = sc->hc;
1052 msci_channel *msci = &hc->sca->msci[sc->scachan];
1053 dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1057 kprintf("srwatchdog(unit=%d)\n", unit);
1059 kprintf("srwatchdog(unit=%d)\n", sc->unit);
1060 #endif /* NETGRAPH */
1064 if (!(ifp->if_flags & IFF_RUNNING))
1067 IFNET_STAT_INC(ifp, oerrors, 1); /* update output error count */
1068 #else /* NETGRAPH */
1069 sc->oerrors++; /* update output error count */
1070 #endif /* NETGRAPH */
1072 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1073 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1074 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1075 got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1079 if (ifp->if_flags & IFF_DEBUG)
1081 kprintf("sr%d: transmit failed, "
1082 #else /* NETGRAPH */
1083 kprintf("sr%d: transmit failed, "
1084 #endif /* NETGRAPH */
1085 "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1087 got_st0, got_st1, got_st3, got_dsr);
1089 if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1090 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1091 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1092 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1096 ifq_clr_oactive(&ifp->if_snd);
1098 /*ifq_clr_oactive(&ifp->if_snd) */
1099 #endif /* NETGRAPH */
1101 if (sc->txb_inuse && --sc->txb_inuse)
1105 srstart(ifp, ifq_get_subq_default(&ifp->if_snd));
1106 /* restart transmitter */
1108 srstart(sc); /* restart transmitter */
1109 #endif /* NETGRAPH */
1113 sr_up(struct sr_softc *sc)
1116 struct sr_hardc *hc = sc->hc;
1117 sca_regs *sca = hc->sca;
1118 msci_channel *msci = &sca->msci[sc->scachan];
1121 kprintf("sr_up(sc=%08x)\n", sc);
1125 * Enable transmitter and receiver. Raise DTR and RTS. Enable
1128 * XXX What about using AUTO mode in msci->md0 ???
1130 SRC_PUT8(hc->sca_base, msci->ctl,
1131 SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1133 if (sc->scachan == 0)
1134 switch (hc->cardtype) {
1136 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1137 *fecrp &= ~SR_FECR_DTR0;
1141 switch (hc->cardtype) {
1143 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1144 *fecrp &= ~SR_FECR_DTR1;
1148 if (sc->scachan == 0) {
1149 SRC_PUT8(hc->sca_base, sca->ier0,
1150 SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1151 SRC_PUT8(hc->sca_base, sca->ier1,
1152 SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1154 SRC_PUT8(hc->sca_base, sca->ier0,
1155 SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1156 SRC_PUT8(hc->sca_base, sca->ier1,
1157 SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1160 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1161 DELAY(1000); /* XXX slow it down a bit. */
1162 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1166 if (sr_watcher == 0)
1169 #else /* NETGRAPH */
1170 callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
1172 #endif /* NETGRAPH */
1176 sr_down(struct sr_softc *sc)
1179 struct sr_hardc *hc = sc->hc;
1180 sca_regs *sca = hc->sca;
1181 msci_channel *msci = &sca->msci[sc->scachan];
1184 kprintf("sr_down(sc=%08x)\n", sc);
1187 callout_stop(&sc->sr_timer);
1189 #endif /* NETGRAPH */
1192 * Disable transmitter and receiver. Lower DTR and RTS. Disable
1195 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1196 DELAY(1000); /* XXX slow it down a bit. */
1197 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1199 SRC_PUT8(hc->sca_base, msci->ctl,
1200 SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1202 if (sc->scachan == 0)
1203 switch (hc->cardtype) {
1205 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1206 *fecrp |= SR_FECR_DTR0;
1210 switch (hc->cardtype) {
1212 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1213 *fecrp |= SR_FECR_DTR1;
1217 if (sc->scachan == 0) {
1218 SRC_PUT8(hc->sca_base, sca->ier0,
1219 SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1220 SRC_PUT8(hc->sca_base, sca->ier1,
1221 SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1223 SRC_PUT8(hc->sca_base, sca->ier0,
1224 SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1225 SRC_PUT8(hc->sca_base, sca->ier1,
1226 SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1231 * Initialize the card, allocate memory for the sr_softc structures
1232 * and fill in the pointers.
1235 src_init(struct sr_hardc *hc)
1237 struct sr_softc *sc = hc->sc;
1245 kprintf("src_init(hc=%08x)\n", hc);
1248 chanmem = hc->memsize / hc->numports;
1251 for (x = 0; x < hc->numports; x++, sc++) {
1254 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1255 sc->block[blk].txdesc = next;
1256 bufmem = (16 * 1024) / SR_TX_BLOCKS;
1257 descneeded = bufmem / SR_BUF_SIZ;
1259 sc->block[blk].txstart = sc->block[blk].txdesc
1260 + ((((descneeded * sizeof(sca_descriptor))
1264 sc->block[blk].txend = next + bufmem;
1265 sc->block[blk].txmax =
1266 (sc->block[blk].txend - sc->block[blk].txstart)
1271 kprintf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1273 sc->block[blk].txdesc, sc->block[blk].txstart);
1278 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1279 descneeded = bufmem / SR_BUF_SIZ;
1280 sc->rxstart = sc->rxdesc +
1281 ((((descneeded * sizeof(sca_descriptor)) /
1282 SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1283 sc->rxend = next + bufmem;
1284 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1290 * The things done here are channel independent.
1292 * Configure the sca waitstates.
1293 * Configure the global interrupt registers.
1294 * Enable master dma enable.
1297 sr_init_sca(struct sr_hardc *hc)
1299 sca_regs *sca = hc->sca;
1302 kprintf("sr_init_sca(hc=%08x)\n", hc);
1306 * Do the wait registers. Set everything to 0 wait states.
1308 SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1309 SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1310 SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1311 SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1312 SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1315 * Configure the interrupt registers. Most are cleared until the
1316 * interface is configured.
1318 SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */
1319 SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */
1320 SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */
1321 SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr
1323 SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1324 SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1327 * Configure the timers. XXX Later
1331 * Set the DMA channel priority to rotate between all four channels.
1333 * Enable all dma channels.
1335 SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1336 SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1340 * Configure the msci
1342 * NOTE: The serial port configuration is hardcoded at the moment.
1345 sr_init_msci(struct sr_softc *sc)
1347 int portndx; /* on-board port number */
1348 u_int *fecrp; /* pointer for PCI's MCR i/o */
1349 struct sr_hardc *hc = sc->hc;
1350 msci_channel *msci = &hc->sca->msci[sc->scachan];
1351 #ifdef N2_TEST_SPEED
1352 int br_v; /* contents for BR divisor */
1353 int etcndx; /* index into ETC table */
1354 int fifo_v, gotspeed; /* final tabled speed found */
1355 int tmc_v; /* timer control register */
1356 int wanted; /* speed (bitrate) wanted... */
1357 struct rate_line *rtp;
1360 portndx = sc->scachan;
1363 kprintf("sr: sr_init_msci( sc=%08x)\n", sc);
1366 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1367 SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1369 SCA_MD0_CRC_ENABLE |
1371 SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1372 SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1375 * According to the manual I should give a reset after changing the
1378 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1379 SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1384 * XXX Later we will have to support different clock settings.
1386 switch (sc->clk_cfg) {
1389 kprintf("sr%: clk_cfg=%08x, selected default clock.\n",
1390 portndx, sc->clk_cfg);
1393 case SR_FLAGS_EXT_CLK:
1395 * For now all interfaces are programmed to use the RX clock
1400 kprintf("sr%d: External Clock Selected.\n", portndx);
1403 SRC_PUT8(hc->sca_base, msci->rxs,
1404 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1405 SRC_PUT8(hc->sca_base, msci->txs,
1406 SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1409 case SR_FLAGS_EXT_SEP_CLK:
1411 kprintf("sr%d: Split Clocking Selected.\n", portndx);
1414 SRC_PUT8(hc->sca_base, msci->rxs,
1415 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1416 SRC_PUT8(hc->sca_base, msci->txs,
1417 SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1420 case SR_FLAGS_INT_CLK:
1422 kprintf("sr%d: Internal Clocking selected.\n", portndx);
1426 * XXX I do need some code to set the baud rate here!
1428 #ifdef N2_TEST_SPEED
1429 switch (hc->cardtype) {
1431 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1437 fifo_v = 0x10; /* stolen from Linux version */
1440 * search for appropriate speed in table, don't calc it:
1442 wanted = sr_test_speed[portndx];
1443 rtp = &n2_rates[0]; /* point to first table item */
1445 while ((rtp->target > 0) /* search table for speed */
1446 &&(rtp->target != wanted))
1450 * We've searched the table for a matching speed. If we've
1451 * found the correct rate line, we'll get the pre-calc'd
1452 * values for the TMC and baud rate divisor for subsequent
1455 if (rtp->target > 0) { /* use table-provided values */
1457 tmc_v = rtp->tmc_reg;
1459 } else { /* otherwise assume 1MBit comm rate */
1466 * Now we mask in the enable clock output for the MCR:
1468 mcr_v |= etc0vals[etcndx + portndx];
1471 * Now we'll program the registers with these speed- related
1474 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1475 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1476 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1477 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1479 switch (hc->cardtype) {
1486 if (wanted != gotspeed)
1487 kprintf("sr%d: Speed wanted=%d, found=%d\n",
1490 kprintf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1491 portndx, gotspeed, tmc_v, br_v);
1494 SRC_PUT8(hc->sca_base, msci->rxs,
1495 SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1496 SRC_PUT8(hc->sca_base, msci->txs,
1497 SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1499 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1502 switch (hc->cardtype) {
1504 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1505 *fecrp |= SR_FECR_ETC0;
1509 switch (hc->cardtype) {
1511 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1512 *fecrp |= SR_FECR_ETC1;
1519 * XXX Disable all interrupts for now. I think if you are using the
1520 * dmac you don't use these interrupts.
1522 SRC_PUT8(hc->sca_base, msci->ie0, 0);
1523 SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1524 SRC_PUT8(hc->sca_base, msci->ie2, 0);
1525 SRC_PUT8(hc->sca_base, msci->fie, 0);
1527 SRC_PUT8(hc->sca_base, msci->sa0, 0);
1528 SRC_PUT8(hc->sca_base, msci->sa1, 0);
1530 SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */
1532 SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1533 SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1534 SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1538 * Configure the rx dma controller.
1541 sr_init_rx_dmac(struct sr_softc *sc)
1543 struct sr_hardc *hc;
1545 sca_descriptor *rxd;
1546 u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1549 kprintf("sr_init_rx_dmac(sc=%08x)\n", sc);
1553 dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1556 * This phase initializes the contents of the descriptor table
1557 * needed to construct a circular buffer...
1559 rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1560 rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1562 for (rxbuf = sc->rxstart;
1564 rxbuf += SR_BUF_SIZ, rxd++) {
1566 * construct the circular chain...
1568 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1569 rxd->cp = (u_short)(rxda & 0xffff);
1572 * set the on-card buffer address...
1574 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1575 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1577 rxd->len = 0; /* bytes resident w/in granule */
1578 rxd->stat = 0xff; /* The sca write here when finished */
1582 * heal the chain so that the last entry points to the first...
1585 rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1588 * reset the reception handler's index...
1593 * We'll now configure the receiver's DMA logic...
1595 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */
1596 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1598 /* XXX maybe also SCA_DMR_CNTE */
1599 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1600 SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1602 cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1603 sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1605 SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1606 SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1608 rxd = (sca_descriptor *)sc->rxstart;
1610 SRC_PUT16(hc->sca_base, dmac->eda,
1611 (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1613 SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1616 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */
1620 * Configure the TX DMA descriptors.
1621 * Initialize the needed values and chain the descriptors.
1624 sr_init_tx_dmac(struct sr_softc *sc)
1627 u_int txbuf, txda, txda_d;
1628 struct sr_hardc *hc;
1629 sca_descriptor *txd;
1631 struct buf_block *blkp;
1636 kprintf("sr_init_tx_dmac(sc=%08x)\n", sc);
1640 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1643 * Initialize the array of descriptors for transmission
1645 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1646 blkp = &sc->block[blk];
1647 txd = (sca_descriptor *)(hc->mem_start
1648 + (blkp->txdesc & hc->winmsk));
1649 txda_d = (u_int) hc->mem_start
1650 - (blkp->txdesc & ~hc->winmsk);
1653 txbuf = blkp->txstart;
1654 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1655 txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1656 txd->cp = (u_short)(txda & 0xffff);
1658 txd->bp = (u_short)((txbuf + hc->mem_pstart)
1660 txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1668 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1671 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1674 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */
1675 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1676 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1677 SRC_PUT8(hc->sca_base, dmac->dir,
1678 SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1680 sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1683 SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1687 * Look through the descriptors to see if there is a complete packet
1688 * available. Stop if we get to where the sca is busy.
1690 * Return the length and status of the packet.
1691 * Return nonzero if there is a packet available.
1694 * It seems that we get the interrupt a bit early. The updateing of
1695 * descriptor values is not always completed when this is called.
1698 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1700 int granules; /* count of granules in pkt */
1702 struct sr_hardc *hc;
1703 sca_descriptor *rxdesc; /* current descriptor */
1704 sca_descriptor *endp; /* ending descriptor */
1705 sca_descriptor *cda; /* starting descriptor */
1707 hc = sc->hc; /* get card's information */
1710 * set up starting descriptor by pulling that info from the DMA half
1713 wki = DMAC_RXCH(sc->scachan);
1714 wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1716 cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1719 kprintf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1724 * open the appropriate memory window and set our expectations...
1726 rxdesc = (sca_descriptor *)
1727 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1729 rxdesc = &rxdesc[sc->rxhind];
1730 endp = &endp[sc->rxmax];
1732 *len = 0; /* reset result total length */
1733 granules = 0; /* reset count of granules */
1736 * This loop will scan descriptors, but it *will* puke up if we wrap
1737 * around to our starting point...
1739 while (rxdesc != cda) {
1740 *len += rxdesc->len; /* increment result length */
1744 * If we hit a valid packet's completion we'll know we've
1745 * got a live one, and that we can deliver the packet.
1746 * Since we're only allowed to report a packet available,
1747 * somebody else does that...
1749 if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */
1750 *rxstat = rxdesc->stat; /* return closing */
1752 kprintf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1753 sc->unit, *len, *rxstat, granules);
1755 return 1; /* indicate success */
1758 * OK, this packet take up multiple granules. Move on to
1759 * the next descriptor so we can consider it...
1763 if (rxdesc == endp) /* recognize & act on wrap point */
1764 rxdesc = (sca_descriptor *)
1765 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1769 * Nothing found in the DPRAM. Let the caller know...
1778 * Copy a packet from the on card memory into a provided mbuf.
1779 * Take into account that buffers wrap and that a packet may
1780 * be larger than a buffer.
1783 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1785 struct sr_hardc *hc;
1786 sca_descriptor *rxdesc;
1793 kprintf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1799 rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1800 rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1802 rxdesc = (sca_descriptor *)
1803 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1804 rxdesc = &rxdesc[sc->rxhind];
1807 * Using the count of bytes in the received packet, we decrement it
1808 * for each granule (controller by an SCA descriptor) to control the
1813 * tlen gets the length of *this* granule... ...which is
1814 * then copied to the target buffer.
1816 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1818 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1819 mtod(m, caddr_t) +off,
1826 * now, return to the descriptor's window in DPRAM and reset
1827 * the descriptor we've just suctioned...
1831 rxdesc->stat = 0xff;
1834 * Move on to the next granule. If we've any remaining
1835 * bytes to process we'll just continue in our loop...
1837 rxdata += SR_BUF_SIZ;
1840 if (rxdata == rxmax) { /* handle the wrap point */
1841 rxdata = sc->rxstart;
1842 rxdesc = (sca_descriptor *)
1843 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1849 * If single is set, just eat a packet. Otherwise eat everything up to
1850 * where cda points. Update pointers to point to the next packet.
1852 * This handles "flushing" of a packet as received...
1854 * If the "single" parameter is zero, all pending reeceive traffic will
1855 * be flushed out of existence. A non-zero value will only drop the
1856 * *next* (currently) pending packet...
1859 sr_eat_packet(struct sr_softc *sc, int single)
1861 struct sr_hardc *hc;
1862 sca_descriptor *rxdesc; /* current descriptor being eval'd */
1863 sca_descriptor *endp; /* last descriptor in chain */
1864 sca_descriptor *cda; /* current start point */
1865 u_int loopcnt = 0; /* count of packets flushed ??? */
1866 u_char stat; /* captured status byte from descr */
1869 cda = (sca_descriptor *)(hc->mem_start +
1870 (SRC_GET16(hc->sca_base,
1871 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1875 * loop until desc->stat == (0xff || EOM) Clear the status and
1876 * length in the descriptor. Increment the descriptor.
1879 rxdesc = (sca_descriptor *)
1880 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1882 rxdesc = &rxdesc[sc->rxhind];
1883 endp = &endp[sc->rxmax];
1886 * allow loop, but abort it if we wrap completely...
1888 while (rxdesc != cda) {
1891 if (loopcnt > sc->rxmax) {
1892 kprintf("sr%d: eat pkt %d loop, cda %x, "
1893 "rxdesc %x, stat %x.\n",
1894 sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1898 stat = rxdesc->stat;
1901 rxdesc->stat = 0xff;
1906 if (rxdesc == endp) {
1907 rxdesc = (sca_descriptor *)
1908 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1911 if (single && (stat == SCA_DESC_EOM))
1916 * Update the eda to the previous descriptor.
1918 rxdesc = (sca_descriptor *)sc->rxdesc;
1919 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
1921 SRC_PUT16(hc->sca_base,
1922 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
1923 (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
1927 * While there is packets available in the rx buffer, read them out
1928 * into mbufs and ship them off.
1931 sr_get_packets(struct sr_softc *sc)
1933 u_char rxstat; /* acquired status byte */
1935 int pkts; /* count of packets found */
1936 int rxndx; /* rcv buffer index */
1937 int tries; /* settling time counter */
1938 u_int len; /* length of pending packet */
1939 struct sr_hardc *hc; /* card-level information */
1940 sca_descriptor *rxdesc; /* descriptor in memory */
1942 struct ifnet *ifp; /* network intf ctl table */
1943 #endif /* NETGRAPH */
1944 struct mbuf *m = NULL; /* message buffer */
1947 kprintf("sr_get_packets(sc=%08x)\n", sc);
1952 ifp = &sc->ifsppp.pp_if;
1953 #endif /* NETGRAPH */
1955 pkts = 0; /* reset count of found packets */
1958 * for each complete packet in the receiving pool, process each
1961 while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */
1963 * I have seen situations where we got the interrupt but the
1964 * status value wasn't deposited. This code should allow
1965 * the status byte's value to settle...
1970 while ((rxstat == 0x00ff)
1972 sr_packet_avail(sc, &len, &rxstat);
1975 kprintf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
1983 #endif /* NETGRAPH */
1986 * OK, we've settled the incoming message status. We can now
1989 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1991 kprintf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
1992 sc->unit, rxstat, len);
1995 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1998 * eat (flush) packet if get mbuf fail!!
2000 sr_eat_packet(sc, 1);
2004 * construct control information for pass-off
2007 m->m_pkthdr.rcvif = ifp;
2009 m->m_pkthdr.rcvif = NULL;
2010 #endif /* NETGRAPH */
2011 m->m_pkthdr.len = m->m_len = len;
2013 MCLGET(m, MB_DONTWAIT);
2014 if ((m->m_flags & M_EXT) == 0) {
2016 * We couldn't get a big enough
2017 * message packet, so we'll send the
2018 * packet to /dev/null...
2021 sr_eat_packet(sc, 1);
2026 * OK, we've got a good message buffer. Now we can
2027 * copy the received message into it
2029 sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */
2039 kprintf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2041 bp[0], bp[1], bp[2],
2042 bp[4], bp[5], bp[6]);
2046 IFNET_STAT_INC(ifp, ipackets, 1);
2048 #else /* NETGRAPH */
2053 bp = mtod(m,u_char *);
2054 kprintf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2056 bp[0], bp[1], bp[2],
2057 bp[4], bp[5], bp[6]);
2058 kprintf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2059 bp[6], bp[7], bp[8],
2060 bp[9], bp[10], bp[11]);
2063 ng_queue_data(sc->hook, m, NULL);
2065 #endif /* NETGRAPH */
2067 * Update the eda to the previous descriptor.
2069 i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2070 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2072 rxdesc = (sca_descriptor *)sc->rxdesc;
2073 rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2074 rxdesc = &rxdesc[rxndx];
2076 SRC_PUT16(hc->sca_base,
2077 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2078 (u_short)((u_int)(rxdesc + hc->mem_pstart)
2082 int got_st3, got_cda, got_eda;
2085 while ((rxstat == 0xff) && --tries)
2086 sr_packet_avail(sc, &len, &rxstat);
2089 * It look like we get an interrupt early
2090 * sometimes and then the status is not
2093 if (tries && (tries != 5))
2097 * This chunk of code handles the error packets.
2098 * We'll log them for posterity...
2100 sr_eat_packet(sc, 1);
2103 IFNET_STAT_INC(ifp, ierrors, 1);
2106 #endif /* NETGRAPH */
2108 got_st3 = SRC_GET8(hc->sca_base,
2109 hc->sca->msci[sc->scachan].st3);
2110 got_cda = SRC_GET16(hc->sca_base,
2111 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2112 got_eda = SRC_GET16(hc->sca_base,
2113 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2116 kprintf("sr%d: Receive error chan %d, "
2117 "stat %02x, msci st3 %02x,"
2118 "rxhind %d, cda %04x, eda %04x.\n",
2119 sc->unit, sc->scachan, rxstat,
2120 got_st3, sc->rxhind, got_cda, got_eda);
2126 kprintf("sr%d: sr_get_packets() found %d packet(s)\n",
2132 * All DMA interrupts come here.
2134 * Each channel has two interrupts.
2135 * Interrupt A for errors and Interrupt B for normal stuff like end
2136 * of transmit or receive dmas.
2139 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2141 u_char dsr; /* contents of DMA Stat Reg */
2142 u_char dotxstart; /* enables for tranmit part */
2143 int mch; /* channel being processed */
2144 struct sr_softc *sc; /* channel's softc structure */
2145 sca_regs *sca = hc->sca;
2146 dmac_channel *dmac; /* dma structure of chip */
2149 kprintf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2152 mch = 0; /* assume chan0 on card */
2153 dotxstart = isr1; /* copy for xmitter starts */
2156 * Shortcut if there is no interrupts for dma channel 0 or 1.
2157 * Skip processing for channel 0 if no incoming hit
2159 if ((isr1 & 0x0F) == 0) {
2167 * Transmit channel - DMA Status Register Evaluation
2172 dmac = &sca->dmac[DMAC_TXCH(mch)];
2175 * get the DMA Status Register contents and write
2176 * back to reset interrupt...
2178 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2179 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2182 * Check for (& process) a Counter overflow
2184 if (dsr & SCA_DSR_COF) {
2186 IFNET_STAT_GET(&sc->ifsppp.pp_if, opackets,
2188 IFNET_STAT_INC(&sc->ifsppp.pp_if, oerrors, 1);
2190 opkts = sc->opackets;
2192 #endif /* NETGRAPH */
2193 kprintf("sr%d: TX DMA Counter overflow, "
2194 "txpacket no %lu.\n",
2198 * Check for (& process) a Buffer overflow
2200 if (dsr & SCA_DSR_BOF) {
2202 IFNET_STAT_GET(&sc->ifsppp.pp_if, opackets,
2204 IFNET_STAT_INC(&sc->ifsppp.pp_if, oerrors, 1);
2206 opkts = sc->opackets;
2208 #endif /* NETGRAPH */
2209 kprintf("sr%d: TX DMA Buffer overflow, "
2210 "txpacket no %lu, dsr %02x, "
2211 "cda %04x, eda %04x.\n",
2214 SRC_GET16(hc->sca_base, dmac->cda),
2215 SRC_GET16(hc->sca_base, dmac->eda));
2218 * Check for (& process) an End of Transfer (OK)
2220 if (dsr & SCA_DSR_EOT) {
2222 * This should be the most common case.
2224 * Clear the OACTIVE flag.
2226 * Call srstart to start a new transmit if
2227 * there is data to transmit.
2230 kprintf("sr%d: TX Completed OK\n", sc->unit);
2234 ifq_clr_oactive(&sc->ifsppp.pp_if.if_snd);
2235 sc->ifsppp.pp_if.if_timer = 0;
2237 /* XXX may need to mark tx inactive? */
2239 sc->out_dog = DOG_HOLDOFF;
2240 #endif /* NETGRAPH */
2242 if (sc->txb_inuse && --sc->txb_inuse)
2247 * Receive channel processing of DMA Status Register
2252 dmac = &sca->dmac[DMAC_RXCH(mch)];
2254 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2255 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2258 * End of frame processing (MSG OK?)
2260 if (dsr & SCA_DSR_EOM) {
2266 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets, tt);
2267 #else /* NETGRAPH */
2269 #endif /* NETGRAPH */
2276 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2278 #else /* NETGRAPH */
2280 #endif /* NETGRAPH */
2282 sca_descriptor *rxdesc;
2285 kprintf("SR: RXINTR isr1 %x, dsr %x, "
2286 "no data %d pkts, orxind %d.\n",
2287 dotxstart, dsr, tt, ind);
2288 kprintf("SR: rxdesc %x, rxstart %x, "
2289 "rxend %x, rxhind %d, "
2291 sc->rxdesc, sc->rxstart,
2292 sc->rxend, sc->rxhind,
2294 kprintf("SR: cda %x, eda %x.\n",
2295 SRC_GET16(hc->sca_base, dmac->cda),
2296 SRC_GET16(hc->sca_base, dmac->eda));
2298 rxdesc = (sca_descriptor *)
2300 (sc->rxdesc & hc->winmsk));
2301 rxdesc = &rxdesc[sc->rxhind];
2303 for (i = 0; i < 3; i++, rxdesc++)
2304 kprintf("SR: rxdesc->stat %x, "
2312 * Check for Counter overflow
2314 if (dsr & SCA_DSR_COF) {
2316 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2318 IFNET_STAT_INC(&sc->ifsppp.pp_if, ierrors, 1);
2319 #else /* NETGRAPH */
2320 ipkts = sc->ipackets;
2322 #endif /* NETGRAPH */
2323 kprintf("sr%d: RX DMA Counter overflow, "
2328 * Check for Buffer overflow
2330 if (dsr & SCA_DSR_BOF) {
2332 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2334 #else /* NETGRAPH */
2335 ipkts = sc->ipackets;
2336 #endif /* NETGRAPH */
2337 kprintf("sr%d: RX DMA Buffer overflow, "
2338 "rxpkts %lu, rxind %d, "
2339 "cda %x, eda %x, dsr %x.\n",
2342 SRC_GET16(hc->sca_base, dmac->cda),
2343 SRC_GET16(hc->sca_base, dmac->eda),
2347 * Make sure we eat as many as possible.
2348 * Then get the system running again.
2351 sr_eat_packet(sc, 0);
2353 IFNET_STAT_INC(&sc->ifsppp.pp_if, ierrors, 1);
2354 #else /* NETGRAPH */
2356 #endif /* NETGRAPH */
2358 SRC_PUT8(hc->sca_base,
2362 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2366 ipkts = sc->ipackets;
2367 #else /* NETGRAPH */
2368 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2370 #endif /* NETGRAPH */
2371 kprintf("sr%d: RX DMA Buffer overflow, "
2372 "rxpkts %lu, rxind %d, "
2373 "cda %x, eda %x, dsr %x. After\n",
2376 SRC_GET16(hc->sca_base, dmac->cda),
2377 SRC_GET16(hc->sca_base, dmac->eda),
2378 SRC_GET8(hc->sca_base, dmac->dsr));
2384 if (dsr & SCA_DSR_EOT) {
2388 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2390 IFNET_STAT_INC(&sc->ifsppp.pp_if, ierrors, 1);
2392 ipkts = sc->ipackets;
2394 #endif /* NETGRAPH */
2396 * If this happen, it means that we are
2397 * receiving faster than what the processor
2400 * XXX We should enable the dma again.
2402 kprintf("sr%d: RX End of xfer, rxpkts %lu.\n",
2406 isr1 >>= 4; /* process next half of ISR */
2407 mch++; /* and move to next channel */
2408 } while ((mch < NCHAN) && isr1); /* loop for each chn */
2411 * Now that we have done all the urgent things, see if we can fill
2412 * the transmit buffers.
2414 for (mch = 0; mch < NCHAN; mch++) {
2415 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2418 srstart(&sc->ifsppp.pp_if,
2419 ifq_get_subq_default(&sc->ifsppp.pp_if.if_snd));
2422 #endif /* NETGRAPH */
2424 dotxstart >>= 4;/* shift for next channel */
2430 * Perform timeout on an FR channel
2432 * Establish a periodic check of open N2 ports; If
2433 * a port is open/active, its DCD state is checked
2434 * and a loss of DCD is recognized (and eventually
2438 sr_modemck(void *arg)
2440 int card; /* card index in table */
2441 int cards; /* card list index */
2442 int mch; /* channel on card */
2443 u_char dcd_v; /* Data Carrier Detect */
2444 u_char got_st0; /* contents of ST0 */
2445 u_char got_st1; /* contents of ST1 */
2446 u_char got_st2; /* contents of ST2 */
2447 u_char got_st3; /* contents of ST3 */
2448 struct sr_hardc *hc; /* card's configuration */
2449 struct sr_hardc *Card[16];/* up to 16 cards in system */
2450 struct sr_softc *sc; /* channel's softc structure */
2451 struct ifnet *ifp; /* interface control table */
2452 msci_channel *msci; /* regs specific to channel */
2457 if (sr_opens == 0) { /* count of "up" channels */
2458 sr_watcher = 0; /* indicate no watcher */
2466 sr_watcher = 1; /* mark that we're online */
2469 * Now we'll need a list of cards to process. Since we can handle
2470 * both ISA and PCI cards (and I didn't think of making this logic
2471 * global YET) we'll generate a single table of card table
2476 for (card = 0; card < NSR; card++) {
2477 hc = &sr_hardc[card];
2493 * OK, we've got work we can do. Let's do it... (Please note that
2494 * this code _only_ deals w/ ISA cards)
2496 for (card = 0; card < cards; card++) {
2497 hc = Card[card];/* get card table */
2499 for (mch = 0; mch < hc->numports; mch++) {
2502 ifp = &sc->ifsppp.pp_if;
2505 * if this channel isn't "up", skip it
2507 if ((ifp->if_flags & IFF_UP) == 0)
2511 * OK, now we can go looking at this channel's
2512 * actual register contents...
2514 msci = &hc->sca->msci[sc->scachan];
2517 * OK, now we'll look into the actual status of this
2520 * I suck in more registers than strictly needed
2522 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2523 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2524 got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2525 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2528 * We want to see if the DCD signal is up (DCD is
2531 dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2534 kprintf("sr%d: DCD lost\n", sc->unit);
2539 * OK, now set up for the next modem signal checking pass...
2541 timeout(sr_modemck, NULL, hz);
2546 #else /* NETGRAPH */
2548 * If a port is open/active, it's DCD state is checked
2549 * and a loss of DCD is recognized (and eventually processed?).
2552 sr_modemck(struct sr_softc *sc )
2554 u_char got_st3; /* contents of ST3 */
2555 struct sr_hardc *hc = sc->hc; /* card's configuration */
2556 msci_channel *msci; /* regs specific to channel */
2560 if (sc->running == 0) {
2566 * OK, now we can go looking at this channel's register contents...
2568 msci = &hc->sca->msci[sc->scachan];
2569 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2572 * We want to see if the DCD signal is up (DCD is true if zero)
2574 sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2579 #endif /* NETGRAPH */
2581 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2583 kprintf("src%d: SRINTR: MSCI\n", hc->cunit);
2587 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2589 kprintf("src%d: SRINTR: TIMER\n", hc->cunit);
2593 /*****************************************
2594 * Device timeout/watchdog routine.
2595 * called once per second.
2596 * checks to see that if activity was expected, that it hapenned.
2597 * At present we only look to see if expected output was completed.
2600 ngsr_watchdog_frame(void * arg)
2602 struct sr_softc * sc = arg;
2607 if (sc->running == 0) {
2609 return; /* if we are not running let timeouts die */
2612 * calculate the apparent throughputs
2616 speed = sc->inbytes - sc->lastinbytes;
2617 sc->lastinbytes = sc->inbytes;
2618 if ( sc->inrate < speed )
2620 speed = sc->outbytes - sc->lastoutbytes;
2621 sc->lastoutbytes = sc->outbytes;
2622 if ( sc->outrate < speed )
2623 sc->outrate = speed;
2628 if ((sc->inlast > QUITE_A_WHILE)
2629 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2630 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2636 sc->inlast = sc->out_deficit = 0;
2639 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2640 if (sc->out_dog == 0) {
2641 log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2654 sc->inlast = sc->out_deficit = 0;
2659 sr_modemck(sc); /* update the DCD status */
2660 callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
2663 /***********************************************************************
2664 * This section contains the methods for the Netgraph interface
2665 ***********************************************************************/
2667 * It is not possible or allowable to create a node of this type.
2668 * If the hardware exists, it will already have created it.
2671 ngsr_constructor(node_p *nodep)
2677 * give our ok for a hook to be added...
2678 * If we are not running this should kick the device into life.
2679 * The hook's private info points to our stash of info about that
2683 ngsr_newhook(node_p node, hook_p hook, const char *name)
2685 struct sr_softc * sc = node->private;
2688 * check if it's our friend the debug hook
2690 if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2691 hook->private = NULL; /* paranoid */
2692 sc->debug_hook = hook;
2697 * Check for raw mode hook.
2699 if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2710 * incoming messages.
2711 * Just respond to the generic TEXT_STATUS message
2714 ngsr_rcvmsg(node_p node,
2715 struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2717 struct sr_softc * sc;
2721 switch (msg->header.typecookie) {
2725 case NGM_GENERIC_COOKIE:
2726 switch(msg->header.cmd) {
2727 case NGM_TEXT_STATUS: {
2730 int resplen = sizeof(struct ng_mesg) + 512;
2731 *resp = kmalloc(resplen, M_NETGRAPH,
2732 M_INTWAIT | M_ZERO);
2733 if (*resp == NULL) {
2737 arg = (*resp)->data;
2740 * Put in the throughput information.
2742 pos = ksprintf(arg, "%ld bytes in, %ld bytes out\n"
2743 "highest rate seen: %ld B/S in, %ld B/S out\n",
2744 sc->inbytes, sc->outbytes,
2745 sc->inrate, sc->outrate);
2746 pos += ksprintf(arg + pos,
2747 "%ld output errors\n",
2749 pos += ksprintf(arg + pos,
2750 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2758 (*resp)->header.version = NG_VERSION;
2759 (*resp)->header.arglen = strlen(arg) + 1;
2760 (*resp)->header.token = msg->header.token;
2761 (*resp)->header.typecookie = NG_SR_COOKIE;
2762 (*resp)->header.cmd = msg->header.cmd;
2763 strlcpy((*resp)->header.cmdstr, "status",
2776 kfree(msg, M_NETGRAPH);
2781 * get data from another node and transmit it to the correct channel
2784 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2787 struct sr_softc * sc = hook->node->private;
2788 struct ifqueue *xmitq_p;
2791 * data doesn't come in from just anywhere (e.g control hook)
2793 if ( hook->private == NULL) {
2799 * Now queue the data for when it can be sent
2801 if (meta && meta->priority > 0) {
2802 xmitq_p = (&sc->xmitq_hipri);
2804 xmitq_p = (&sc->xmitq);
2809 if (IF_QFULL(xmitq_p)) {
2817 IF_ENQUEUE(xmitq_p, m);
2826 * It was an error case.
2827 * check if we need to free the mbuf, and then return the error
2829 NG_FREE_DATA(m, meta);
2834 * do local shutdown processing..
2835 * this node will refuse to go away, unless the hardware says to..
2836 * don't unref the node, or remove our name. just clear our links up.
2839 ngsr_rmnode(node_p node)
2841 struct sr_softc * sc = node->private;
2845 node->flags &= ~NG_INVALID; /* bounce back to life */
2849 /* already linked */
2851 ngsr_connect(hook_p hook)
2853 /* be really amiable and just say "YUP that's OK by me! " */
2858 * notify on hook disconnection (destruction)
2860 * Invalidate the private data associated with this dlci.
2861 * For this type, removal of the last link resets tries to destroy the node.
2862 * As the device still exists, the shutdown method will not actually
2863 * destroy the node, but reset the device and leave it 'fresh' :)
2865 * The node removal code will remove all references except that owned by the
2869 ngsr_disconnect(hook_p hook)
2871 struct sr_softc * sc = hook->node->private;
2873 * If it's the data hook, then free resources etc.
2875 if (hook->private) {
2879 if (sc->datahooks == 0)
2884 sc->debug_hook = NULL;
2890 * called during bootup
2891 * or LKM loading to put this type into the list of known modules
2894 ngsr_init(void *ignored)
2896 if (ng_newtype(&typestruct))
2897 kprintf("ngsr install failed\n");
2900 #endif /* NETGRAPH */
2903 ********************************* END ************************************