2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
30 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
32 * These cards are based on SMC83c17x (EPIC) chip and one of the various
33 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
34 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
35 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
36 * supports fibre optics.
38 * Thanks are going to Steve Bauer and Jason Wright.
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
45 #include <sys/malloc.h>
46 #include <sys/kernel.h>
47 #include <sys/socket.h>
48 #include <sys/queue.h>
49 #include <sys/serialize.h>
52 #include <sys/thread2.h>
53 #include <sys/interrupt.h>
56 #include <net/ifq_var.h>
57 #include <net/if_arp.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
64 #include <net/vlan/if_vlan_var.h>
66 #include <vm/vm.h> /* for vtophys */
67 #include <vm/pmap.h> /* for vtophys */
69 #include <bus/pci/pcireg.h>
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcidevs.h>
73 #include <dev/netif/mii_layer/mii.h>
74 #include <dev/netif/mii_layer/miivar.h>
75 #include <dev/netif/mii_layer/miidevs.h>
76 #include <dev/netif/mii_layer/lxtphyreg.h>
78 #include "miibus_if.h"
80 #include <dev/netif/tx/if_txreg.h>
81 #include <dev/netif/tx/if_txvar.h>
83 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
84 static void epic_intr(void *);
85 static void epic_tx_underrun(epic_softc_t *);
86 static int epic_common_attach(epic_softc_t *);
87 static void epic_ifstart(struct ifnet *, struct ifaltq_subque *);
88 static void epic_ifwatchdog(struct ifnet *);
89 static void epic_stats_update(void *);
90 static int epic_init(epic_softc_t *);
91 static void epic_stop(epic_softc_t *);
92 static void epic_rx_done(epic_softc_t *);
93 static void epic_tx_done(epic_softc_t *);
94 static int epic_init_rings(epic_softc_t *);
95 static void epic_free_rings(epic_softc_t *);
96 static void epic_stop_activity(epic_softc_t *);
97 static int epic_queue_last_packet(epic_softc_t *);
98 static void epic_start_activity(epic_softc_t *);
99 static void epic_set_rx_mode(epic_softc_t *);
100 static void epic_set_tx_mode(epic_softc_t *);
101 static void epic_set_mc_table(epic_softc_t *);
102 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
103 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
104 static u_int16_t epic_input_eepromw(epic_softc_t *);
105 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
106 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
107 static u_int8_t epic_read_eepromreg(epic_softc_t *);
109 static int epic_read_phy_reg(epic_softc_t *, int, int);
110 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
112 static int epic_miibus_readreg(device_t, int, int);
113 static int epic_miibus_writereg(device_t, int, int, int);
114 static void epic_miibus_statchg(device_t);
115 static void epic_miibus_mediainit(device_t);
117 static int epic_ifmedia_upd(struct ifnet *);
118 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
120 static int epic_probe(device_t);
121 static int epic_attach(device_t);
122 static void epic_shutdown(device_t);
123 static int epic_detach(device_t);
125 static device_method_t epic_methods[] = {
126 /* Device interface */
127 DEVMETHOD(device_probe, epic_probe),
128 DEVMETHOD(device_attach, epic_attach),
129 DEVMETHOD(device_detach, epic_detach),
130 DEVMETHOD(device_shutdown, epic_shutdown),
133 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
134 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
135 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
136 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
141 static driver_t epic_driver = {
147 static devclass_t epic_devclass;
149 DECLARE_DUMMY_MODULE(if_tx);
150 MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
151 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, NULL, NULL);
152 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, NULL, NULL);
154 static struct epic_type epic_devs[] = {
155 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170,
156 "SMC EtherPower II 10/100" },
161 epic_probe(device_t dev)
166 vid = pci_get_vendor(dev);
167 did = pci_get_device(dev);
168 for (t = epic_devs; t->name != NULL; ++t) {
169 if (vid == t->ven_id && did == t->dev_id) {
170 device_set_desc(dev, t->name);
177 #if defined(EPIC_USEIOSPACE)
178 #define EPIC_RES SYS_RES_IOPORT
179 #define EPIC_RID PCIR_BAR(0)
181 #define EPIC_RES SYS_RES_MEMORY
182 #define EPIC_RID PCIR_BAR(1)
186 * Attach routine: map registers, allocate softc, rings and descriptors.
187 * Reset to known state.
190 epic_attach(device_t dev)
197 sc = device_get_softc(dev);
199 /* Preinitialize softc structure */
201 callout_init(&sc->tx_stat_timer);
203 /* Fill ifnet structure */
205 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
207 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
208 ifp->if_ioctl = epic_ifioctl;
209 ifp->if_start = epic_ifstart;
210 ifp->if_watchdog = epic_ifwatchdog;
211 ifp->if_init = (if_init_f_t*)epic_init;
213 ifp->if_baudrate = 10000000;
214 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
215 ifq_set_ready(&ifp->if_snd);
217 pci_enable_busmaster(dev);
220 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
222 if (sc->res == NULL) {
223 device_printf(dev, "couldn't map ports/memory\n");
228 sc->sc_st = rman_get_bustag(sc->res);
229 sc->sc_sh = rman_get_bushandle(sc->res);
231 /* Allocate interrupt */
233 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
234 RF_SHAREABLE | RF_ACTIVE);
236 if (sc->irq == NULL) {
237 device_printf(dev, "couldn't map interrupt\n");
242 /* Do OS independent part, including chip wakeup and reset */
243 error = epic_common_attach(sc);
249 /* Do ifmedia setup */
250 if (mii_phy_probe(dev, &sc->miibus,
251 epic_ifmedia_upd, epic_ifmedia_sts)) {
252 device_printf(dev, "ERROR! MII without any PHY!?\n");
257 /* board type and ... */
259 for(i=0x2c;i<0x32;i++) {
260 tmp = epic_read_eeprom(sc, i);
261 if (' ' == (u_int8_t)tmp) break;
262 kprintf("%c", (u_int8_t)tmp);
264 if (' ' == (u_int8_t)tmp) break;
265 kprintf("%c", (u_int8_t)tmp);
269 /* Attach to OS's managers */
270 ether_ifattach(ifp, sc->sc_macaddr, NULL);
271 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
273 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
274 epic_intr, sc, &sc->sc_ih,
278 device_printf(dev, "couldn't set up irq\n");
283 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq));
293 * Detach driver and free resources
296 epic_detach(device_t dev)
298 epic_softc_t *sc = device_get_softc(dev);
299 struct ifnet *ifp = &sc->arpcom.ac_if;
301 if (device_is_attached(dev)) {
302 lwkt_serialize_enter(ifp->if_serializer);
304 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
305 lwkt_serialize_exit(ifp->if_serializer);
311 device_delete_child(dev, sc->miibus);
312 bus_generic_detach(dev);
315 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
317 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
320 kfree(sc->tx_flist, M_DEVBUF);
322 kfree(sc->tx_desc, M_DEVBUF);
324 kfree(sc->rx_desc, M_DEVBUF);
333 * Stop all chip I/O so that the kernel's probe routines don't
334 * get confused by errant DMAs when rebooting.
337 epic_shutdown(device_t dev)
342 sc = device_get_softc(dev);
343 ifp = &sc->arpcom.ac_if;
344 lwkt_serialize_enter(ifp->if_serializer);
346 lwkt_serialize_exit(ifp->if_serializer);
350 * This is if_ioctl handler.
353 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
355 epic_softc_t *sc = ifp->if_softc;
356 struct mii_data *mii;
357 struct ifreq *ifr = (struct ifreq *) data;
362 if (ifp->if_mtu == ifr->ifr_mtu)
365 /* XXX Though the datasheet doesn't imply any
366 * limitations on RX and TX sizes beside max 64Kb
367 * DMA transfer, seems we can't send more then 1600
368 * data bytes per ethernet packet. (Transmitter hangs
369 * up if more data is sent)
371 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
372 ifp->if_mtu = ifr->ifr_mtu;
381 * If the interface is marked up and stopped, then start it.
382 * If it is marked down and running, then stop it.
384 if (ifp->if_flags & IFF_UP) {
385 if ((ifp->if_flags & IFF_RUNNING) == 0) {
390 if (ifp->if_flags & IFF_RUNNING) {
396 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
397 epic_stop_activity(sc);
398 epic_set_mc_table(sc);
399 epic_set_rx_mode(sc);
400 epic_start_activity(sc);
405 epic_set_mc_table(sc);
411 mii = device_get_softc(sc->miibus);
412 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
416 error = ether_ioctl(ifp, command, data);
423 * OS-independed part of attach process. allocate memory for descriptors
424 * and frag lists, wake up chip, read MAC address and PHY identyfier.
425 * Return -1 on failure.
428 epic_common_attach(epic_softc_t *sc)
433 sc->tx_flist = kmalloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
434 M_DEVBUF, M_WAITOK | M_ZERO);
435 sc->tx_desc = kmalloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
436 M_DEVBUF, M_WAITOK | M_ZERO);
437 sc->rx_desc = kmalloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
438 M_DEVBUF, M_WAITOK | M_ZERO);
440 /* Bring the chip out of low-power mode. */
441 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
444 /* Workaround for Application Note 7-15 */
445 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
447 /* Read mac address from EEPROM */
448 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
449 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
451 /* Set Non-Volatile Control Register from EEPROM */
452 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
455 sc->tx_threshold = TRANSMIT_THRESHOLD;
456 sc->txcon = TXCON_DEFAULT;
457 sc->miicfg = MIICFG_SMI_ENABLE;
458 sc->phyid = EPIC_UNKN_PHY;
462 sub_vid = pci_get_subvendor(sc->dev);
463 sc->cardid = pci_get_subdevice(sc->dev);
465 if (sub_vid != PCI_VENDOR_SMC)
466 device_printf(sc->dev, "unknown card vendor %04xh\n", sub_vid);
472 * This is if_start handler. It takes mbufs from if_snd queue
473 * and queue them for transmit, one by one, until TX ring become full
474 * or queue become empty.
477 epic_ifstart(struct ifnet *ifp, struct ifaltq_subque *ifsq)
479 epic_softc_t *sc = ifp->if_softc;
480 struct epic_tx_buffer *buf;
481 struct epic_tx_desc *desc;
482 struct epic_frag_list *flist;
487 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
489 while (sc->pending_txs < TX_RING_SIZE) {
490 buf = sc->tx_buffer + sc->cur_tx;
491 desc = sc->tx_desc + sc->cur_tx;
492 flist = sc->tx_flist + sc->cur_tx;
494 /* Get next packet to send */
495 m0 = ifq_dequeue(&ifp->if_snd, NULL);
497 /* If nothing to send, return */
501 /* Fill fragments list */
503 (NULL != m) && (i < EPIC_MAX_FRAGS);
504 m = m->m_next, i++) {
505 flist->frag[i].fraglen = m->m_len;
506 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
510 /* If packet was more than EPIC_MAX_FRAGS parts, */
511 /* recopy packet to new allocated mbuf cluster */
513 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
516 IFNET_STAT_INC(ifp, oerrors, 1);
520 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
521 flist->frag[0].fraglen =
522 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
523 m->m_pkthdr.rcvif = ifp;
526 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
533 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
534 desc->control = 0x01;
536 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
537 desc->status = 0x8000;
538 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
540 /* Set watchdog timer */
546 ifq_set_oactive(&ifp->if_snd);
553 * Synopsis: Finish all received frames.
556 epic_rx_done(epic_softc_t *sc)
559 struct ifnet *ifp = &sc->sc_if;
560 struct epic_rx_buffer *buf;
561 struct epic_rx_desc *desc;
564 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
565 buf = sc->rx_buffer + sc->cur_rx;
566 desc = sc->rx_desc + sc->cur_rx;
568 /* Switch to next descriptor */
569 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
572 * Check for RX errors. This should only happen if
573 * SAVE_ERRORED_PACKETS is set. RX errors generate
574 * RXE interrupt usually.
576 if ((desc->status & 1) == 0) {
577 IFNET_STAT_INC(&sc->sc_if, ierrors, 1);
578 desc->status = 0x8000;
582 /* Save packet length and mbuf contained packet */
583 len = desc->rxlength - ETHER_CRC_LEN;
586 /* Try to get mbuf cluster */
587 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
588 if (NULL == buf->mbuf) {
590 desc->status = 0x8000;
591 IFNET_STAT_INC(ifp, ierrors, 1);
595 /* Point to new mbuf, and give descriptor to chip */
596 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
597 desc->status = 0x8000;
599 /* First mbuf in packet holds the ethernet and packet headers */
600 m->m_pkthdr.rcvif = ifp;
601 m->m_pkthdr.len = m->m_len = len;
603 /* Give mbuf to OS */
604 ifp->if_input(ifp, m);
606 /* Successfuly received frame */
607 IFNET_STAT_INC(ifp, ipackets, 1);
614 * Synopsis: Do last phase of transmission. I.e. if desc is
615 * transmitted, decrease pending_txs counter, free mbuf contained
616 * packet, switch to next descriptor and repeat until no packets
617 * are pending or descriptor is not transmitted yet.
620 epic_tx_done(epic_softc_t *sc)
622 struct epic_tx_buffer *buf;
623 struct epic_tx_desc *desc;
626 while (sc->pending_txs > 0) {
627 buf = sc->tx_buffer + sc->dirty_tx;
628 desc = sc->tx_desc + sc->dirty_tx;
629 status = desc->status;
631 /* If packet is not transmitted, thou followed */
632 /* packets are not transmitted too */
633 if (status & 0x8000) break;
635 /* Packet is transmitted. Switch to next and */
638 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
642 /* Check for errors and collisions */
643 if (status & 0x0001) IFNET_STAT_INC(&sc->sc_if, opackets, 1);
644 else IFNET_STAT_INC(&sc->sc_if, oerrors, 1);
645 IFNET_STAT_INC(&sc->sc_if, collisions, (status >> 8) & 0x1F);
646 #if defined(EPIC_DIAG)
647 if ((status & 0x1001) == 0x1001) {
648 if_printf(&sc->sc_if,
649 "Tx ERROR: excessive coll. number\n");
654 if (sc->pending_txs < TX_RING_SIZE)
655 ifq_clr_oactive(&sc->sc_if.if_snd);
664 epic_softc_t * sc = (epic_softc_t *) arg;
667 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
668 CSR_WRITE_4(sc, INTSTAT, status);
670 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
672 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
673 #if defined(EPIC_DIAG)
674 if (status & INTSTAT_OVW)
675 if_printf(&sc->sc_if, "RX buffer overflow\n");
676 if (status & INTSTAT_RQE)
677 if_printf(&sc->sc_if, "RX FIFO overflow\n");
679 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
680 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
681 IFNET_STAT_INC(&sc->sc_if, ierrors, 1);
685 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
687 if (!ifq_is_empty(&sc->sc_if.if_snd))
688 if_devstart(&sc->sc_if);
691 /* Check for rare errors */
692 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
693 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
694 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
695 INTSTAT_APE|INTSTAT_DPE)) {
696 if_printf(&sc->sc_if, "PCI fatal errors occurred: %s%s%s%s\n",
697 (status&INTSTAT_PMA)?"PMA ":"",
698 (status&INTSTAT_PTA)?"PTA ":"",
699 (status&INTSTAT_APE)?"APE ":"",
700 (status&INTSTAT_DPE)?"DPE":""
709 if (status & INTSTAT_RXE) {
710 #if defined(EPIC_DIAG)
711 if_printf(sc->sc_if, "CRC/Alignment error\n");
713 IFNET_STAT_INC(&sc->sc_if, ierrors, 1);
716 if (status & INTSTAT_TXU) {
717 epic_tx_underrun(sc);
718 IFNET_STAT_INC(&sc->sc_if, oerrors, 1);
723 /* If no packets are pending, then no timeouts */
724 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
730 * Handle the TX underrun error: increase the TX threshold
731 * and restart the transmitter.
734 epic_tx_underrun(epic_softc_t *sc)
736 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
737 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
738 #if defined(EPIC_DIAG)
739 if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n");
742 sc->tx_threshold += 0x40;
743 #if defined(EPIC_DIAG)
744 if_printf(&sc->sc_if, "Tx UNDERRUN: "
745 "TX threshold increased to %d\n", sc->tx_threshold);
749 /* We must set TXUGO to reset the stuck transmitter */
750 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
752 /* Update the TX threshold */
753 epic_stop_activity(sc);
754 epic_set_tx_mode(sc);
755 epic_start_activity(sc);
761 * Synopsis: This one is called if packets wasn't transmitted
762 * during timeout. Try to deallocate transmitted packets, and
763 * if success continue to work.
766 epic_ifwatchdog(struct ifnet *ifp)
768 epic_softc_t *sc = ifp->if_softc;
770 if_printf(ifp, "device timeout %d packets\n", sc->pending_txs);
772 /* Try to finish queued packets */
775 /* If not successful */
776 if (sc->pending_txs > 0) {
778 IFNET_STAT_INC(ifp, oerrors, sc->pending_txs);
780 /* Reinitialize board */
781 if_printf(ifp, "reinitialization\n");
786 if_printf(ifp, "seems we can continue normally\n");
789 if (!ifq_is_empty(&ifp->if_snd))
794 * Despite the name of this function, it doesn't update statistics, it only
795 * helps in autonegotiation process.
798 epic_stats_update(void *xsc)
800 epic_softc_t *sc = xsc;
801 struct ifnet *ifp = &sc->sc_if;
802 struct mii_data * mii;
804 lwkt_serialize_enter(ifp->if_serializer);
806 mii = device_get_softc(sc->miibus);
809 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
811 lwkt_serialize_exit(ifp->if_serializer);
818 epic_ifmedia_upd(struct ifnet *ifp)
821 struct mii_data *mii;
823 struct mii_softc *miisc;
827 mii = device_get_softc(sc->miibus);
828 ifm = &mii->mii_media;
829 media = ifm->ifm_cur->ifm_media;
831 /* Do not do anything if interface is not up */
832 if ((ifp->if_flags & IFF_UP) == 0)
836 * Lookup current selected PHY
838 if (IFM_INST(media) == sc->serinst) {
839 sc->phyid = EPIC_SERIAL;
842 /* If we're not selecting serial interface, select MII mode */
843 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
844 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
846 /* Default to unknown PHY */
847 sc->phyid = EPIC_UNKN_PHY;
849 /* Lookup selected PHY */
850 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
851 miisc = LIST_NEXT(miisc, mii_list)) {
852 if (IFM_INST(media) == miisc->mii_inst) {
858 /* Identify selected PHY */
860 int id1, id2, model, oui;
862 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
863 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
865 oui = MII_OUI(id1, id2);
866 model = MII_MODEL(id2);
868 case MII_OUI_QUALSEMI:
869 if (model == MII_MODEL_QUALSEMI_QS6612)
870 sc->phyid = EPIC_QS6612_PHY;
872 case MII_OUI_xxALTIMA:
873 if (model == MII_MODEL_xxALTIMA_AC101)
874 sc->phyid = EPIC_AC101_PHY;
876 case MII_OUI_xxLEVEL1:
877 if (model == MII_MODEL_xxLEVEL1_LXT970)
878 sc->phyid = EPIC_LXT970_PHY;
885 * Do PHY specific card setup
888 /* Call this, to isolate all not selected PHYs and
893 /* Do our own setup */
895 case EPIC_QS6612_PHY:
898 /* We have to powerup fiber tranceivers */
899 if (IFM_SUBTYPE(media) == IFM_100_FX)
900 sc->miicfg |= MIICFG_694_ENABLE;
902 sc->miicfg &= ~MIICFG_694_ENABLE;
903 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
906 case EPIC_LXT970_PHY:
907 /* We have to powerup fiber tranceivers */
908 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
909 if (IFM_SUBTYPE(media) == IFM_100_FX)
910 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
912 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
913 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
917 /* Select serial PHY, (10base2/BNC usually) */
918 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
919 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
921 /* There is no driver to fill this */
922 mii->mii_media_active = media;
923 mii->mii_media_status = 0;
925 /* We need to call this manualy as i wasn't called
928 epic_miibus_statchg(sc->dev);
932 if_printf(ifp, "ERROR! Unknown PHY selected\n");
940 * Report current media status.
943 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
946 struct mii_data *mii;
949 mii = device_get_softc(sc->miibus);
951 /* Nothing should be selected if interface is down */
952 if ((ifp->if_flags & IFF_UP) == 0) {
953 ifmr->ifm_active = IFM_NONE;
954 ifmr->ifm_status = 0;
959 /* Call underlying pollstat, if not serial PHY */
960 if (sc->phyid != EPIC_SERIAL)
963 /* Simply copy media info */
964 ifmr->ifm_active = mii->mii_media_active;
965 ifmr->ifm_status = mii->mii_media_status;
971 * Callback routine, called on media change.
974 epic_miibus_statchg(device_t dev)
977 struct mii_data *mii;
980 sc = device_get_softc(dev);
981 mii = device_get_softc(sc->miibus);
982 media = mii->mii_media_active;
984 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
986 /* If we are in full-duplex mode or loopback operation,
987 * we need to decouple receiver and transmitter.
989 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
990 sc->txcon |= TXCON_FULL_DUPLEX;
992 /* On some cards we need manualy set fullduplex led */
993 if (sc->cardid == SMC9432FTX ||
994 sc->cardid == SMC9432FTX_SC) {
995 if (IFM_OPTIONS(media) & IFM_FDX)
996 sc->miicfg |= MIICFG_694_ENABLE;
998 sc->miicfg &= ~MIICFG_694_ENABLE;
1000 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1003 /* Update baudrate */
1004 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1005 IFM_SUBTYPE(media) == IFM_100_FX)
1006 sc->sc_if.if_baudrate = 100000000;
1008 sc->sc_if.if_baudrate = 10000000;
1010 epic_stop_activity(sc);
1011 epic_set_tx_mode(sc);
1012 epic_start_activity(sc);
1018 epic_miibus_mediainit(device_t dev)
1021 struct mii_data *mii;
1022 struct ifmedia *ifm;
1025 sc = device_get_softc(dev);
1026 mii = device_get_softc(sc->miibus);
1027 ifm = &mii->mii_media;
1029 /* Add Serial Media Interface if present, this applies to
1032 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1033 /* Store its instance */
1034 sc->serinst = mii->mii_instance++;
1036 /* Add as 10base2/BNC media */
1037 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1038 ifmedia_add(ifm, media, 0, NULL);
1040 /* Report to user */
1041 if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n");
1048 * Reset chip, allocate rings, and update media.
1051 epic_init(epic_softc_t *sc)
1053 struct ifnet *ifp = &sc->sc_if;
1056 /* If interface is already running, then we need not do anything */
1057 if (ifp->if_flags & IFF_RUNNING) {
1061 /* Soft reset the chip (we have to power up card before) */
1062 CSR_WRITE_4(sc, GENCTL, 0);
1063 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1066 * Reset takes 15 pci ticks which depends on PCI bus speed.
1067 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1072 CSR_WRITE_4(sc, GENCTL, 0);
1074 /* Workaround for Application Note 7-15 */
1075 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1077 /* Initialize rings */
1078 if (epic_init_rings(sc)) {
1079 if_printf(ifp, "failed to init rings\n");
1083 /* Give rings to EPIC */
1084 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1085 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1087 /* Put node address to EPIC */
1088 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1089 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1090 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1092 /* Set tx mode, includeing transmit threshold */
1093 epic_set_tx_mode(sc);
1095 /* Compute and set RXCON. */
1096 epic_set_rx_mode(sc);
1098 /* Set multicast table */
1099 epic_set_mc_table(sc);
1101 /* Enable interrupts by setting the interrupt mask. */
1102 CSR_WRITE_4(sc, INTMASK,
1103 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1104 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1107 /* Acknowledge all pending interrupts */
1108 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1110 /* Enable interrupts, set for PCI read multiple and etc */
1111 CSR_WRITE_4(sc, GENCTL,
1112 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1113 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1115 /* Mark interface running ... */
1116 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1117 else ifp->if_flags &= ~IFF_RUNNING;
1120 ifq_clr_oactive(&ifp->if_snd);
1122 /* Start Rx process */
1123 epic_start_activity(sc);
1125 /* Set appropriate media */
1126 epic_ifmedia_upd(ifp);
1128 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
1134 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1138 epic_set_rx_mode(epic_softc_t *sc)
1140 u_int32_t flags = sc->sc_if.if_flags;
1141 u_int32_t rxcon = RXCON_DEFAULT;
1143 #if defined(EPIC_EARLY_RX)
1144 rxcon |= RXCON_EARLY_RX;
1147 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1149 CSR_WRITE_4(sc, RXCON, rxcon);
1155 * Synopsis: Set transmit control register. Chip must be in idle state to
1159 epic_set_tx_mode(epic_softc_t *sc)
1161 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1162 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1164 CSR_WRITE_4(sc, TXCON, sc->txcon);
1168 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1169 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1170 * individual frames, multicast filter must be manually programmed)
1172 * Note: EPIC must be in idle state.
1175 epic_set_mc_table(epic_softc_t *sc)
1177 struct ifnet *ifp = &sc->sc_if;
1178 struct ifmultiaddr *ifma;
1179 u_int16_t filter[4];
1182 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1183 CSR_WRITE_4(sc, MC0, 0xFFFF);
1184 CSR_WRITE_4(sc, MC1, 0xFFFF);
1185 CSR_WRITE_4(sc, MC2, 0xFFFF);
1186 CSR_WRITE_4(sc, MC3, 0xFFFF);
1196 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1197 if (ifma->ifma_addr->sa_family != AF_LINK)
1199 h = (ether_crc32_be(
1200 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1201 ETHER_ADDR_LEN) >> 26) & 0x3f;
1202 filter[h >> 4] |= 1 << (h & 0xF);
1205 CSR_WRITE_4(sc, MC0, filter[0]);
1206 CSR_WRITE_4(sc, MC1, filter[1]);
1207 CSR_WRITE_4(sc, MC2, filter[2]);
1208 CSR_WRITE_4(sc, MC3, filter[3]);
1214 * Synopsis: Start receive process and transmit one, if they need.
1217 epic_start_activity(epic_softc_t *sc)
1219 /* Start rx process */
1220 CSR_WRITE_4(sc, COMMAND,
1221 COMMAND_RXQUEUED | COMMAND_START_RX |
1222 (sc->pending_txs?COMMAND_TXQUEUED:0));
1226 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1227 * packet needs to be queued to stop Tx DMA.
1230 epic_stop_activity(epic_softc_t *sc)
1234 /* Stop Tx and Rx DMA */
1235 CSR_WRITE_4(sc, COMMAND,
1236 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1238 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1239 for (i=0; i<0x1000; i++) {
1240 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1241 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1246 /* Catch all finished packets */
1250 status = CSR_READ_4(sc, INTSTAT);
1252 if ((status & INTSTAT_RXIDLE) == 0)
1253 if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n");
1255 if ((status & INTSTAT_TXIDLE) == 0)
1256 if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n");
1259 * May need to queue one more packet if TQE, this is rare
1260 * but existing case.
1262 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1263 epic_queue_last_packet(sc);
1268 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1269 * a packet from current descriptor will be copied to internal RAM. We
1270 * compose a dummy packet here and queue it for transmission.
1272 * XXX the packet will then be actually sent over network...
1275 epic_queue_last_packet(epic_softc_t *sc)
1277 struct epic_tx_desc *desc;
1278 struct epic_frag_list *flist;
1279 struct epic_tx_buffer *buf;
1283 if_printf(&sc->sc_if, "queue last packet\n");
1285 desc = sc->tx_desc + sc->cur_tx;
1286 flist = sc->tx_flist + sc->cur_tx;
1287 buf = sc->tx_buffer + sc->cur_tx;
1289 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1292 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
1297 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1298 flist->frag[0].fraglen = m0->m_len;
1299 m0->m_pkthdr.len = m0->m_len;
1300 m0->m_pkthdr.rcvif = &sc->sc_if;
1301 bzero(mtod(m0,caddr_t), m0->m_len);
1303 /* Fill fragments list */
1304 flist->frag[0].fraglen = m0->m_len;
1305 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1306 flist->numfrags = 1;
1308 /* Fill in descriptor */
1311 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1312 desc->control = 0x01;
1313 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1314 desc->status = 0x8000;
1316 /* Launch transmition */
1317 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1319 /* Wait Tx DMA to stop (for how long??? XXX) */
1320 for (i=0; i<1000; i++) {
1321 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1326 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1327 if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n");
1335 * Synopsis: Shut down board and deallocates rings.
1338 epic_stop(epic_softc_t *sc)
1340 sc->sc_if.if_timer = 0;
1342 callout_stop(&sc->tx_stat_timer);
1344 /* Disable interrupts */
1345 CSR_WRITE_4(sc, INTMASK, 0);
1346 CSR_WRITE_4(sc, GENCTL, 0);
1348 /* Try to stop Rx and TX processes */
1349 epic_stop_activity(sc);
1352 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1355 /* Make chip go to bed */
1356 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1358 /* Free memory allocated for rings */
1359 epic_free_rings(sc);
1361 /* Mark as stoped */
1362 sc->sc_if.if_flags &= ~IFF_RUNNING;
1366 * Synopsis: This function should free all memory allocated for rings.
1369 epic_free_rings(epic_softc_t *sc)
1373 for (i=0; i<RX_RING_SIZE; i++) {
1374 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1375 struct epic_rx_desc *desc = sc->rx_desc + i;
1378 desc->buflength = 0;
1381 if (buf->mbuf) m_freem(buf->mbuf);
1385 for (i=0; i<TX_RING_SIZE; i++) {
1386 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1387 struct epic_tx_desc *desc = sc->tx_desc + i;
1390 desc->buflength = 0;
1393 if (buf->mbuf) m_freem(buf->mbuf);
1399 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1400 * Point Tx descs to fragment lists. Check that all descs and fraglists
1401 * are bounded and aligned properly.
1404 epic_init_rings(epic_softc_t *sc)
1408 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1410 for (i = 0; i < RX_RING_SIZE; i++) {
1411 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1412 struct epic_rx_desc *desc = sc->rx_desc + i;
1414 desc->status = 0; /* Owned by driver */
1415 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1417 if ((desc->next & 3) ||
1418 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1419 epic_free_rings(sc);
1423 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1424 if (NULL == buf->mbuf) {
1425 epic_free_rings(sc);
1428 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1430 desc->buflength = MCLBYTES; /* Max RX buffer length */
1431 desc->status = 0x8000; /* Set owner bit to NIC */
1434 for (i = 0; i < TX_RING_SIZE; i++) {
1435 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1436 struct epic_tx_desc *desc = sc->tx_desc + i;
1439 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1441 if ((desc->next & 3) ||
1442 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1443 epic_free_rings(sc);
1448 desc->bufaddr = vtophys(sc->tx_flist + i);
1450 if ((desc->bufaddr & 3) ||
1451 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1452 epic_free_rings(sc);
1461 * EEPROM operation functions
1464 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val)
1468 CSR_WRITE_1(sc, EECTL, val);
1470 for (i=0; i<0xFF; i++)
1471 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1477 epic_read_eepromreg(epic_softc_t *sc)
1479 return CSR_READ_1(sc, EECTL);
1483 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val)
1485 epic_write_eepromreg(sc, val);
1486 epic_write_eepromreg(sc, (val | 0x4));
1487 epic_write_eepromreg(sc, val);
1489 return epic_read_eepromreg(sc);
1493 epic_output_eepromw(epic_softc_t *sc, u_int16_t val)
1497 for (i = 0xF; i >= 0; i--) {
1499 epic_eeprom_clock(sc, 0x0B);
1501 epic_eeprom_clock(sc, 0x03);
1506 epic_input_eepromw(epic_softc_t *sc)
1508 u_int16_t retval = 0;
1511 for (i = 0xF; i >= 0; i--) {
1512 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1520 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc)
1525 epic_write_eepromreg(sc, 3);
1527 if (epic_read_eepromreg(sc) & 0x40)
1528 read_cmd = (loc & 0x3F) | 0x180;
1530 read_cmd = (loc & 0xFF) | 0x600;
1532 epic_output_eepromw(sc, read_cmd);
1534 dataval = epic_input_eepromw(sc);
1536 epic_write_eepromreg(sc, 1);
1542 * Here goes MII read/write routines
1545 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)
1549 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1551 for (i = 0; i < 0x100; i++) {
1552 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1556 return (CSR_READ_4(sc, MIIDATA));
1560 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)
1564 CSR_WRITE_4(sc, MIIDATA, val);
1565 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1567 for(i=0;i<0x100;i++) {
1568 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1576 epic_miibus_readreg(device_t dev, int phy, int reg)
1580 sc = device_get_softc(dev);
1582 return (PHY_READ_2(sc, phy, reg));
1586 epic_miibus_writereg(device_t dev, int phy, int reg, int data)
1590 sc = device_get_softc(dev);
1592 PHY_WRITE_2(sc, phy, reg, data);