4 * Copyright (c) Comtrol Corporation <support@comtrol.com>
7 * Redistribution and use in source and binary forms, with or without
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16 * must display the following acknowledgement:
17 * This product includes software developed by Comtrol Corporation.
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34 * $FreeBSD: src/sys/dev/rp/rp.c,v 1.45.2.2 2002/11/07 22:26:59 tegge Exp $
38 * rp.c - for RocketPort FreeBSD
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/fcntl.h>
44 #include <sys/malloc.h>
48 #include <sys/dkstat.h>
50 #include <sys/kernel.h>
53 #include <sys/thread2.h>
58 static const char RocketPortVersion[] = "3.02";
60 static Byte_t RData[RDATASIZE] =
62 0x00, 0x09, 0xf6, 0x82,
63 0x02, 0x09, 0x86, 0xfb,
64 0x04, 0x09, 0x00, 0x0a,
65 0x06, 0x09, 0x01, 0x0a,
66 0x08, 0x09, 0x8a, 0x13,
67 0x0a, 0x09, 0xc5, 0x11,
68 0x0c, 0x09, 0x86, 0x85,
69 0x0e, 0x09, 0x20, 0x0a,
70 0x10, 0x09, 0x21, 0x0a,
71 0x12, 0x09, 0x41, 0xff,
72 0x14, 0x09, 0x82, 0x00,
73 0x16, 0x09, 0x82, 0x7b,
74 0x18, 0x09, 0x8a, 0x7d,
75 0x1a, 0x09, 0x88, 0x81,
76 0x1c, 0x09, 0x86, 0x7a,
77 0x1e, 0x09, 0x84, 0x81,
78 0x20, 0x09, 0x82, 0x7c,
79 0x22, 0x09, 0x0a, 0x0a
82 static Byte_t RRegData[RREGDATASIZE]=
84 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
85 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
86 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
87 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
88 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
89 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
90 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
91 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
92 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
93 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
94 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
95 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
96 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
99 Byte_t rp_sBitMapClrTbl[8] =
101 0xfe,0xfd,0xfb,0xf7,0xef,0xdf,0xbf,0x7f
104 Byte_t rp_sBitMapSetTbl[8] =
106 0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80
109 /***************************************************************************
110 Function: sReadAiopID
111 Purpose: Read the AIOP idenfication number directly from an AIOP.
112 Call: sReadAiopID(CtlP, aiop)
113 CONTROLLER_T *CtlP; Ptr to controller structure
115 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
116 is replace by an identifying number.
117 Flag AIOPID_NULL if no valid AIOP is found
118 Warnings: No context switches are allowed while executing this function.
121 int sReadAiopID(CONTROLLER_T *CtlP, int aiop)
123 Byte_t AiopID; /* ID byte from AIOP */
126 rp_writeaiop1(CtlP, aiop, _CMD_REG, RESET_ALL); /* reset AIOP */
127 rp_writeaiop1(CtlP, aiop, _CMD_REG, 0x0);
128 AiopID = rp_readaiop1(CtlP, aiop, _CHN_STAT0) & 0x07;
132 else /* AIOP does not exist */
136 /***************************************************************************
137 Function: sReadAiopNumChan
138 Purpose: Read the number of channels available in an AIOP directly from
140 Call: sReadAiopNumChan(CtlP, aiop)
141 CONTROLLER_T *CtlP; Ptr to controller structure
143 Return: int: The number of channels available
144 Comments: The number of channels is determined by write/reads from identical
145 offsets within the SRAM address spaces for channels 0 and 4.
146 If the channel 4 space is mirrored to channel 0 it is a 4 channel
147 AIOP, otherwise it is an 8 channel.
148 Warnings: No context switches are allowed while executing this function.
150 int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop)
155 rp_writeaiop4(CtlP, aiop, _INDX_ADDR,0x12340000L); /* write to chan 0 SRAM */
156 rp_writeaiop2(CtlP, aiop, _INDX_ADDR,0); /* read from SRAM, chan 0 */
157 x = rp_readaiop2(CtlP, aiop, _INDX_DATA);
158 rp_writeaiop2(CtlP, aiop, _INDX_ADDR,0x4000); /* read from SRAM, chan 4 */
159 y = rp_readaiop2(CtlP, aiop, _INDX_DATA);
161 if(x != y) /* if different must be 8 chan */
167 /***************************************************************************
169 Purpose: Initialization of a channel and channel structure
170 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
171 CONTROLLER_T *CtlP; Ptr to controller structure
172 CHANNEL_T *ChP; Ptr to channel structure
173 int AiopNum; AIOP number within controller
174 int ChanNum; Channel number within AIOP
175 Return: int: TRUE if initialization succeeded, FALSE if it fails because channel
176 number exceeds number of channels available in AIOP.
177 Comments: This function must be called before a channel can be used.
178 Warnings: No range checking on any of the parameters is done.
180 No context switches are allowed while executing this function.
182 int sInitChan( CONTROLLER_T *CtlP,
191 if(ChanNum >= CtlP->AiopNumChan[AiopNum])
192 return(FALSE); /* exceeds num chans in AIOP */
195 /* Channel, AIOP, and controller identifiers */
197 ChP->ChanID = CtlP->AiopID[AiopNum];
198 ChP->AiopNum = AiopNum;
199 ChP->ChanNum = ChanNum;
201 /* Initialize the channel from the RData array */
202 for(i=0; i < RDATASIZE; i+=4)
205 R[1] = RData[i+1] + 0x10 * ChanNum;
208 rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)&R[0]));
212 for(i=0; i < RREGDATASIZE; i+=4)
214 ChR[i] = RRegData[i];
215 ChR[i+1] = RRegData[i+1] + 0x10 * ChanNum;
216 ChR[i+2] = RRegData[i+2];
217 ChR[i+3] = RRegData[i+3];
220 /* Indexed registers */
221 ChOff = (Word_t)ChanNum * 0x1000;
223 ChP->BaudDiv[0] = (Byte_t)(ChOff + _BAUD);
224 ChP->BaudDiv[1] = (Byte_t)((ChOff + _BAUD) >> 8);
225 ChP->BaudDiv[2] = (Byte_t)BRD9600;
226 ChP->BaudDiv[3] = (Byte_t)(BRD9600 >> 8);
227 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->BaudDiv[0]);
229 ChP->TxControl[0] = (Byte_t)(ChOff + _TX_CTRL);
230 ChP->TxControl[1] = (Byte_t)((ChOff + _TX_CTRL) >> 8);
231 ChP->TxControl[2] = 0;
232 ChP->TxControl[3] = 0;
233 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
235 ChP->RxControl[0] = (Byte_t)(ChOff + _RX_CTRL);
236 ChP->RxControl[1] = (Byte_t)((ChOff + _RX_CTRL) >> 8);
237 ChP->RxControl[2] = 0;
238 ChP->RxControl[3] = 0;
239 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
241 ChP->TxEnables[0] = (Byte_t)(ChOff + _TX_ENBLS);
242 ChP->TxEnables[1] = (Byte_t)((ChOff + _TX_ENBLS) >> 8);
243 ChP->TxEnables[2] = 0;
244 ChP->TxEnables[3] = 0;
245 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxEnables[0]);
247 ChP->TxCompare[0] = (Byte_t)(ChOff + _TXCMP1);
248 ChP->TxCompare[1] = (Byte_t)((ChOff + _TXCMP1) >> 8);
249 ChP->TxCompare[2] = 0;
250 ChP->TxCompare[3] = 0;
251 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxCompare[0]);
253 ChP->TxReplace1[0] = (Byte_t)(ChOff + _TXREP1B1);
254 ChP->TxReplace1[1] = (Byte_t)((ChOff + _TXREP1B1) >> 8);
255 ChP->TxReplace1[2] = 0;
256 ChP->TxReplace1[3] = 0;
257 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxReplace1[0]);
259 ChP->TxReplace2[0] = (Byte_t)(ChOff + _TXREP2);
260 ChP->TxReplace2[1] = (Byte_t)((ChOff + _TXREP2) >> 8);
261 ChP->TxReplace2[2] = 0;
262 ChP->TxReplace2[3] = 0;
263 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxReplace2[0]);
265 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
266 ChP->TxFIFO = ChOff + _TX_FIFO;
268 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
269 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum); /* remove reset Tx FIFO count */
270 rp_writech2(ChP,_INDX_ADDR,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
271 rp_writech2(ChP,_INDX_DATA,0);
272 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
273 ChP->RxFIFO = ChOff + _RX_FIFO;
275 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
276 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum); /* remove reset Rx FIFO count */
277 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs); /* clear Rx out ptr */
278 rp_writech2(ChP,_INDX_DATA,0);
279 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
280 rp_writech2(ChP,_INDX_DATA,0);
281 ChP->TxPrioCnt = ChOff + _TXP_CNT;
282 rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt);
283 rp_writech1(ChP,_INDX_DATA,0);
284 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
285 rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioPtr);
286 rp_writech1(ChP,_INDX_DATA,0);
287 ChP->TxPrioBuf = ChOff + _TXP_BUF;
288 sEnRxProcessor(ChP); /* start the Rx processor */
294 /***************************************************************************
295 Function: sStopRxProcessor
296 Purpose: Stop the receive processor from processing a channel.
297 Call: sStopRxProcessor(ChP)
298 CHANNEL_T *ChP; Ptr to channel structure
300 Comments: The receive processor can be started again with sStartRxProcessor().
301 This function causes the receive processor to skip over the
302 stopped channel. It does not stop it from processing other channels.
304 Warnings: No context switches are allowed while executing this function.
306 Do not leave the receive processor stopped for more than one
309 After calling this function a delay of 4 uS is required to ensure
310 that the receive processor is no longer processing this channel.
312 void sStopRxProcessor(CHANNEL_T *ChP)
321 rp_writech4(ChP, _INDX_ADDR,*(DWord_t *)&R[0]);
325 /***************************************************************************
326 Function: sFlushRxFIFO
327 Purpose: Flush the Rx FIFO
328 Call: sFlushRxFIFO(ChP)
329 CHANNEL_T *ChP; Ptr to channel structure
331 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
332 while it is being flushed the receive processor is stopped
333 and the transmitter is disabled. After these operations a
334 4 uS delay is done before clearing the pointers to allow
335 the receive processor to stop. These items are handled inside
337 Warnings: No context switches are allowed while executing this function.
339 void sFlushRxFIFO(CHANNEL_T *ChP)
342 Byte_t Ch; /* channel number within AIOP */
343 int RxFIFOEnabled; /* TRUE if Rx FIFO enabled */
345 if(sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
346 return; /* don't need to flush */
349 RxFIFOEnabled = FALSE;
350 if(ChP->R[0x32] == 0x08) /* Rx FIFO is enabled */
352 RxFIFOEnabled = TRUE;
353 sDisRxFIFO(ChP); /* disable it */
354 for(i=0; i < 2000/200; i++) /* delay 2 uS to allow proc to disable FIFO*/
355 rp_readch1(ChP,_INT_CHAN); /* depends on bus i/o timing */
357 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
358 Ch = (Byte_t)sGetChanNum(ChP);
359 rp_writech1(ChP,_CMD_REG,Ch | RESRXFCNT); /* apply reset Rx FIFO count */
360 rp_writech1(ChP,_CMD_REG,Ch); /* remove reset Rx FIFO count */
361 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs); /* clear Rx out ptr */
362 rp_writech2(ChP,_INDX_DATA,0);
363 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
364 rp_writech2(ChP,_INDX_DATA,0);
366 sEnRxFIFO(ChP); /* enable Rx FIFO */
370 /***************************************************************************
371 Function: sFlushTxFIFO
372 Purpose: Flush the Tx FIFO
373 Call: sFlushTxFIFO(ChP)
374 CHANNEL_T *ChP; Ptr to channel structure
376 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
377 while it is being flushed the receive processor is stopped
378 and the transmitter is disabled. After these operations a
379 4 uS delay is done before clearing the pointers to allow
380 the receive processor to stop. These items are handled inside
382 Warnings: No context switches are allowed while executing this function.
384 void sFlushTxFIFO(CHANNEL_T *ChP)
387 Byte_t Ch; /* channel number within AIOP */
388 int TxEnabled; /* TRUE if transmitter enabled */
391 if(sGetTxCnt(ChP) == 0) { /* Tx FIFO empty */
393 return; /* don't need to flush */
397 if(ChP->TxControl[3] & TX_ENABLE)
400 sDisTransmit(ChP); /* disable transmitter */
402 sStopRxProcessor(ChP); /* stop Rx processor */
403 for(i = 0; i < 4000/200; i++) /* delay 4 uS to allow proc to stop */
404 rp_readch1(ChP,_INT_CHAN); /* depends on bus i/o timing */
405 Ch = (Byte_t)sGetChanNum(ChP);
406 rp_writech1(ChP,_CMD_REG,Ch | RESTXFCNT); /* apply reset Tx FIFO count */
407 rp_writech1(ChP,_CMD_REG,Ch); /* remove reset Tx FIFO count */
408 rp_writech2(ChP,_INDX_ADDR,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
409 rp_writech2(ChP,_INDX_DATA,0);
411 sEnTransmit(ChP); /* enable transmitter */
412 sStartRxProcessor(ChP); /* restart Rx processor */
416 /***************************************************************************
417 Function: sWriteTxPrioByte
418 Purpose: Write a byte of priority transmit data to a channel
419 Call: sWriteTxPrioByte(ChP,Data)
420 CHANNEL_T *ChP; Ptr to channel structure
421 Byte_t Data; The transmit data byte
423 Return: int: 1 if the bytes is successfully written, otherwise 0.
425 Comments: The priority byte is transmitted before any data in the Tx FIFO.
427 Warnings: No context switches are allowed while executing this function.
429 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data)
431 Byte_t DWBuf[4]; /* buffer for double word writes */
432 Word_t *WordPtr; /* must be far because Win SS != DS */
435 if(sGetTxCnt(ChP) > 1) /* write it to Tx priority buffer */
437 rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt); /* get priority buffer status */
438 if(rp_readch1(ChP,_INDX_DATA) & PRI_PEND) {/* priority buffer busy */
440 return(0); /* nothing sent */
443 WordPtr = (Word_t *)(&DWBuf[0]);
444 *WordPtr = ChP->TxPrioBuf; /* data byte address */
446 DWBuf[2] = Data; /* data byte value */
447 rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)(&DWBuf[0]))); /* write it out */
449 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
451 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
452 DWBuf[3] = 0; /* priority buffer pointer */
453 rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)(&DWBuf[0]))); /* write it out */
455 else /* write it to Tx FIFO */
457 sWriteTxByte(ChP,sGetTxRxDataIO(ChP),Data);
460 return(1); /* 1 byte sent */
463 /***************************************************************************
464 Function: sEnInterrupts
465 Purpose: Enable one or more interrupts for a channel
466 Call: sEnInterrupts(ChP,Flags)
467 CHANNEL_T *ChP; Ptr to channel structure
468 Word_t Flags: Interrupt enable flags, can be any combination
469 of the following flags:
470 TXINT_EN: Interrupt on Tx FIFO empty
471 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
473 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
474 MCINT_EN: Interrupt on modem input change
475 CHANINT_EN: Allow channel interrupt signal to the AIOP's
476 Interrupt Channel Register.
478 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
479 enabled. If an interrupt enable flag is not set in Flags, that
480 interrupt will not be changed. Interrupts can be disabled with
481 function sDisInterrupts().
483 This function sets the appropriate bit for the channel in the AIOP's
484 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
485 this channel's bit to be set in the AIOP's Interrupt Channel Register.
487 Interrupts must also be globally enabled before channel interrupts
488 will be passed on to the host. This is done with function
491 In some cases it may be desirable to disable interrupts globally but
492 enable channel interrupts. This would allow the global interrupt
493 status register to be used to determine which AIOPs need service.
495 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags)
497 Byte_t Mask; /* Interrupt Mask Register */
500 ((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
502 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
504 ChP->TxControl[2] |= ((Byte_t)Flags & TXINT_EN);
506 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
508 if(Flags & CHANINT_EN)
510 Mask = rp_readch1(ChP,_INT_MASK) | rp_sBitMapSetTbl[ChP->ChanNum];
511 rp_writech1(ChP,_INT_MASK,Mask);
515 /***************************************************************************
516 Function: sDisInterrupts
517 Purpose: Disable one or more interrupts for a channel
518 Call: sDisInterrupts(ChP,Flags)
519 CHANNEL_T *ChP; Ptr to channel structure
520 Word_t Flags: Interrupt flags, can be any combination
521 of the following flags:
522 TXINT_EN: Interrupt on Tx FIFO empty
523 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
525 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
526 MCINT_EN: Interrupt on modem input change
527 CHANINT_EN: Disable channel interrupt signal to the
528 AIOP's Interrupt Channel Register.
530 Comments: If an interrupt flag is set in Flags, that interrupt will be
531 disabled. If an interrupt flag is not set in Flags, that
532 interrupt will not be changed. Interrupts can be enabled with
533 function sEnInterrupts().
535 This function clears the appropriate bit for the channel in the AIOP's
536 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
537 this channel's bit from being set in the AIOP's Interrupt Channel
540 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags)
542 Byte_t Mask; /* Interrupt Mask Register */
545 ~((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
546 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
547 ChP->TxControl[2] &= ~((Byte_t)Flags & TXINT_EN);
548 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
550 if(Flags & CHANINT_EN)
552 Mask = rp_readch1(ChP,_INT_MASK) & rp_sBitMapClrTbl[ChP->ChanNum];
553 rp_writech1(ChP,_INT_MASK,Mask);
557 /*********************************************************************
558 Begin FreeBsd-specific driver code
559 **********************************************************************/
561 static timeout_t rpdtrwakeup;
563 static d_open_t rpopen;
564 static d_close_t rpclose;
565 static d_write_t rpwrite;
566 static d_ioctl_t rpioctl;
568 static struct dev_ops rp_ops = {
575 .d_kqfilter = ttykqfilter,
576 .d_revoke = ttyrevoke
579 static int rp_num_ports_open = 0;
580 static int rp_ndevs = 0;
581 static int minor_to_unit[128];
582 static int rp_initialized;
583 static struct callout rp_poll_ch;
585 static int rp_num_ports[4]; /* Number of ports on each controller */
587 #define POLL_INTERVAL 1
589 #define CALLOUT_MASK 0x80
590 #define CONTROL_MASK 0x60
591 #define CONTROL_INIT_STATE 0x20
592 #define CONTROL_LOCK_STATE 0x40
593 #define DEV_UNIT(dev) (MINOR_TO_UNIT(minor(dev))
594 #define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
595 #define MINOR_MAGIC(dev) ((minor(dev)) & ~MINOR_MAGIC_MASK)
596 #define IS_CALLOUT(dev) (minor(dev) & CALLOUT_MASK)
597 #define IS_CONTROL(dev) (minor(dev) & CONTROL_MASK)
599 #define RP_ISMULTIPORT(dev) ((dev)->id_flags & 0x1)
600 #define RP_MPMASTER(dev) (((dev)->id_flags >> 8) & 0xff)
601 #define RP_NOTAST4(dev) ((dev)->id_flags & 0x04)
603 static struct rp_port *p_rp_addr[4];
604 static struct rp_port *p_rp_table[MAX_RP_PORTS];
605 #define rp_addr(unit) (p_rp_addr[unit])
606 #define rp_table(port) (p_rp_table[port])
609 * The top-level routines begin here
612 static int rpparam (struct tty *, struct termios *);
613 static void rpstart (struct tty *);
614 static void rpstop (struct tty *, int);
615 static void rphardclose (struct rp_port *);
616 static void rp_disc_optim (struct tty *tp, struct termios *t);
619 * NOTE: Must be called with tty_token held
622 rp_do_receive(struct rp_port *rp, struct tty *tp,
623 CHANNEL_t *cp, unsigned int ChanStatus)
625 unsigned int CharNStat;
626 int ToRecv, wRecv, ch, ttynocopy;
628 ASSERT_LWKT_TOKEN_HELD(&tty_token);
629 ToRecv = sGetRxCnt(cp);
633 /* If status indicates there are errored characters in the
634 FIFO, then enter status mode (a word in FIFO holds
635 characters and status)
638 if(ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
639 if(!(ChanStatus & STATMODE)) {
640 ChanStatus |= STATMODE;
645 if we previously entered status mode then read down the
646 FIFO one word at a time, pulling apart the character and
647 the status. Update error counters depending on status.
649 if(ChanStatus & STATMODE) {
651 if(tp->t_state & TS_TBLOCK) {
654 CharNStat = rp_readch2(cp,sGetTxRxDataIO(cp));
655 ch = CharNStat & 0xff;
657 if((CharNStat & STMBREAK) || (CharNStat & STMFRAMEH))
659 else if (CharNStat & STMPARITYH)
661 else if (CharNStat & STMRCVROVRH)
664 (*linesw[tp->t_line].l_rint)(ch, tp);
668 After emtying FIFO in status mode, turn off status mode
671 if(sGetRxCnt(cp) == 0) {
672 sDisRxStatusMode(cp);
676 * Avoid the grotesquely inefficient lineswitch routine
677 * (ttyinput) in "raw" mode. It usually takes about 450
678 * instructions (that's without canonical processing or echo!).
679 * slinput is reasonably fast (usually 40 instructions plus
682 ToRecv = sGetRxCnt(cp);
683 if ( tp->t_state & TS_CAN_BYPASS_L_RINT ) {
684 if ( ToRecv > RXFIFO_SIZE ) {
685 ToRecv = RXFIFO_SIZE;
689 rp_readmultich2(cp,sGetTxRxDataIO(cp),(u_int16_t *)rp->RxBuf,wRecv);
692 ((unsigned char *)rp->RxBuf)[(ToRecv-1)] = (u_char) rp_readch1(cp,sGetTxRxDataIO(cp));
696 tp->t_rawcc += ToRecv;
697 ttynocopy = b_to_q((char *)rp->RxBuf, ToRecv, &tp->t_rawq);
701 if(tp->t_state & TS_TBLOCK) {
704 ch = (u_char) rp_readch1(cp,sGetTxRxDataIO(cp));
706 (*linesw[tp->t_line].l_rint)(ch, tp);
715 * NOTE: Must be called with tty_token held
718 rp_handle_port(struct rp_port *rp)
722 unsigned int IntMask, ChanStatus;
724 ASSERT_LWKT_TOKEN_HELD(&tty_token);
729 cp = &rp->rp_channel;
731 IntMask = sGetChanIntID(cp);
732 IntMask = IntMask & rp->rp_intmask;
733 ChanStatus = sGetChanStatus(cp);
734 if(IntMask & RXF_TRIG)
735 if(!(tp->t_state & TS_TBLOCK) && (tp->t_state & TS_CARR_ON) && (tp->t_state & TS_ISOPEN)) {
736 rp_do_receive(rp, tp, cp, ChanStatus);
738 if(IntMask & DELTA_CD) {
739 if(ChanStatus & CD_ACT) {
740 if(!(tp->t_state & TS_CARR_ON) ) {
741 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
744 if((tp->t_state & TS_CARR_ON)) {
745 (void)(*linesw[tp->t_line].l_modem)(tp, 0);
746 if((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
752 /* oldcts = rp->rp_cts;
753 rp->rp_cts = ((ChanStatus & CTS_ACT) != 0);
754 if(oldcts != rp->rp_cts) {
755 kprintf("CTS change (now %s)... on port %d\n", rp->rp_cts ? "on" : "off", rp->rp_port);
760 static void rp_do_poll(void *not_used)
765 int unit, aiop, ch, line, count;
766 unsigned char CtlMask, AiopMask;
768 lwkt_gettoken(&tty_token);
769 for(unit = 0; unit < rp_ndevs; unit++) {
772 CtlMask = ctl->ctlmask(ctl);
773 for(aiop=0; CtlMask; CtlMask >>=1, aiop++) {
775 AiopMask = sGetAiopIntStatus(ctl, aiop);
776 for(ch = 0; AiopMask; AiopMask >>=1, ch++) {
778 line = (unit << 5) | (aiop << 3) | ch;
786 for(line = 0, rp = rp_addr(unit); line < rp_num_ports[unit];
789 if((tp->t_state & TS_BUSY) && (tp->t_state & TS_ISOPEN)) {
790 count = sGetTxCnt(&rp->rp_channel);
792 tp->t_state &= ~(TS_BUSY);
793 if(!(tp->t_state & TS_TTSTOP) &&
794 (count <= rp->rp_restart)) {
795 (*linesw[tp->t_line].l_start)(tp);
800 if(rp_num_ports_open)
801 callout_reset(&rp_poll_ch, POLL_INTERVAL, rp_do_poll, NULL);
802 lwkt_reltoken(&tty_token);
806 rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports)
810 int aiop, chan, port;
811 int ChanStatus, line, i, count;
816 lwkt_gettoken(&tty_token);
817 unit = device_get_unit(ctlp->dev);
819 kprintf("RocketPort%d (Version %s) %d ports.\n", unit,
820 RocketPortVersion, num_ports);
821 rp_num_ports[unit] = num_ports;
823 ctlp->rp = rp = kmalloc(sizeof(struct rp_port) * num_ports,
824 M_TTYS, M_WAITOK | M_ZERO);
826 count = unit * 32; /* board times max ports per card SG */
827 for(i=count;i < (count + rp_num_ports[unit]);i++)
828 minor_to_unit[i] = unit;
830 ctlp->tty = tty = kmalloc(sizeof(struct tty) * num_ports,
831 M_TTYS, M_WAITOK | M_ZERO);
837 for (i = 0 ; i < rp_num_ports[unit] ; i++) {
838 make_dev(&rp_ops, ((unit + 1) << 16) | i,
839 UID_ROOT, GID_WHEEL, 0666, "ttyR%c",
840 i <= 9 ? '0' + i : 'a' + i - 10);
841 make_dev(&rp_ops, ((unit + 1) << 16) | i | 0x20,
842 UID_ROOT, GID_WHEEL, 0666, "ttyiR%c",
843 i <= 9 ? '0' + i : 'a' + i - 10);
844 make_dev(&rp_ops, ((unit + 1) << 16) | i | 0x40,
845 UID_ROOT, GID_WHEEL, 0666, "ttylR%c",
846 i <= 9 ? '0' + i : 'a' + i - 10);
847 make_dev(&rp_ops, ((unit + 1) << 16) | i | 0x80,
848 UID_ROOT, GID_WHEEL, 0666, "cuaR%c",
849 i <= 9 ? '0' + i : 'a' + i - 10);
850 make_dev(&rp_ops, ((unit + 1) << 16) | i | 0xa0,
851 UID_ROOT, GID_WHEEL, 0666, "cuaiR%c",
852 i <= 9 ? '0' + i : 'a' + i - 10);
853 make_dev(&rp_ops, ((unit + 1) << 16) | i | 0xc0,
854 UID_ROOT, GID_WHEEL, 0666, "cualR%c",
855 i <= 9 ? '0' + i : 'a' + i - 10);
859 for(aiop=0; aiop < num_aiops; aiop++) {
860 num_chan = sGetAiopNumChan(ctlp, aiop);
861 for(chan=0; chan < num_chan; chan++, port++, rp++, tty++) {
870 /* tty->t_termios = deftermios;
872 rp->dtr_wait = 3 * hz;
873 rp->it_in.c_iflag = 0;
874 rp->it_in.c_oflag = 0;
875 rp->it_in.c_cflag = TTYDEF_CFLAG;
876 rp->it_in.c_lflag = 0;
877 termioschars(&rp->it_in);
878 /* termioschars(&tty->t_termios);
880 rp->it_in.c_ispeed = rp->it_in.c_ospeed = TTYDEF_SPEED;
881 rp->it_out = rp->it_in;
883 rp->rp_intmask = RXF_TRIG | TXFIFO_MT | SRC_INT |
884 DELTA_CD | DELTA_CTS | DELTA_DSR;
885 if(sInitChan(ctlp, &rp->rp_channel, aiop, chan) == 0) {
886 device_printf(ctlp->dev, "RocketPort sInitChan(%d, %d, %d) failed.\n",
891 ChanStatus = sGetChanStatus(&rp->rp_channel);
892 rp->rp_cts = (ChanStatus & CTS_ACT) != 0;
893 line = (unit << 5) | (aiop << 3) | chan;
899 lwkt_reltoken(&tty_token);
903 rp_releaseresource(ctlp);
904 lwkt_reltoken(&tty_token);
909 rp_releaseresource(CONTROLLER_t *ctlp)
913 lwkt_gettoken(&tty_token);
914 unit = device_get_unit(ctlp->dev);
916 if (ctlp->rp != NULL) {
918 for (i = 0 ; i < NELEM(p_rp_addr) ; i++)
919 if (p_rp_addr[i] == ctlp->rp)
921 for (i = 0 ; i < NELEM(p_rp_table) ; i++)
922 if (p_rp_table[i] == ctlp->rp)
923 p_rp_table[i] = NULL;
925 kfree(ctlp->rp, M_DEVBUF);
928 if (ctlp->tty != NULL) {
929 kfree(ctlp->tty, M_DEVBUF);
932 if (ctlp->dev != NULL)
934 dev_ops_remove_minor(&rp_ops, /*0xffff0000, */(unit + 1) << 16);
935 lwkt_reltoken(&tty_token);
939 rpopen(struct dev_open_args *ap)
941 cdev_t dev = ap->a_head.a_dev;
943 int unit, port, mynor, umynor, flags; /* SG */
946 unsigned int IntMask, ChanStatus;
948 lwkt_gettoken(&tty_token);
949 if (!rp_initialized) {
951 callout_init_mp(&rp_poll_ch);
954 umynor = (((minor(dev) >> 16) -1) * 32); /* SG */
955 port = (minor(dev) & 0x1f); /* SG */
956 mynor = (port + umynor); /* SG */
957 unit = minor_to_unit[mynor];
958 if (rp_addr(unit) == NULL) {
959 lwkt_reltoken(&tty_token);
962 if(IS_CONTROL(dev)) {
963 lwkt_reltoken(&tty_token);
966 rp = rp_addr(unit) + port;
967 /* rp->rp_tty = &rp_tty[rp->rp_port];
969 callout_init_mp(&rp->wakeup_callout);
976 while(rp->state & ~SET_DTR) {
977 error = tsleep(&rp->dtr_wait, PCATCH, "rpdtr", 0);
982 if(tp->t_state & TS_ISOPEN) {
983 if(IS_CALLOUT(dev)) {
984 if(!rp->active_out) {
990 if(ap->a_oflags & O_NONBLOCK) {
994 error = tsleep(&rp->active_out,
1001 if(tp->t_state & TS_XCLUDE && priv_check_cred(ap->a_cred, PRIV_ROOT, 0) != 0) {
1009 tp->t_param = rpparam;
1010 tp->t_oproc = rpstart;
1011 tp->t_stop = rpstop;
1013 tp->t_termios = IS_CALLOUT(dev) ? rp->it_out : rp->it_in;
1014 tp->t_ififosize = 512;
1015 tp->t_ispeedwat = (speed_t)-1;
1016 tp->t_ospeedwat = (speed_t)-1;
1020 rp->rp_channel.TxControl[3] =
1021 ((rp->rp_channel.TxControl[3]
1022 & ~(SET_RTS | SET_DTR)) | flags);
1023 rp_writech4(&rp->rp_channel,_INDX_ADDR,
1024 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1025 sSetRxTrigger(&rp->rp_channel, TRIG_1);
1026 sDisRxStatusMode(&rp->rp_channel);
1027 sFlushRxFIFO(&rp->rp_channel);
1028 sFlushTxFIFO(&rp->rp_channel);
1030 sEnInterrupts(&rp->rp_channel,
1031 (TXINT_EN|MCINT_EN|RXINT_EN|SRCINT_EN|CHANINT_EN));
1032 sSetRxTrigger(&rp->rp_channel, TRIG_1);
1034 sDisRxStatusMode(&rp->rp_channel);
1035 sClrTxXOFF(&rp->rp_channel);
1037 /* sDisRTSFlowCtl(&rp->rp_channel);
1038 sDisCTSFlowCtl(&rp->rp_channel);
1040 sDisTxSoftFlowCtl(&rp->rp_channel);
1042 sStartRxProcessor(&rp->rp_channel);
1044 sEnRxFIFO(&rp->rp_channel);
1045 sEnTransmit(&rp->rp_channel);
1047 /* sSetDTR(&rp->rp_channel);
1048 sSetRTS(&rp->rp_channel);
1052 error = rpparam(tp, &tp->t_termios);
1056 lwkt_reltoken(&tty_token);
1060 rp_num_ports_open++;
1062 IntMask = sGetChanIntID(&rp->rp_channel);
1063 IntMask = IntMask & rp->rp_intmask;
1064 ChanStatus = sGetChanStatus(&rp->rp_channel);
1065 if((IntMask & DELTA_CD) || IS_CALLOUT(dev)) {
1066 if((ChanStatus & CD_ACT) || IS_CALLOUT(dev)) {
1067 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
1071 if(rp_num_ports_open == 1)
1072 callout_reset(&rp_poll_ch, POLL_INTERVAL, rp_do_poll, NULL);
1076 if(!(ap->a_oflags&O_NONBLOCK) && !(tp->t_cflag&CLOCAL) &&
1077 !(tp->t_state & TS_CARR_ON) && !(IS_CALLOUT(dev))) {
1079 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rpdcd", 0);
1085 error = (*linesw[tp->t_line].l_open)(dev, tp);
1087 rp_disc_optim(tp, &tp->t_termios);
1088 if(tp->t_state & TS_ISOPEN && IS_CALLOUT(dev))
1089 rp->active_out = TRUE;
1091 /* if(rp_num_ports_open == 1)
1092 callout_reset(&rp_poll_ch, POLL_INTERVAL, rp_do_poll, NULL);
1096 if(!(tp->t_state & TS_ISOPEN) && rp->wopeners == 0) {
1101 device_busy(rp->rp_ctlp->dev);
1102 lwkt_reltoken(&tty_token);
1107 rpclose(struct dev_close_args *ap)
1109 cdev_t dev = ap->a_head.a_dev;
1110 int unit, mynor, umynor, port; /* SG */
1114 lwkt_gettoken(&tty_token);
1115 umynor = (((minor(dev) >> 16) -1) * 32); /* SG */
1116 port = (minor(dev) & 0x1f); /* SG */
1117 mynor = (port + umynor); /* SG */
1118 unit = minor_to_unit[mynor]; /* SG */
1120 if(IS_CONTROL(dev)) {
1121 lwkt_reltoken(&tty_token);
1124 rp = rp_addr(unit) + port;
1128 (*linesw[tp->t_line].l_close)(tp, ap->a_fflag);
1129 rp_disc_optim(tp, &tp->t_termios);
1130 rpstop(tp, FREAD | FWRITE);
1133 tp->t_state &= ~TS_BUSY;
1138 device_unbusy(rp->rp_ctlp->dev);
1140 lwkt_reltoken(&tty_token);
1145 * NOTE: Must be called with tty_token held
1148 rphardclose(struct rp_port *rp)
1153 ASSERT_LWKT_TOKEN_HELD(&tty_token);
1154 cp = &rp->rp_channel;
1160 sDisInterrupts(cp, TXINT_EN|MCINT_EN|RXINT_EN|SRCINT_EN|CHANINT_EN);
1163 sDisTxSoftFlowCtl(cp);
1166 if(tp->t_cflag&HUPCL || !(tp->t_state&TS_ISOPEN) || !rp->active_out) {
1169 if(IS_CALLOUT(tp->t_dev)) {
1172 if(rp->dtr_wait != 0) {
1173 callout_reset(&rp->wakeup_callout, rp->dtr_wait,
1175 rp->state |= ~SET_DTR;
1178 rp->active_out = FALSE;
1179 wakeup(&rp->active_out);
1180 wakeup(TSA_CARR_ON(tp));
1185 rpwrite(struct dev_write_args *ap)
1187 cdev_t dev = ap->a_head.a_dev;
1190 int unit, mynor, port, umynor, error = 0; /* SG */
1192 umynor = (((minor(dev) >> 16) -1) * 32); /* SG */
1193 port = (minor(dev) & 0x1f); /* SG */
1194 mynor = (port + umynor); /* SG */
1195 unit = minor_to_unit[mynor]; /* SG */
1199 lwkt_gettoken(&tty_token);
1200 rp = rp_addr(unit) + port;
1202 while(rp->rp_disable_writes) {
1204 error = ttysleep(tp, (caddr_t)rp, PCATCH, "rp_write", 0);
1206 lwkt_reltoken(&tty_token);
1211 error = (*linesw[tp->t_line].l_write)(tp, ap->a_uio, ap->a_ioflag);
1212 lwkt_reltoken(&tty_token);
1217 rpdtrwakeup(void *chan)
1221 lwkt_gettoken(&tty_token);
1222 rp = (struct rp_port *)chan;
1223 rp->state &= SET_DTR;
1224 wakeup(&rp->dtr_wait);
1225 lwkt_reltoken(&tty_token);
1229 rpioctl(struct dev_ioctl_args *ap)
1231 cdev_t dev = ap->a_head.a_dev;
1232 u_long cmd = ap->a_cmd;
1233 caddr_t data = ap->a_data;
1236 int unit, mynor, port, umynor; /* SG */
1238 int arg, flags, result, ChanStatus;
1240 lwkt_gettoken(&tty_token);
1241 umynor = (((minor(dev) >> 16) -1) * 32); /* SG */
1242 port = (minor(dev) & 0x1f); /* SG */
1243 mynor = (port + umynor); /* SG */
1244 unit = minor_to_unit[mynor];
1245 rp = rp_addr(unit) + port;
1247 if(IS_CONTROL(dev)) {
1250 switch (IS_CONTROL(dev)) {
1251 case CONTROL_INIT_STATE:
1252 ct = IS_CALLOUT(dev) ? &rp->it_out : &rp->it_in;
1254 case CONTROL_LOCK_STATE:
1255 ct = IS_CALLOUT(dev) ? &rp->lt_out : &rp->lt_in;
1258 lwkt_reltoken(&tty_token);
1259 return(ENODEV); /* /dev/nodev */
1263 error = priv_check_cred(ap->a_cred, PRIV_ROOT, 0);
1265 lwkt_reltoken(&tty_token);
1268 *ct = *(struct termios *)data;
1269 lwkt_reltoken(&tty_token);
1272 *(struct termios *)data = *ct;
1273 lwkt_reltoken(&tty_token);
1276 *(int *)data = TTYDISC;
1277 lwkt_reltoken(&tty_token);
1280 bzero(data, sizeof(struct winsize));
1281 lwkt_reltoken(&tty_token);
1284 lwkt_reltoken(&tty_token);
1291 #if defined(COMPAT_43)
1292 term = tp->t_termios;
1294 error = ttsetcompat(tp, &cmd, data, &term);
1296 lwkt_reltoken(&tty_token);
1300 data = (caddr_t)&term;
1303 if((cmd == TIOCSETA) || (cmd == TIOCSETAW) || (cmd == TIOCSETAF)) {
1305 struct termios *dt = (struct termios *)data;
1306 struct termios *lt = IS_CALLOUT(dev)
1307 ? &rp->lt_out : &rp->lt_in;
1309 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
1310 | (dt->c_iflag & ~lt->c_iflag);
1311 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
1312 | (dt->c_oflag & ~lt->c_oflag);
1313 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
1314 | (dt->c_cflag & ~lt->c_cflag);
1315 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
1316 | (dt->c_lflag & ~lt->c_lflag);
1317 for(cc = 0; cc < NCCS; ++cc)
1318 if(lt->c_cc[cc] != 0)
1319 dt->c_cc[cc] = tp->t_cc[cc];
1320 if(lt->c_ispeed != 0)
1321 dt->c_ispeed = tp->t_ispeed;
1322 if(lt->c_ospeed != 0)
1323 dt->c_ospeed = tp->t_ospeed;
1326 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data,
1327 ap->a_fflag, ap->a_cred);
1328 if(error != ENOIOCTL) {
1329 lwkt_reltoken(&tty_token);
1334 flags = rp->rp_channel.TxControl[3];
1336 error = ttioctl(tp, cmd, data, ap->a_fflag);
1337 flags = rp->rp_channel.TxControl[3];
1338 rp_disc_optim(tp, &tp->t_termios);
1339 if(error != ENOIOCTL) {
1341 lwkt_reltoken(&tty_token);
1346 sSendBreak(&rp->rp_channel);
1350 sClrBreak(&rp->rp_channel);
1354 sSetDTR(&rp->rp_channel);
1355 sSetRTS(&rp->rp_channel);
1359 sClrDTR(&rp->rp_channel);
1363 arg = *(int *) data;
1369 rp->rp_channel.TxControl[3] =
1370 ((rp->rp_channel.TxControl[3]
1371 & ~(SET_RTS | SET_DTR)) | flags);
1372 rp_writech4(&rp->rp_channel,_INDX_ADDR,
1373 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1376 arg = *(int *) data;
1382 rp->rp_channel.TxControl[3] |= flags;
1383 rp_writech4(&rp->rp_channel,_INDX_ADDR,
1384 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1387 arg = *(int *) data;
1393 rp->rp_channel.TxControl[3] &= ~flags;
1394 rp_writech4(&rp->rp_channel,_INDX_ADDR,
1395 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1400 ChanStatus = sGetChanStatusLo(&rp->rp_channel);
1401 flags = rp->rp_channel.TxControl[3];
1402 result = TIOCM_LE; /* always on while open for some reason */
1403 result |= (((flags & SET_DTR) ? TIOCM_DTR : 0)
1404 | ((flags & SET_RTS) ? TIOCM_RTS : 0)
1405 | ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0)
1406 | ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0)
1407 | ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0));
1409 if(rp->rp_channel.RxControl[2] & RTSFC_EN)
1411 result |= TIOCM_RTS;
1414 *(int *)data = result;
1417 error = priv_check_cred(ap->a_cred, PRIV_ROOT, 0);
1420 lwkt_reltoken(&tty_token);
1423 rp->dtr_wait = *(int *)data * hz/100;
1426 *(int *)data = rp->dtr_wait * 100/hz;
1430 lwkt_reltoken(&tty_token);
1434 lwkt_reltoken(&tty_token);
1438 static struct speedtab baud_table[] = {
1439 {B0, 0}, {B50, BRD50}, {B75, BRD75},
1440 {B110, BRD110}, {B134, BRD134}, {B150, BRD150},
1441 {B200, BRD200}, {B300, BRD300}, {B600, BRD600},
1442 {B1200, BRD1200}, {B1800, BRD1800}, {B2400, BRD2400},
1443 {B4800, BRD4800}, {B9600, BRD9600}, {B19200, BRD19200},
1444 {B38400, BRD38400}, {B7200, BRD7200}, {B14400, BRD14400},
1445 {B57600, BRD57600}, {B76800, BRD76800},
1446 {B115200, BRD115200}, {B230400, BRD230400},
1451 rpparam(struct tty *tp, struct termios *t)
1455 int unit, mynor, port, umynor; /* SG */
1456 int cflag, iflag, oflag, lflag;
1462 lwkt_gettoken(&tty_token);
1463 umynor = (((minor(tp->t_dev) >> 16) -1) * 32); /* SG */
1464 port = (minor(tp->t_dev) & 0x1f); /* SG */
1465 mynor = (port + umynor); /* SG */
1467 unit = minor_to_unit[mynor];
1468 rp = rp_addr(unit) + port;
1469 cp = &rp->rp_channel;
1474 devshift = umynor / 32;
1475 devshift = 1 << devshift;
1476 if ( devshift & RPCLOCAL ) {
1484 ospeed = ttspeedtab(t->c_ispeed, baud_table);
1485 if(ospeed < 0 || t->c_ispeed != t->c_ospeed) {
1487 lwkt_reltoken(&tty_token);
1491 tp->t_ispeed = t->c_ispeed;
1492 tp->t_ospeed = t->c_ospeed;
1493 tp->t_cflag = cflag;
1494 tp->t_iflag = iflag;
1495 tp->t_oflag = oflag;
1496 tp->t_lflag = lflag;
1498 if(t->c_ospeed == 0) {
1501 lwkt_reltoken(&tty_token);
1504 rp->rp_fifo_lw = ((t->c_ospeed*2) / 1000) +1;
1506 /* Set baud rate ----- we only pay attention to ispeed */
1509 sSetBaud(cp, ospeed);
1511 if(cflag & CSTOPB) {
1517 if(cflag & PARENB) {
1519 if(cflag & PARODD) {
1528 if((cflag & CSIZE) == CS8) {
1530 rp->rp_imask = 0xFF;
1533 rp->rp_imask = 0x7F;
1536 if(iflag & ISTRIP) {
1537 rp->rp_imask &= 0x7F;
1540 if(cflag & CLOCAL) {
1541 rp->rp_intmask &= ~DELTA_CD;
1543 rp->rp_intmask |= DELTA_CD;
1546 /* Put flow control stuff here */
1548 if(cflag & CCTS_OFLOW) {
1554 if(cflag & CRTS_IFLOW) {
1555 rp->rp_rts_iflow = 1;
1557 rp->rp_rts_iflow = 0;
1560 if(cflag & CRTS_IFLOW) {
1565 rp_disc_optim(tp, t);
1567 if((cflag & CLOCAL) || (sGetChanStatusLo(cp) & CD_ACT)) {
1568 tp->t_state |= TS_CARR_ON;
1569 wakeup(TSA_CARR_ON(tp));
1572 /* tp->t_state |= TS_CAN_BYPASS_L_RINT;
1573 flags = rp->rp_channel.TxControl[3];
1581 lwkt_reltoken(&tty_token);
1586 rp_disc_optim(struct tty *tp, struct termios *t)
1588 lwkt_gettoken(&tty_token);
1589 if(!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1590 &&(!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1591 &&(!(t->c_iflag & PARMRK)
1592 ||(t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1593 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1594 && linesw[tp->t_line].l_rint == ttyinput)
1595 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1597 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1598 lwkt_reltoken(&tty_token);
1602 rpstart(struct tty *tp)
1607 int unit, mynor, port, umynor; /* SG */
1612 lwkt_gettoken(&tty_token);
1613 umynor = (((minor(tp->t_dev) >> 16) -1) * 32); /* SG */
1614 port = (minor(tp->t_dev) & 0x1f); /* SG */
1615 mynor = (port + umynor); /* SG */
1616 unit = minor_to_unit[mynor];
1617 rp = rp_addr(unit) + port;
1618 cp = &rp->rp_channel;
1621 if(tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
1624 lwkt_reltoken(&tty_token);
1627 if(rp->rp_xmit_stopped) {
1629 rp->rp_xmit_stopped = 0;
1631 count = sGetTxCnt(cp);
1633 if(tp->t_outq.c_cc == 0) {
1634 if((tp->t_state & TS_BUSY) && (count == 0)) {
1635 tp->t_state &= ~TS_BUSY;
1639 lwkt_reltoken(&tty_token);
1642 xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1644 if(xmit_fifo_room > 0 && qp->c_cc > 0) {
1645 tp->t_state |= TS_BUSY;
1646 count = q_to_b( qp, (char *)rp->TxBuf, xmit_fifo_room );
1647 wcount = count >> 1;
1649 rp_writemultich2(cp, sGetTxRxDataIO(cp), (u_int16_t *)rp->TxBuf, wcount);
1652 rp_writech1(cp, sGetTxRxDataIO(cp),
1653 ((unsigned char *)(rp->TxBuf))[(count-1)]);
1656 rp->rp_restart = (qp->c_cc > 0) ? rp->rp_fifo_lw : 0;
1660 lwkt_reltoken(&tty_token);
1665 rpstop(struct tty *tp, int flag)
1669 int unit, mynor, port, umynor; /* SG */
1671 lwkt_gettoken(&tty_token);
1672 umynor = (((minor(tp->t_dev) >> 16) -1) * 32); /* SG */
1673 port = (minor(tp->t_dev) & 0x1f); /* SG */
1674 mynor = (port + umynor); /* SG */
1675 unit = minor_to_unit[mynor];
1676 rp = rp_addr(unit) + port;
1677 cp = &rp->rp_channel;
1681 if(tp->t_state & TS_BUSY) {
1682 if((tp->t_state&TS_TTSTOP) == 0) {
1685 if(rp->rp_xmit_stopped == 0) {
1687 rp->rp_xmit_stopped = 1;
1693 lwkt_reltoken(&tty_token);