2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
35 * Used in the LinkSys USB200M and various other adapters.
37 * Manuals available from:
38 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
39 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
40 * controller) to find the definitions for the RX control register.
41 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
43 * Written by Bill Paul <wpaul@windriver.com>
49 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
50 * It uses an external PHY (reference designs use a RealTek chip),
51 * and has a 64-bit multicast hash filter. There is some information
52 * missing from the manual which one needs to know in order to make
55 * - You must set bit 7 in the RX control register, otherwise the
56 * chip won't receive any packets.
57 * - You must initialize all 3 IPG registers, or you won't be able
58 * to send any packets.
60 * Note that this device appears to only support loading the station
61 * address via autload from the EEPROM (i.e. there's no way to manaully
64 * (Adam Weinberger wanted me to name this driver if_gir.c.)
68 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
69 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
72 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
73 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
76 #include <sys/param.h>
77 #include <sys/systm.h>
79 #include <sys/condvar.h>
80 #include <sys/endian.h>
81 #include <sys/kernel.h>
83 #include <sys/malloc.h>
85 #include <sys/module.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
91 #include <net/ethernet.h>
92 #include <net/if_types.h>
93 #include <net/if_media.h>
94 #include <net/vlan/if_vlan_var.h>
95 #include <net/ifq_var.h>
97 #include <dev/netif/mii_layer/mii.h>
98 #include <dev/netif/mii_layer/miivar.h>
100 #include <bus/u4b/usb.h>
101 #include <bus/u4b/usbdi.h>
102 #include <bus/u4b/usbdi_util.h>
105 #define USB_DEBUG_VAR axe_debug
106 #include <bus/u4b/usb_debug.h>
107 #include <bus/u4b/usb_process.h>
109 #include <bus/u4b/net/usb_ethernet.h>
110 #include <bus/u4b/net/if_axereg.h>
113 * AXE_178_MAX_FRAME_BURST
114 * max frame burst size for Ax88178 and Ax88772
119 * use the largest your system can handle without USB stalling.
121 * NB: 88772 parts appear to generate lots of input errors with
122 * a 2K rx buffer and 8K is only slightly faster than 4K on an
123 * EHCI port on a T42 so change at your own risk.
125 #define AXE_178_MAX_FRAME_BURST 1
127 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
130 static int axe_debug = 0;
132 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe");
133 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0,
138 * Various supported device vendors/products.
140 static const STRUCT_USB_HOST_ID axe_devs[] = {
141 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
142 AXE_DEV(ABOCOM, UF200, 0),
143 AXE_DEV(ACERCM, EP1427X2, 0),
144 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
145 AXE_DEV(ASIX, AX88172, 0),
146 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
147 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
148 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
149 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
150 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B),
151 AXE_DEV(ATEN, UC210T, 0),
152 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
153 AXE_DEV(BILLIONTON, USB2AR, 0),
154 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
155 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
156 AXE_DEV(DLINK, DUBE100, 0),
157 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
158 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B),
159 AXE_DEV(GOODWAY, GWUSB2E, 0),
160 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
161 AXE_DEV(JVC, MP_PRX1, 0),
162 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B),
163 AXE_DEV(LINKSYS2, USB200M, 0),
164 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
165 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
166 AXE_DEV(MELCO, LUAU2KTX, 0),
167 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
168 AXE_DEV(NETGEAR, FA120, 0),
169 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
170 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
171 AXE_DEV(SITECOM, LN029, 0),
172 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
173 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
177 static device_probe_t axe_probe;
178 static device_attach_t axe_attach;
179 static device_detach_t axe_detach;
181 static usb_callback_t axe_bulk_read_callback;
182 static usb_callback_t axe_bulk_write_callback;
184 static miibus_readreg_t axe_miibus_readreg;
185 static miibus_writereg_t axe_miibus_writereg;
186 static miibus_statchg_t axe_miibus_statchg;
189 static int axe_miibus_readreg(device_t dev, int phy, int reg);
190 static int axe_miibus_writereg(device_t dev, int phy, int reg, int val);
191 static void axe_miibus_statchg(device_t dev);
193 static uether_fn_t axe_attach_post;
194 static uether_fn_t axe_init;
195 static uether_fn_t axe_stop;
196 static uether_fn_t axe_start;
197 static uether_fn_t axe_tick;
198 static uether_fn_t axe_setmulti;
199 static uether_fn_t axe_setpromisc;
201 static int axe_attach_post_sub(struct usb_ether *);
202 static int axe_ifmedia_upd(struct ifnet *);
203 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
204 static int axe_cmd(struct axe_softc *, int, int, int, void *);
205 static void axe_ax88178_init(struct axe_softc *);
206 static void axe_ax88772_init(struct axe_softc *);
207 static void axe_ax88772_phywake(struct axe_softc *);
208 static void axe_ax88772a_init(struct axe_softc *);
209 static void axe_ax88772b_init(struct axe_softc *);
210 static int axe_get_phyno(struct axe_softc *, int);
211 static int axe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
212 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
213 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *,
214 unsigned int offset, unsigned int, struct axe_csum_hdr *);
215 static void axe_csum_cfg(struct usb_ether *);
217 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
221 .endpoint = UE_ADDR_ANY,
222 .direction = UE_DIR_OUT,
224 .bufsize = 16 * MCLBYTES,
225 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
226 .callback = axe_bulk_write_callback,
227 .timeout = 10000, /* 10 seconds */
232 .endpoint = UE_ADDR_ANY,
233 .direction = UE_DIR_IN,
234 .bufsize = 16384, /* bytes */
235 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
236 .callback = axe_bulk_read_callback,
237 .timeout = 0, /* no timeout */
241 static const struct ax88772b_mfb ax88772b_mfb_table[] = {
242 { 0x8000, 0x8001, 2048 },
243 { 0x8100, 0x8147, 4096},
244 { 0x8200, 0x81EB, 6144},
245 { 0x8300, 0x83D7, 8192},
246 { 0x8400, 0x851E, 16384},
247 { 0x8500, 0x8666, 20480},
248 { 0x8600, 0x87AE, 24576},
249 { 0x8700, 0x8A3D, 32768}
252 static device_method_t axe_methods[] = {
253 /* Device interface */
254 DEVMETHOD(device_probe, axe_probe),
255 DEVMETHOD(device_attach, axe_attach),
256 DEVMETHOD(device_detach, axe_detach),
259 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
260 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
261 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
266 static driver_t axe_driver = {
268 .methods = axe_methods,
269 .size = sizeof(struct axe_softc),
272 static devclass_t axe_devclass;
274 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, NULL);
275 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, NULL, NULL);
276 MODULE_DEPEND(axe, uether, 1, 1, 1);
277 MODULE_DEPEND(axe, usb, 1, 1, 1);
278 MODULE_DEPEND(axe, ether, 1, 1, 1);
279 MODULE_DEPEND(axe, miibus, 1, 1, 1);
280 MODULE_VERSION(axe, 1);
282 static const struct usb_ether_methods axe_ue_methods = {
283 .ue_attach_post = axe_attach_post,
284 .ue_attach_post_sub = axe_attach_post_sub,
285 .ue_start = axe_start,
289 .ue_setmulti = axe_setmulti,
290 .ue_setpromisc = axe_setpromisc,
291 .ue_mii_upd = axe_ifmedia_upd,
292 .ue_mii_sts = axe_ifmedia_sts,
296 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
298 struct usb_device_request req;
303 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
304 UT_WRITE_VENDOR_DEVICE :
305 UT_READ_VENDOR_DEVICE);
306 req.bRequest = AXE_CMD_CMD(cmd);
307 USETW(req.wValue, val);
308 USETW(req.wIndex, index);
309 USETW(req.wLength, AXE_CMD_LEN(cmd));
311 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
317 axe_miibus_readreg(device_t dev, int phy, int reg)
319 struct axe_softc *sc = device_get_softc(dev);
323 locked = lockowned(&sc->sc_lock);
327 if(phy != sc->sc_phyno){
333 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
334 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
335 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
338 if (AXE_IS_772(sc) && reg == MII_BMSR) {
340 * BMSR of AX88772 indicates that it supports extended
341 * capability but the extended status register is
342 * revered for embedded ethernet PHY. So clear the
343 * extended capability bit of BMSR.
354 axe_miibus_writereg(device_t dev, int phy, int reg, int val)
356 struct axe_softc *sc = device_get_softc(dev);
360 locked = lockowned(&sc->sc_lock);
364 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
365 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
366 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
374 axe_miibus_statchg(device_t dev)
376 struct axe_softc *sc = device_get_softc(dev);
377 struct mii_data *mii = GET_MII(sc);
382 locked = lockowned(&sc->sc_lock);
386 ifp = uether_getifp(&sc->sc_ue);
387 if (mii == NULL || ifp == NULL ||
388 (ifp->if_flags & IFF_RUNNING) == 0)
391 sc->sc_flags &= ~AXE_FLAG_LINK;
392 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
393 (IFM_ACTIVE | IFM_AVALID)) {
394 switch (IFM_SUBTYPE(mii->mii_media_active)) {
397 sc->sc_flags |= AXE_FLAG_LINK;
400 if ((sc->sc_flags & AXE_FLAG_178) == 0)
402 sc->sc_flags |= AXE_FLAG_LINK;
403 DPRINTFN(11, "miibus_statchg: link should be up\n");
409 DPRINTFN(11, "miibus_statchg: not active or not valid: %x\n", mii->mii_media_status);
412 /* Lost link, do nothing. */
413 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
418 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
419 val |= AXE_MEDIA_FULL_DUPLEX;
420 if (AXE_IS_178_FAMILY(sc)) {
421 if ((IFM_OPTIONS(mii->mii_media_active) &
422 IFM_ETH_TXPAUSE) != 0)
423 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN;
424 if ((IFM_OPTIONS(mii->mii_media_active) &
425 IFM_ETH_RXPAUSE) != 0)
426 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN;
429 if (AXE_IS_178_FAMILY(sc)) {
430 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
431 if ((sc->sc_flags & AXE_FLAG_178) != 0)
432 val |= AXE_178_MEDIA_ENCK;
433 switch (IFM_SUBTYPE(mii->mii_media_active)) {
435 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
438 val |= AXE_178_MEDIA_100TX;
441 /* doesn't need to be handled */
445 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
447 device_printf(dev, "media change failed, error %d\n", err);
457 axe_ifmedia_upd(struct ifnet *ifp)
459 struct axe_softc *sc = ifp->if_softc;
460 struct mii_data *mii = GET_MII(sc);
461 struct mii_softc *miisc;
466 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
467 mii_phy_reset(miisc);
468 error = mii_mediachg(mii);
473 * Report current media status.
476 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
478 struct axe_softc *sc = ifp->if_softc;
479 struct mii_data *mii = GET_MII(sc);
483 ifmr->ifm_active = mii->mii_media_active;
484 ifmr->ifm_status = mii->mii_media_status;
489 axe_setmulti(struct usb_ether *ue)
491 struct axe_softc *sc = uether_getsc(ue);
492 struct ifnet *ifp = uether_getifp(ue);
493 struct ifmultiaddr *ifma;
496 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
500 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
501 rxmode = le16toh(rxmode);
503 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
504 rxmode |= AXE_RXCMD_ALLMULTI;
505 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
508 rxmode &= ~AXE_RXCMD_ALLMULTI;
510 /* if_maddr_rlock(ifp); */
511 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
513 if (ifma->ifma_addr->sa_family != AF_LINK)
515 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
516 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
517 hashtbl[h / 8] |= 1 << (h % 8);
519 /* if_maddr_runlock(ifp); */
521 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
522 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
526 axe_get_phyno(struct axe_softc *sc, int sel)
530 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
531 case PHY_TYPE_100_HOME:
533 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
535 case PHY_TYPE_SPECIAL:
539 case PHY_TYPE_NON_SUP:
549 #define AXE_GPIO_WRITE(x, y) do { \
550 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
551 uether_pause(ue, (y)); \
555 axe_ax88178_init(struct axe_softc *sc)
557 struct usb_ether *ue;
558 int gpio0, ledmode, phymode;
559 uint16_t eeprom, val;
562 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
564 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
565 eeprom = le16toh(eeprom);
566 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
568 /* if EEPROM is invalid we have to use to GPIO0 */
569 if (eeprom == 0xffff) {
570 phymode = AXE_PHY_MODE_MARVELL;
574 phymode = eeprom & 0x7f;
575 gpio0 = (eeprom & 0x80) ? 0 : 1;
576 ledmode = eeprom >> 8;
580 device_printf(sc->sc_ue.ue_dev,
581 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
583 /* Program GPIOs depending on PHY hardware. */
585 case AXE_PHY_MODE_MARVELL:
587 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
589 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
591 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
592 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
595 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
596 AXE_GPIO1_EN, hz / 3);
598 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
599 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
602 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
603 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
604 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
605 AXE_GPIO2_EN, hz / 4);
606 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
607 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
611 case AXE_PHY_MODE_CICADA:
612 case AXE_PHY_MODE_CICADA_V2:
613 case AXE_PHY_MODE_CICADA_V2_ASIX:
615 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
616 AXE_GPIO0_EN, hz / 32);
618 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
619 AXE_GPIO1_EN, hz / 32);
621 case AXE_PHY_MODE_AGERE:
622 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
623 AXE_GPIO1_EN, hz / 32);
624 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
625 AXE_GPIO2_EN, hz / 32);
626 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
627 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
628 AXE_GPIO2_EN, hz / 32);
630 case AXE_PHY_MODE_REALTEK_8211CL:
631 case AXE_PHY_MODE_REALTEK_8211BN:
632 case AXE_PHY_MODE_REALTEK_8251CL:
633 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
634 AXE_GPIO1 | AXE_GPIO1_EN;
635 AXE_GPIO_WRITE(val, hz / 32);
636 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
637 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
638 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
639 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
640 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
642 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
644 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
646 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
648 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
653 /* Unknown PHY model or no need to program GPIOs. */
658 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
659 uether_pause(ue, hz / 4);
661 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
662 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
663 uether_pause(ue, hz / 4);
664 /* Enable MII/GMII/RGMII interface to work with external PHY. */
665 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
666 uether_pause(ue, hz / 4);
668 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
672 axe_ax88772_init(struct axe_softc *sc)
674 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
675 uether_pause(&sc->sc_ue, hz / 16);
677 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
678 /* ask for the embedded PHY */
679 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
680 uether_pause(&sc->sc_ue, hz / 64);
682 /* power down and reset state, pin reset state */
683 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
684 AXE_SW_RESET_CLEAR, NULL);
685 uether_pause(&sc->sc_ue, hz / 16);
687 /* power down/reset state, pin operating state */
688 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
689 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
690 uether_pause(&sc->sc_ue, hz / 4);
692 /* power up, reset */
693 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
695 /* power up, operating */
696 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
697 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
699 /* ask for external PHY */
700 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
701 uether_pause(&sc->sc_ue, hz / 64);
703 /* power down internal PHY */
704 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
705 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
708 uether_pause(&sc->sc_ue, hz / 4);
709 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
713 axe_ax88772_phywake(struct axe_softc *sc)
715 struct usb_ether *ue;
718 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
719 /* Manually select internal(embedded) PHY - MAC mode. */
720 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
721 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
723 uether_pause(&sc->sc_ue, hz / 32);
726 * Manually select external PHY - MAC mode.
727 * Reverse MII/RMII is for AX88772A PHY mode.
729 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
730 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
731 uether_pause(&sc->sc_ue, hz / 32);
733 /* Take PHY out of power down. */
734 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
735 AXE_SW_RESET_IPRL, NULL);
736 uether_pause(&sc->sc_ue, hz / 4);
737 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
738 uether_pause(&sc->sc_ue, hz);
739 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
740 uether_pause(&sc->sc_ue, hz / 32);
741 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
742 uether_pause(&sc->sc_ue, hz / 32);
746 axe_ax88772a_init(struct axe_softc *sc)
748 struct usb_ether *ue;
752 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
753 axe_ax88772_phywake(sc);
755 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
759 axe_ax88772b_init(struct axe_softc *sc)
761 struct usb_ether *ue;
768 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
770 * Save PHY power saving configuration(high byte) and
771 * clear EEPROM checksum value(low byte).
773 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
774 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
777 * Auto-loaded default station address from internal ROM is
778 * 00:00:00:00:00:00 such that an explicit access to EEPROM
779 * is required to get real station address.
781 eaddr = ue->ue_eaddr;
782 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
783 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
785 eeprom = le16toh(eeprom);
786 *eaddr++ = (uint8_t)(eeprom & 0xFF);
787 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
790 axe_ax88772_phywake(sc);
792 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
795 #undef AXE_GPIO_WRITE
798 axe_reset(struct axe_softc *sc)
800 struct usb_config_descriptor *cd;
803 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
805 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_lock,
806 cd->bConfigurationValue);
808 DPRINTF("reset failed (ignored)\n");
810 /* Wait a little while for the chip to get its brains in order. */
811 uether_pause(&sc->sc_ue, hz / 100);
813 /* Reinitialize controller to achieve full reset. */
814 if (sc->sc_flags & AXE_FLAG_178)
815 axe_ax88178_init(sc);
816 else if (sc->sc_flags & AXE_FLAG_772)
817 axe_ax88772_init(sc);
818 else if (sc->sc_flags & AXE_FLAG_772A)
819 axe_ax88772a_init(sc);
820 else if (sc->sc_flags & AXE_FLAG_772B)
821 axe_ax88772b_init(sc);
825 axe_attach_post(struct usb_ether *ue)
827 struct axe_softc *sc = uether_getsc(ue);
830 * Load PHY indexes first. Needed by axe_xxx_init().
832 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
834 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
835 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
836 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
837 if (sc->sc_phyno == -1)
838 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
839 if (sc->sc_phyno == -1) {
840 device_printf(sc->sc_ue.ue_dev,
841 "no valid PHY address found, assuming PHY address 0\n");
845 /* Initialize controller and get station address. */
846 if (sc->sc_flags & AXE_FLAG_178) {
847 axe_ax88178_init(sc);
848 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
849 } else if (sc->sc_flags & AXE_FLAG_772) {
850 axe_ax88772_init(sc);
851 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
852 } else if (sc->sc_flags & AXE_FLAG_772A) {
853 axe_ax88772a_init(sc);
854 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
855 } else if (sc->sc_flags & AXE_FLAG_772B) {
856 axe_ax88772b_init(sc);
858 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
863 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
864 /* Set IPG values. */
865 sc->sc_ipgs[0] = 0x15;
866 sc->sc_ipgs[1] = 0x16;
867 sc->sc_ipgs[2] = 0x1A;
869 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
874 axe_attach_post_sub(struct usb_ether *ue)
876 struct axe_softc *sc;
881 sc = uether_getsc(ue);
883 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
884 ifp->if_start = uether_start;
885 ifp->if_ioctl = axe_ioctl;
886 ifp->if_init = uether_init;
887 ifq_set_maxlen(&ifp->if_snd, ifqmaxlen);
889 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
891 ifq_set_ready(&ifp->if_snd);
893 if (AXE_IS_178_FAMILY(sc))
894 ifp->if_capabilities |= IFCAP_VLAN_MTU;
895 if (sc->sc_flags & AXE_FLAG_772B) {
896 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM;
897 ifp->if_hwassist = AXE_CSUM_FEATURES;
899 * Checksum offloading of AX88772B also works with VLAN
900 * tagged frames but there is no way to take advantage
901 * of the feature because vlan(4) assumes
902 * IFCAP_VLAN_HWTAGGING is prerequisite condition to
903 * support checksum offloading with VLAN. VLAN hardware
904 * tagging support of AX88772B is very limited so it's
905 * not possible to announce IFCAP_VLAN_HWTAGGING.
908 ifp->if_capenable = ifp->if_capabilities;
909 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178))
910 adv_pause = MIIF_DOPAUSE;
914 error = mii_phy_probe(ue->ue_dev, &ue->ue_miibus,
915 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts);
917 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
918 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
919 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause);
925 * Probe for a AX88172 chip.
928 axe_probe(device_t dev)
930 struct usb_attach_arg *uaa = device_get_ivars(dev);
932 if (uaa->usb_mode != USB_MODE_HOST)
934 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
936 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
939 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
943 * Attach the interface. Allocate softc structures, do ifmedia
944 * setup and ethernet/BPF attach.
947 axe_attach(device_t dev)
949 struct usb_attach_arg *uaa = device_get_ivars(dev);
950 struct axe_softc *sc = device_get_softc(dev);
951 struct usb_ether *ue = &sc->sc_ue;
955 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
957 device_set_usb_desc(dev);
959 lockinit(&sc->sc_lock, device_get_nameunit(dev), 0, 0);
961 iface_index = AXE_IFACE_IDX;
962 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
963 axe_config, AXE_N_TRANSFER, sc, &sc->sc_lock);
965 device_printf(dev, "allocating USB transfers failed\n");
971 ue->ue_udev = uaa->device;
972 ue->ue_lock = &sc->sc_lock;
973 ue->ue_methods = &axe_ue_methods;
975 error = uether_ifattach(ue);
977 device_printf(dev, "could not attach interface\n");
980 return (0); /* success */
984 return (ENXIO); /* failure */
988 axe_detach(device_t dev)
990 struct axe_softc *sc = device_get_softc(dev);
991 struct usb_ether *ue = &sc->sc_ue;
993 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
995 lockuninit(&sc->sc_lock);
1000 #if (AXE_BULK_BUF_SIZE >= 0x10000)
1001 #error "Please update axe_bulk_read_callback()!"
1005 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
1007 struct axe_softc *sc = usbd_xfer_softc(xfer);
1008 struct usb_ether *ue = &sc->sc_ue;
1009 struct usb_page_cache *pc;
1012 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
1014 switch (USB_GET_STATE(xfer)) {
1015 case USB_ST_TRANSFERRED:
1016 pc = usbd_xfer_get_frame(xfer, 0);
1017 axe_rx_frame(ue, pc, actlen);
1022 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
1023 usbd_transfer_submit(xfer);
1027 default: /* Error */
1028 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
1030 if (error != USB_ERR_CANCELLED) {
1031 /* try to clear stall first */
1032 usbd_xfer_set_stall(xfer);
1041 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
1043 struct axe_softc *sc;
1044 struct axe_sframe_hdr hdr;
1045 struct axe_csum_hdr csum_hdr;
1046 int error, len, pos;
1048 sc = uether_getsc(ue);
1052 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
1053 while (pos < actlen) {
1054 if ((int)(pos + sizeof(hdr)) > actlen) {
1055 /* too little data */
1059 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
1061 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
1067 len = le16toh(hdr.len);
1068 if (pos + len > actlen) {
1069 /* invalid length */
1073 axe_rxeof(ue, pc, pos, len, NULL);
1074 pos += len + (len % 2);
1076 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
1077 while (pos < actlen) {
1078 if ((int)(pos + sizeof(csum_hdr)) > actlen) {
1079 /* too little data */
1083 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr));
1085 csum_hdr.len = le16toh(csum_hdr.len);
1086 csum_hdr.ilen = le16toh(csum_hdr.ilen);
1087 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
1088 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
1089 AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
1096 * Get total transferred frame length including
1097 * checksum header. The length should be multiple
1100 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len);
1101 len = (len + 3) & ~3;
1102 if (pos + len > actlen) {
1103 /* invalid length */
1107 axe_rxeof(ue, pc, pos + sizeof(csum_hdr),
1108 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr);
1112 axe_rxeof(ue, pc, 0, actlen, NULL);
1115 IFNET_STAT_INC(ue->ue_ifp, ierrors, 1);
1120 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
1121 unsigned int len, struct axe_csum_hdr *csum_hdr)
1123 struct ifnet *ifp = ue->ue_ifp;
1126 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1127 IFNET_STAT_INC(ifp, ierrors, 1);
1131 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1133 IFNET_STAT_INC(ifp, iqdrops, 1);
1136 m->m_len = m->m_pkthdr.len = MCLBYTES;
1137 m_adj(m, ETHER_ALIGN);
1139 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1141 IFNET_STAT_INC(ifp, ipackets, 1);
1142 m->m_pkthdr.rcvif = ifp;
1143 m->m_pkthdr.len = m->m_len = len;
1145 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) {
1146 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR |
1147 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) {
1148 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1150 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1151 AXE_CSUM_HDR_L4_TYPE_TCP ||
1152 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1153 AXE_CSUM_HDR_L4_TYPE_UDP) {
1154 m->m_pkthdr.csum_flags |=
1155 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1156 m->m_pkthdr.csum_data = 0xffff;
1161 IF_ENQUEUE(&ue->ue_rxq, m);
1165 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1166 #error "Please update axe_bulk_write_callback()!"
1170 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1172 struct axe_softc *sc = usbd_xfer_softc(xfer);
1173 struct axe_sframe_hdr hdr;
1174 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
1175 struct usb_page_cache *pc;
1179 DPRINTFN(11, "starting transfer\n");
1181 switch (USB_GET_STATE(xfer)) {
1182 case USB_ST_TRANSFERRED:
1183 DPRINTFN(11, "transfer complete\n");
1185 ifq_clr_oactive(&ifp->if_snd);
1190 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1191 ifq_is_oactive(&ifp->if_snd)) {
1193 * Don't send anything if there is no link or
1194 * controller is busy.
1196 DPRINTFN(11, "controller busy: sc_flags: %x if_flags %x\n",sc->sc_flags, ifp->if_flags);
1200 DPRINTFN(11, "copying frames, 16 at a time\n");
1201 for (nframes = 0; nframes < 16 &&
1202 !ifq_is_empty(&ifp->if_snd); nframes++) {
1203 m = ifq_dequeue(&ifp->if_snd);
1206 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1209 pc = usbd_xfer_get_frame(xfer, nframes);
1210 if (AXE_IS_178_FAMILY(sc)) {
1211 hdr.len = htole16(m->m_pkthdr.len);
1212 hdr.ilen = ~hdr.len;
1214 * If upper stack computed checksum, driver
1215 * should tell controller not to insert
1216 * computed checksum for checksum offloading
1217 * enabled controller.
1219 if (ifp->if_capabilities & IFCAP_TXCSUM) {
1220 if ((m->m_pkthdr.csum_flags &
1221 AXE_CSUM_FEATURES) != 0)
1223 AXE_TX_CSUM_PSEUDO_HDR);
1228 DPRINTFN(11, "usbd copy in\n");
1229 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1231 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1232 pos += m->m_pkthdr.len;
1233 if ((pos % 512) == 0) {
1236 usbd_copy_in(pc, pos, &hdr,
1241 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1242 pos += m->m_pkthdr.len;
1247 * Update TX packet counter here. This is not
1248 * correct way but it seems that there is no way
1249 * to know how many packets are sent at the end
1250 * of transfer because controller combines
1251 * multiple writes into single one if there is
1252 * room in TX buffer of controller.
1254 IFNET_STAT_INC(ifp, opackets, 1);
1257 * if there's a BPF listener, bounce a copy
1258 * of this frame to him:
1264 /* Set frame length. */
1265 usbd_xfer_set_frame_len(xfer, nframes, pos);
1268 usbd_xfer_set_frames(xfer, nframes);
1269 DPRINTFN(5, "submitting transfer\n");
1270 usbd_transfer_submit(xfer);
1271 ifq_set_oactive(&ifp->if_snd);
1275 default: /* Error */
1276 DPRINTFN(11, "transfer error, %s\n",
1277 usbd_errstr(error));
1279 IFNET_STAT_INC(ifp, oerrors, 1);
1280 ifq_clr_oactive(&ifp->if_snd);
1281 if (error != USB_ERR_CANCELLED) {
1282 /* try to clear stall first */
1283 usbd_xfer_set_stall(xfer);
1292 axe_tick(struct usb_ether *ue)
1294 struct axe_softc *sc = uether_getsc(ue);
1295 struct mii_data *mii = GET_MII(sc);
1297 AXE_LOCK_ASSERT(sc);
1300 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1301 axe_miibus_statchg(ue->ue_dev);
1302 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1308 axe_start(struct usb_ether *ue)
1310 struct axe_softc *sc = uether_getsc(ue);
1313 * start the USB transfers, if not already started:
1315 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1316 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1320 axe_csum_cfg(struct usb_ether *ue)
1322 struct axe_softc *sc;
1324 uint16_t csum1, csum2;
1326 sc = uether_getsc(ue);
1327 AXE_LOCK_ASSERT(sc);
1329 if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1330 ifp = uether_getifp(ue);
1333 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1334 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP |
1336 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1339 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1340 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE |
1341 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP |
1343 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1348 axe_init(struct usb_ether *ue)
1350 struct axe_softc *sc = uether_getsc(ue);
1351 struct ifnet *ifp = uether_getifp(ue);
1354 AXE_LOCK_ASSERT(sc);
1357 if ((ifp->if_flags & IFF_RUNNING) != 0)
1360 /* Cancel pending I/O */
1365 /* Set MAC address and transmitter IPG values. */
1366 if (AXE_IS_178_FAMILY(sc)) {
1367 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1368 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1369 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1371 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1372 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1373 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1374 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1377 if (AXE_IS_178_FAMILY(sc)) {
1378 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1379 if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1380 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK;
1381 sc->sc_flags |= AXE_FLAG_CSUM_FRAME;
1383 sc->sc_lenmask = AXE_HDR_LEN_MASK;
1384 sc->sc_flags |= AXE_FLAG_STD_FRAME;
1388 /* Configure TX/RX checksum offloading. */
1391 if (sc->sc_flags & AXE_FLAG_772B) {
1392 /* AX88772B uses different maximum frame burst configuration. */
1393 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1394 ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1395 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1398 /* Enable receiver, set RX mode. */
1399 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1400 if (AXE_IS_178_FAMILY(sc)) {
1401 if (sc->sc_flags & AXE_FLAG_772B) {
1403 * Select RX header format type 1. Aligning IP
1404 * header on 4 byte boundary is not needed when
1405 * checksum offloading feature is not used
1406 * because we always copy the received frame in
1407 * RX handler. When RX checksum offloading is
1408 * active, aligning IP header is required to
1409 * reflect actual frame length including RX
1412 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1413 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1414 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN;
1417 * Default Rx buffer size is too small to get
1418 * maximum performance.
1420 rxmode |= AXE_178_RXCMD_MFB_16384;
1423 rxmode |= AXE_172_RXCMD_UNICAST;
1426 /* If we want promiscuous mode, set the allframes bit. */
1427 if (ifp->if_flags & IFF_PROMISC)
1428 rxmode |= AXE_RXCMD_PROMISC;
1430 if (ifp->if_flags & IFF_BROADCAST)
1431 rxmode |= AXE_RXCMD_BROADCAST;
1433 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1435 /* Load the multicast filter. */
1438 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1441 ifp->if_flags |= IFF_RUNNING;
1443 /* Switch to selected media. */
1444 axe_ifmedia_upd(ifp);
1448 axe_setpromisc(struct usb_ether *ue)
1450 struct axe_softc *sc = uether_getsc(ue);
1451 struct ifnet *ifp = uether_getifp(ue);
1454 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1456 rxmode = le16toh(rxmode);
1458 if (ifp->if_flags & IFF_PROMISC) {
1459 rxmode |= AXE_RXCMD_PROMISC;
1461 rxmode &= ~AXE_RXCMD_PROMISC;
1464 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1470 axe_stop(struct usb_ether *ue)
1472 struct axe_softc *sc = uether_getsc(ue);
1473 struct ifnet *ifp = uether_getifp(ue);
1475 AXE_LOCK_ASSERT(sc);
1478 ifp->if_flags &= ~IFF_RUNNING;
1479 ifq_clr_oactive(&ifp->if_snd);
1481 sc->sc_flags &= ~AXE_FLAG_LINK;
1484 * stop all the transfers, if not already stopped:
1486 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1487 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1491 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *uc)
1493 struct usb_ether *ue = ifp->if_softc;
1494 struct axe_softc *sc;
1496 int error, mask, reinit;
1498 sc = uether_getsc(ue);
1499 ifr = (struct ifreq *)data;
1502 if (cmd == SIOCSIFCAP) {
1504 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1505 if ((mask & IFCAP_TXCSUM) != 0 &&
1506 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1507 ifp->if_capenable ^= IFCAP_TXCSUM;
1508 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1509 ifp->if_hwassist |= AXE_CSUM_FEATURES;
1511 ifp->if_hwassist &= ~AXE_CSUM_FEATURES;
1514 if ((mask & IFCAP_RXCSUM) != 0 &&
1515 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1516 ifp->if_capenable ^= IFCAP_RXCSUM;
1519 if (reinit > 0 && ifp->if_flags & IFF_RUNNING)
1520 ifp->if_flags &= ~IFF_RUNNING;
1527 error = uether_ioctl(ifp, cmd, data, uc);