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40 #define IGB_MAX_RING_82575 4
41 #define IGB_MAX_RING_I350 8
42 #define IGB_MAX_RING_82580 8
43 #define IGB_MAX_RING_82576 16
44 #define IGB_MIN_RING 1
47 * Max TX/RX interrupt bits
49 #define IGB_MAX_TXRXINT_82575 4 /* XXX not used */
50 #define IGB_MAX_TXRXINT_I350 8
51 #define IGB_MAX_TXRXINT_82580 8
52 #define IGB_MAX_TXRXINT_82576 16
53 #define IGB_MIN_TXRXINT 2 /* XXX VF? */
56 * IGB_TXD: Maximum number of Transmit Descriptors
58 * This value is the number of transmit descriptors allocated by the driver.
59 * Increasing this value allows the driver to queue more transmits. Each
60 * descriptor is 16 bytes.
61 * Since TDLEN should be multiple of 128bytes, the number of transmit
62 * desscriptors should meet the following condition.
63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
65 #define IGB_MIN_TXD 256
66 #define IGB_DEFAULT_TXD 1024
67 #define IGB_MAX_TXD 4096
70 * IGB_RXD: Maximum number of Transmit Descriptors
72 * This value is the number of receive descriptors allocated by the driver.
73 * Increasing this value allows the driver to buffer more incoming packets.
74 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
75 * descriptor. The maximum MTU size is 16110.
76 * Since TDLEN should be multiple of 128bytes, the number of transmit
77 * desscriptors should meet the following condition.
78 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
80 #define IGB_MIN_RXD 256
81 #define IGB_DEFAULT_RXD 1024
82 #define IGB_MAX_RXD 4096
85 * This parameter controls when the driver calls the routine to reclaim
86 * transmit descriptors. Cleaning earlier seems a win.
88 #define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2)
91 * This parameter controls whether or not autonegotation is enabled.
92 * 0 - Disable autonegotiation
93 * 1 - Enable autonegotiation
98 * This parameter control whether or not the driver will wait for
99 * autonegotiation to complete.
100 * 1 - Wait for autonegotiation to complete
101 * 0 - Don't wait for autonegotiation to complete
103 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
105 /* Tunables -- End */
107 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
108 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
111 #define AUTO_ALL_MODES 0
113 /* PHY master/slave setting */
114 #define IGB_MASTER_SLAVE e1000_ms_hw_default
117 * Micellaneous constants
119 #define IGB_VENDOR_ID 0x8086
121 #define IGB_JUMBO_PBA 0x00000028
122 #define IGB_DEFAULT_PBA 0x00000030
123 #define IGB_SMARTSPEED_DOWNSHIFT 3
124 #define IGB_SMARTSPEED_MAX 15
125 #define IGB_MAX_LOOP 10
127 #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
128 #define IGB_RX_HTHRESH 8
129 #define IGB_RX_WTHRESH 1
131 #define IGB_TX_PTHRESH 8
132 #define IGB_TX_HTHRESH 1
133 #define IGB_TX_WTHRESH 16
135 #define MAX_NUM_MULTICAST_ADDRESSES 128
136 #define IGB_FC_PAUSE_TIME 0x0680
138 #define IGB_INTR_RATE 10000
141 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
142 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
143 * also optimize cache line size effect. H/W supports up to cache line size 128.
145 #define IGB_DBA_ALIGN 128
147 /* PCI Config defines */
148 #define IGB_MSIX_BAR 3
150 #define IGB_MAX_SCATTER 64
151 #define IGB_VFTA_SIZE 128
152 #define IGB_TSO_SIZE (65535 + \
153 sizeof(struct ether_vlan_header))
154 #define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
155 #define IGB_HDR_BUF 128
156 #define IGB_PKTTYPE_MASK 0x0000FFF0
158 #define IGB_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
159 #define IGB_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
160 #define IGB_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
163 /* One for TX csum offloading desc, the other 2 are reserved */
164 #define IGB_TX_RESERVED 3
166 /* Large enough for 64K TSO */
167 #define IGB_TX_SPARE 32
169 #define IGB_TX_OACTIVE_MAX 64
171 /* main + 16x RX + 16x TX */
172 #define IGB_NSERIALIZE 33
174 #define IGB_NRSSRK 10
175 #define IGB_RSSRK_SIZE 4
176 #define IGB_RSSRK_VAL(key, i) (key[(i) * IGB_RSSRK_SIZE] | \
177 key[(i) * IGB_RSSRK_SIZE + 1] << 8 | \
178 key[(i) * IGB_RSSRK_SIZE + 2] << 16 | \
179 key[(i) * IGB_RSSRK_SIZE + 3] << 24)
182 #define IGB_RETA_SIZE 4
183 #define IGB_RETA_SHIFT 0
184 #define IGB_RETA_SHIFT_82575 6
189 * Bus dma information structure
192 bus_addr_t dma_paddr;
194 bus_dma_tag_t dma_tag;
195 bus_dmamap_t dma_map;
199 * Transmit ring: one per queue
202 struct lwkt_serialize tx_serialize;
203 struct igb_softc *sc;
205 struct igb_dma txdma;
206 bus_dma_tag_t tx_hdr_dtag;
207 bus_dmamap_t tx_hdr_dmap;
208 bus_addr_t tx_hdr_paddr;
209 struct e1000_tx_desc *tx_base;
211 uint32_t next_avail_desc;
212 uint32_t next_to_clean;
215 struct igb_tx_buf *tx_buf;
216 bus_dma_tag_t tx_tag;
223 uint32_t tx_intr_mask;
225 u_long no_desc_avail;
228 u_long ctx_try_pullup;
232 u_long ctx_pullup1_failed;
234 u_long ctx_pullup2_failed;
238 * Receive ring: one per queue
241 struct lwkt_serialize rx_serialize;
242 struct igb_softc *sc;
244 struct igb_dma rxdma;
245 union e1000_adv_rx_desc *rx_base;
248 uint32_t next_to_check;
249 struct igb_rx_buf *rx_buf;
250 bus_dma_tag_t rx_tag;
251 bus_dmamap_t rx_sparemap;
253 uint32_t rx_intr_mask;
256 * First/last mbuf pointers, for
257 * collecting multisegment RX packets.
267 struct arpcom arpcom;
270 struct e1000_osdep osdep;
273 #define IGB_FLAG_SHARED_INTR 0x1
274 #define IGB_FLAG_HAS_MGMT 0x2
276 bus_dma_tag_t parent_tag;
279 struct resource *mem_res;
281 struct ifmedia media;
282 struct callout timer;
286 struct resource *intr_res;
292 uint16_t vf_ifp; /* a VF interface */
294 /* Management and WOL features */
297 /* Info about the interface */
300 uint16_t link_duplex;
302 uint32_t dma_coalesce;
304 /* Multicast array pointer */
310 struct lwkt_serialize *serializes[IGB_NSERIALIZE];
311 struct lwkt_serialize main_serialize;
320 struct igb_tx_ring *tx_rings;
327 struct igb_rx_ring *rx_rings;
329 /* Misc stats maintained by the driver */
331 u_long mbuf_defrag_failed;
332 u_long no_tx_dma_setup;
333 u_long watchdog_events;
335 u_long device_control;
339 u_long packet_buf_alloc_rx;
340 u_long packet_buf_alloc_tx;
342 /* sysctl tree glue */
343 struct sysctl_ctx_list sysctl_ctx;
344 struct sysctl_oid *sysctl_tree;
349 #define IGB_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1)
353 bus_dmamap_t map; /* bus_dma map for packet */
358 bus_dmamap_t map; /* bus_dma map for packet */
362 #define UPDATE_VF_REG(reg, last, cur) \
364 uint32_t new = E1000_READ_REG(hw, reg); \
366 cur += 0x100000000LL; \
368 cur &= 0xFFFFFFFF00000000LL; \
372 #define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc)
373 #define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc)
375 #endif /* _IF_IGB_H_ */