2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
68 * SERIALIZATION API RULES:
70 * - If the driver uses the same serializer for the interrupt as for the
71 * ifnet, most of the serialization will be done automatically for the
74 * - ifmedia entry points will be serialized by the ifmedia code using the
77 * - if_* entry points except for if_input will be serialized by the IF
78 * and protocol layers.
80 * - The device driver must be sure to serialize access from timeout code
81 * installed by the device driver.
83 * - The device driver typically holds the serializer at the time it wishes
86 * - We must call lwkt_serialize_handler_enable() prior to enabling the
87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
88 * the hardware interrupt in order to avoid handler execution races from
89 * scheduled interrupt threads.
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
96 #include "opt_polling.h"
98 #include <sys/param.h>
100 #include <sys/endian.h>
101 #include <sys/interrupt.h>
102 #include <sys/kernel.h>
104 #include <sys/malloc.h>
105 #include <sys/mbuf.h>
106 #include <sys/proc.h>
107 #include <sys/rman.h>
108 #include <sys/serialize.h>
109 #include <sys/socket.h>
110 #include <sys/sockio.h>
111 #include <sys/sysctl.h>
112 #include <sys/systm.h>
115 #include <net/ethernet.h>
117 #include <net/if_arp.h>
118 #include <net/if_dl.h>
119 #include <net/if_media.h>
120 #include <net/ifq_var.h>
121 #include <net/vlan/if_vlan_var.h>
122 #include <net/vlan/if_vlan_ether.h>
124 #include <netinet/ip.h>
125 #include <netinet/tcp.h>
126 #include <netinet/udp.h>
128 #include <bus/pci/pcivar.h>
129 #include <bus/pci/pcireg.h>
131 #include <dev/netif/ig_hal/e1000_api.h>
132 #include <dev/netif/ig_hal/e1000_82571.h>
133 #include <dev/netif/em/if_em.h>
135 #define EM_NAME "Intel(R) PRO/1000 Network Connection "
136 #define EM_VER " 7.2.4"
138 #define _EM_DEVICE(id, ret) \
139 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
140 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
141 #define EM_DEVICE(id) _EM_DEVICE(id, 0)
142 #define EM_DEVICE_NULL { 0, 0, 0, NULL }
144 static const struct em_vendor_info em_vendor_info_array[] = {
146 EM_DEVICE(82540EM_LOM),
148 EM_DEVICE(82540EP_LOM),
149 EM_DEVICE(82540EP_LP),
153 EM_DEVICE(82541ER_LOM),
154 EM_DEVICE(82541EI_MOBILE),
156 EM_DEVICE(82541GI_LF),
157 EM_DEVICE(82541GI_MOBILE),
161 EM_DEVICE(82543GC_FIBER),
162 EM_DEVICE(82543GC_COPPER),
164 EM_DEVICE(82544EI_COPPER),
165 EM_DEVICE(82544EI_FIBER),
166 EM_DEVICE(82544GC_COPPER),
167 EM_DEVICE(82544GC_LOM),
169 EM_DEVICE(82545EM_COPPER),
170 EM_DEVICE(82545EM_FIBER),
171 EM_DEVICE(82545GM_COPPER),
172 EM_DEVICE(82545GM_FIBER),
173 EM_DEVICE(82545GM_SERDES),
175 EM_DEVICE(82546EB_COPPER),
176 EM_DEVICE(82546EB_FIBER),
177 EM_DEVICE(82546EB_QUAD_COPPER),
178 EM_DEVICE(82546GB_COPPER),
179 EM_DEVICE(82546GB_FIBER),
180 EM_DEVICE(82546GB_SERDES),
181 EM_DEVICE(82546GB_PCIE),
182 EM_DEVICE(82546GB_QUAD_COPPER),
183 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
186 EM_DEVICE(82547EI_MOBILE),
189 EM_EMX_DEVICE(82571EB_COPPER),
190 EM_EMX_DEVICE(82571EB_FIBER),
191 EM_EMX_DEVICE(82571EB_SERDES),
192 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
193 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
194 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
195 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
196 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
197 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
198 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
200 EM_EMX_DEVICE(82572EI_COPPER),
201 EM_EMX_DEVICE(82572EI_FIBER),
202 EM_EMX_DEVICE(82572EI_SERDES),
203 EM_EMX_DEVICE(82572EI),
205 EM_EMX_DEVICE(82573E),
206 EM_EMX_DEVICE(82573E_IAMT),
207 EM_EMX_DEVICE(82573L),
211 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
212 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
213 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
214 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
216 EM_DEVICE(ICH8_IGP_M_AMT),
217 EM_DEVICE(ICH8_IGP_AMT),
218 EM_DEVICE(ICH8_IGP_C),
220 EM_DEVICE(ICH8_IFE_GT),
221 EM_DEVICE(ICH8_IFE_G),
222 EM_DEVICE(ICH8_IGP_M),
223 EM_DEVICE(ICH8_82567V_3),
225 EM_DEVICE(ICH9_IGP_M_AMT),
226 EM_DEVICE(ICH9_IGP_AMT),
227 EM_DEVICE(ICH9_IGP_C),
228 EM_DEVICE(ICH9_IGP_M),
229 EM_DEVICE(ICH9_IGP_M_V),
231 EM_DEVICE(ICH9_IFE_GT),
232 EM_DEVICE(ICH9_IFE_G),
235 EM_EMX_DEVICE(82574L),
236 EM_EMX_DEVICE(82574LA),
238 EM_DEVICE(ICH10_R_BM_LM),
239 EM_DEVICE(ICH10_R_BM_LF),
240 EM_DEVICE(ICH10_R_BM_V),
241 EM_DEVICE(ICH10_D_BM_LM),
242 EM_DEVICE(ICH10_D_BM_LF),
243 EM_DEVICE(ICH10_D_BM_V),
245 EM_DEVICE(PCH_M_HV_LM),
246 EM_DEVICE(PCH_M_HV_LC),
247 EM_DEVICE(PCH_D_HV_DM),
248 EM_DEVICE(PCH_D_HV_DC),
250 EM_DEVICE(PCH2_LV_LM),
251 EM_DEVICE(PCH2_LV_V),
253 /* required last entry */
257 static int em_probe(device_t);
258 static int em_attach(device_t);
259 static int em_detach(device_t);
260 static int em_shutdown(device_t);
261 static int em_suspend(device_t);
262 static int em_resume(device_t);
264 static void em_init(void *);
265 static void em_stop(struct adapter *);
266 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
267 static void em_start(struct ifnet *);
268 #ifdef DEVICE_POLLING
269 static void em_poll(struct ifnet *, enum poll_cmd, int);
271 static void em_watchdog(struct ifnet *);
272 static void em_media_status(struct ifnet *, struct ifmediareq *);
273 static int em_media_change(struct ifnet *);
274 static void em_timer(void *);
276 static void em_intr(void *);
277 static void em_intr_mask(void *);
278 static void em_intr_body(struct adapter *, boolean_t);
279 static void em_rxeof(struct adapter *, int);
280 static void em_txeof(struct adapter *);
281 static void em_tx_collect(struct adapter *);
282 static void em_tx_purge(struct adapter *);
283 static void em_enable_intr(struct adapter *);
284 static void em_disable_intr(struct adapter *);
286 static int em_dma_malloc(struct adapter *, bus_size_t,
287 struct em_dma_alloc *);
288 static void em_dma_free(struct adapter *, struct em_dma_alloc *);
289 static void em_init_tx_ring(struct adapter *);
290 static int em_init_rx_ring(struct adapter *);
291 static int em_create_tx_ring(struct adapter *);
292 static int em_create_rx_ring(struct adapter *);
293 static void em_destroy_tx_ring(struct adapter *, int);
294 static void em_destroy_rx_ring(struct adapter *, int);
295 static int em_newbuf(struct adapter *, int, int);
296 static int em_encap(struct adapter *, struct mbuf **);
297 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
299 static int em_txcsum(struct adapter *, struct mbuf *,
300 uint32_t *, uint32_t *);
301 static int em_tso_pullup(struct adapter *, struct mbuf **);
302 static int em_tso_setup(struct adapter *, struct mbuf *,
303 uint32_t *, uint32_t *);
305 static int em_get_hw_info(struct adapter *);
306 static int em_is_valid_eaddr(const uint8_t *);
307 static int em_alloc_pci_res(struct adapter *);
308 static void em_free_pci_res(struct adapter *);
309 static int em_reset(struct adapter *);
310 static void em_setup_ifp(struct adapter *);
311 static void em_init_tx_unit(struct adapter *);
312 static void em_init_rx_unit(struct adapter *);
313 static void em_update_stats(struct adapter *);
314 static void em_set_promisc(struct adapter *);
315 static void em_disable_promisc(struct adapter *);
316 static void em_set_multi(struct adapter *);
317 static void em_update_link_status(struct adapter *);
318 static void em_smartspeed(struct adapter *);
319 static void em_set_itr(struct adapter *, uint32_t);
320 static void em_disable_aspm(struct adapter *);
322 /* Hardware workarounds */
323 static int em_82547_fifo_workaround(struct adapter *, int);
324 static void em_82547_update_fifo_head(struct adapter *, int);
325 static int em_82547_tx_fifo_reset(struct adapter *);
326 static void em_82547_move_tail(void *);
327 static void em_82547_move_tail_serialized(struct adapter *);
328 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
330 static void em_print_debug_info(struct adapter *);
331 static void em_print_nvm_info(struct adapter *);
332 static void em_print_hw_stats(struct adapter *);
334 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
335 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
336 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
337 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
338 static void em_add_sysctl(struct adapter *adapter);
340 /* Management and WOL Support */
341 static void em_get_mgmt(struct adapter *);
342 static void em_rel_mgmt(struct adapter *);
343 static void em_get_hw_control(struct adapter *);
344 static void em_rel_hw_control(struct adapter *);
345 static void em_enable_wol(device_t);
347 static device_method_t em_methods[] = {
348 /* Device interface */
349 DEVMETHOD(device_probe, em_probe),
350 DEVMETHOD(device_attach, em_attach),
351 DEVMETHOD(device_detach, em_detach),
352 DEVMETHOD(device_shutdown, em_shutdown),
353 DEVMETHOD(device_suspend, em_suspend),
354 DEVMETHOD(device_resume, em_resume),
358 static driver_t em_driver = {
361 sizeof(struct adapter),
364 static devclass_t em_devclass;
366 DECLARE_DUMMY_MODULE(if_em);
367 MODULE_DEPEND(em, ig_hal, 1, 1, 1);
368 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
373 static int em_int_throttle_ceil = EM_DEFAULT_ITR;
374 static int em_rxd = EM_DEFAULT_RXD;
375 static int em_txd = EM_DEFAULT_TXD;
376 static int em_smart_pwr_down = 0;
378 /* Controls whether promiscuous also shows bad packets */
379 static int em_debug_sbp = FALSE;
381 static int em_82573_workaround = 1;
382 static int em_msi_enable = 1;
384 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
385 TUNABLE_INT("hw.em.rxd", &em_rxd);
386 TUNABLE_INT("hw.em.txd", &em_txd);
387 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
388 TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
389 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
390 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable);
392 /* Global used in WOL setup with multiport cards */
393 static int em_global_quad_port_a = 0;
395 /* Set this to one to display debug statistics */
396 static int em_display_debug_stats = 0;
398 #if !defined(KTR_IF_EM)
399 #define KTR_IF_EM KTR_ALL
401 KTR_INFO_MASTER(if_em);
402 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin");
403 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end");
404 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet");
405 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet");
406 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean");
407 #define logif(name) KTR_LOG(if_em_ ## name)
410 em_probe(device_t dev)
412 const struct em_vendor_info *ent;
415 vid = pci_get_vendor(dev);
416 did = pci_get_device(dev);
418 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
419 if (vid == ent->vendor_id && did == ent->device_id) {
420 device_set_desc(dev, ent->desc);
421 device_set_async_attach(dev, TRUE);
429 em_attach(device_t dev)
431 struct adapter *adapter = device_get_softc(dev);
432 struct ifnet *ifp = &adapter->arpcom.ac_if;
435 uint16_t eeprom_data, device_id, apme_mask;
436 driver_intr_t *intr_func;
438 adapter->dev = adapter->osdep.dev = dev;
440 callout_init_mp(&adapter->timer);
441 callout_init_mp(&adapter->tx_fifo_timer);
443 /* Determine hardware and mac info */
444 error = em_get_hw_info(adapter);
446 device_printf(dev, "Identify hardware failed\n");
450 /* Setup PCI resources */
451 error = em_alloc_pci_res(adapter);
453 device_printf(dev, "Allocation of PCI resources failed\n");
458 * For ICH8 and family we need to map the flash memory,
459 * and this must happen after the MAC is identified.
461 if (adapter->hw.mac.type == e1000_ich8lan ||
462 adapter->hw.mac.type == e1000_ich9lan ||
463 adapter->hw.mac.type == e1000_ich10lan ||
464 adapter->hw.mac.type == e1000_pchlan ||
465 adapter->hw.mac.type == e1000_pch2lan) {
466 adapter->flash_rid = EM_BAR_FLASH;
468 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
469 &adapter->flash_rid, RF_ACTIVE);
470 if (adapter->flash == NULL) {
471 device_printf(dev, "Mapping of Flash failed\n");
475 adapter->osdep.flash_bus_space_tag =
476 rman_get_bustag(adapter->flash);
477 adapter->osdep.flash_bus_space_handle =
478 rman_get_bushandle(adapter->flash);
481 * This is used in the shared code
482 * XXX this goof is actually not used.
484 adapter->hw.flash_address = (uint8_t *)adapter->flash;
487 switch (adapter->hw.mac.type) {
491 * Pullup extra 4bytes into the first data segment, see:
492 * 82571/82572 specification update errata #7
495 * 4bytes instead of 2bytes, which are mentioned in the
496 * errata, are pulled; mainly to keep rest of the data
499 adapter->flags |= EM_FLAG_TSO_PULLEX;
504 case e1000_80003es2lan:
505 adapter->flags |= EM_FLAG_TSO;
512 /* Do Shared Code initialization */
513 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
514 device_printf(dev, "Setup of Shared code failed\n");
519 e1000_get_bus_info(&adapter->hw);
522 * Validate number of transmit and receive descriptors. It
523 * must not exceed hardware maximum, and must be multiple
524 * of E1000_DBA_ALIGN.
526 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
527 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
528 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
529 em_txd < EM_MIN_TXD) {
530 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
531 EM_DEFAULT_TXD, em_txd);
532 adapter->num_tx_desc = EM_DEFAULT_TXD;
534 adapter->num_tx_desc = em_txd;
536 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
537 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
538 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
539 em_rxd < EM_MIN_RXD) {
540 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
541 EM_DEFAULT_RXD, em_rxd);
542 adapter->num_rx_desc = EM_DEFAULT_RXD;
544 adapter->num_rx_desc = em_rxd;
547 adapter->hw.mac.autoneg = DO_AUTO_NEG;
548 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
549 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
550 adapter->rx_buffer_len = MCLBYTES;
553 * Interrupt throttle rate
555 if (em_int_throttle_ceil == 0) {
556 adapter->int_throttle_ceil = 0;
558 int throttle = em_int_throttle_ceil;
561 throttle = EM_DEFAULT_ITR;
563 /* Recalculate the tunable value to get the exact frequency. */
564 throttle = 1000000000 / 256 / throttle;
566 /* Upper 16bits of ITR is reserved and should be zero */
567 if (throttle & 0xffff0000)
568 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
570 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
573 e1000_init_script_state_82541(&adapter->hw, TRUE);
574 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
577 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
578 adapter->hw.phy.mdix = AUTO_ALL_MODES;
579 adapter->hw.phy.disable_polarity_correction = FALSE;
580 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
583 /* Set the frame limits assuming standard ethernet sized frames. */
584 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
585 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
587 /* This controls when hardware reports transmit completion status. */
588 adapter->hw.mac.report_tx_early = 1;
591 * Create top level busdma tag
593 error = bus_dma_tag_create(NULL, 1, 0,
594 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
596 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
597 0, &adapter->parent_dtag);
599 device_printf(dev, "could not create top level DMA tag\n");
604 * Allocate Transmit Descriptor ring
606 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
608 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
610 device_printf(dev, "Unable to allocate tx_desc memory\n");
613 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
616 * Allocate Receive Descriptor ring
618 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
620 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
622 device_printf(dev, "Unable to allocate rx_desc memory\n");
625 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
627 /* Allocate multicast array memory. */
628 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
631 /* Indicate SOL/IDER usage */
632 if (e1000_check_reset_block(&adapter->hw)) {
634 "PHY reset is blocked due to SOL/IDER session.\n");
638 * Start from a known state, this is important in reading the
639 * nvm and mac from that.
641 e1000_reset_hw(&adapter->hw);
643 /* Make sure we have a good EEPROM before we read from it */
644 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
646 * Some PCI-E parts fail the first check due to
647 * the link being in sleep state, call it again,
648 * if it fails a second time its a real issue.
650 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
652 "The EEPROM Checksum Is Not Valid\n");
658 /* Copy the permanent MAC address out of the EEPROM */
659 if (e1000_read_mac_addr(&adapter->hw) < 0) {
660 device_printf(dev, "EEPROM read error while reading MAC"
665 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
666 device_printf(dev, "Invalid MAC address\n");
671 /* Allocate transmit descriptors and buffers */
672 error = em_create_tx_ring(adapter);
674 device_printf(dev, "Could not setup transmit structures\n");
678 /* Allocate receive descriptors and buffers */
679 error = em_create_rx_ring(adapter);
681 device_printf(dev, "Could not setup receive structures\n");
685 /* Manually turn off all interrupts */
686 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
688 /* Determine if we have to control management hardware */
689 if (e1000_enable_mng_pass_thru(&adapter->hw))
690 adapter->flags |= EM_FLAG_HAS_MGMT;
695 apme_mask = EM_EEPROM_APME;
697 switch (adapter->hw.mac.type) {
704 adapter->flags |= EM_FLAG_HAS_AMT;
708 case e1000_82546_rev_3:
711 case e1000_80003es2lan:
712 if (adapter->hw.bus.func == 1) {
713 e1000_read_nvm(&adapter->hw,
714 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
716 e1000_read_nvm(&adapter->hw,
717 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
726 apme_mask = E1000_WUC_APME;
727 adapter->flags |= EM_FLAG_HAS_AMT;
728 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
732 e1000_read_nvm(&adapter->hw,
733 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
736 if (eeprom_data & apme_mask)
737 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
740 * We have the eeprom settings, now apply the special cases
741 * where the eeprom may be wrong or the board won't support
742 * wake on lan on a particular port
744 device_id = pci_get_device(dev);
746 case E1000_DEV_ID_82546GB_PCIE:
750 case E1000_DEV_ID_82546EB_FIBER:
751 case E1000_DEV_ID_82546GB_FIBER:
752 case E1000_DEV_ID_82571EB_FIBER:
754 * Wake events only supported on port A for dual fiber
755 * regardless of eeprom setting
757 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
762 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
763 case E1000_DEV_ID_82571EB_QUAD_COPPER:
764 case E1000_DEV_ID_82571EB_QUAD_FIBER:
765 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
766 /* if quad port adapter, disable WoL on all but port A */
767 if (em_global_quad_port_a != 0)
769 /* Reset for multiple quad port adapters */
770 if (++em_global_quad_port_a == 4)
771 em_global_quad_port_a = 0;
775 /* XXX disable wol */
778 /* Setup OS specific network interface */
779 em_setup_ifp(adapter);
781 /* Add sysctl tree, must after em_setup_ifp() */
782 em_add_sysctl(adapter);
784 /* Reset the hardware */
785 error = em_reset(adapter);
787 device_printf(dev, "Unable to reset the hardware\n");
791 /* Initialize statistics */
792 em_update_stats(adapter);
794 adapter->hw.mac.get_link_status = 1;
795 em_update_link_status(adapter);
797 /* Do we need workaround for 82544 PCI-X adapter? */
798 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
799 adapter->hw.mac.type == e1000_82544)
800 adapter->pcix_82544 = TRUE;
802 adapter->pcix_82544 = FALSE;
804 if (adapter->pcix_82544) {
806 * 82544 on PCI-X may split one TX segment
807 * into two TX descs, so we double its number
808 * of spare TX desc here.
810 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
812 adapter->spare_tx_desc = EM_TX_SPARE;
814 if (adapter->flags & EM_FLAG_TSO)
815 adapter->spare_tx_desc = EM_TX_SPARE_TSO;
818 * Keep following relationship between spare_tx_desc, oact_tx_desc
820 * (spare_tx_desc + EM_TX_RESERVED) <=
821 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
823 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
824 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
825 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
826 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
827 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
829 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
830 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
831 adapter->tx_int_nsegs = adapter->oact_tx_desc;
833 /* Non-AMT based hardware can now take control from firmware */
834 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
835 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571)
836 em_get_hw_control(adapter);
839 * Missing Interrupt Following ICR read:
841 * 82571/82572 specification update errata #76
842 * 82573 specification update errata #31
843 * 82574 specification update errata #12
844 * 82583 specification update errata #4
847 if ((adapter->flags & EM_FLAG_SHARED_INTR) &&
848 (adapter->hw.mac.type == e1000_82571 ||
849 adapter->hw.mac.type == e1000_82572 ||
850 adapter->hw.mac.type == e1000_82573 ||
851 adapter->hw.mac.type == e1000_82574 ||
852 adapter->hw.mac.type == e1000_82583))
853 intr_func = em_intr_mask;
855 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
856 intr_func, adapter, &adapter->intr_tag,
859 device_printf(dev, "Failed to register interrupt handler");
860 ether_ifdetach(&adapter->arpcom.ac_if);
864 ifp->if_cpuid = rman_get_cpuid(adapter->intr_res);
865 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
873 em_detach(device_t dev)
875 struct adapter *adapter = device_get_softc(dev);
877 if (device_is_attached(dev)) {
878 struct ifnet *ifp = &adapter->arpcom.ac_if;
880 lwkt_serialize_enter(ifp->if_serializer);
884 e1000_phy_hw_reset(&adapter->hw);
886 em_rel_mgmt(adapter);
887 em_rel_hw_control(adapter);
890 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
892 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
896 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
898 lwkt_serialize_exit(ifp->if_serializer);
901 } else if (adapter->memory != NULL) {
902 em_rel_hw_control(adapter);
904 bus_generic_detach(dev);
906 em_free_pci_res(adapter);
908 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
909 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
911 /* Free Transmit Descriptor ring */
912 if (adapter->tx_desc_base)
913 em_dma_free(adapter, &adapter->txdma);
915 /* Free Receive Descriptor ring */
916 if (adapter->rx_desc_base)
917 em_dma_free(adapter, &adapter->rxdma);
919 /* Free top level busdma tag */
920 if (adapter->parent_dtag != NULL)
921 bus_dma_tag_destroy(adapter->parent_dtag);
923 /* Free sysctl tree */
924 if (adapter->sysctl_tree != NULL)
925 sysctl_ctx_free(&adapter->sysctl_ctx);
927 if (adapter->mta != NULL)
928 kfree(adapter->mta, M_DEVBUF);
934 em_shutdown(device_t dev)
936 return em_suspend(dev);
940 em_suspend(device_t dev)
942 struct adapter *adapter = device_get_softc(dev);
943 struct ifnet *ifp = &adapter->arpcom.ac_if;
945 lwkt_serialize_enter(ifp->if_serializer);
949 em_rel_mgmt(adapter);
950 em_rel_hw_control(adapter);
953 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
954 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
958 lwkt_serialize_exit(ifp->if_serializer);
960 return bus_generic_suspend(dev);
964 em_resume(device_t dev)
966 struct adapter *adapter = device_get_softc(dev);
967 struct ifnet *ifp = &adapter->arpcom.ac_if;
969 lwkt_serialize_enter(ifp->if_serializer);
972 em_get_mgmt(adapter);
975 lwkt_serialize_exit(ifp->if_serializer);
977 return bus_generic_resume(dev);
981 em_start(struct ifnet *ifp)
983 struct adapter *adapter = ifp->if_softc;
986 ASSERT_SERIALIZED(ifp->if_serializer);
988 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
991 if (!adapter->link_active) {
992 ifq_purge(&ifp->if_snd);
996 while (!ifq_is_empty(&ifp->if_snd)) {
997 /* Now do we at least have a minimal? */
998 if (EM_IS_OACTIVE(adapter)) {
999 em_tx_collect(adapter);
1000 if (EM_IS_OACTIVE(adapter)) {
1001 ifp->if_flags |= IFF_OACTIVE;
1002 adapter->no_tx_desc_avail1++;
1008 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1012 if (em_encap(adapter, &m_head)) {
1014 em_tx_collect(adapter);
1018 /* Send a copy of the frame to the BPF listener */
1019 ETHER_BPF_MTAP(ifp, m_head);
1021 /* Set timeout in case hardware has problems transmitting. */
1022 ifp->if_timer = EM_TX_TIMEOUT;
1027 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1029 struct adapter *adapter = ifp->if_softc;
1030 struct ifreq *ifr = (struct ifreq *)data;
1031 uint16_t eeprom_data = 0;
1032 int max_frame_size, mask, reinit;
1035 ASSERT_SERIALIZED(ifp->if_serializer);
1039 switch (adapter->hw.mac.type) {
1042 * 82573 only supports jumbo frames
1043 * if ASPM is disabled.
1045 e1000_read_nvm(&adapter->hw,
1046 NVM_INIT_3GIO_3, 1, &eeprom_data);
1047 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1048 max_frame_size = ETHER_MAX_LEN;
1053 /* Limit Jumbo Frame size */
1057 case e1000_ich10lan:
1061 case e1000_80003es2lan:
1062 max_frame_size = 9234;
1066 max_frame_size = 4096;
1069 /* Adapters that do not support jumbo frames */
1072 max_frame_size = ETHER_MAX_LEN;
1076 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1079 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1085 ifp->if_mtu = ifr->ifr_mtu;
1086 adapter->max_frame_size =
1087 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1089 if (ifp->if_flags & IFF_RUNNING)
1094 if (ifp->if_flags & IFF_UP) {
1095 if ((ifp->if_flags & IFF_RUNNING)) {
1096 if ((ifp->if_flags ^ adapter->if_flags) &
1097 (IFF_PROMISC | IFF_ALLMULTI)) {
1098 em_disable_promisc(adapter);
1099 em_set_promisc(adapter);
1104 } else if (ifp->if_flags & IFF_RUNNING) {
1107 adapter->if_flags = ifp->if_flags;
1112 if (ifp->if_flags & IFF_RUNNING) {
1113 em_disable_intr(adapter);
1114 em_set_multi(adapter);
1115 if (adapter->hw.mac.type == e1000_82542 &&
1116 adapter->hw.revision_id == E1000_REVISION_2)
1117 em_init_rx_unit(adapter);
1118 #ifdef DEVICE_POLLING
1119 if (!(ifp->if_flags & IFF_POLLING))
1121 em_enable_intr(adapter);
1126 /* Check SOL/IDER usage */
1127 if (e1000_check_reset_block(&adapter->hw)) {
1128 device_printf(adapter->dev, "Media change is"
1129 " blocked due to SOL/IDER session.\n");
1135 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1140 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1141 if (mask & IFCAP_RXCSUM) {
1142 ifp->if_capenable ^= IFCAP_RXCSUM;
1145 if (mask & IFCAP_TXCSUM) {
1146 ifp->if_capenable ^= IFCAP_TXCSUM;
1147 if (ifp->if_capenable & IFCAP_TXCSUM)
1148 ifp->if_hwassist |= EM_CSUM_FEATURES;
1150 ifp->if_hwassist &= ~EM_CSUM_FEATURES;
1152 if (mask & IFCAP_TSO) {
1153 ifp->if_capenable ^= IFCAP_TSO;
1154 if (ifp->if_capenable & IFCAP_TSO)
1155 ifp->if_hwassist |= CSUM_TSO;
1157 ifp->if_hwassist &= ~CSUM_TSO;
1159 if (mask & IFCAP_VLAN_HWTAGGING) {
1160 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1163 if (reinit && (ifp->if_flags & IFF_RUNNING))
1168 error = ether_ioctl(ifp, command, data);
1175 em_watchdog(struct ifnet *ifp)
1177 struct adapter *adapter = ifp->if_softc;
1179 ASSERT_SERIALIZED(ifp->if_serializer);
1182 * The timer is set to 5 every time start queues a packet.
1183 * Then txeof keeps resetting it as long as it cleans at
1184 * least one descriptor.
1185 * Finally, anytime all descriptors are clean the timer is
1189 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1190 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1192 * If we reach here, all TX jobs are completed and
1193 * the TX engine should have been idled for some time.
1194 * We don't need to call if_devstart() here.
1196 ifp->if_flags &= ~IFF_OACTIVE;
1202 * If we are in this routine because of pause frames, then
1203 * don't reset the hardware.
1205 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1206 E1000_STATUS_TXOFF) {
1207 ifp->if_timer = EM_TX_TIMEOUT;
1211 if (e1000_check_for_link(&adapter->hw) == 0)
1212 if_printf(ifp, "watchdog timeout -- resetting\n");
1215 adapter->watchdog_events++;
1219 if (!ifq_is_empty(&ifp->if_snd))
1226 struct adapter *adapter = xsc;
1227 struct ifnet *ifp = &adapter->arpcom.ac_if;
1228 device_t dev = adapter->dev;
1231 ASSERT_SERIALIZED(ifp->if_serializer);
1236 * Packet Buffer Allocation (PBA)
1237 * Writing PBA sets the receive portion of the buffer
1238 * the remainder is used for the transmit buffer.
1240 * Devices before the 82547 had a Packet Buffer of 64K.
1241 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1242 * After the 82547 the buffer was reduced to 40K.
1243 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1244 * Note: default does not leave enough room for Jumbo Frame >10k.
1246 switch (adapter->hw.mac.type) {
1248 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1249 if (adapter->max_frame_size > 8192)
1250 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
1252 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
1253 adapter->tx_fifo_head = 0;
1254 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1255 adapter->tx_fifo_size =
1256 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
1259 /* Total Packet Buffer on these is 48K */
1262 case e1000_80003es2lan:
1263 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1266 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1267 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1272 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1280 case e1000_ich10lan:
1281 #define E1000_PBA_10K 0x000A
1282 pba = E1000_PBA_10K;
1287 pba = E1000_PBA_26K;
1291 /* Devices before 82547 had a Packet Buffer of 64K. */
1292 if (adapter->max_frame_size > 8192)
1293 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1295 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1297 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
1299 /* Get the latest mac address, User can use a LAA */
1300 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1302 /* Put the address into the Receive Address Array */
1303 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1306 * With the 82571 adapter, RAR[0] may be overwritten
1307 * when the other port is reset, we make a duplicate
1308 * in RAR[14] for that eventuality, this assures
1309 * the interface continues to function.
1311 if (adapter->hw.mac.type == e1000_82571) {
1312 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1313 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1314 E1000_RAR_ENTRIES - 1);
1317 /* Reset the hardware */
1318 if (em_reset(adapter)) {
1319 device_printf(dev, "Unable to reset the hardware\n");
1320 /* XXX em_stop()? */
1323 em_update_link_status(adapter);
1325 /* Setup VLAN support, basic and offload if available */
1326 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1328 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1331 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1332 ctrl |= E1000_CTRL_VME;
1333 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1336 /* Configure for OS presence */
1337 em_get_mgmt(adapter);
1339 /* Prepare transmit descriptors and buffers */
1340 em_init_tx_ring(adapter);
1341 em_init_tx_unit(adapter);
1343 /* Setup Multicast table */
1344 em_set_multi(adapter);
1346 /* Prepare receive descriptors and buffers */
1347 if (em_init_rx_ring(adapter)) {
1348 device_printf(dev, "Could not setup receive structures\n");
1352 em_init_rx_unit(adapter);
1354 /* Don't lose promiscuous settings */
1355 em_set_promisc(adapter);
1357 ifp->if_flags |= IFF_RUNNING;
1358 ifp->if_flags &= ~IFF_OACTIVE;
1360 callout_reset(&adapter->timer, hz, em_timer, adapter);
1361 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1363 /* MSI/X configuration for 82574 */
1364 if (adapter->hw.mac.type == e1000_82574) {
1367 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1368 tmp |= E1000_CTRL_EXT_PBA_CLR;
1369 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1372 * Set the IVAR - interrupt vector routing.
1373 * Each nibble represents a vector, high bit
1374 * is enable, other 3 bits are the MSIX table
1375 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1376 * Link (other) to 2, hence the magic number.
1378 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1381 #ifdef DEVICE_POLLING
1383 * Only enable interrupts if we are not polling, make sure
1384 * they are off otherwise.
1386 if (ifp->if_flags & IFF_POLLING)
1387 em_disable_intr(adapter);
1389 #endif /* DEVICE_POLLING */
1390 em_enable_intr(adapter);
1392 /* AMT based hardware can now take control from firmware */
1393 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
1394 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) &&
1395 adapter->hw.mac.type >= e1000_82571)
1396 em_get_hw_control(adapter);
1398 /* Don't reset the phy next time init gets called */
1399 adapter->hw.phy.reset_disable = TRUE;
1402 #ifdef DEVICE_POLLING
1405 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1407 struct adapter *adapter = ifp->if_softc;
1410 ASSERT_SERIALIZED(ifp->if_serializer);
1414 em_disable_intr(adapter);
1417 case POLL_DEREGISTER:
1418 em_enable_intr(adapter);
1421 case POLL_AND_CHECK_STATUS:
1422 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1423 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1424 callout_stop(&adapter->timer);
1425 adapter->hw.mac.get_link_status = 1;
1426 em_update_link_status(adapter);
1427 callout_reset(&adapter->timer, hz, em_timer, adapter);
1431 if (ifp->if_flags & IFF_RUNNING) {
1432 em_rxeof(adapter, count);
1435 if (!ifq_is_empty(&ifp->if_snd))
1442 #endif /* DEVICE_POLLING */
1447 em_intr_body(xsc, TRUE);
1451 em_intr_body(struct adapter *adapter, boolean_t chk_asserted)
1453 struct ifnet *ifp = &adapter->arpcom.ac_if;
1457 ASSERT_SERIALIZED(ifp->if_serializer);
1459 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1462 ((adapter->hw.mac.type >= e1000_82571 &&
1463 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1470 * XXX: some laptops trigger several spurious interrupts
1471 * on em(4) when in the resume cycle. The ICR register
1472 * reports all-ones value in this case. Processing such
1473 * interrupts would lead to a freeze. I don't know why.
1475 if (reg_icr == 0xffffffff) {
1480 if (ifp->if_flags & IFF_RUNNING) {
1482 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
1483 em_rxeof(adapter, -1);
1484 if (reg_icr & E1000_ICR_TXDW) {
1486 if (!ifq_is_empty(&ifp->if_snd))
1491 /* Link status change */
1492 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1493 callout_stop(&adapter->timer);
1494 adapter->hw.mac.get_link_status = 1;
1495 em_update_link_status(adapter);
1497 /* Deal with TX cruft when link lost */
1498 em_tx_purge(adapter);
1500 callout_reset(&adapter->timer, hz, em_timer, adapter);
1503 if (reg_icr & E1000_ICR_RXO)
1504 adapter->rx_overruns++;
1510 em_intr_mask(void *xsc)
1512 struct adapter *adapter = xsc;
1514 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
1517 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1518 * so don't check it.
1520 em_intr_body(adapter, FALSE);
1521 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
1525 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1527 struct adapter *adapter = ifp->if_softc;
1528 u_char fiber_type = IFM_1000_SX;
1530 ASSERT_SERIALIZED(ifp->if_serializer);
1532 em_update_link_status(adapter);
1534 ifmr->ifm_status = IFM_AVALID;
1535 ifmr->ifm_active = IFM_ETHER;
1537 if (!adapter->link_active)
1540 ifmr->ifm_status |= IFM_ACTIVE;
1542 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1543 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
1544 if (adapter->hw.mac.type == e1000_82545)
1545 fiber_type = IFM_1000_LX;
1546 ifmr->ifm_active |= fiber_type | IFM_FDX;
1548 switch (adapter->link_speed) {
1550 ifmr->ifm_active |= IFM_10_T;
1553 ifmr->ifm_active |= IFM_100_TX;
1557 ifmr->ifm_active |= IFM_1000_T;
1560 if (adapter->link_duplex == FULL_DUPLEX)
1561 ifmr->ifm_active |= IFM_FDX;
1563 ifmr->ifm_active |= IFM_HDX;
1568 em_media_change(struct ifnet *ifp)
1570 struct adapter *adapter = ifp->if_softc;
1571 struct ifmedia *ifm = &adapter->media;
1573 ASSERT_SERIALIZED(ifp->if_serializer);
1575 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1578 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1580 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1581 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1587 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1588 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1592 adapter->hw.mac.autoneg = FALSE;
1593 adapter->hw.phy.autoneg_advertised = 0;
1594 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1595 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1597 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1601 adapter->hw.mac.autoneg = FALSE;
1602 adapter->hw.phy.autoneg_advertised = 0;
1603 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1604 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1606 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1610 if_printf(ifp, "Unsupported media type\n");
1615 * As the speed/duplex settings my have changed we need to
1618 adapter->hw.phy.reset_disable = FALSE;
1626 em_encap(struct adapter *adapter, struct mbuf **m_headp)
1628 bus_dma_segment_t segs[EM_MAX_SCATTER];
1630 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1631 struct e1000_tx_desc *ctxd = NULL;
1632 struct mbuf *m_head = *m_headp;
1633 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
1634 int maxsegs, nsegs, i, j, first, last = 0, error;
1636 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1637 error = em_tso_pullup(adapter, m_headp);
1643 txd_upper = txd_lower = 0;
1647 * Capture the first descriptor index, this descriptor
1648 * will have the index of the EOP which is the only one
1649 * that now gets a DONE bit writeback.
1651 first = adapter->next_avail_tx_desc;
1652 tx_buffer = &adapter->tx_buffer_area[first];
1653 tx_buffer_mapped = tx_buffer;
1654 map = tx_buffer->map;
1656 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1657 KASSERT(maxsegs >= adapter->spare_tx_desc,
1658 ("not enough spare TX desc"));
1659 if (adapter->pcix_82544) {
1660 /* Half it; see the comment in em_attach() */
1663 if (maxsegs > EM_MAX_SCATTER)
1664 maxsegs = EM_MAX_SCATTER;
1666 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1667 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1669 if (error == ENOBUFS)
1670 adapter->mbuf_alloc_failed++;
1672 adapter->no_tx_dma_setup++;
1678 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
1681 adapter->tx_nsegs += nsegs;
1683 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1684 /* TSO will consume one TX desc */
1685 adapter->tx_nsegs += em_tso_setup(adapter, m_head,
1686 &txd_upper, &txd_lower);
1687 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
1688 /* TX csum offloading will consume one TX desc */
1689 adapter->tx_nsegs += em_txcsum(adapter, m_head,
1690 &txd_upper, &txd_lower);
1692 i = adapter->next_avail_tx_desc;
1694 /* Set up our transmit descriptors */
1695 for (j = 0; j < nsegs; j++) {
1696 /* If adapter is 82544 and on PCIX bus */
1697 if(adapter->pcix_82544) {
1698 DESC_ARRAY desc_array;
1699 uint32_t array_elements, counter;
1702 * Check the Address and Length combination and
1703 * split the data accordingly
1705 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1706 segs[j].ds_len, &desc_array);
1707 for (counter = 0; counter < array_elements; counter++) {
1708 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1710 tx_buffer = &adapter->tx_buffer_area[i];
1711 ctxd = &adapter->tx_desc_base[i];
1713 ctxd->buffer_addr = htole64(
1714 desc_array.descriptor[counter].address);
1715 ctxd->lower.data = htole32(
1716 E1000_TXD_CMD_IFCS | txd_lower |
1717 desc_array.descriptor[counter].length);
1718 ctxd->upper.data = htole32(txd_upper);
1721 if (++i == adapter->num_tx_desc)
1727 tx_buffer = &adapter->tx_buffer_area[i];
1728 ctxd = &adapter->tx_desc_base[i];
1730 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1731 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1732 txd_lower | segs[j].ds_len);
1733 ctxd->upper.data = htole32(txd_upper);
1736 if (++i == adapter->num_tx_desc)
1741 adapter->next_avail_tx_desc = i;
1742 if (adapter->pcix_82544) {
1743 KKASSERT(adapter->num_tx_desc_avail > txd_used);
1744 adapter->num_tx_desc_avail -= txd_used;
1746 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1747 adapter->num_tx_desc_avail -= nsegs;
1750 /* Handle VLAN tag */
1751 if (m_head->m_flags & M_VLANTAG) {
1752 /* Set the vlan id. */
1753 ctxd->upper.fields.special =
1754 htole16(m_head->m_pkthdr.ether_vlantag);
1756 /* Tell hardware to add tag */
1757 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1760 tx_buffer->m_head = m_head;
1761 tx_buffer_mapped->map = tx_buffer->map;
1762 tx_buffer->map = map;
1764 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1765 adapter->tx_nsegs = 0;
1768 * Report Status (RS) is turned on
1769 * every tx_int_nsegs descriptors.
1771 cmd = E1000_TXD_CMD_RS;
1774 * Keep track of the descriptor, which will
1775 * be written back by hardware.
1777 adapter->tx_dd[adapter->tx_dd_tail] = last;
1778 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1779 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1783 * Last Descriptor of Packet needs End Of Packet (EOP)
1785 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1788 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
1789 * that this frame is available to transmit.
1791 if (adapter->hw.mac.type == e1000_82547 &&
1792 adapter->link_duplex == HALF_DUPLEX) {
1793 em_82547_move_tail_serialized(adapter);
1795 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
1796 if (adapter->hw.mac.type == e1000_82547) {
1797 em_82547_update_fifo_head(adapter,
1798 m_head->m_pkthdr.len);
1805 * 82547 workaround to avoid controller hang in half-duplex environment.
1806 * The workaround is to avoid queuing a large packet that would span
1807 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1808 * in this case. We do that only when FIFO is quiescent.
1811 em_82547_move_tail_serialized(struct adapter *adapter)
1813 struct e1000_tx_desc *tx_desc;
1814 uint16_t hw_tdt, sw_tdt, length = 0;
1817 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1819 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
1820 sw_tdt = adapter->next_avail_tx_desc;
1822 while (hw_tdt != sw_tdt) {
1823 tx_desc = &adapter->tx_desc_base[hw_tdt];
1824 length += tx_desc->lower.flags.length;
1825 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1826 if (++hw_tdt == adapter->num_tx_desc)
1830 if (em_82547_fifo_workaround(adapter, length)) {
1831 adapter->tx_fifo_wrk_cnt++;
1832 callout_reset(&adapter->tx_fifo_timer, 1,
1833 em_82547_move_tail, adapter);
1836 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
1837 em_82547_update_fifo_head(adapter, length);
1844 em_82547_move_tail(void *xsc)
1846 struct adapter *adapter = xsc;
1847 struct ifnet *ifp = &adapter->arpcom.ac_if;
1849 lwkt_serialize_enter(ifp->if_serializer);
1850 em_82547_move_tail_serialized(adapter);
1851 lwkt_serialize_exit(ifp->if_serializer);
1855 em_82547_fifo_workaround(struct adapter *adapter, int len)
1857 int fifo_space, fifo_pkt_len;
1859 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1861 if (adapter->link_duplex == HALF_DUPLEX) {
1862 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1864 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1865 if (em_82547_tx_fifo_reset(adapter))
1875 em_82547_update_fifo_head(struct adapter *adapter, int len)
1877 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1879 /* tx_fifo_head is always 16 byte aligned */
1880 adapter->tx_fifo_head += fifo_pkt_len;
1881 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1882 adapter->tx_fifo_head -= adapter->tx_fifo_size;
1886 em_82547_tx_fifo_reset(struct adapter *adapter)
1890 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1891 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1892 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1893 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1894 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1895 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1896 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
1897 /* Disable TX unit */
1898 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1899 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1900 tctl & ~E1000_TCTL_EN);
1902 /* Reset FIFO pointers */
1903 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1904 adapter->tx_head_addr);
1905 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1906 adapter->tx_head_addr);
1907 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1908 adapter->tx_head_addr);
1909 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1910 adapter->tx_head_addr);
1912 /* Re-enable TX unit */
1913 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
1914 E1000_WRITE_FLUSH(&adapter->hw);
1916 adapter->tx_fifo_head = 0;
1917 adapter->tx_fifo_reset_cnt++;
1926 em_set_promisc(struct adapter *adapter)
1928 struct ifnet *ifp = &adapter->arpcom.ac_if;
1931 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1933 if (ifp->if_flags & IFF_PROMISC) {
1934 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1935 /* Turn this on if you want to see bad packets */
1937 reg_rctl |= E1000_RCTL_SBP;
1938 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1939 } else if (ifp->if_flags & IFF_ALLMULTI) {
1940 reg_rctl |= E1000_RCTL_MPE;
1941 reg_rctl &= ~E1000_RCTL_UPE;
1942 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1947 em_disable_promisc(struct adapter *adapter)
1951 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1953 reg_rctl &= ~E1000_RCTL_UPE;
1954 reg_rctl &= ~E1000_RCTL_MPE;
1955 reg_rctl &= ~E1000_RCTL_SBP;
1956 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1960 em_set_multi(struct adapter *adapter)
1962 struct ifnet *ifp = &adapter->arpcom.ac_if;
1963 struct ifmultiaddr *ifma;
1964 uint32_t reg_rctl = 0;
1969 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1971 if (adapter->hw.mac.type == e1000_82542 &&
1972 adapter->hw.revision_id == E1000_REVISION_2) {
1973 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1974 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1975 e1000_pci_clear_mwi(&adapter->hw);
1976 reg_rctl |= E1000_RCTL_RST;
1977 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1981 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1982 if (ifma->ifma_addr->sa_family != AF_LINK)
1985 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1988 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1989 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1993 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1994 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1995 reg_rctl |= E1000_RCTL_MPE;
1996 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1998 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
2001 if (adapter->hw.mac.type == e1000_82542 &&
2002 adapter->hw.revision_id == E1000_REVISION_2) {
2003 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
2004 reg_rctl &= ~E1000_RCTL_RST;
2005 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
2007 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2008 e1000_pci_set_mwi(&adapter->hw);
2013 * This routine checks for link status and updates statistics.
2018 struct adapter *adapter = xsc;
2019 struct ifnet *ifp = &adapter->arpcom.ac_if;
2021 lwkt_serialize_enter(ifp->if_serializer);
2023 em_update_link_status(adapter);
2024 em_update_stats(adapter);
2026 /* Reset LAA into RAR[0] on 82571 */
2027 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
2028 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2030 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
2031 em_print_hw_stats(adapter);
2033 em_smartspeed(adapter);
2035 callout_reset(&adapter->timer, hz, em_timer, adapter);
2037 lwkt_serialize_exit(ifp->if_serializer);
2041 em_update_link_status(struct adapter *adapter)
2043 struct e1000_hw *hw = &adapter->hw;
2044 struct ifnet *ifp = &adapter->arpcom.ac_if;
2045 device_t dev = adapter->dev;
2046 uint32_t link_check = 0;
2048 /* Get the cached link value or read phy for real */
2049 switch (hw->phy.media_type) {
2050 case e1000_media_type_copper:
2051 if (hw->mac.get_link_status) {
2052 /* Do the work to read phy */
2053 e1000_check_for_link(hw);
2054 link_check = !hw->mac.get_link_status;
2055 if (link_check) /* ESB2 fix */
2056 e1000_cfg_on_link_up(hw);
2062 case e1000_media_type_fiber:
2063 e1000_check_for_link(hw);
2065 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
2068 case e1000_media_type_internal_serdes:
2069 e1000_check_for_link(hw);
2070 link_check = adapter->hw.mac.serdes_has_link;
2073 case e1000_media_type_unknown:
2078 /* Now check for a transition */
2079 if (link_check && adapter->link_active == 0) {
2080 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2081 &adapter->link_duplex);
2084 * Check if we should enable/disable SPEED_MODE bit on
2087 if (adapter->link_speed != SPEED_1000 &&
2088 (hw->mac.type == e1000_82571 ||
2089 hw->mac.type == e1000_82572)) {
2092 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2093 tarc0 &= ~SPEED_MODE_BIT;
2094 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
2097 device_printf(dev, "Link is up %d Mbps %s\n",
2098 adapter->link_speed,
2099 ((adapter->link_duplex == FULL_DUPLEX) ?
2100 "Full Duplex" : "Half Duplex"));
2102 adapter->link_active = 1;
2103 adapter->smartspeed = 0;
2104 ifp->if_baudrate = adapter->link_speed * 1000000;
2105 ifp->if_link_state = LINK_STATE_UP;
2106 if_link_state_change(ifp);
2107 } else if (!link_check && adapter->link_active == 1) {
2108 ifp->if_baudrate = adapter->link_speed = 0;
2109 adapter->link_duplex = 0;
2111 device_printf(dev, "Link is Down\n");
2112 adapter->link_active = 0;
2114 /* Link down, disable watchdog */
2117 ifp->if_link_state = LINK_STATE_DOWN;
2118 if_link_state_change(ifp);
2123 em_stop(struct adapter *adapter)
2125 struct ifnet *ifp = &adapter->arpcom.ac_if;
2128 ASSERT_SERIALIZED(ifp->if_serializer);
2130 em_disable_intr(adapter);
2132 callout_stop(&adapter->timer);
2133 callout_stop(&adapter->tx_fifo_timer);
2135 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2138 e1000_reset_hw(&adapter->hw);
2139 if (adapter->hw.mac.type >= e1000_82544)
2140 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2142 for (i = 0; i < adapter->num_tx_desc; i++) {
2143 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2145 if (tx_buffer->m_head != NULL) {
2146 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2147 m_freem(tx_buffer->m_head);
2148 tx_buffer->m_head = NULL;
2152 for (i = 0; i < adapter->num_rx_desc; i++) {
2153 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2155 if (rx_buffer->m_head != NULL) {
2156 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2157 m_freem(rx_buffer->m_head);
2158 rx_buffer->m_head = NULL;
2162 if (adapter->fmp != NULL)
2163 m_freem(adapter->fmp);
2164 adapter->fmp = NULL;
2165 adapter->lmp = NULL;
2167 adapter->csum_flags = 0;
2168 adapter->csum_lhlen = 0;
2169 adapter->csum_iphlen = 0;
2170 adapter->csum_thlen = 0;
2171 adapter->csum_mss = 0;
2172 adapter->csum_pktlen = 0;
2174 adapter->tx_dd_head = 0;
2175 adapter->tx_dd_tail = 0;
2176 adapter->tx_nsegs = 0;
2180 em_get_hw_info(struct adapter *adapter)
2182 device_t dev = adapter->dev;
2184 /* Save off the information about this board */
2185 adapter->hw.vendor_id = pci_get_vendor(dev);
2186 adapter->hw.device_id = pci_get_device(dev);
2187 adapter->hw.revision_id = pci_get_revid(dev);
2188 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
2189 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
2191 /* Do Shared Code Init and Setup */
2192 if (e1000_set_mac_type(&adapter->hw))
2198 em_alloc_pci_res(struct adapter *adapter)
2200 device_t dev = adapter->dev;
2202 int val, rid, msi_enable;
2204 /* Enable bus mastering */
2205 pci_enable_busmaster(dev);
2207 adapter->memory_rid = EM_BAR_MEM;
2208 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2209 &adapter->memory_rid, RF_ACTIVE);
2210 if (adapter->memory == NULL) {
2211 device_printf(dev, "Unable to allocate bus resource: memory\n");
2214 adapter->osdep.mem_bus_space_tag =
2215 rman_get_bustag(adapter->memory);
2216 adapter->osdep.mem_bus_space_handle =
2217 rman_get_bushandle(adapter->memory);
2219 /* XXX This is quite goofy, it is not actually used */
2220 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2222 /* Only older adapters use IO mapping */
2223 if (adapter->hw.mac.type > e1000_82543 &&
2224 adapter->hw.mac.type < e1000_82571) {
2225 /* Figure our where our IO BAR is ? */
2226 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
2227 val = pci_read_config(dev, rid, 4);
2228 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
2229 adapter->io_rid = rid;
2233 /* check for 64bit BAR */
2234 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2237 if (rid >= PCIR_CARDBUSCIS) {
2238 device_printf(dev, "Unable to locate IO BAR\n");
2241 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2242 &adapter->io_rid, RF_ACTIVE);
2243 if (adapter->ioport == NULL) {
2244 device_printf(dev, "Unable to allocate bus resource: "
2248 adapter->hw.io_base = 0;
2249 adapter->osdep.io_bus_space_tag =
2250 rman_get_bustag(adapter->ioport);
2251 adapter->osdep.io_bus_space_handle =
2252 rman_get_bushandle(adapter->ioport);
2256 * Don't enable MSI-X on 82574, see:
2257 * 82574 specification update errata #15
2259 * Don't enable MSI on PCI/PCI-X chips, see:
2260 * 82540 specification update errata #6
2261 * 82545 specification update errata #4
2263 * Don't enable MSI on 82571/82572, see:
2264 * 82571/82572 specification update errata #63
2266 msi_enable = em_msi_enable;
2268 (!pci_is_pcie(dev) ||
2269 adapter->hw.mac.type == e1000_82571 ||
2270 adapter->hw.mac.type == e1000_82572))
2273 adapter->intr_type = pci_alloc_1intr(dev, msi_enable,
2274 &adapter->intr_rid, &intr_flags);
2276 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) {
2279 unshared = device_getenv_int(dev, "irq.unshared", 0);
2281 adapter->flags |= EM_FLAG_SHARED_INTR;
2283 device_printf(dev, "IRQ shared\n");
2285 intr_flags &= ~RF_SHAREABLE;
2287 device_printf(dev, "IRQ unshared\n");
2291 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
2292 &adapter->intr_rid, intr_flags);
2293 if (adapter->intr_res == NULL) {
2294 device_printf(dev, "Unable to allocate bus resource: "
2299 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
2300 adapter->hw.back = &adapter->osdep;
2305 em_free_pci_res(struct adapter *adapter)
2307 device_t dev = adapter->dev;
2309 if (adapter->intr_res != NULL) {
2310 bus_release_resource(dev, SYS_RES_IRQ,
2311 adapter->intr_rid, adapter->intr_res);
2314 if (adapter->intr_type == PCI_INTR_TYPE_MSI)
2315 pci_release_msi(dev);
2317 if (adapter->memory != NULL) {
2318 bus_release_resource(dev, SYS_RES_MEMORY,
2319 adapter->memory_rid, adapter->memory);
2322 if (adapter->flash != NULL) {
2323 bus_release_resource(dev, SYS_RES_MEMORY,
2324 adapter->flash_rid, adapter->flash);
2327 if (adapter->ioport != NULL) {
2328 bus_release_resource(dev, SYS_RES_IOPORT,
2329 adapter->io_rid, adapter->ioport);
2334 em_reset(struct adapter *adapter)
2336 device_t dev = adapter->dev;
2337 uint16_t rx_buffer_size;
2339 /* When hardware is reset, fifo_head is also reset */
2340 adapter->tx_fifo_head = 0;
2342 /* Set up smart power down as default off on newer adapters. */
2343 if (!em_smart_pwr_down &&
2344 (adapter->hw.mac.type == e1000_82571 ||
2345 adapter->hw.mac.type == e1000_82572)) {
2346 uint16_t phy_tmp = 0;
2348 /* Speed up time to link by disabling smart power down. */
2349 e1000_read_phy_reg(&adapter->hw,
2350 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2351 phy_tmp &= ~IGP02E1000_PM_SPD;
2352 e1000_write_phy_reg(&adapter->hw,
2353 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2357 * These parameters control the automatic generation (Tx) and
2358 * response (Rx) to Ethernet PAUSE frames.
2359 * - High water mark should allow for at least two frames to be
2360 * received after sending an XOFF.
2361 * - Low water mark works best when it is very near the high water mark.
2362 * This allows the receiver to restart by sending XON when it has
2363 * drained a bit. Here we use an arbitary value of 1500 which will
2364 * restart after one full frame is pulled from the buffer. There
2365 * could be several smaller frames in the buffer and if so they will
2366 * not trigger the XON until their total number reduces the buffer
2368 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2371 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
2373 adapter->hw.fc.high_water = rx_buffer_size -
2374 roundup2(adapter->max_frame_size, 1024);
2375 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2377 if (adapter->hw.mac.type == e1000_80003es2lan)
2378 adapter->hw.fc.pause_time = 0xFFFF;
2380 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2382 adapter->hw.fc.send_xon = TRUE;
2384 adapter->hw.fc.requested_mode = e1000_fc_full;
2386 /* Workaround: no TX flow ctrl for PCH */
2387 if (adapter->hw.mac.type == e1000_pchlan)
2388 adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
2390 /* Override - settings for PCH2LAN, ya its magic :) */
2391 if (adapter->hw.mac.type == e1000_pch2lan) {
2392 adapter->hw.fc.high_water = 0x5C20;
2393 adapter->hw.fc.low_water = 0x5048;
2394 adapter->hw.fc.pause_time = 0x0650;
2395 adapter->hw.fc.refresh_time = 0x0400;
2397 /* Jumbos need adjusted PBA */
2398 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2399 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2401 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
2404 /* Issue a global reset */
2405 e1000_reset_hw(&adapter->hw);
2406 if (adapter->hw.mac.type >= e1000_82544)
2407 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2408 em_disable_aspm(adapter);
2410 if (e1000_init_hw(&adapter->hw) < 0) {
2411 device_printf(dev, "Hardware Initialization Failed\n");
2415 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2416 e1000_get_phy_info(&adapter->hw);
2417 e1000_check_for_link(&adapter->hw);
2423 em_setup_ifp(struct adapter *adapter)
2425 struct ifnet *ifp = &adapter->arpcom.ac_if;
2427 if_initname(ifp, device_get_name(adapter->dev),
2428 device_get_unit(adapter->dev));
2429 ifp->if_softc = adapter;
2430 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2431 ifp->if_init = em_init;
2432 ifp->if_ioctl = em_ioctl;
2433 ifp->if_start = em_start;
2434 #ifdef DEVICE_POLLING
2435 ifp->if_poll = em_poll;
2437 ifp->if_watchdog = em_watchdog;
2438 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
2439 ifq_set_ready(&ifp->if_snd);
2441 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
2443 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2444 if (adapter->hw.mac.type >= e1000_82543)
2445 ifp->if_capabilities |= IFCAP_HWCSUM;
2446 if (adapter->flags & EM_FLAG_TSO)
2447 ifp->if_capabilities |= IFCAP_TSO;
2448 ifp->if_capenable = ifp->if_capabilities;
2450 if (ifp->if_capenable & IFCAP_TXCSUM)
2451 ifp->if_hwassist |= EM_CSUM_FEATURES;
2452 if (ifp->if_capenable & IFCAP_TSO)
2453 ifp->if_hwassist |= CSUM_TSO;
2456 * Tell the upper layer(s) we support long frames.
2458 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2461 * Specify the media types supported by this adapter and register
2462 * callbacks to update media and link information
2464 ifmedia_init(&adapter->media, IFM_IMASK,
2465 em_media_change, em_media_status);
2466 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2467 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2468 u_char fiber_type = IFM_1000_SX; /* default type */
2470 if (adapter->hw.mac.type == e1000_82545)
2471 fiber_type = IFM_1000_LX;
2472 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
2474 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2476 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2477 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2479 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
2481 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2483 if (adapter->hw.phy.type != e1000_phy_ife) {
2484 ifmedia_add(&adapter->media,
2485 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2486 ifmedia_add(&adapter->media,
2487 IFM_ETHER | IFM_1000_T, 0, NULL);
2490 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2491 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
2496 * Workaround for SmartSpeed on 82541 and 82547 controllers
2499 em_smartspeed(struct adapter *adapter)
2503 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2504 adapter->hw.mac.autoneg == 0 ||
2505 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2508 if (adapter->smartspeed == 0) {
2510 * If Master/Slave config fault is asserted twice,
2511 * we assume back-to-back
2513 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2514 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2516 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2517 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2518 e1000_read_phy_reg(&adapter->hw,
2519 PHY_1000T_CTRL, &phy_tmp);
2520 if (phy_tmp & CR_1000T_MS_ENABLE) {
2521 phy_tmp &= ~CR_1000T_MS_ENABLE;
2522 e1000_write_phy_reg(&adapter->hw,
2523 PHY_1000T_CTRL, phy_tmp);
2524 adapter->smartspeed++;
2525 if (adapter->hw.mac.autoneg &&
2526 !e1000_phy_setup_autoneg(&adapter->hw) &&
2527 !e1000_read_phy_reg(&adapter->hw,
2528 PHY_CONTROL, &phy_tmp)) {
2529 phy_tmp |= MII_CR_AUTO_NEG_EN |
2530 MII_CR_RESTART_AUTO_NEG;
2531 e1000_write_phy_reg(&adapter->hw,
2532 PHY_CONTROL, phy_tmp);
2537 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2538 /* If still no link, perhaps using 2/3 pair cable */
2539 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2540 phy_tmp |= CR_1000T_MS_ENABLE;
2541 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2542 if (adapter->hw.mac.autoneg &&
2543 !e1000_phy_setup_autoneg(&adapter->hw) &&
2544 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2545 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2546 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2550 /* Restart process after EM_SMARTSPEED_MAX iterations */
2551 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2552 adapter->smartspeed = 0;
2556 em_dma_malloc(struct adapter *adapter, bus_size_t size,
2557 struct em_dma_alloc *dma)
2559 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2560 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2561 &dma->dma_tag, &dma->dma_map,
2563 if (dma->dma_vaddr == NULL)
2570 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2572 if (dma->dma_tag == NULL)
2574 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2575 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2576 bus_dma_tag_destroy(dma->dma_tag);
2580 em_create_tx_ring(struct adapter *adapter)
2582 device_t dev = adapter->dev;
2583 struct em_buffer *tx_buffer;
2586 adapter->tx_buffer_area =
2587 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2588 M_DEVBUF, M_WAITOK | M_ZERO);
2591 * Create DMA tags for tx buffers
2593 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2594 1, 0, /* alignment, bounds */
2595 BUS_SPACE_MAXADDR, /* lowaddr */
2596 BUS_SPACE_MAXADDR, /* highaddr */
2597 NULL, NULL, /* filter, filterarg */
2598 EM_TSO_SIZE, /* maxsize */
2599 EM_MAX_SCATTER, /* nsegments */
2600 PAGE_SIZE, /* maxsegsize */
2601 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2602 BUS_DMA_ONEBPAGE, /* flags */
2605 device_printf(dev, "Unable to allocate TX DMA tag\n");
2606 kfree(adapter->tx_buffer_area, M_DEVBUF);
2607 adapter->tx_buffer_area = NULL;
2612 * Create DMA maps for tx buffers
2614 for (i = 0; i < adapter->num_tx_desc; i++) {
2615 tx_buffer = &adapter->tx_buffer_area[i];
2617 error = bus_dmamap_create(adapter->txtag,
2618 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2621 device_printf(dev, "Unable to create TX DMA map\n");
2622 em_destroy_tx_ring(adapter, i);
2630 em_init_tx_ring(struct adapter *adapter)
2632 /* Clear the old ring contents */
2633 bzero(adapter->tx_desc_base,
2634 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2637 adapter->next_avail_tx_desc = 0;
2638 adapter->next_tx_to_clean = 0;
2639 adapter->num_tx_desc_avail = adapter->num_tx_desc;
2643 em_init_tx_unit(struct adapter *adapter)
2645 uint32_t tctl, tarc, tipg = 0;
2648 /* Setup the Base and Length of the Tx Descriptor Ring */
2649 bus_addr = adapter->txdma.dma_paddr;
2650 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2651 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2652 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2653 (uint32_t)(bus_addr >> 32));
2654 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2655 (uint32_t)bus_addr);
2656 /* Setup the HW Tx Head and Tail descriptor pointers */
2657 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2658 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
2660 /* Set the default values for the Tx Inter Packet Gap timer */
2661 switch (adapter->hw.mac.type) {
2663 tipg = DEFAULT_82542_TIPG_IPGT;
2664 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2665 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2668 case e1000_80003es2lan:
2669 tipg = DEFAULT_82543_TIPG_IPGR1;
2670 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2671 E1000_TIPG_IPGR2_SHIFT;
2675 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2676 adapter->hw.phy.media_type ==
2677 e1000_media_type_internal_serdes)
2678 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2680 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2681 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2682 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2686 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
2688 /* NOTE: 0 is not allowed for TIDV */
2689 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2690 if(adapter->hw.mac.type >= e1000_82540)
2691 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
2693 if (adapter->hw.mac.type == e1000_82571 ||
2694 adapter->hw.mac.type == e1000_82572) {
2695 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2696 tarc |= SPEED_MODE_BIT;
2697 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2698 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2699 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2701 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2702 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2704 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2707 /* Program the Transmit Control Register */
2708 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2709 tctl &= ~E1000_TCTL_CT;
2710 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2711 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2713 if (adapter->hw.mac.type >= e1000_82571)
2714 tctl |= E1000_TCTL_MULR;
2716 /* This write will effectively turn on the transmit unit. */
2717 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
2721 em_destroy_tx_ring(struct adapter *adapter, int ndesc)
2723 struct em_buffer *tx_buffer;
2726 if (adapter->tx_buffer_area == NULL)
2729 for (i = 0; i < ndesc; i++) {
2730 tx_buffer = &adapter->tx_buffer_area[i];
2732 KKASSERT(tx_buffer->m_head == NULL);
2733 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
2735 bus_dma_tag_destroy(adapter->txtag);
2737 kfree(adapter->tx_buffer_area, M_DEVBUF);
2738 adapter->tx_buffer_area = NULL;
2742 * The offload context needs to be set when we transfer the first
2743 * packet of a particular protocol (TCP/UDP). This routine has been
2744 * enhanced to deal with inserted VLAN headers.
2746 * If the new packet's ether header length, ip header length and
2747 * csum offloading type are same as the previous packet, we should
2748 * avoid allocating a new csum context descriptor; mainly to take
2749 * advantage of the pipeline effect of the TX data read request.
2751 * This function returns number of TX descrptors allocated for
2755 em_txcsum(struct adapter *adapter, struct mbuf *mp,
2756 uint32_t *txd_upper, uint32_t *txd_lower)
2758 struct e1000_context_desc *TXD;
2759 int curr_txd, ehdrlen, csum_flags;
2760 uint32_t cmd, hdr_len, ip_hlen;
2762 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
2763 ip_hlen = mp->m_pkthdr.csum_iphlen;
2764 ehdrlen = mp->m_pkthdr.csum_lhlen;
2766 if (adapter->csum_lhlen == ehdrlen &&
2767 adapter->csum_iphlen == ip_hlen &&
2768 adapter->csum_flags == csum_flags) {
2770 * Same csum offload context as the previous packets;
2773 *txd_upper = adapter->csum_txd_upper;
2774 *txd_lower = adapter->csum_txd_lower;
2779 * Setup a new csum offload context.
2782 curr_txd = adapter->next_avail_tx_desc;
2783 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2787 /* Setup of IP header checksum. */
2788 if (csum_flags & CSUM_IP) {
2790 * Start offset for header checksum calculation.
2791 * End offset for header checksum calculation.
2792 * Offset of place to put the checksum.
2794 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2795 TXD->lower_setup.ip_fields.ipcse =
2796 htole16(ehdrlen + ip_hlen - 1);
2797 TXD->lower_setup.ip_fields.ipcso =
2798 ehdrlen + offsetof(struct ip, ip_sum);
2799 cmd |= E1000_TXD_CMD_IP;
2800 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2802 hdr_len = ehdrlen + ip_hlen;
2804 if (csum_flags & CSUM_TCP) {
2806 * Start offset for payload checksum calculation.
2807 * End offset for payload checksum calculation.
2808 * Offset of place to put the checksum.
2810 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2811 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2812 TXD->upper_setup.tcp_fields.tucso =
2813 hdr_len + offsetof(struct tcphdr, th_sum);
2814 cmd |= E1000_TXD_CMD_TCP;
2815 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2816 } else if (csum_flags & CSUM_UDP) {
2818 * Start offset for header checksum calculation.
2819 * End offset for header checksum calculation.
2820 * Offset of place to put the checksum.
2822 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2823 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2824 TXD->upper_setup.tcp_fields.tucso =
2825 hdr_len + offsetof(struct udphdr, uh_sum);
2826 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2829 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2830 E1000_TXD_DTYP_D; /* Data descr */
2832 /* Save the information for this csum offloading context */
2833 adapter->csum_lhlen = ehdrlen;
2834 adapter->csum_iphlen = ip_hlen;
2835 adapter->csum_flags = csum_flags;
2836 adapter->csum_txd_upper = *txd_upper;
2837 adapter->csum_txd_lower = *txd_lower;
2839 TXD->tcp_seg_setup.data = htole32(0);
2840 TXD->cmd_and_length =
2841 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2843 if (++curr_txd == adapter->num_tx_desc)
2846 KKASSERT(adapter->num_tx_desc_avail > 0);
2847 adapter->num_tx_desc_avail--;
2849 adapter->next_avail_tx_desc = curr_txd;
2854 em_txeof(struct adapter *adapter)
2856 struct ifnet *ifp = &adapter->arpcom.ac_if;
2857 struct em_buffer *tx_buffer;
2858 int first, num_avail;
2860 if (adapter->tx_dd_head == adapter->tx_dd_tail)
2863 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2866 num_avail = adapter->num_tx_desc_avail;
2867 first = adapter->next_tx_to_clean;
2869 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
2870 struct e1000_tx_desc *tx_desc;
2871 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2873 tx_desc = &adapter->tx_desc_base[dd_idx];
2874 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2875 EM_INC_TXDD_IDX(adapter->tx_dd_head);
2877 if (++dd_idx == adapter->num_tx_desc)
2880 while (first != dd_idx) {
2885 tx_buffer = &adapter->tx_buffer_area[first];
2886 if (tx_buffer->m_head) {
2888 bus_dmamap_unload(adapter->txtag,
2890 m_freem(tx_buffer->m_head);
2891 tx_buffer->m_head = NULL;
2894 if (++first == adapter->num_tx_desc)
2901 adapter->next_tx_to_clean = first;
2902 adapter->num_tx_desc_avail = num_avail;
2904 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2905 adapter->tx_dd_head = 0;
2906 adapter->tx_dd_tail = 0;
2909 if (!EM_IS_OACTIVE(adapter)) {
2910 ifp->if_flags &= ~IFF_OACTIVE;
2912 /* All clean, turn off the timer */
2913 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2919 em_tx_collect(struct adapter *adapter)
2921 struct ifnet *ifp = &adapter->arpcom.ac_if;
2922 struct em_buffer *tx_buffer;
2923 int tdh, first, num_avail, dd_idx = -1;
2925 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2928 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
2929 if (tdh == adapter->next_tx_to_clean)
2932 if (adapter->tx_dd_head != adapter->tx_dd_tail)
2933 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2935 num_avail = adapter->num_tx_desc_avail;
2936 first = adapter->next_tx_to_clean;
2938 while (first != tdh) {
2943 tx_buffer = &adapter->tx_buffer_area[first];
2944 if (tx_buffer->m_head) {
2946 bus_dmamap_unload(adapter->txtag,
2948 m_freem(tx_buffer->m_head);
2949 tx_buffer->m_head = NULL;
2952 if (first == dd_idx) {
2953 EM_INC_TXDD_IDX(adapter->tx_dd_head);
2954 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2955 adapter->tx_dd_head = 0;
2956 adapter->tx_dd_tail = 0;
2959 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2963 if (++first == adapter->num_tx_desc)
2966 adapter->next_tx_to_clean = first;
2967 adapter->num_tx_desc_avail = num_avail;
2969 if (!EM_IS_OACTIVE(adapter)) {
2970 ifp->if_flags &= ~IFF_OACTIVE;
2972 /* All clean, turn off the timer */
2973 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2979 * When Link is lost sometimes there is work still in the TX ring
2980 * which will result in a watchdog, rather than allow that do an
2981 * attempted cleanup and then reinit here. Note that this has been
2982 * seens mostly with fiber adapters.
2985 em_tx_purge(struct adapter *adapter)
2987 struct ifnet *ifp = &adapter->arpcom.ac_if;
2989 if (!adapter->link_active && ifp->if_timer) {
2990 em_tx_collect(adapter);
2991 if (ifp->if_timer) {
2992 if_printf(ifp, "Link lost, TX pending, reinit\n");
3000 em_newbuf(struct adapter *adapter, int i, int init)
3003 bus_dma_segment_t seg;
3005 struct em_buffer *rx_buffer;
3008 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3010 adapter->mbuf_cluster_failed++;
3012 if_printf(&adapter->arpcom.ac_if,
3013 "Unable to allocate RX mbuf\n");
3017 m->m_len = m->m_pkthdr.len = MCLBYTES;
3019 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN)
3020 m_adj(m, ETHER_ALIGN);
3022 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
3023 adapter->rx_sparemap, m,
3024 &seg, 1, &nseg, BUS_DMA_NOWAIT);
3028 if_printf(&adapter->arpcom.ac_if,
3029 "Unable to load RX mbuf\n");
3034 rx_buffer = &adapter->rx_buffer_area[i];
3035 if (rx_buffer->m_head != NULL)
3036 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3038 map = rx_buffer->map;
3039 rx_buffer->map = adapter->rx_sparemap;
3040 adapter->rx_sparemap = map;
3042 rx_buffer->m_head = m;
3044 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
3049 em_create_rx_ring(struct adapter *adapter)
3051 device_t dev = adapter->dev;
3052 struct em_buffer *rx_buffer;
3055 adapter->rx_buffer_area =
3056 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3057 M_DEVBUF, M_WAITOK | M_ZERO);
3060 * Create DMA tag for rx buffers
3062 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3063 1, 0, /* alignment, bounds */
3064 BUS_SPACE_MAXADDR, /* lowaddr */
3065 BUS_SPACE_MAXADDR, /* highaddr */
3066 NULL, NULL, /* filter, filterarg */
3067 MCLBYTES, /* maxsize */
3069 MCLBYTES, /* maxsegsize */
3070 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3073 device_printf(dev, "Unable to allocate RX DMA tag\n");
3074 kfree(adapter->rx_buffer_area, M_DEVBUF);
3075 adapter->rx_buffer_area = NULL;
3080 * Create spare DMA map for rx buffers
3082 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3083 &adapter->rx_sparemap);
3085 device_printf(dev, "Unable to create spare RX DMA map\n");
3086 bus_dma_tag_destroy(adapter->rxtag);
3087 kfree(adapter->rx_buffer_area, M_DEVBUF);
3088 adapter->rx_buffer_area = NULL;
3093 * Create DMA maps for rx buffers
3095 for (i = 0; i < adapter->num_rx_desc; i++) {
3096 rx_buffer = &adapter->rx_buffer_area[i];
3098 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3101 device_printf(dev, "Unable to create RX DMA map\n");
3102 em_destroy_rx_ring(adapter, i);
3110 em_init_rx_ring(struct adapter *adapter)
3114 /* Reset descriptor ring */
3115 bzero(adapter->rx_desc_base,
3116 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc);
3118 /* Allocate new ones. */
3119 for (i = 0; i < adapter->num_rx_desc; i++) {
3120 error = em_newbuf(adapter, i, 1);
3125 /* Setup our descriptor pointers */
3126 adapter->next_rx_desc_to_check = 0;
3132 em_init_rx_unit(struct adapter *adapter)
3134 struct ifnet *ifp = &adapter->arpcom.ac_if;
3139 * Make sure receives are disabled while setting
3140 * up the descriptor ring
3142 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3143 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3145 if (adapter->hw.mac.type >= e1000_82540) {
3149 * Set the interrupt throttling rate. Value is calculated
3150 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3152 if (adapter->int_throttle_ceil)
3153 itr = 1000000000 / 256 / adapter->int_throttle_ceil;
3156 em_set_itr(adapter, itr);
3159 /* Disable accelerated ackknowledge */
3160 if (adapter->hw.mac.type == e1000_82574) {
3161 E1000_WRITE_REG(&adapter->hw,
3162 E1000_RFCTL, E1000_RFCTL_ACK_DIS);
3165 /* Receive Checksum Offload for TCP and UDP */
3166 if (ifp->if_capenable & IFCAP_RXCSUM) {
3169 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM);
3170 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3171 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum);
3175 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3176 * long latencies are observed, like Lenovo X60. This
3177 * change eliminates the problem, but since having positive
3178 * values in RDTR is a known source of problems on other
3179 * platforms another solution is being sought.
3181 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) {
3182 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573);
3183 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573);
3187 * Setup the Base and Length of the Rx Descriptor Ring
3189 bus_addr = adapter->rxdma.dma_paddr;
3190 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
3191 adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
3192 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0),
3193 (uint32_t)(bus_addr >> 32));
3194 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0),
3195 (uint32_t)bus_addr);
3198 * Setup the HW Rx Head and Tail Descriptor Pointers
3200 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
3201 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
3203 /* Set early receive threshold on appropriate hw */
3204 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3205 (adapter->hw.mac.type == e1000_pch2lan) ||
3206 (adapter->hw.mac.type == e1000_ich10lan)) &&
3207 (ifp->if_mtu > ETHERMTU)) {
3210 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0));
3211 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3);
3212 E1000_WRITE_REG(&adapter->hw, E1000_ERT, 0x100 | (1 << 13));
3215 if (adapter->hw.mac.type == e1000_pch2lan) {
3216 if (ifp->if_mtu > ETHERMTU)
3217 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE);
3219 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE);
3222 /* Setup the Receive Control Register */
3223 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3224 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3225 E1000_RCTL_RDMTS_HALF |
3226 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3228 /* Make sure VLAN Filters are off */
3229 rctl &= ~E1000_RCTL_VFE;
3231 if (e1000_tbi_sbp_enabled_82543(&adapter->hw))
3232 rctl |= E1000_RCTL_SBP;
3234 rctl &= ~E1000_RCTL_SBP;
3236 switch (adapter->rx_buffer_len) {
3239 rctl |= E1000_RCTL_SZ_2048;
3243 rctl |= E1000_RCTL_SZ_4096 |
3244 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3248 rctl |= E1000_RCTL_SZ_8192 |
3249 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3253 rctl |= E1000_RCTL_SZ_16384 |
3254 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3258 if (ifp->if_mtu > ETHERMTU)
3259 rctl |= E1000_RCTL_LPE;
3261 rctl &= ~E1000_RCTL_LPE;
3263 /* Enable Receives */
3264 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3268 em_destroy_rx_ring(struct adapter *adapter, int ndesc)
3270 struct em_buffer *rx_buffer;
3273 if (adapter->rx_buffer_area == NULL)
3276 for (i = 0; i < ndesc; i++) {
3277 rx_buffer = &adapter->rx_buffer_area[i];
3279 KKASSERT(rx_buffer->m_head == NULL);
3280 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map);
3282 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap);
3283 bus_dma_tag_destroy(adapter->rxtag);
3285 kfree(adapter->rx_buffer_area, M_DEVBUF);
3286 adapter->rx_buffer_area = NULL;
3290 em_rxeof(struct adapter *adapter, int count)
3292 struct ifnet *ifp = &adapter->arpcom.ac_if;
3293 uint8_t status, accept_frame = 0, eop = 0;
3294 uint16_t len, desc_len, prev_len_adj;
3295 struct e1000_rx_desc *current_desc;
3299 i = adapter->next_rx_desc_to_check;
3300 current_desc = &adapter->rx_desc_base[i];
3302 if (!(current_desc->status & E1000_RXD_STAT_DD))
3305 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) {
3306 struct mbuf *m = NULL;
3310 mp = adapter->rx_buffer_area[i].m_head;
3313 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3314 * needs to access the last received byte in the mbuf.
3316 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map,
3317 BUS_DMASYNC_POSTREAD);
3321 desc_len = le16toh(current_desc->length);
3322 status = current_desc->status;
3323 if (status & E1000_RXD_STAT_EOP) {
3326 if (desc_len < ETHER_CRC_LEN) {
3328 prev_len_adj = ETHER_CRC_LEN - desc_len;
3330 len = desc_len - ETHER_CRC_LEN;
3337 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
3339 uint32_t pkt_len = desc_len;
3341 if (adapter->fmp != NULL)
3342 pkt_len += adapter->fmp->m_pkthdr.len;
3344 last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
3345 if (TBI_ACCEPT(&adapter->hw, status,
3346 current_desc->errors, pkt_len, last_byte,
3347 adapter->min_frame_size, adapter->max_frame_size)) {
3348 e1000_tbi_adjust_stats_82543(&adapter->hw,
3349 &adapter->stats, pkt_len,
3350 adapter->hw.mac.addr,
3351 adapter->max_frame_size);
3360 if (em_newbuf(adapter, i, 0) != 0) {
3365 /* Assign correct length to the current fragment */
3368 if (adapter->fmp == NULL) {
3369 mp->m_pkthdr.len = len;
3370 adapter->fmp = mp; /* Store the first mbuf */
3374 * Chain mbuf's together
3378 * Adjust length of previous mbuf in chain if
3379 * we received less than 4 bytes in the last
3382 if (prev_len_adj > 0) {
3383 adapter->lmp->m_len -= prev_len_adj;
3384 adapter->fmp->m_pkthdr.len -=
3387 adapter->lmp->m_next = mp;
3388 adapter->lmp = adapter->lmp->m_next;
3389 adapter->fmp->m_pkthdr.len += len;
3393 adapter->fmp->m_pkthdr.rcvif = ifp;
3396 if (ifp->if_capenable & IFCAP_RXCSUM) {
3397 em_rxcsum(adapter, current_desc,
3401 if (status & E1000_RXD_STAT_VP) {
3402 adapter->fmp->m_pkthdr.ether_vlantag =
3403 (le16toh(current_desc->special) &
3404 E1000_RXD_SPC_VLAN_MASK);
3405 adapter->fmp->m_flags |= M_VLANTAG;
3408 adapter->fmp = NULL;
3409 adapter->lmp = NULL;
3415 /* Reuse loaded DMA map and just update mbuf chain */
3416 mp = adapter->rx_buffer_area[i].m_head;
3417 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
3418 mp->m_data = mp->m_ext.ext_buf;
3420 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN))
3421 m_adj(mp, ETHER_ALIGN);
3423 if (adapter->fmp != NULL) {
3424 m_freem(adapter->fmp);
3425 adapter->fmp = NULL;
3426 adapter->lmp = NULL;
3431 /* Zero out the receive descriptors status. */
3432 current_desc->status = 0;
3435 ifp->if_input(ifp, m);
3437 /* Advance our pointers to the next descriptor. */
3438 if (++i == adapter->num_rx_desc)
3440 current_desc = &adapter->rx_desc_base[i];
3442 adapter->next_rx_desc_to_check = i;
3444 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */
3446 i = adapter->num_rx_desc - 1;
3447 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i);
3451 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc,
3454 /* 82543 or newer only */
3455 if (adapter->hw.mac.type < e1000_82543 ||
3456 /* Ignore Checksum bit is set */
3457 (rx_desc->status & E1000_RXD_STAT_IXSM))
3460 if ((rx_desc->status & E1000_RXD_STAT_IPCS) &&
3461 !(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3462 /* IP Checksum Good */
3463 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
3466 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) &&
3467 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3468 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3470 CSUM_FRAG_NOT_CHECKED;
3471 mp->m_pkthdr.csum_data = htons(0xffff);
3476 em_enable_intr(struct adapter *adapter)
3478 uint32_t ims_mask = IMS_ENABLE_MASK;
3480 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer);
3484 if (adapter->hw.mac.type == e1000_82574) {
3485 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK);
3486 ims_mask |= EM_MSIX_MASK;
3489 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask);
3493 em_disable_intr(struct adapter *adapter)
3495 uint32_t clear = 0xffffffff;
3498 * The first version of 82542 had an errata where when link was forced
3499 * it would stay up even up even if the cable was disconnected.
3500 * Sequence errors were used to detect the disconnect and then the
3501 * driver would unforce the link. This code in the in the ISR. For
3502 * this to work correctly the Sequence error interrupt had to be
3503 * enabled all the time.
3505 if (adapter->hw.mac.type == e1000_82542 &&
3506 adapter->hw.revision_id == E1000_REVISION_2)
3507 clear &= ~E1000_ICR_RXSEQ;
3508 else if (adapter->hw.mac.type == e1000_82574)
3509 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0);
3511 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear);
3513 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer);
3517 * Bit of a misnomer, what this really means is
3518 * to enable OS management of the system... aka
3519 * to disable special hardware management features
3522 em_get_mgmt(struct adapter *adapter)
3524 /* A shared code workaround */
3525 #define E1000_82542_MANC2H E1000_MANC2H
3526 if (adapter->flags & EM_FLAG_HAS_MGMT) {
3527 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3528 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3530 /* disable hardware interception of ARP */
3531 manc &= ~(E1000_MANC_ARP_EN);
3533 /* enable receiving management packets to the host */
3534 if (adapter->hw.mac.type >= e1000_82571) {
3535 manc |= E1000_MANC_EN_MNG2HOST;
3536 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3537 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3538 manc2h |= E1000_MNG2HOST_PORT_623;
3539 manc2h |= E1000_MNG2HOST_PORT_664;
3540 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3543 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3548 * Give control back to hardware management
3549 * controller if there is one.
3552 em_rel_mgmt(struct adapter *adapter)
3554 if (adapter->flags & EM_FLAG_HAS_MGMT) {
3555 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3557 /* re-enable hardware interception of ARP */
3558 manc |= E1000_MANC_ARP_EN;
3560 if (adapter->hw.mac.type >= e1000_82571)
3561 manc &= ~E1000_MANC_EN_MNG2HOST;
3563 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3568 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3569 * For ASF and Pass Through versions of f/w this means that
3570 * the driver is loaded. For AMT version (only with 82573)
3571 * of the f/w this means that the network i/f is open.
3574 em_get_hw_control(struct adapter *adapter)
3576 /* Let firmware know the driver has taken over */
3577 if (adapter->hw.mac.type == e1000_82573) {
3580 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3581 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3582 swsm | E1000_SWSM_DRV_LOAD);
3586 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3587 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3588 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3590 adapter->flags |= EM_FLAG_HW_CTRL;
3594 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3595 * For ASF and Pass Through versions of f/w this means that the
3596 * driver is no longer loaded. For AMT version (only with 82573)
3597 * of the f/w this means that the network i/f is closed.
3600 em_rel_hw_control(struct adapter *adapter)
3602 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0)
3604 adapter->flags &= ~EM_FLAG_HW_CTRL;
3606 /* Let firmware taken over control of h/w */
3607 if (adapter->hw.mac.type == e1000_82573) {
3610 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3611 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3612 swsm & ~E1000_SWSM_DRV_LOAD);
3616 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3617 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3618 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3623 em_is_valid_eaddr(const uint8_t *addr)
3625 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3627 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3634 * Enable PCI Wake On Lan capability
3637 em_enable_wol(device_t dev)
3639 uint16_t cap, status;
3642 /* First find the capabilities pointer*/
3643 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3645 /* Read the PM Capabilities */
3646 id = pci_read_config(dev, cap, 1);
3647 if (id != PCIY_PMG) /* Something wrong */
3651 * OK, we have the power capabilities,
3652 * so now get the status register
3654 cap += PCIR_POWER_STATUS;
3655 status = pci_read_config(dev, cap, 2);
3656 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3657 pci_write_config(dev, cap, status, 2);
3662 * 82544 Coexistence issue workaround.
3663 * There are 2 issues.
3664 * 1. Transmit Hang issue.
3665 * To detect this issue, following equation can be used...
3666 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3667 * If SUM[3:0] is in between 1 to 4, we will have this issue.
3670 * To detect this issue, following equation can be used...
3671 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3672 * If SUM[3:0] is in between 9 to c, we will have this issue.
3675 * Make sure we do not have ending address
3676 * as 1,2,3,4(Hang) or 9,a,b,c (DAC)
3679 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array)
3681 uint32_t safe_terminator;
3684 * Since issue is sensitive to length and address.
3685 * Let us first check the address...
3688 desc_array->descriptor[0].address = address;
3689 desc_array->descriptor[0].length = length;
3690 desc_array->elements = 1;
3691 return (desc_array->elements);
3695 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF);
3697 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3698 if (safe_terminator == 0 ||
3699 (safe_terminator > 4 && safe_terminator < 9) ||
3700 (safe_terminator > 0xC && safe_terminator <= 0xF)) {
3701 desc_array->descriptor[0].address = address;
3702 desc_array->descriptor[0].length = length;
3703 desc_array->elements = 1;
3704 return (desc_array->elements);
3707 desc_array->descriptor[0].address = address;
3708 desc_array->descriptor[0].length = length - 4;
3709 desc_array->descriptor[1].address = address + (length - 4);
3710 desc_array->descriptor[1].length = 4;
3711 desc_array->elements = 2;
3712 return (desc_array->elements);
3716 em_update_stats(struct adapter *adapter)
3718 struct ifnet *ifp = &adapter->arpcom.ac_if;
3720 if (adapter->hw.phy.media_type == e1000_media_type_copper ||
3721 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3722 adapter->stats.symerrs +=
3723 E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3724 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3726 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3727 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3728 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3729 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3731 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3732 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3733 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3734 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3735 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3736 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3737 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3738 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3739 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3740 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3741 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3742 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3743 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3744 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3745 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3746 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3747 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3748 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3749 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3750 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3752 /* For the 64-bit byte counters the low dword must be read first. */
3753 /* Both registers clear on the read of the high dword */
3755 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH);
3756 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH);
3758 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3759 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3760 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3761 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3762 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3764 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3765 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3767 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3768 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3769 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3770 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3771 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3772 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3773 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3774 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3775 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3776 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3778 if (adapter->hw.mac.type >= e1000_82543) {
3779 adapter->stats.algnerrc +=
3780 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3781 adapter->stats.rxerrc +=
3782 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3783 adapter->stats.tncrs +=
3784 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3785 adapter->stats.cexterr +=
3786 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3787 adapter->stats.tsctc +=
3788 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3789 adapter->stats.tsctfc +=
3790 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3793 ifp->if_collisions = adapter->stats.colc;
3797 adapter->dropped_pkts + adapter->stats.rxerrc +
3798 adapter->stats.crcerrs + adapter->stats.algnerrc +
3799 adapter->stats.ruc + adapter->stats.roc +
3800 adapter->stats.mpc + adapter->stats.cexterr;
3804 adapter->stats.ecol + adapter->stats.latecol +
3805 adapter->watchdog_events;
3809 em_print_debug_info(struct adapter *adapter)
3811 device_t dev = adapter->dev;
3812 uint8_t *hw_addr = adapter->hw.hw_addr;
3814 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3815 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3816 E1000_READ_REG(&adapter->hw, E1000_CTRL),
3817 E1000_READ_REG(&adapter->hw, E1000_RCTL));
3818 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3819 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\
3820 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) );
3821 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3822 adapter->hw.fc.high_water,
3823 adapter->hw.fc.low_water);
3824 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3825 E1000_READ_REG(&adapter->hw, E1000_TIDV),
3826 E1000_READ_REG(&adapter->hw, E1000_TADV));
3827 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3828 E1000_READ_REG(&adapter->hw, E1000_RDTR),
3829 E1000_READ_REG(&adapter->hw, E1000_RADV));
3830 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n",
3831 (long long)adapter->tx_fifo_wrk_cnt,
3832 (long long)adapter->tx_fifo_reset_cnt);
3833 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3834 E1000_READ_REG(&adapter->hw, E1000_TDH(0)),
3835 E1000_READ_REG(&adapter->hw, E1000_TDT(0)));
3836 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3837 E1000_READ_REG(&adapter->hw, E1000_RDH(0)),
3838 E1000_READ_REG(&adapter->hw, E1000_RDT(0)));
3839 device_printf(dev, "Num Tx descriptors avail = %d\n",
3840 adapter->num_tx_desc_avail);
3841 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3842 adapter->no_tx_desc_avail1);
3843 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3844 adapter->no_tx_desc_avail2);
3845 device_printf(dev, "Std mbuf failed = %ld\n",
3846 adapter->mbuf_alloc_failed);
3847 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3848 adapter->mbuf_cluster_failed);
3849 device_printf(dev, "Driver dropped packets = %ld\n",
3850 adapter->dropped_pkts);
3851 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3852 adapter->no_tx_dma_setup);
3856 em_print_hw_stats(struct adapter *adapter)
3858 device_t dev = adapter->dev;
3860 device_printf(dev, "Excessive collisions = %lld\n",
3861 (long long)adapter->stats.ecol);
3862 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3863 device_printf(dev, "Symbol errors = %lld\n",
3864 (long long)adapter->stats.symerrs);
3866 device_printf(dev, "Sequence errors = %lld\n",
3867 (long long)adapter->stats.sec);
3868 device_printf(dev, "Defer count = %lld\n",
3869 (long long)adapter->stats.dc);
3870 device_printf(dev, "Missed Packets = %lld\n",
3871 (long long)adapter->stats.mpc);
3872 device_printf(dev, "Receive No Buffers = %lld\n",
3873 (long long)adapter->stats.rnbc);
3874 /* RLEC is inaccurate on some hardware, calculate our own. */
3875 device_printf(dev, "Receive Length Errors = %lld\n",
3876 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc));
3877 device_printf(dev, "Receive errors = %lld\n",
3878 (long long)adapter->stats.rxerrc);
3879 device_printf(dev, "Crc errors = %lld\n",
3880 (long long)adapter->stats.crcerrs);
3881 device_printf(dev, "Alignment errors = %lld\n",
3882 (long long)adapter->stats.algnerrc);
3883 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3884 (long long)adapter->stats.cexterr);
3885 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns);
3886 device_printf(dev, "watchdog timeouts = %ld\n",
3887 adapter->watchdog_events);
3888 device_printf(dev, "XON Rcvd = %lld\n",
3889 (long long)adapter->stats.xonrxc);
3890 device_printf(dev, "XON Xmtd = %lld\n",
3891 (long long)adapter->stats.xontxc);
3892 device_printf(dev, "XOFF Rcvd = %lld\n",
3893 (long long)adapter->stats.xoffrxc);
3894 device_printf(dev, "XOFF Xmtd = %lld\n",
3895 (long long)adapter->stats.xofftxc);
3896 device_printf(dev, "Good Packets Rcvd = %lld\n",
3897 (long long)adapter->stats.gprc);
3898 device_printf(dev, "Good Packets Xmtd = %lld\n",
3899 (long long)adapter->stats.gptc);
3903 em_print_nvm_info(struct adapter *adapter)
3905 uint16_t eeprom_data;
3908 /* Its a bit crude, but it gets the job done */
3909 kprintf("\nInterface EEPROM Dump:\n");
3910 kprintf("Offset\n0x0000 ");
3911 for (i = 0, j = 0; i < 32; i++, j++) {
3912 if (j == 8) { /* Make the offset block */
3914 kprintf("\n0x00%x0 ",row);
3916 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
3917 kprintf("%04x ", eeprom_data);
3923 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3925 struct adapter *adapter;
3930 error = sysctl_handle_int(oidp, &result, 0, req);
3931 if (error || !req->newptr)
3934 adapter = (struct adapter *)arg1;
3935 ifp = &adapter->arpcom.ac_if;
3937 lwkt_serialize_enter(ifp->if_serializer);
3940 em_print_debug_info(adapter);
3943 * This value will cause a hex dump of the
3944 * first 32 16-bit words of the EEPROM to
3948 em_print_nvm_info(adapter);
3950 lwkt_serialize_exit(ifp->if_serializer);
3956 em_sysctl_stats(SYSCTL_HANDLER_ARGS)
3961 error = sysctl_handle_int(oidp, &result, 0, req);
3962 if (error || !req->newptr)
3966 struct adapter *adapter = (struct adapter *)arg1;
3967 struct ifnet *ifp = &adapter->arpcom.ac_if;
3969 lwkt_serialize_enter(ifp->if_serializer);
3970 em_print_hw_stats(adapter);
3971 lwkt_serialize_exit(ifp->if_serializer);
3977 em_add_sysctl(struct adapter *adapter)
3979 sysctl_ctx_init(&adapter->sysctl_ctx);
3980 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx,
3981 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3982 device_get_nameunit(adapter->dev),
3984 if (adapter->sysctl_tree == NULL) {
3985 device_printf(adapter->dev, "can't add sysctl node\n");
3987 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
3988 SYSCTL_CHILDREN(adapter->sysctl_tree),
3989 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
3990 em_sysctl_debug_info, "I", "Debug Information");
3992 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
3993 SYSCTL_CHILDREN(adapter->sysctl_tree),
3994 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
3995 em_sysctl_stats, "I", "Statistics");
3997 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
3998 SYSCTL_CHILDREN(adapter->sysctl_tree),
3999 OID_AUTO, "rxd", CTLFLAG_RD,
4000 &adapter->num_rx_desc, 0, NULL);
4001 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
4002 SYSCTL_CHILDREN(adapter->sysctl_tree),
4003 OID_AUTO, "txd", CTLFLAG_RD,
4004 &adapter->num_tx_desc, 0, NULL);
4006 if (adapter->hw.mac.type >= e1000_82540) {
4007 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4008 SYSCTL_CHILDREN(adapter->sysctl_tree),
4009 OID_AUTO, "int_throttle_ceil",
4010 CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4011 em_sysctl_int_throttle, "I",
4012 "interrupt throttling rate");
4014 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4015 SYSCTL_CHILDREN(adapter->sysctl_tree),
4016 OID_AUTO, "int_tx_nsegs",
4017 CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4018 em_sysctl_int_tx_nsegs, "I",
4019 "# segments per TX interrupt");
4024 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
4026 struct adapter *adapter = (void *)arg1;
4027 struct ifnet *ifp = &adapter->arpcom.ac_if;
4028 int error, throttle;
4030 throttle = adapter->int_throttle_ceil;
4031 error = sysctl_handle_int(oidp, &throttle, 0, req);
4032 if (error || req->newptr == NULL)
4034 if (throttle < 0 || throttle > 1000000000 / 256)
4039 * Set the interrupt throttling rate in 256ns increments,
4040 * recalculate sysctl value assignment to get exact frequency.
4042 throttle = 1000000000 / 256 / throttle;
4044 /* Upper 16bits of ITR is reserved and should be zero */
4045 if (throttle & 0xffff0000)
4049 lwkt_serialize_enter(ifp->if_serializer);
4052 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
4054 adapter->int_throttle_ceil = 0;
4056 if (ifp->if_flags & IFF_RUNNING)
4057 em_set_itr(adapter, throttle);
4059 lwkt_serialize_exit(ifp->if_serializer);
4062 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
4063 adapter->int_throttle_ceil);
4069 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
4071 struct adapter *adapter = (void *)arg1;
4072 struct ifnet *ifp = &adapter->arpcom.ac_if;
4075 segs = adapter->tx_int_nsegs;
4076 error = sysctl_handle_int(oidp, &segs, 0, req);
4077 if (error || req->newptr == NULL)
4082 lwkt_serialize_enter(ifp->if_serializer);
4085 * Don't allow int_tx_nsegs to become:
4086 * o Less the oact_tx_desc
4087 * o Too large that no TX desc will cause TX interrupt to
4088 * be generated (OACTIVE will never recover)
4089 * o Too small that will cause tx_dd[] overflow
4091 if (segs < adapter->oact_tx_desc ||
4092 segs >= adapter->num_tx_desc - adapter->oact_tx_desc ||
4093 segs < adapter->num_tx_desc / EM_TXDD_SAFE) {
4097 adapter->tx_int_nsegs = segs;
4100 lwkt_serialize_exit(ifp->if_serializer);
4106 em_set_itr(struct adapter *adapter, uint32_t itr)
4108 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr);
4109 if (adapter->hw.mac.type == e1000_82574) {
4113 * When using MSIX interrupts we need to
4114 * throttle using the EITR register
4116 for (i = 0; i < 4; ++i) {
4117 E1000_WRITE_REG(&adapter->hw,
4118 E1000_EITR_82574(i), itr);
4124 em_disable_aspm(struct adapter *adapter)
4126 uint16_t link_cap, link_ctrl, disable;
4127 uint8_t pcie_ptr, reg;
4128 device_t dev = adapter->dev;
4130 switch (adapter->hw.mac.type) {
4135 * 82573 specification update
4136 * errata #8 disable L0s
4137 * errata #41 disable L1
4139 * 82571/82572 specification update
4140 # errata #13 disable L1
4141 * errata #68 disable L0s
4143 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4149 * 82574 specification update errata #20
4150 * 82583 specification update errata #9
4152 * There is no need to disable L1
4154 disable = PCIEM_LNKCTL_ASPM_L0S;
4161 pcie_ptr = pci_get_pciecap_ptr(dev);
4165 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4166 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4170 if_printf(&adapter->arpcom.ac_if,
4171 "disable ASPM %#02x\n", disable);
4174 reg = pcie_ptr + PCIER_LINKCTRL;
4175 link_ctrl = pci_read_config(dev, reg, 2);
4176 link_ctrl &= ~disable;
4177 pci_write_config(dev, reg, link_ctrl, 2);
4181 em_tso_pullup(struct adapter *adapter, struct mbuf **mp)
4183 int iphlen, hoff, thoff, ex = 0;
4188 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4190 iphlen = m->m_pkthdr.csum_iphlen;
4191 thoff = m->m_pkthdr.csum_thlen;
4192 hoff = m->m_pkthdr.csum_lhlen;
4194 KASSERT(iphlen > 0, ("invalid ip hlen"));
4195 KASSERT(thoff > 0, ("invalid tcp hlen"));
4196 KASSERT(hoff > 0, ("invalid ether hlen"));
4198 if (adapter->flags & EM_FLAG_TSO_PULLEX)
4201 if (m->m_len < hoff + iphlen + thoff + ex) {
4202 m = m_pullup(m, hoff + iphlen + thoff + ex);
4209 ip = mtodoff(m, struct ip *, hoff);
4216 em_tso_setup(struct adapter *adapter, struct mbuf *mp,
4217 uint32_t *txd_upper, uint32_t *txd_lower)
4219 struct e1000_context_desc *TXD;
4220 int hoff, iphlen, thoff, hlen;
4221 int mss, pktlen, curr_txd;
4223 iphlen = mp->m_pkthdr.csum_iphlen;
4224 thoff = mp->m_pkthdr.csum_thlen;
4225 hoff = mp->m_pkthdr.csum_lhlen;
4226 mss = mp->m_pkthdr.tso_segsz;
4227 pktlen = mp->m_pkthdr.len;
4229 if (adapter->csum_flags == CSUM_TSO &&
4230 adapter->csum_iphlen == iphlen &&
4231 adapter->csum_lhlen == hoff &&
4232 adapter->csum_thlen == thoff &&
4233 adapter->csum_mss == mss &&
4234 adapter->csum_pktlen == pktlen) {
4235 *txd_upper = adapter->csum_txd_upper;
4236 *txd_lower = adapter->csum_txd_lower;
4239 hlen = hoff + iphlen + thoff;
4242 * Setup a new TSO context.
4245 curr_txd = adapter->next_avail_tx_desc;
4246 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
4248 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4249 E1000_TXD_DTYP_D | /* Data descr type */
4250 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4252 /* IP and/or TCP header checksum calculation and insertion. */
4253 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4256 * Start offset for header checksum calculation.
4257 * End offset for header checksum calculation.
4258 * Offset of place put the checksum.
4260 TXD->lower_setup.ip_fields.ipcss = hoff;
4261 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4262 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4265 * Start offset for payload checksum calculation.
4266 * End offset for payload checksum calculation.
4267 * Offset of place to put the checksum.
4269 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4270 TXD->upper_setup.tcp_fields.tucse = 0;
4271 TXD->upper_setup.tcp_fields.tucso =
4272 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4275 * Payload size per packet w/o any headers.
4276 * Length of all headers up to payload.
4278 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4279 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4280 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4281 E1000_TXD_CMD_DEXT | /* Extended descr */
4282 E1000_TXD_CMD_TSE | /* TSE context */
4283 E1000_TXD_CMD_IP | /* Do IP csum */
4284 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4285 (pktlen - hlen)); /* Total len */
4287 /* Save the information for this TSO context */
4288 adapter->csum_flags = CSUM_TSO;
4289 adapter->csum_lhlen = hoff;
4290 adapter->csum_iphlen = iphlen;
4291 adapter->csum_thlen = thoff;
4292 adapter->csum_mss = mss;
4293 adapter->csum_pktlen = pktlen;
4294 adapter->csum_txd_upper = *txd_upper;
4295 adapter->csum_txd_lower = *txd_lower;
4297 if (++curr_txd == adapter->num_tx_desc)
4300 KKASSERT(adapter->num_tx_desc_avail > 0);
4301 adapter->num_tx_desc_avail--;
4303 adapter->next_avail_tx_desc = curr_txd;