2 * Copyright (c) 2000 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/agp/agp_intel.c,v 1.36 2007/11/12 21:51:36 jhb Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/malloc.h>
34 #include <sys/kernel.h>
38 #include <bus/pci/pcivar.h>
39 #include <bus/pci/pcireg.h>
44 #include <vm/vm_object.h>
47 #define MAX_APSIZE 0x3f /* 256 MB */
49 struct agp_intel_softc {
51 u_int32_t initial_aperture; /* aperture size at startup */
52 struct agp_gatt *gatt;
54 u_int32_t current_aperture; /* current aperture size */
58 agp_intel_match(device_t dev)
60 if (pci_get_class(dev) != PCIC_BRIDGE
61 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
64 if (agp_find_caps(dev) == 0)
67 switch (pci_get_devid(dev)) {
68 /* Intel -- vendor 0x8086 */
70 return ("Intel 82443LX (440 LX) host to PCI bridge");
72 return ("Intel 82443BX (440 BX) host to PCI bridge");
74 return ("Intel 82443GX host to PCI bridge");
76 return ("Intel 82443GX host to AGP bridge");
78 return ("Intel 82815 (i815 GMCH) host to PCI bridge");
81 return ("Intel 82820 host to AGP bridge");
83 return ("Intel 82830 host to AGP bridge");
85 return ("Intel 82840 host to AGP bridge");
87 return ("Intel 82845 host to AGP bridge");
89 return ("Intel 82850 host to AGP bridge");
91 return ("Intel 82855 host to AGP bridge");
93 return ("Intel 82860 host to AGP bridge");
95 return ("Intel 82865 host to AGP bridge");
97 return ("Intel E7205 host to AGP bridge");
99 return ("Intel E7505 host to AGP bridge");
101 return ("Intel 82875P host to AGP bridge");
103 return ("Intel 82845G host to AGP bridge");
105 return ("Intel 82855GM host to AGP bridge");
112 agp_intel_probe(device_t dev)
116 if (resource_disabled("agp", device_get_unit(dev)))
118 desc = agp_intel_match(dev);
121 device_set_desc(dev, desc);
122 return (BUS_PROBE_DEFAULT);
129 agp_intel_commit_gatt(device_t dev)
131 struct agp_intel_softc *sc;
135 sc = device_get_softc(dev);
136 type = pci_get_devid(dev);
138 /* Install the gatt. */
139 pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4);
141 /* Enable the GLTB and setup the control register. */
143 case 0x71908086: /* 440LX/EX */
144 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
146 case 0x71808086: /* 440BX */
148 * XXX: Should be 0xa080? Bit 9 is undefined, and
149 * bit 13 being on and bit 15 being clear is illegal.
151 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
154 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
155 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
158 /* Enable aperture accesses. */
160 case 0x25008086: /* i820 */
161 case 0x25018086: /* i820 */
162 pci_write_config(dev, AGP_INTEL_I820_RDCR,
163 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
166 case 0x1a308086: /* i845 */
167 case 0x25608086: /* i845G */
168 case 0x33408086: /* i855 */
169 case 0x35808086: /* i855GM */
170 case 0x25708086: /* i865 */
171 case 0x25788086: /* i875P */
172 pci_write_config(dev, AGP_INTEL_I845_AGPM,
173 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
176 case 0x1a218086: /* i840 */
177 case 0x25308086: /* i850 */
178 case 0x25318086: /* i860 */
179 case 0x255d8086: /* E7205 */
180 case 0x25508086: /* E7505 */
181 pci_write_config(dev, AGP_INTEL_MCHCFG,
182 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
185 default: /* Intel Generic (maybe) */
186 pci_write_config(dev, AGP_INTEL_NBXCFG,
187 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
188 & ~(1 << 10)) | (1 << 9), 4);
193 case 0x1a218086: /* i840 */
194 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
196 case 0x25008086: /* i820 */
197 case 0x25018086: /* i820 */
198 case 0x1a308086: /* i845 */
199 case 0x25608086: /* i845G */
200 case 0x25308086: /* i850 */
201 case 0x33408086: /* i855 */
202 case 0x25318086: /* i860 */
203 case 0x25708086: /* i865 */
204 case 0x25788086: /* i875P */
205 case 0x255d8086: /* E7205 */
206 case 0x25508086: /* E7505 */
207 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
209 default: /* Intel Generic (maybe) */
210 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
215 agp_intel_attach(device_t dev)
217 struct agp_intel_softc *sc;
218 struct agp_gatt *gatt;
222 sc = device_get_softc(dev);
224 error = agp_generic_attach(dev);
228 /* Determine maximum supported aperture size. */
229 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
230 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
231 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
233 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
234 sc->current_aperture = sc->initial_aperture = AGP_GET_APERTURE(dev);
235 if (sc->initial_aperture == 0) {
236 device_printf(dev, "bad initial aperture size, disabling\n");
241 gatt = agp_alloc_gatt(dev);
246 * Probably contigmalloc failure. Try reducing the
247 * aperture so that the gatt size reduces.
249 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
250 agp_generic_detach(dev);
256 agp_intel_commit_gatt(dev);
262 agp_intel_detach(device_t dev)
264 struct agp_intel_softc *sc;
267 sc = device_get_softc(dev);
271 /* Disable aperture accesses. */
272 switch (pci_get_devid(dev)) {
273 case 0x25008086: /* i820 */
274 case 0x25018086: /* i820 */
275 reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
276 kprintf("%s: set RDCR to %02x\n", __func__, reg & 0xff);
277 pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);
279 case 0x1a308086: /* i845 */
280 case 0x25608086: /* i845G */
281 case 0x33408086: /* i855 */
282 case 0x35808086: /* i855GM */
283 case 0x25708086: /* i865 */
284 case 0x25788086: /* i875P */
285 reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
286 kprintf("%s: set AGPM to %02x\n", __func__, reg & 0xff);
287 pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);
289 case 0x1a218086: /* i840 */
290 case 0x25308086: /* i850 */
291 case 0x25318086: /* i860 */
292 case 0x255d8086: /* E7205 */
293 case 0x25508086: /* E7505 */
294 reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);
295 kprintf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff);
296 pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);
298 default: /* Intel Generic (maybe) */
299 reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);
300 kprintf("%s: set NBXCFG to %08x\n", __func__, reg);
301 pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);
303 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
304 AGP_SET_APERTURE(dev, sc->initial_aperture);
305 agp_free_gatt(sc->gatt);
312 agp_intel_resume(device_t dev)
314 struct agp_intel_softc *sc;
315 sc = device_get_softc(dev);
317 AGP_SET_APERTURE(dev, sc->current_aperture);
318 agp_intel_commit_gatt(dev);
319 return (bus_generic_resume(dev));
323 agp_intel_get_aperture(device_t dev)
325 struct agp_intel_softc *sc;
328 sc = device_get_softc(dev);
330 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
333 * The size is determined by the number of low bits of
334 * register APBASE which are forced to zero. The low 22 bits
335 * are always forced to zero and each zero bit in the apsize
336 * field just read forces the corresponding bit in the 27:22
337 * to be zero. We calculate the aperture size accordingly.
339 return ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1);
343 agp_intel_set_aperture(device_t dev, u_int32_t aperture)
345 struct agp_intel_softc *sc;
348 sc = device_get_softc(dev);
351 * Reverse the magic from get_aperture.
353 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask;
356 * Double check for sanity.
358 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
361 sc->current_aperture = apsize;
363 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
369 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
371 struct agp_intel_softc *sc;
373 sc = device_get_softc(dev);
375 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
378 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
383 agp_intel_unbind_page(device_t dev, int offset)
385 struct agp_intel_softc *sc;
387 sc = device_get_softc(dev);
389 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
392 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
397 agp_intel_flush_tlb(device_t dev)
401 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
402 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4);
403 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);
406 static device_method_t agp_intel_methods[] = {
407 /* Device interface */
408 DEVMETHOD(device_probe, agp_intel_probe),
409 DEVMETHOD(device_attach, agp_intel_attach),
410 DEVMETHOD(device_detach, agp_intel_detach),
411 DEVMETHOD(device_shutdown, bus_generic_shutdown),
412 DEVMETHOD(device_suspend, bus_generic_suspend),
413 DEVMETHOD(device_resume, agp_intel_resume),
416 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture),
417 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture),
418 DEVMETHOD(agp_bind_page, agp_intel_bind_page),
419 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page),
420 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb),
421 DEVMETHOD(agp_enable, agp_generic_enable),
422 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
423 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
424 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
425 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
430 static driver_t agp_intel_driver = {
433 sizeof(struct agp_intel_softc),
436 static devclass_t agp_devclass;
438 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, NULL, NULL);
439 MODULE_DEPEND(agp_intel, agp, 1, 1, 1);
440 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);