2 * Copyright (c) 2003-2005 Nate Lawson (SDG)
3 * Copyright (c) 2001 Michael Smith
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/acpica/acpi_cpu.c,v 1.72 2008/04/12 12:06:00 rpaulo Exp $
28 * $DragonFly: src/sys/dev/acpica5/acpi_cpu.c,v 1.21 2008/09/05 10:28:35 hasso Exp $
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/globaldata.h>
37 #include <sys/power.h>
40 #include <sys/thread2.h>
42 #include <bus/pci/pcivar.h>
43 #include <machine/atomic.h>
44 #include <machine/globaldata.h>
45 #include <machine/md_var.h>
46 #include <machine/smp.h>
54 * Support for ACPI Processor devices, including C[1-3] sleep states.
57 /* Hooks for the ACPI CA debugging infrastructure */
58 #define _COMPONENT ACPI_PROCESSOR
59 ACPI_MODULE_NAME("PROCESSOR")
62 struct resource *p_lvlx; /* Register to read to enter state. */
63 uint32_t type; /* C1-3 (C4 and up treated as C3). */
64 uint32_t trans_lat; /* Transition latency (usec). */
65 uint32_t power; /* Power consumed (mW). */
66 int res_type; /* Resource type for p_lvlx. */
68 #define MAX_CX_STATES 8
70 struct acpi_cpu_softc {
72 struct acpi_cpux_softc *cpu_parent;
73 ACPI_HANDLE cpu_handle;
74 struct mdglobaldata *md;
75 uint32_t cpu_acpi_id; /* ACPI processor id */
76 uint32_t cpu_p_blk; /* ACPI P_BLK location */
77 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */
78 struct acpi_cx cpu_cx_states[MAX_CX_STATES];
79 int cpu_cx_count; /* Number of valid Cx states. */
80 int cpu_prev_sleep;/* Last idle sleep duration. */
81 int cpu_features; /* Child driver supported features. */
83 int cpu_non_c3; /* Index of lowest non-C3 state. */
84 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */
85 /* Values for sysctl. */
87 char cpu_cx_supported[64];
91 struct acpi_cpu_device {
92 struct resource_list ad_rl;
95 #define CPU_GET_REG(reg, width) \
96 (bus_space_read_ ## width(rman_get_bustag((reg)), \
97 rman_get_bushandle((reg)), 0))
98 #define CPU_SET_REG(reg, width, val) \
99 (bus_space_write_ ## width(rman_get_bustag((reg)), \
100 rman_get_bushandle((reg)), 0, (val)))
102 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */
104 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */
106 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */
107 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */
109 #define PCI_VENDOR_INTEL 0x8086
110 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */
111 #define PCI_REVISION_A_STEP 0
112 #define PCI_REVISION_B_STEP 1
113 #define PCI_REVISION_4E 2
114 #define PCI_REVISION_4M 3
115 #define PIIX4_DEVACTB_REG 0x58
116 #define PIIX4_BRLD_EN_IRQ0 (1<<0)
117 #define PIIX4_BRLD_EN_IRQ (1<<1)
118 #define PIIX4_BRLD_EN_IRQ8 (1<<5)
119 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8)
120 #define PIIX4_PCNTRL_BST_EN (1<<10)
122 /* Platform hardware resource information. */
123 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */
124 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */
125 static int cpu_quirks; /* Indicate any hardware bugs. */
128 static int cpu_disable_idle; /* Disable entry to idle function */
129 static int cpu_cx_count; /* Number of valid Cx states */
131 /* Values for sysctl. */
132 static int cpu_cx_generic;
133 static int cpu_cx_lowest;
135 /* C3 state transition */
136 static int cpu_c3_ncpus;
138 static device_t *cpu_devices;
139 static int cpu_ndevices;
140 static struct acpi_cpu_softc **cpu_softc;
142 static int acpi_cpu_cst_probe(device_t dev);
143 static int acpi_cpu_cst_attach(device_t dev);
144 static int acpi_cpu_suspend(device_t dev);
145 static int acpi_cpu_resume(device_t dev);
146 static struct resource_list *acpi_cpu_cst_get_rlist(device_t dev,
148 static device_t acpi_cpu_add_child(device_t bus, device_t parent, int order,
149 const char *name, int unit);
150 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index,
152 static int acpi_cpu_shutdown(device_t dev);
153 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc);
154 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc);
155 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc);
156 static void acpi_cpu_startup(void *arg);
157 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc);
158 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc);
159 static void acpi_cpu_idle(void);
160 static void acpi_cpu_cst_notify(device_t);
161 static int acpi_cpu_quirks(void);
162 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS);
163 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val);
164 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
165 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
167 static void acpi_cpu_c1(void); /* XXX */
169 static device_method_t acpi_cpu_cst_methods[] = {
170 /* Device interface */
171 DEVMETHOD(device_probe, acpi_cpu_cst_probe),
172 DEVMETHOD(device_attach, acpi_cpu_cst_attach),
173 DEVMETHOD(device_detach, bus_generic_detach),
174 DEVMETHOD(device_shutdown, acpi_cpu_shutdown),
175 DEVMETHOD(device_suspend, acpi_cpu_suspend),
176 DEVMETHOD(device_resume, acpi_cpu_resume),
179 DEVMETHOD(bus_add_child, acpi_cpu_add_child),
180 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar),
181 DEVMETHOD(bus_get_resource_list, acpi_cpu_cst_get_rlist),
182 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
183 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
184 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
185 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
186 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
187 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
188 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
189 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
190 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
194 static driver_t acpi_cpu_cst_driver = {
196 acpi_cpu_cst_methods,
197 sizeof(struct acpi_cpu_softc),
200 static devclass_t acpi_cpu_cst_devclass;
201 DRIVER_MODULE(cpu_cst, cpu, acpi_cpu_cst_driver, acpi_cpu_cst_devclass, 0, 0);
202 MODULE_DEPEND(cpu_cst, acpi, 1, 1, 1);
205 acpi_cpu_cst_probe(device_t dev)
209 if (acpi_disabled("cpu_cst") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR)
212 cpu_id = acpi_get_magic(dev);
214 if (cpu_softc == NULL)
215 cpu_softc = kmalloc(sizeof(struct acpi_cpu_softc *) *
216 SMP_MAXCPU, M_TEMP /* XXX */, M_INTWAIT | M_ZERO);
219 * Check if we already probed this processor. We scan the bus twice
220 * so it's possible we've already seen this one.
222 if (cpu_softc[cpu_id] != NULL) {
223 device_printf(dev, "CPU%d cstate already exist\n", cpu_id);
227 /* Mark this processor as in-use and save our derived id for attach. */
228 cpu_softc[cpu_id] = (void *)1;
229 device_set_desc(dev, "ACPI CPU C-State");
235 acpi_cpu_cst_attach(device_t dev)
238 ACPI_OBJECT arg[4], *obj;
239 ACPI_OBJECT_LIST arglist;
240 struct mdglobaldata *md;
241 struct acpi_cpu_softc *sc;
244 int cpu_id, drv_count, i;
248 /* UUID needed by _OSC evaluation */
249 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29,
250 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70,
251 0x58, 0x71, 0x39, 0x53 };
253 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
255 sc = device_get_softc(dev);
257 sc->cpu_parent = device_get_softc(device_get_parent(dev));
258 sc->cpu_handle = acpi_get_handle(dev);
259 cpu_id = acpi_get_magic(dev);
260 cpu_softc[cpu_id] = sc;
261 md = (struct mdglobaldata *)globaldata_find(device_get_unit(dev));
263 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand;
264 cpu_cst_cnt = AcpiGbl_FADT.CstControl;
267 buf.Length = ACPI_ALLOCATE_BUFFER;
268 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf);
269 if (ACPI_FAILURE(status)) {
270 device_printf(dev, "attach failed to get Processor obj - %s\n",
271 AcpiFormatException(status));
274 obj = (ACPI_OBJECT *)buf.Pointer;
275 sc->cpu_p_blk = obj->Processor.PblkAddress;
276 sc->cpu_p_blk_len = obj->Processor.PblkLength;
277 sc->cpu_acpi_id = obj->Processor.ProcId;
279 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n",
280 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len));
283 * If this is the first cpu we attach, create and initialize the generic
284 * resources that will be used by all acpi cpu devices.
286 if (device_get_unit(dev) == 0) {
287 /* Assume we won't be using generic Cx mode by default */
288 cpu_cx_generic = FALSE;
290 /* Queue post cpu-probing task handler */
291 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL);
295 * Before calling any CPU methods, collect child driver feature hints
296 * and notify ACPI of them. We support unified SMP power control
297 * so advertise this ourselves. Note this is not the same as independent
298 * SMP control where each CPU can have different settings.
300 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3;
301 if (devclass_get_drivers(acpi_cpu_cst_devclass,
302 &drivers, &drv_count) == 0) {
303 for (i = 0; i < drv_count; i++) {
304 if (ACPI_GET_FEATURES(drivers[i], &features) == 0)
305 sc->cpu_features |= features;
307 kfree(drivers, M_TEMP);
311 * CPU capabilities are specified as a buffer of 32-bit integers:
312 * revision, count, and one or more capabilities. The revision of
313 * "1" is not specified anywhere but seems to match Linux.
315 if (sc->cpu_features) {
316 arglist.Pointer = arg;
318 arg[0].Type = ACPI_TYPE_BUFFER;
319 arg[0].Buffer.Length = sizeof(cap_set);
320 arg[0].Buffer.Pointer = (uint8_t *)cap_set;
321 cap_set[0] = 1; /* revision */
322 cap_set[1] = 1; /* number of capabilities integers */
323 cap_set[2] = sc->cpu_features;
324 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL);
327 * On some systems we need to evaluate _OSC so that the ASL
328 * loads the _PSS and/or _PDC methods at runtime.
330 * TODO: evaluate failure of _OSC.
332 arglist.Pointer = arg;
334 arg[0].Type = ACPI_TYPE_BUFFER;
335 arg[0].Buffer.Length = sizeof(cpu_oscuuid);
336 arg[0].Buffer.Pointer = cpu_oscuuid; /* UUID */
337 arg[1].Type = ACPI_TYPE_INTEGER;
338 arg[1].Integer.Value = 1; /* revision */
339 arg[2].Type = ACPI_TYPE_INTEGER;
340 arg[2].Integer.Value = 1; /* count */
341 arg[3].Type = ACPI_TYPE_BUFFER;
342 arg[3].Buffer.Length = sizeof(cap_set); /* Capabilities buffer */
343 arg[3].Buffer.Pointer = (uint8_t *)cap_set;
345 AcpiEvaluateObject(sc->cpu_handle, "_OSC", &arglist, NULL);
348 /* Probe for Cx state support. */
349 acpi_cpu_cx_probe(sc);
351 /* Finally, call identify and probe/attach for child devices. */
352 bus_generic_probe(dev);
353 bus_generic_attach(dev);
359 * Disable any entry to the idle function during suspend and re-enable it
363 acpi_cpu_suspend(device_t dev)
367 error = bus_generic_suspend(dev);
370 cpu_disable_idle = TRUE;
375 acpi_cpu_resume(device_t dev)
378 cpu_disable_idle = FALSE;
379 return (bus_generic_resume(dev));
382 static struct resource_list *
383 acpi_cpu_cst_get_rlist(device_t dev, device_t child)
385 struct acpi_cpu_device *ad;
387 ad = device_get_ivars(child);
394 acpi_cpu_add_child(device_t bus, device_t parent, int order,
395 const char *name, int unit)
397 struct acpi_cpu_device *ad;
400 if ((ad = kmalloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL)
403 resource_list_init(&ad->ad_rl);
405 child = device_add_child_ordered(parent, order, name, unit);
407 device_set_ivars(child, ad);
414 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
416 struct acpi_cpu_softc *sc;
418 sc = device_get_softc(dev);
420 case ACPI_IVAR_HANDLE:
421 *result = (uintptr_t)sc->cpu_handle;
425 *result = (uintptr_t)sc->cpu_pcpu;
435 acpi_cpu_shutdown(device_t dev)
437 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
439 /* Allow children to shutdown first. */
440 bus_generic_shutdown(dev);
443 * Disable any entry to the idle function. There is a small race where
444 * an idle thread have passed this check but not gone to sleep. This
445 * is ok since device_shutdown() does not free the softc, otherwise
446 * we'd have to be sure all threads were evicted before returning.
448 cpu_disable_idle = TRUE;
454 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc)
456 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
458 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
459 sc->cpu_prev_sleep = 1000000;
460 sc->cpu_cx_lowest = 0;
463 * Check for the ACPI 2.0 _CST sleep states object. If we can't find
464 * any, we'll revert to generic FADT/P_BLK Cx control method which will
465 * be handled by acpi_cpu_startup. We need to defer to after having
466 * probed all the cpus in the system before probing for generic Cx
467 * states as we may already have found cpus with valid _CST packages
469 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) {
471 * We were unable to find a _CST package for this cpu or there
472 * was an error parsing it. Switch back to generic mode.
474 cpu_cx_generic = TRUE;
476 device_printf(sc->cpu_dev, "switching to generic Cx mode\n");
480 * TODO: _CSD Package should be checked here.
485 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc)
487 ACPI_GENERIC_ADDRESS gas;
488 struct acpi_cx *cx_ptr;
490 sc->cpu_cx_count = 0;
491 cx_ptr = sc->cpu_cx_states;
493 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
494 sc->cpu_prev_sleep = 1000000;
496 /* C1 has been required since just after ACPI 1.0 */
497 cx_ptr->type = ACPI_STATE_C1;
498 cx_ptr->trans_lat = 0;
503 * The spec says P_BLK must be 6 bytes long. However, some systems
504 * use it to indicate a fractional set of features present so we
505 * take 5 as C2. Some may also have a value of 7 to indicate
506 * another C3 but most use _CST for this (as required) and having
507 * "only" C1-C3 is not a hardship.
509 if (sc->cpu_p_blk_len < 5)
512 /* Validate and allocate resources for C2 (P_LVL2). */
513 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO;
515 if (AcpiGbl_FADT.C2Latency <= 100) {
516 gas.Address = sc->cpu_p_blk + 4;
517 cx_ptr->p_lvlx = acpi_bus_alloc_gas(sc->cpu_dev, &sc->cpu_rid, &gas,
519 if (cx_ptr->p_lvlx != NULL) {
521 cx_ptr->type = ACPI_STATE_C2;
522 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency;
527 if (sc->cpu_p_blk_len < 6)
530 /* Validate and allocate resources for C3 (P_LVL3). */
531 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) {
532 gas.Address = sc->cpu_p_blk + 5;
533 cx_ptr->p_lvlx = acpi_bus_alloc_gas(sc->cpu_dev, &sc->cpu_rid, &gas,
535 if (cx_ptr->p_lvlx != NULL) {
537 cx_ptr->type = ACPI_STATE_C3;
538 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency;
546 * Parse a _CST package and set up its Cx states. Since the _CST object
547 * can change dynamically, our notify handler may call this function
548 * to clean up and probe the new _CST package.
551 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc)
553 struct acpi_cx *cx_ptr;
561 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
564 buf.Length = ACPI_ALLOCATE_BUFFER;
565 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf);
566 if (ACPI_FAILURE(status))
569 /* _CST is a package with a count and at least one Cx package. */
570 top = (ACPI_OBJECT *)buf.Pointer;
571 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) {
572 device_printf(sc->cpu_dev, "invalid _CST package\n");
573 AcpiOsFree(buf.Pointer);
576 if (count != top->Package.Count - 1) {
577 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n",
578 count, top->Package.Count - 1);
579 count = top->Package.Count - 1;
581 if (count > MAX_CX_STATES) {
582 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count);
583 count = MAX_CX_STATES;
586 /* Set up all valid states. */
587 sc->cpu_cx_count = 0;
588 cx_ptr = sc->cpu_cx_states;
589 for (i = 0; i < count; i++) {
590 pkg = &top->Package.Elements[i + 1];
591 if (!ACPI_PKG_VALID(pkg, 4) ||
592 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 ||
593 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 ||
594 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) {
596 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n");
600 /* Validate the state to see if we should use it. */
601 switch (cx_ptr->type) {
608 if (cx_ptr->trans_lat > 100) {
609 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
610 "acpi_cpu%d: C2[%d] not available.\n",
611 device_get_unit(sc->cpu_dev), i));
618 if (cx_ptr->trans_lat > 1000 ||
619 (cpu_quirks & CPU_QUIRK_NO_C3) != 0) {
621 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
622 "acpi_cpu%d: C3[%d] not available.\n",
623 device_get_unit(sc->cpu_dev), i));
630 /* Free up any previous register. */
631 if (cx_ptr->p_lvlx != NULL) {
632 bus_release_resource(sc->cpu_dev, 0, 0, cx_ptr->p_lvlx);
633 cx_ptr->p_lvlx = NULL;
637 /* Allocate the control register for C2 or C3. */
638 acpi_PkgGas(sc->cpu_dev, pkg, 0, &sc->cpu_rid, &cx_ptr->p_lvlx,
640 if (cx_ptr->p_lvlx) {
642 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
643 "acpi_cpu%d: Got C%d - %d latency\n",
644 device_get_unit(sc->cpu_dev), cx_ptr->type,
650 AcpiOsFree(buf.Pointer);
656 * Call this *after* all CPUs have been attached.
659 acpi_cpu_startup(void *arg)
661 struct acpi_cpu_softc *sc;
664 /* Get set of CPU devices */
665 devclass_get_devices(acpi_cpu_cst_devclass, &cpu_devices, &cpu_ndevices);
668 * Setup any quirks that might necessary now that we have probed
674 if (cpu_cx_generic) {
676 * We are using generic Cx mode, probe for available Cx states
677 * for all processors.
679 for (i = 0; i < cpu_ndevices; i++) {
680 sc = device_get_softc(cpu_devices[i]);
681 acpi_cpu_generic_cx_probe(sc);
682 if (sc->cpu_cx_count > cpu_cx_count)
683 cpu_cx_count = sc->cpu_cx_count;
687 * Find the highest Cx state common to all CPUs
688 * in the system, taking quirks into account.
690 for (i = 0; i < cpu_ndevices; i++) {
691 sc = device_get_softc(cpu_devices[i]);
692 if (sc->cpu_cx_count < cpu_cx_count)
693 cpu_cx_count = sc->cpu_cx_count;
697 * We are using _CST mode, remove C3 state if necessary.
698 * Update the largest Cx state supported in the global cpu_cx_count.
699 * It will be used in the global Cx sysctl handler.
700 * As we now know for sure that we will be using _CST mode
701 * install our notify handler.
703 for (i = 0; i < cpu_ndevices; i++) {
704 sc = device_get_softc(cpu_devices[i]);
705 if (cpu_quirks & CPU_QUIRK_NO_C3) {
706 sc->cpu_cx_count = sc->cpu_non_c3 + 1;
708 if (sc->cpu_cx_count > cpu_cx_count)
709 cpu_cx_count = sc->cpu_cx_count;
710 sc->cpu_parent->cpux_cst_notify = acpi_cpu_cst_notify;
714 /* Perform Cx final initialization. */
715 for (i = 0; i < cpu_ndevices; i++) {
716 sc = device_get_softc(cpu_devices[i]);
717 acpi_cpu_startup_cx(sc);
719 if (sc->cpu_parent->glob_sysctl_tree != NULL) {
720 struct acpi_cpux_softc *cpux = sc->cpu_parent;
722 /* Add a sysctl handler to handle global Cx lowest setting */
723 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx,
724 SYSCTL_CHILDREN(cpux->glob_sysctl_tree),
725 OID_AUTO, "cx_lowest",
726 CTLTYPE_STRING | CTLFLAG_RW, NULL, 0,
727 acpi_cpu_global_cx_lowest_sysctl, "A",
728 "Global lowest Cx sleep state to use");
732 /* Take over idling from cpu_idle_default(). */
734 cpu_disable_idle = FALSE;
735 cpu_idle_hook = acpi_cpu_idle;
739 acpi_cpu_cx_list(struct acpi_cpu_softc *sc)
745 * Set up the list of Cx states
748 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported),
750 for (i = 0; i < sc->cpu_cx_count; i++) {
751 sbuf_printf(&sb, "C%d/%d ", i + 1, sc->cpu_cx_states[i].trans_lat);
752 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3)
760 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc)
762 struct acpi_cpux_softc *cpux = sc->cpu_parent;
764 acpi_cpu_cx_list(sc);
766 SYSCTL_ADD_STRING(&cpux->pcpu_sysctl_ctx,
767 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree),
768 OID_AUTO, "cx_supported", CTLFLAG_RD,
769 sc->cpu_cx_supported, 0,
770 "Cx/microsecond values for supported Cx states");
771 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx,
772 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree),
773 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW,
774 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A",
775 "lowest Cx sleep state to use");
776 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx,
777 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree),
778 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD,
779 (void *)sc, 0, acpi_cpu_usage_sysctl, "A",
780 "percent usage for each Cx state");
783 /* Signal platform that we can handle _CST notification. */
784 if (!cpu_cx_generic && cpu_cst_cnt != 0) {
786 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8);
793 * Idle the CPU in the lowest state possible. This function is called with
794 * interrupts disabled. Note that once it re-enables interrupts, a task
795 * switch can occur so do not access shared data (i.e. the softc) after
796 * interrupts are re-enabled.
801 struct acpi_cpu_softc *sc;
802 struct acpi_cx *cx_next;
803 uint32_t start_time, end_time;
804 int bm_active, cx_next_idx, i;
806 /* If disabled, return immediately. */
807 if (cpu_disable_idle) {
813 * Look up our CPU id to get our softc. If it's NULL, we'll use C1
814 * since there is no ACPI processor object for this CPU. This occurs
815 * for logical CPUs in the HTT case.
817 sc = cpu_softc[mdcpu->mi.gd_cpuid];
823 /* Find the lowest state that has small enough latency. */
825 for (i = sc->cpu_cx_lowest; i >= 0; i--) {
826 if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) {
833 * Check for bus master activity. If there was activity, clear
834 * the bit and use the lowest non-C3 state. Note that the USB
835 * driver polling for new devices keeps this bit set all the
836 * time if USB is loaded.
838 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
839 AcpiGetRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
840 if (bm_active != 0) {
841 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
842 cx_next_idx = min(cx_next_idx, sc->cpu_non_c3);
846 /* Select the next state and update statistics. */
847 cx_next = &sc->cpu_cx_states[cx_next_idx];
848 sc->cpu_cx_stats[cx_next_idx]++;
849 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));
852 * Execute HLT (or equivalent) and wait for an interrupt. We can't
853 * calculate the time spent in C1 since the place we wake up is an
854 * ISR. Assume we slept half of quantum and return.
856 if (cx_next->type == ACPI_STATE_C1) {
857 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + 500000 / hz) / 4;
863 * For C3, disable bus master arbitration and enable bus master wake
864 * if BM control is available, otherwise flush the CPU cache.
866 if (cx_next->type == ACPI_STATE_C3) {
867 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
868 AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 1);
869 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
871 ACPI_FLUSH_CPU_CACHE();
875 * Read from P_LVLx to enter C2(+), checking time spent asleep.
876 * Use the ACPI timer for measuring sleep time. Since we need to
877 * get the time very close to the CPU start/stop clock logic, this
878 * is the only reliable time source.
880 AcpiHwLowLevelRead(32, &start_time, &AcpiGbl_FADT.XPmTimerBlock);
881 CPU_GET_REG(cx_next->p_lvlx, 1);
884 * Read the end time twice. Since it may take an arbitrary time
885 * to enter the idle state, the first read may be executed before
886 * the processor has stopped. Doing it again provides enough
887 * margin that we are certain to have a correct value.
889 AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT.XPmTimerBlock);
890 AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT.XPmTimerBlock);
892 /* Enable bus master arbitration and disable bus master wakeup. */
893 if (cx_next->type == ACPI_STATE_C3) {
894 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
895 AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 0);
896 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
901 /* Find the actual time asleep in microseconds. */
902 end_time = acpi_TimerDelta(end_time, start_time);
903 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4;
907 * Re-evaluate the _CST object when we are notified that it changed.
909 * XXX Re-evaluation disabled until locking is done.
912 acpi_cpu_cst_notify(device_t dev)
914 struct acpi_cpu_softc *sc = device_get_softc(dev);
915 struct acpi_cpu_softc *isc;
918 /* Update the list of Cx states. */
920 acpi_cpu_cx_list(sc);
922 /* Update the new lowest useable Cx state for all CPUs. */
925 for (i = 0; i < cpu_ndevices; i++) {
926 isc = device_get_softc(cpu_devices[i]);
927 if (isc->cpu_cx_count > cpu_cx_count)
928 cpu_cx_count = isc->cpu_cx_count;
934 acpi_cpu_quirks(void)
939 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
942 * Bus mastering arbitration control is needed to keep caches coherent
943 * while sleeping in C3. If it's not present but a working flush cache
944 * instruction is present, flush the caches before entering C3 instead.
945 * Otherwise, just disable C3 completely.
947 if (AcpiGbl_FADT.Pm2ControlBlock == 0 ||
948 AcpiGbl_FADT.Pm2ControlLength == 0) {
949 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) &&
950 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) {
951 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
952 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
953 "acpi_cpu: no BM control, using flush cache method\n"));
955 cpu_quirks |= CPU_QUIRK_NO_C3;
956 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
957 "acpi_cpu: no BM control, C3 not available\n"));
962 * If we are using generic Cx mode, C3 on multiple CPUs requires using
963 * the expensive flush cache instruction.
965 if (cpu_cx_generic && ncpus > 1) {
966 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
967 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
968 "acpi_cpu: SMP, using flush cache mode for C3\n"));
971 /* Look for various quirks of the PIIX4 part. */
972 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3);
973 if (acpi_dev != NULL) {
974 switch (pci_get_revid(acpi_dev)) {
976 * Disable C3 support for all PIIX4 chipsets. Some of these parts
977 * do not report the BMIDE status to the BM status register and
978 * others have a livelock bug if Type-F DMA is enabled. Linux
979 * works around the BMIDE bug by reading the BM status directly
980 * but we take the simpler approach of disabling C3 for these
983 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA
984 * Livelock") from the January 2002 PIIX4 specification update.
985 * Applies to all PIIX4 models.
987 * Also, make sure that all interrupts cause a "Stop Break"
988 * event to exit from C2 state.
989 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
990 * should be set to zero, otherwise it causes C2 to short-sleep.
991 * PIIX4 doesn't properly support C3 and bus master activity
992 * need not break out of C2.
994 case PCI_REVISION_A_STEP:
995 case PCI_REVISION_B_STEP:
996 case PCI_REVISION_4E:
997 case PCI_REVISION_4M:
998 cpu_quirks |= CPU_QUIRK_NO_C3;
999 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1000 "acpi_cpu: working around PIIX4 bug, disabling C3\n"));
1002 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
1003 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
1004 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1005 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
1006 val |= PIIX4_STOP_BREAK_MASK;
1007 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
1009 AcpiGetRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
1011 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1012 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
1013 AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
1025 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS)
1027 struct acpi_cpu_softc *sc;
1031 uintmax_t fract, sum, whole;
1033 sc = (struct acpi_cpu_softc *) arg1;
1035 for (i = 0; i < sc->cpu_cx_count; i++)
1036 sum += sc->cpu_cx_stats[i];
1037 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN);
1038 for (i = 0; i < sc->cpu_cx_count; i++) {
1040 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100;
1041 fract = (whole % sum) * 100;
1042 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum),
1043 (u_int)(fract / sum));
1045 sbuf_printf(&sb, "0.00%% ");
1047 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep);
1050 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
1057 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val)
1059 int i, old_lowest, error = 0;
1060 uint32_t old_type, type;
1064 old_lowest = atomic_swap_int(&sc->cpu_cx_lowest, val);
1066 old_type = sc->cpu_cx_states[old_lowest].type;
1067 type = sc->cpu_cx_states[val].type;
1068 if (old_type == ACPI_STATE_C3 && type != ACPI_STATE_C3) {
1069 KKASSERT(cpu_c3_ncpus > 0);
1070 if (atomic_fetchadd_int(&cpu_c3_ncpus, -1) == 1) {
1072 * All of the CPUs exit C3 state, use a better
1075 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_NONE);
1077 cputimer_intr_restart();
1079 } else if (type == ACPI_STATE_C3 && old_type != ACPI_STATE_C3) {
1080 if (atomic_fetchadd_int(&cpu_c3_ncpus, 1) == 0) {
1082 * When the first CPU enters C3 state, switch
1083 * to an one shot timer, which could handle
1084 * C3 state, i.e. the timer will not hang.
1086 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_PS);
1088 cputimer_intr_restart();
1090 kprintf("no suitable intr cuptimer found\n");
1093 sc->cpu_cx_lowest = old_lowest;
1094 atomic_fetchadd_int(&cpu_c3_ncpus, -1);
1104 /* If not disabling, cache the new lowest non-C3 state. */
1106 for (i = sc->cpu_cx_lowest; i >= 0; i--) {
1107 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) {
1113 /* Reset the statistics counters. */
1114 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats));
1119 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1121 struct acpi_cpu_softc *sc;
1125 sc = (struct acpi_cpu_softc *) arg1;
1126 ksnprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest + 1);
1127 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1128 if (error != 0 || req->newptr == NULL)
1130 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1132 val = (int) strtol(state + 1, NULL, 10) - 1;
1133 if (val < 0 || val > sc->cpu_cx_count - 1)
1137 error = acpi_cpu_set_cx_lowest(sc, val);
1144 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1146 struct acpi_cpu_softc *sc;
1150 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest + 1);
1151 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1152 if (error != 0 || req->newptr == NULL)
1154 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1156 val = (int) strtol(state + 1, NULL, 10) - 1;
1157 if (val < 0 || val > cpu_cx_count - 1)
1159 cpu_cx_lowest = val;
1161 /* Update the new lowest useable Cx state for all CPUs. */
1163 for (i = 0; i < cpu_ndevices; i++) {
1164 sc = device_get_softc(cpu_devices[i]);
1165 error = acpi_cpu_set_cx_lowest(sc, val);
1177 * Put the CPU in C1 in a machine-dependant way.
1178 * XXX: shouldn't be here!
1184 ia64_call_pal_static(PAL_HALT_LIGHT, 0, 0, 0);
1188 if (!lwkt_runnable())
1189 __asm __volatile("sti; hlt");
1191 __asm __volatile("sti; pause");
1193 if (!lwkt_runnable())
1194 __asm __volatile("sti; hlt");
1196 __asm __volatile("sti");
1198 #endif /* !__ia64__ */