2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
32 #include "opt_compat_oldpci.h"
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
45 #include <sys/machintr.h>
47 #include <machine/msi_machdep.h>
51 #include <vm/vm_extern.h>
55 #include <sys/device.h>
57 #include <sys/pciio.h>
58 #include <bus/pci/pcireg.h>
59 #include <bus/pci/pcivar.h>
60 #include <bus/pci/pci_private.h>
66 #include <contrib/dev/acpica/acpi.h>
69 #define ACPI_PWR_FOR_SLEEP(x, y, z)
72 extern struct dev_ops pcic_ops; /* XXX */
74 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
76 static uint32_t pci_mapbase(unsigned mapreg);
77 static const char *pci_maptype(unsigned mapreg);
78 static int pci_mapsize(unsigned testval);
79 static int pci_maprange(unsigned mapreg);
80 static void pci_fixancient(pcicfgregs *cfg);
82 static int pci_porten(device_t pcib, int b, int s, int f);
83 static int pci_memen(device_t pcib, int b, int s, int f);
84 static void pci_assign_interrupt(device_t bus, device_t dev,
86 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
87 int b, int s, int f, int reg,
88 struct resource_list *rl, int force, int prefetch);
89 static int pci_probe(device_t dev);
90 static int pci_attach(device_t dev);
91 static void pci_child_detached(device_t, device_t);
92 static void pci_load_vendor_data(void);
93 static int pci_describe_parse_line(char **ptr, int *vendor,
94 int *device, char **desc);
95 static char *pci_describe_device(device_t dev);
96 static int pci_modevent(module_t mod, int what, void *arg);
97 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
99 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
100 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
101 int reg, uint32_t *data);
103 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
104 int reg, uint32_t data);
106 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
107 static void pci_disable_msi(device_t dev);
108 static void pci_enable_msi(device_t dev, uint64_t address,
110 static void pci_setup_msix_vector(device_t dev, u_int index,
111 uint64_t address, uint32_t data);
112 static void pci_mask_msix_vector(device_t dev, u_int index);
113 static void pci_unmask_msix_vector(device_t dev, u_int index);
114 static void pci_mask_msix_allvectors(device_t dev);
115 static struct msix_vector *pci_find_msix_vector(device_t dev, int rid);
116 static int pci_msi_blacklisted(void);
117 static void pci_resume_msi(device_t dev);
118 static void pci_resume_msix(device_t dev);
119 static int pcie_slotimpl(const pcicfgregs *);
120 static void pci_print_verbose_expr(const pcicfgregs *);
122 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
127 static void pci_read_cap_subvendor(device_t, int, int,
129 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
130 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
132 static device_method_t pci_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, pci_probe),
135 DEVMETHOD(device_attach, pci_attach),
136 DEVMETHOD(device_detach, bus_generic_detach),
137 DEVMETHOD(device_shutdown, bus_generic_shutdown),
138 DEVMETHOD(device_suspend, pci_suspend),
139 DEVMETHOD(device_resume, pci_resume),
142 DEVMETHOD(bus_print_child, pci_print_child),
143 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
144 DEVMETHOD(bus_read_ivar, pci_read_ivar),
145 DEVMETHOD(bus_write_ivar, pci_write_ivar),
146 DEVMETHOD(bus_driver_added, pci_driver_added),
147 DEVMETHOD(bus_child_detached, pci_child_detached),
148 DEVMETHOD(bus_setup_intr, pci_setup_intr),
149 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
151 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
152 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
153 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
154 DEVMETHOD(bus_delete_resource, pci_delete_resource),
155 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
156 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
157 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
158 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
159 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
160 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
163 DEVMETHOD(pci_read_config, pci_read_config_method),
164 DEVMETHOD(pci_write_config, pci_write_config_method),
165 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
166 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
167 DEVMETHOD(pci_enable_io, pci_enable_io_method),
168 DEVMETHOD(pci_disable_io, pci_disable_io_method),
169 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
170 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
171 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
172 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
173 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
174 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
175 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
176 DEVMETHOD(pci_release_msi, pci_release_msi_method),
177 DEVMETHOD(pci_alloc_msix_vector, pci_alloc_msix_vector_method),
178 DEVMETHOD(pci_release_msix_vector, pci_release_msix_vector_method),
179 DEVMETHOD(pci_msi_count, pci_msi_count_method),
180 DEVMETHOD(pci_msix_count, pci_msix_count_method),
185 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
187 static devclass_t pci_devclass;
188 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
189 MODULE_VERSION(pci, 1);
191 static char *pci_vendordata;
192 static size_t pci_vendordata_size;
195 static const struct pci_read_cap {
197 pci_read_cap_t read_cap;
198 } pci_read_caps[] = {
199 { PCIY_PMG, pci_read_cap_pmgt },
200 { PCIY_HT, pci_read_cap_ht },
201 { PCIY_MSI, pci_read_cap_msi },
202 { PCIY_MSIX, pci_read_cap_msix },
203 { PCIY_VPD, pci_read_cap_vpd },
204 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
205 { PCIY_PCIX, pci_read_cap_pcix },
206 { PCIY_EXPRESS, pci_read_cap_express },
207 { 0, NULL } /* required last entry */
211 uint32_t devid; /* Vendor/device of the card */
213 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
214 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
219 struct pci_quirk pci_quirks[] = {
220 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
221 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
223 /* As does the Serverworks OSB4 (the SMBus mapping register) */
224 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
227 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
228 * or the CMIC-SL (AKA ServerWorks GC_LE).
230 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
231 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 * MSI doesn't work on earlier Intel chipsets including
235 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
237 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
243 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
246 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
249 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
254 /* map register information */
255 #define PCI_MAPMEM 0x01 /* memory map */
256 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
257 #define PCI_MAPPORT 0x04 /* port map */
259 #define PCI_MSIX_RID2VEC(rid) ((rid) - 1) /* rid -> MSI-X vector # */
260 #define PCI_MSIX_VEC2RID(vec) ((vec) + 1) /* MSI-X vector # -> rid */
262 struct devlist pci_devq;
263 uint32_t pci_generation;
264 uint32_t pci_numdevs = 0;
265 static int pcie_chipset, pcix_chipset;
268 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
270 static int pci_enable_io_modes = 1;
271 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
272 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
273 &pci_enable_io_modes, 1,
274 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
275 enable these bits correctly. We'd like to do this all the time, but there\n\
276 are some peripherals that this causes problems with.");
278 static int pci_do_power_nodriver = 0;
279 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
280 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
281 &pci_do_power_nodriver, 0,
282 "Place a function into D3 state when no driver attaches to it. 0 means\n\
283 disable. 1 means conservatively place devices into D3 state. 2 means\n\
284 aggressively place devices into D3 state. 3 means put absolutely everything\n\
287 static int pci_do_power_resume = 1;
288 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
289 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
290 &pci_do_power_resume, 1,
291 "Transition from D3 -> D0 on resume.");
293 static int pci_do_msi = 1;
294 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
295 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
296 "Enable support for MSI interrupts");
298 static int pci_do_msix = 1;
299 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
300 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
301 "Enable support for MSI-X interrupts");
303 static int pci_honor_msi_blacklist = 1;
304 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
305 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
306 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
308 static int pci_msi_cpuid;
310 /* Find a device_t by bus/slot/function in domain 0 */
313 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
316 return (pci_find_dbsf(0, bus, slot, func));
319 /* Find a device_t by domain/bus/slot/function */
322 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
324 struct pci_devinfo *dinfo;
326 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
327 if ((dinfo->cfg.domain == domain) &&
328 (dinfo->cfg.bus == bus) &&
329 (dinfo->cfg.slot == slot) &&
330 (dinfo->cfg.func == func)) {
331 return (dinfo->cfg.dev);
338 /* Find a device_t by vendor/device ID */
341 pci_find_device(uint16_t vendor, uint16_t device)
343 struct pci_devinfo *dinfo;
345 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
346 if ((dinfo->cfg.vendor == vendor) &&
347 (dinfo->cfg.device == device)) {
348 return (dinfo->cfg.dev);
355 /* return base address of memory or port map */
358 pci_mapbase(uint32_t mapreg)
361 if (PCI_BAR_MEM(mapreg))
362 return (mapreg & PCIM_BAR_MEM_BASE);
364 return (mapreg & PCIM_BAR_IO_BASE);
367 /* return map type of memory or port map */
370 pci_maptype(unsigned mapreg)
373 if (PCI_BAR_IO(mapreg))
375 if (mapreg & PCIM_BAR_MEM_PREFETCH)
376 return ("Prefetchable Memory");
380 /* return log2 of map size decoded for memory or port map */
383 pci_mapsize(uint32_t testval)
387 testval = pci_mapbase(testval);
390 while ((testval & 1) == 0)
399 /* return log2 of address range supported by map register */
402 pci_maprange(unsigned mapreg)
406 if (PCI_BAR_IO(mapreg))
409 switch (mapreg & PCIM_BAR_MEM_TYPE) {
410 case PCIM_BAR_MEM_32:
413 case PCIM_BAR_MEM_1MB:
416 case PCIM_BAR_MEM_64:
423 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
426 pci_fixancient(pcicfgregs *cfg)
428 if (cfg->hdrtype != 0)
431 /* PCI to PCI bridges use header type 1 */
432 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
436 /* extract header type specific config data */
439 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
441 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
442 switch (cfg->hdrtype) {
444 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
445 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
446 cfg->nummaps = PCI_MAXMAPS_0;
449 cfg->nummaps = PCI_MAXMAPS_1;
451 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
455 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
456 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
457 cfg->nummaps = PCI_MAXMAPS_2;
459 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
466 /* read configuration header into pcicfgregs structure */
468 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
470 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
471 pcicfgregs *cfg = NULL;
472 struct pci_devinfo *devlist_entry;
473 struct devlist *devlist_head;
475 devlist_head = &pci_devq;
477 devlist_entry = NULL;
479 if (REG(PCIR_DEVVENDOR, 4) != -1) {
480 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
482 cfg = &devlist_entry->cfg;
488 cfg->vendor = REG(PCIR_VENDOR, 2);
489 cfg->device = REG(PCIR_DEVICE, 2);
490 cfg->cmdreg = REG(PCIR_COMMAND, 2);
491 cfg->statreg = REG(PCIR_STATUS, 2);
492 cfg->baseclass = REG(PCIR_CLASS, 1);
493 cfg->subclass = REG(PCIR_SUBCLASS, 1);
494 cfg->progif = REG(PCIR_PROGIF, 1);
495 cfg->revid = REG(PCIR_REVID, 1);
496 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
497 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
498 cfg->lattimer = REG(PCIR_LATTIMER, 1);
499 cfg->intpin = REG(PCIR_INTPIN, 1);
500 cfg->intline = REG(PCIR_INTLINE, 1);
502 cfg->mingnt = REG(PCIR_MINGNT, 1);
503 cfg->maxlat = REG(PCIR_MAXLAT, 1);
505 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
506 cfg->hdrtype &= ~PCIM_MFDEV;
509 pci_hdrtypedata(pcib, b, s, f, cfg);
511 pci_read_capabilities(pcib, cfg);
513 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
515 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
516 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
517 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
518 devlist_entry->conf.pc_sel.pc_func = cfg->func;
519 devlist_entry->conf.pc_hdr = cfg->hdrtype;
521 devlist_entry->conf.pc_subvendor = cfg->subvendor;
522 devlist_entry->conf.pc_subdevice = cfg->subdevice;
523 devlist_entry->conf.pc_vendor = cfg->vendor;
524 devlist_entry->conf.pc_device = cfg->device;
526 devlist_entry->conf.pc_class = cfg->baseclass;
527 devlist_entry->conf.pc_subclass = cfg->subclass;
528 devlist_entry->conf.pc_progif = cfg->progif;
529 devlist_entry->conf.pc_revid = cfg->revid;
534 return (devlist_entry);
539 pci_fixup_nextptr(int *nextptr0)
541 int nextptr = *nextptr0;
543 /* "Next pointer" is only one byte */
544 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d", nextptr));
548 * PCI local bus spec 3.0:
550 * "... The bottom two bits of all pointers are reserved
551 * and must be implemented as 00b although software must
552 * mask them to allow for future uses of these bits ..."
555 kprintf("Illegal PCI extended capability "
556 "offset, fixup 0x%02x -> 0x%02x\n",
557 nextptr, nextptr & ~0x3);
563 if (nextptr < 0x40) {
565 kprintf("Illegal PCI extended capability "
566 "offset 0x%02x", nextptr);
574 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
577 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
579 struct pcicfg_pp *pp = &cfg->pp;
584 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
585 pp->pp_status = ptr + PCIR_POWER_STATUS;
586 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
588 if ((nextptr - ptr) > PCIR_POWER_DATA) {
591 * We should write to data_select and read back from
592 * data_scale to determine whether data register is
596 pp->pp_data = ptr + PCIR_POWER_DATA;
606 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
608 #if defined(__i386__) || defined(__x86_64__)
611 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
613 struct pcicfg_ht *ht = &cfg->ht;
617 /* Determine HT-specific capability type. */
618 val = REG(ptr + PCIR_HT_COMMAND, 2);
620 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
621 cfg->ht.ht_slave = ptr;
623 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
626 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
627 /* Sanity check the mapping window. */
628 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
630 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
631 if (addr != MSI_X86_ADDR_BASE) {
632 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
633 "has non-default MSI window 0x%llx\n",
634 cfg->domain, cfg->bus, cfg->slot, cfg->func,
638 addr = MSI_X86_ADDR_BASE;
642 ht->ht_msictrl = val;
643 ht->ht_msiaddr = addr;
647 #endif /* __i386__ || __x86_64__ */
651 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
654 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
656 struct pcicfg_msi *msi = &cfg->msi;
658 msi->msi_location = ptr;
659 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
660 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
666 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
669 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
671 struct pcicfg_msix *msix = &cfg->msix;
674 msix->msix_location = ptr;
675 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
676 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
678 val = REG(ptr + PCIR_MSIX_TABLE, 4);
679 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
680 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
682 val = REG(ptr + PCIR_MSIX_PBA, 4);
683 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
684 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
686 TAILQ_INIT(&msix->msix_vectors);
692 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
694 cfg->vpd.vpd_reg = ptr;
698 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
701 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
703 /* Should always be true. */
704 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
707 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
708 cfg->subvendor = val & 0xffff;
709 cfg->subdevice = val >> 16;
716 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
719 * Assume we have a PCI-X chipset if we have
720 * at least one PCI-PCI bridge with a PCI-X
721 * capability. Note that some systems with
722 * PCI-express or HT chipsets might match on
723 * this check as well.
725 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
728 cfg->pcix.pcix_ptr = ptr;
732 pcie_slotimpl(const pcicfgregs *cfg)
734 const struct pcicfg_expr *expr = &cfg->expr;
738 * - Slot implemented bit is meaningful iff current port is
739 * root port or down stream port.
740 * - Testing for root port or down stream port is meanningful
741 * iff PCI configure has type 1 header.
744 if (cfg->hdrtype != 1)
747 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
748 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
751 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
758 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
761 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
763 struct pcicfg_expr *expr = &cfg->expr;
766 * Assume we have a PCI-express chipset if we have
767 * at least one PCI-express device.
771 expr->expr_ptr = ptr;
772 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
775 * Read slot capabilities. Slot capabilities exists iff
776 * current port's slot is implemented
778 if (pcie_slotimpl(cfg))
779 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
785 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
787 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
788 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
793 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
794 /* No capabilities */
798 switch (cfg->hdrtype & PCIM_HDRTYPE) {
801 ptrptr = PCIR_CAP_PTR;
804 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
807 return; /* no capabilities support */
809 nextptr = REG(ptrptr, 1); /* sanity check? */
812 * Read capability entries.
814 while (pci_fixup_nextptr(&nextptr)) {
815 const struct pci_read_cap *rc;
818 /* Find the next entry */
819 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
821 /* Process this entry */
822 val = REG(ptr + PCICAP_ID, 1);
823 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
824 if (rc->cap == val) {
825 rc->read_cap(pcib, ptr, nextptr, cfg);
831 #if defined(__i386__) || defined(__x86_64__)
833 * Enable the MSI mapping window for all HyperTransport
834 * slaves. PCI-PCI bridges have their windows enabled via
837 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
838 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
840 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
841 cfg->domain, cfg->bus, cfg->slot, cfg->func);
842 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
843 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
848 /* REG and WREG use carry through to next functions */
852 * PCI Vital Product Data
855 #define PCI_VPD_TIMEOUT 1000000
858 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
860 int count = PCI_VPD_TIMEOUT;
862 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
864 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
866 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
869 DELAY(1); /* limit looping */
871 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
878 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
880 int count = PCI_VPD_TIMEOUT;
882 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
884 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
885 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
886 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
889 DELAY(1); /* limit looping */
896 #undef PCI_VPD_TIMEOUT
898 struct vpd_readstate {
908 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
913 if (vrs->bytesinval == 0) {
914 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
916 vrs->val = le32toh(reg);
918 byte = vrs->val & 0xff;
921 vrs->val = vrs->val >> 8;
922 byte = vrs->val & 0xff;
932 pcie_slot_implemented(device_t dev)
934 struct pci_devinfo *dinfo = device_get_ivars(dev);
936 return pcie_slotimpl(&dinfo->cfg);
940 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
945 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
946 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
947 panic("%s: invalid max read request size 0x%02x",
948 device_get_nameunit(dev), rqsize);
951 expr_ptr = pci_get_pciecap_ptr(dev);
953 panic("%s: not PCIe device", device_get_nameunit(dev));
955 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
956 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
958 device_printf(dev, "adjust device control 0x%04x", val);
960 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
962 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
965 kprintf(" -> 0x%04x\n", val);
970 pcie_get_max_readrq(device_t dev)
975 expr_ptr = pci_get_pciecap_ptr(dev);
977 panic("%s: not PCIe device", device_get_nameunit(dev));
979 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
980 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
984 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
986 struct vpd_readstate vrs;
991 int alloc, off; /* alloc/off for RO/W arrays */
997 /* init vpd reader */
1005 name = remain = i = 0; /* shut up stupid gcc */
1006 alloc = off = 0; /* shut up stupid gcc */
1007 dflen = 0; /* shut up stupid gcc */
1009 while (state >= 0) {
1010 if (vpd_nextbyte(&vrs, &byte)) {
1015 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1016 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1017 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1020 case 0: /* item name */
1022 if (vpd_nextbyte(&vrs, &byte2)) {
1027 if (vpd_nextbyte(&vrs, &byte2)) {
1031 remain |= byte2 << 8;
1032 if (remain > (0x7f*4 - vrs.off)) {
1035 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1036 cfg->domain, cfg->bus, cfg->slot,
1041 remain = byte & 0x7;
1042 name = (byte >> 3) & 0xf;
1045 case 0x2: /* String */
1046 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1047 M_DEVBUF, M_WAITOK);
1054 case 0x10: /* VPD-R */
1057 cfg->vpd.vpd_ros = kmalloc(alloc *
1058 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1062 case 0x11: /* VPD-W */
1065 cfg->vpd.vpd_w = kmalloc(alloc *
1066 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1070 default: /* Invalid data, abort */
1076 case 1: /* Identifier String */
1077 cfg->vpd.vpd_ident[i++] = byte;
1080 cfg->vpd.vpd_ident[i] = '\0';
1085 case 2: /* VPD-R Keyword Header */
1087 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1088 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1089 M_DEVBUF, M_WAITOK | M_ZERO);
1091 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1092 if (vpd_nextbyte(&vrs, &byte2)) {
1096 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1097 if (vpd_nextbyte(&vrs, &byte2)) {
1103 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1106 * if this happens, we can't trust the rest
1110 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1111 cfg->domain, cfg->bus, cfg->slot,
1116 } else if (dflen == 0) {
1117 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1118 sizeof(*cfg->vpd.vpd_ros[off].value),
1119 M_DEVBUF, M_WAITOK);
1120 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1122 cfg->vpd.vpd_ros[off].value = kmalloc(
1124 sizeof(*cfg->vpd.vpd_ros[off].value),
1125 M_DEVBUF, M_WAITOK);
1128 /* keep in sync w/ state 3's transistions */
1129 if (dflen == 0 && remain == 0)
1131 else if (dflen == 0)
1137 case 3: /* VPD-R Keyword Value */
1138 cfg->vpd.vpd_ros[off].value[i++] = byte;
1139 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1140 "RV", 2) == 0 && cksumvalid == -1) {
1146 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1147 cfg->domain, cfg->bus,
1148 cfg->slot, cfg->func,
1157 /* keep in sync w/ state 2's transistions */
1159 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1160 if (dflen == 0 && remain == 0) {
1161 cfg->vpd.vpd_rocnt = off;
1162 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1163 off * sizeof(*cfg->vpd.vpd_ros),
1164 M_DEVBUF, M_WAITOK | M_ZERO);
1166 } else if (dflen == 0)
1176 case 5: /* VPD-W Keyword Header */
1178 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1179 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1180 M_DEVBUF, M_WAITOK | M_ZERO);
1182 cfg->vpd.vpd_w[off].keyword[0] = byte;
1183 if (vpd_nextbyte(&vrs, &byte2)) {
1187 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1188 if (vpd_nextbyte(&vrs, &byte2)) {
1192 cfg->vpd.vpd_w[off].len = dflen = byte2;
1193 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1194 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1195 sizeof(*cfg->vpd.vpd_w[off].value),
1196 M_DEVBUF, M_WAITOK);
1199 /* keep in sync w/ state 6's transistions */
1200 if (dflen == 0 && remain == 0)
1202 else if (dflen == 0)
1208 case 6: /* VPD-W Keyword Value */
1209 cfg->vpd.vpd_w[off].value[i++] = byte;
1212 /* keep in sync w/ state 5's transistions */
1214 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1215 if (dflen == 0 && remain == 0) {
1216 cfg->vpd.vpd_wcnt = off;
1217 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1218 off * sizeof(*cfg->vpd.vpd_w),
1219 M_DEVBUF, M_WAITOK | M_ZERO);
1221 } else if (dflen == 0)
1226 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1227 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1234 if (cksumvalid == 0 || state < -1) {
1235 /* read-only data bad, clean up */
1236 if (cfg->vpd.vpd_ros != NULL) {
1237 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1238 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1239 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1240 cfg->vpd.vpd_ros = NULL;
1244 /* I/O error, clean up */
1245 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1246 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1247 if (cfg->vpd.vpd_ident != NULL) {
1248 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1249 cfg->vpd.vpd_ident = NULL;
1251 if (cfg->vpd.vpd_w != NULL) {
1252 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1253 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1254 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1255 cfg->vpd.vpd_w = NULL;
1258 cfg->vpd.vpd_cached = 1;
1264 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1266 struct pci_devinfo *dinfo = device_get_ivars(child);
1267 pcicfgregs *cfg = &dinfo->cfg;
1269 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1270 pci_read_vpd(device_get_parent(dev), cfg);
1272 *identptr = cfg->vpd.vpd_ident;
1274 if (*identptr == NULL)
1281 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1284 struct pci_devinfo *dinfo = device_get_ivars(child);
1285 pcicfgregs *cfg = &dinfo->cfg;
1288 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1289 pci_read_vpd(device_get_parent(dev), cfg);
1291 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1292 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1293 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1294 *vptr = cfg->vpd.vpd_ros[i].value;
1297 if (i != cfg->vpd.vpd_rocnt)
1305 * Return the offset in configuration space of the requested extended
1306 * capability entry or 0 if the specified capability was not found.
1309 pci_find_extcap_method(device_t dev, device_t child, int capability,
1312 struct pci_devinfo *dinfo = device_get_ivars(child);
1313 pcicfgregs *cfg = &dinfo->cfg;
1318 * Check the CAP_LIST bit of the PCI status register first.
1320 status = pci_read_config(child, PCIR_STATUS, 2);
1321 if (!(status & PCIM_STATUS_CAPPRESENT))
1325 * Determine the start pointer of the capabilities list.
1327 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1333 ptr = PCIR_CAP_PTR_2;
1337 return (ENXIO); /* no extended capabilities support */
1339 ptr = pci_read_config(child, ptr, 1);
1342 * Traverse the capabilities list.
1345 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1350 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1357 * Support for MSI-X message interrupts.
1360 pci_setup_msix_vector(device_t dev, u_int index, uint64_t address,
1363 struct pci_devinfo *dinfo = device_get_ivars(dev);
1364 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1367 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1368 offset = msix->msix_table_offset + index * 16;
1369 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1370 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1371 bus_write_4(msix->msix_table_res, offset + 8, data);
1373 /* Enable MSI -> HT mapping. */
1374 pci_ht_map_msi(dev, address);
1378 pci_mask_msix_vector(device_t dev, u_int index)
1380 struct pci_devinfo *dinfo = device_get_ivars(dev);
1381 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1382 uint32_t offset, val;
1384 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1385 offset = msix->msix_table_offset + index * 16 + 12;
1386 val = bus_read_4(msix->msix_table_res, offset);
1387 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1388 val |= PCIM_MSIX_VCTRL_MASK;
1389 bus_write_4(msix->msix_table_res, offset, val);
1394 pci_unmask_msix_vector(device_t dev, u_int index)
1396 struct pci_devinfo *dinfo = device_get_ivars(dev);
1397 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1398 uint32_t offset, val;
1400 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1401 offset = msix->msix_table_offset + index * 16 + 12;
1402 val = bus_read_4(msix->msix_table_res, offset);
1403 if (val & PCIM_MSIX_VCTRL_MASK) {
1404 val &= ~PCIM_MSIX_VCTRL_MASK;
1405 bus_write_4(msix->msix_table_res, offset, val);
1410 pci_pending_msix_vector(device_t dev, u_int index)
1412 struct pci_devinfo *dinfo = device_get_ivars(dev);
1413 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1414 uint32_t offset, bit;
1416 KASSERT(msix->msix_table_res != NULL && msix->msix_pba_res != NULL,
1417 ("MSI-X is not setup yet"));
1419 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1420 offset = msix->msix_pba_offset + (index / 32) * 4;
1421 bit = 1 << index % 32;
1422 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1426 * Restore MSI-X registers and table during resume. If MSI-X is
1427 * enabled then walk the virtual table to restore the actual MSI-X
1431 pci_resume_msix(device_t dev)
1433 struct pci_devinfo *dinfo = device_get_ivars(dev);
1434 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1436 if (msix->msix_table_res != NULL) {
1437 const struct msix_vector *mv;
1439 pci_mask_msix_allvectors(dev);
1441 TAILQ_FOREACH(mv, &msix->msix_vectors, mv_link) {
1444 if (mv->mv_address == 0)
1447 vector = PCI_MSIX_RID2VEC(mv->mv_rid);
1448 pci_setup_msix_vector(dev, vector,
1449 mv->mv_address, mv->mv_data);
1450 pci_unmask_msix_vector(dev, vector);
1453 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1454 msix->msix_ctrl, 2);
1458 * Attempt to allocate one MSI-X message at the specified vector on cpuid.
1460 * After this function returns, the MSI-X's rid will be saved in rid0.
1463 pci_alloc_msix_vector_method(device_t dev, device_t child, u_int vector,
1464 int *rid0, int cpuid)
1466 struct pci_devinfo *dinfo = device_get_ivars(child);
1467 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1468 struct msix_vector *mv;
1469 struct resource_list_entry *rle;
1470 int error, irq, rid;
1472 KASSERT(msix->msix_table_res != NULL &&
1473 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
1474 KASSERT(cpuid >= 0 && cpuid < ncpus, ("invalid cpuid %d", cpuid));
1475 KASSERT(vector < msix->msix_msgnum,
1476 ("invalid MSI-X vector %u, total %d", vector, msix->msix_msgnum));
1479 device_printf(child,
1480 "attempting to allocate MSI-X #%u vector (%d supported)\n",
1481 vector, msix->msix_msgnum);
1484 /* Set rid according to vector number */
1485 rid = PCI_MSIX_VEC2RID(vector);
1487 /* Vector has already been allocated */
1488 mv = pci_find_msix_vector(child, rid);
1492 /* Allocate a message. */
1493 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq, cpuid);
1496 resource_list_add(&dinfo->resources, SYS_RES_IRQ, rid,
1497 irq, irq, 1, cpuid);
1500 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
1501 device_printf(child, "using IRQ %lu for MSI-X on cpu%d\n",
1505 /* Update counts of alloc'd messages. */
1508 mv = kmalloc(sizeof(*mv), M_DEVBUF, M_WAITOK | M_ZERO);
1510 TAILQ_INSERT_TAIL(&msix->msix_vectors, mv, mv_link);
1517 pci_release_msix_vector_method(device_t dev, device_t child, int rid)
1519 struct pci_devinfo *dinfo = device_get_ivars(child);
1520 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1521 struct resource_list_entry *rle;
1522 struct msix_vector *mv;
1525 KASSERT(msix->msix_table_res != NULL &&
1526 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
1527 KASSERT(msix->msix_alloc > 0, ("No MSI-X allocated"));
1528 KASSERT(rid > 0, ("invalid rid %d", rid));
1530 mv = pci_find_msix_vector(child, rid);
1531 KASSERT(mv != NULL, ("MSI-X rid %d is not allocated", rid));
1532 KASSERT(mv->mv_address == 0, ("MSI-X rid %d not teardown", rid));
1534 /* Make sure resource is no longer allocated. */
1535 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
1536 KASSERT(rle != NULL, ("missing MSI-X resource, rid %d", rid));
1537 KASSERT(rle->res == NULL,
1538 ("MSI-X resource is still allocated, rid %d", rid));
1543 /* Free the resource list entries. */
1544 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, rid);
1546 /* Release the IRQ. */
1547 PCIB_RELEASE_MSIX(device_get_parent(dev), child, irq, cpuid);
1549 TAILQ_REMOVE(&msix->msix_vectors, mv, mv_link);
1550 kfree(mv, M_DEVBUF);
1557 * Return the max supported MSI-X messages this device supports.
1558 * Basically, assuming the MD code can alloc messages, this function
1559 * should return the maximum value that pci_alloc_msix() can return.
1560 * Thus, it is subject to the tunables, etc.
1563 pci_msix_count_method(device_t dev, device_t child)
1565 struct pci_devinfo *dinfo = device_get_ivars(child);
1566 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1568 if (pci_do_msix && msix->msix_location != 0)
1569 return (msix->msix_msgnum);
1574 pci_setup_msix(device_t dev)
1576 struct pci_devinfo *dinfo = device_get_ivars(dev);
1577 pcicfgregs *cfg = &dinfo->cfg;
1578 struct resource_list_entry *rle;
1579 struct resource *table_res, *pba_res;
1581 KASSERT(cfg->msix.msix_table_res == NULL &&
1582 cfg->msix.msix_pba_res == NULL, ("MSI-X has been setup yet"));
1584 /* If rid 0 is allocated, then fail. */
1585 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1586 if (rle != NULL && rle->res != NULL)
1589 /* Already have allocated MSIs? */
1590 if (cfg->msi.msi_alloc != 0)
1593 /* If MSI is blacklisted for this system, fail. */
1594 if (pci_msi_blacklisted())
1597 /* MSI-X capability present? */
1598 if (cfg->msix.msix_location == 0 || cfg->msix.msix_msgnum == 0 ||
1602 KASSERT(cfg->msix.msix_alloc == 0 &&
1603 TAILQ_EMPTY(&cfg->msix.msix_vectors),
1604 ("MSI-X vector has been allocated"));
1606 /* Make sure the appropriate BARs are mapped. */
1607 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1608 cfg->msix.msix_table_bar);
1609 if (rle == NULL || rle->res == NULL ||
1610 !(rman_get_flags(rle->res) & RF_ACTIVE))
1612 table_res = rle->res;
1613 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1614 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1615 cfg->msix.msix_pba_bar);
1616 if (rle == NULL || rle->res == NULL ||
1617 !(rman_get_flags(rle->res) & RF_ACTIVE))
1622 cfg->msix.msix_table_res = table_res;
1623 cfg->msix.msix_pba_res = pba_res;
1625 pci_mask_msix_allvectors(dev);
1631 pci_teardown_msix(device_t dev)
1633 struct pci_devinfo *dinfo = device_get_ivars(dev);
1634 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1636 KASSERT(msix->msix_table_res != NULL &&
1637 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
1638 KASSERT(msix->msix_alloc == 0 && TAILQ_EMPTY(&msix->msix_vectors),
1639 ("MSI-X vector is still allocated"));
1641 pci_mask_msix_allvectors(dev);
1643 msix->msix_table_res = NULL;
1644 msix->msix_pba_res = NULL;
1648 pci_enable_msix(device_t dev)
1650 struct pci_devinfo *dinfo = device_get_ivars(dev);
1651 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1653 KASSERT(msix->msix_table_res != NULL &&
1654 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
1656 /* Update control register to enable MSI-X. */
1657 msix->msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1658 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1659 msix->msix_ctrl, 2);
1663 pci_disable_msix(device_t dev)
1665 struct pci_devinfo *dinfo = device_get_ivars(dev);
1666 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1668 KASSERT(msix->msix_table_res != NULL &&
1669 msix->msix_pba_res != NULL, ("MSI-X is not setup yet"));
1671 /* Disable MSI -> HT mapping. */
1672 pci_ht_map_msi(dev, 0);
1674 /* Update control register to disable MSI-X. */
1675 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1676 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1677 msix->msix_ctrl, 2);
1681 pci_mask_msix_allvectors(device_t dev)
1683 struct pci_devinfo *dinfo = device_get_ivars(dev);
1686 for (i = 0; i < dinfo->cfg.msix.msix_msgnum; ++i)
1687 pci_mask_msix_vector(dev, i);
1690 static struct msix_vector *
1691 pci_find_msix_vector(device_t dev, int rid)
1693 struct pci_devinfo *dinfo = device_get_ivars(dev);
1694 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1695 struct msix_vector *mv;
1697 TAILQ_FOREACH(mv, &msix->msix_vectors, mv_link) {
1698 if (mv->mv_rid == rid)
1705 * HyperTransport MSI mapping control
1708 pci_ht_map_msi(device_t dev, uint64_t addr)
1710 struct pci_devinfo *dinfo = device_get_ivars(dev);
1711 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1716 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1717 ht->ht_msiaddr >> 20 == addr >> 20) {
1718 /* Enable MSI -> HT mapping. */
1719 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1720 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1724 if (!addr && (ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
1725 /* Disable MSI -> HT mapping. */
1726 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1727 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1733 * Support for MSI message signalled interrupts.
1736 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1738 struct pci_devinfo *dinfo = device_get_ivars(dev);
1739 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1741 /* Write data and address values. */
1742 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1743 address & 0xffffffff, 4);
1744 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1745 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1747 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1750 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1753 /* Enable MSI in the control register. */
1754 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1755 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1758 /* Enable MSI -> HT mapping. */
1759 pci_ht_map_msi(dev, address);
1763 pci_disable_msi(device_t dev)
1765 struct pci_devinfo *dinfo = device_get_ivars(dev);
1766 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1768 /* Disable MSI -> HT mapping. */
1769 pci_ht_map_msi(dev, 0);
1771 /* Disable MSI in the control register. */
1772 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1773 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1778 * Restore MSI registers during resume. If MSI is enabled then
1779 * restore the data and address registers in addition to the control
1783 pci_resume_msi(device_t dev)
1785 struct pci_devinfo *dinfo = device_get_ivars(dev);
1786 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1790 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1791 address = msi->msi_addr;
1792 data = msi->msi_data;
1793 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1794 address & 0xffffffff, 4);
1795 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1796 pci_write_config(dev, msi->msi_location +
1797 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1798 pci_write_config(dev, msi->msi_location +
1799 PCIR_MSI_DATA_64BIT, data, 2);
1801 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1804 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1809 * Returns true if the specified device is blacklisted because MSI
1813 pci_msi_device_blacklisted(device_t dev)
1815 struct pci_quirk *q;
1817 if (!pci_honor_msi_blacklist)
1820 for (q = &pci_quirks[0]; q->devid; q++) {
1821 if (q->devid == pci_get_devid(dev) &&
1822 q->type == PCI_QUIRK_DISABLE_MSI)
1829 * Determine if MSI is blacklisted globally on this sytem. Currently,
1830 * we just check for blacklisted chipsets as represented by the
1831 * host-PCI bridge at device 0:0:0. In the future, it may become
1832 * necessary to check other system attributes, such as the kenv values
1833 * that give the motherboard manufacturer and model number.
1836 pci_msi_blacklisted(void)
1840 if (!pci_honor_msi_blacklist)
1843 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1844 if (!(pcie_chipset || pcix_chipset))
1847 dev = pci_find_bsf(0, 0, 0);
1849 return (pci_msi_device_blacklisted(dev));
1854 * Attempt to allocate count MSI messages on start_cpuid.
1856 * If start_cpuid < 0, then the MSI messages' target CPU will be
1857 * selected automaticly.
1859 * If the caller explicitly specified the MSI messages' target CPU,
1860 * i.e. start_cpuid >= 0, then we will try to allocate the count MSI
1861 * messages on the specified CPU, if the allocation fails due to MD
1862 * does not have enough vectors (EMSGSIZE), then we will try next
1863 * available CPU, until the allocation fails on all CPUs.
1865 * EMSGSIZE will be returned, if all available CPUs does not have
1866 * enough vectors for the requested amount of MSI messages. Caller
1867 * should either reduce the amount of MSI messages to be requested,
1868 * or simply giving up using MSI.
1870 * The available SYS_RES_IRQ resources' rids, which are >= 1, are
1871 * returned in 'rid' array, if the allocation succeeds.
1874 pci_alloc_msi_method(device_t dev, device_t child, int *rid, int count,
1877 struct pci_devinfo *dinfo = device_get_ivars(child);
1878 pcicfgregs *cfg = &dinfo->cfg;
1879 struct resource_list_entry *rle;
1880 int error, i, irqs[32], cpuid = 0;
1883 KASSERT(count != 0 && count <= 32 && powerof2(count),
1884 ("invalid MSI count %d", count));
1885 KASSERT(start_cpuid < ncpus, ("invalid cpuid %d", start_cpuid));
1887 /* If rid 0 is allocated, then fail. */
1888 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1889 if (rle != NULL && rle->res != NULL)
1892 /* Already have allocated messages? */
1893 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_table_res != NULL)
1896 /* If MSI is blacklisted for this system, fail. */
1897 if (pci_msi_blacklisted())
1900 /* MSI capability present? */
1901 if (cfg->msi.msi_location == 0 || cfg->msi.msi_msgnum == 0 ||
1905 KASSERT(count <= cfg->msi.msi_msgnum, ("large MSI count %d, max %d",
1906 count, cfg->msi.msi_msgnum));
1909 device_printf(child,
1910 "attempting to allocate %d MSI vector%s (%d supported)\n",
1911 count, count > 1 ? "s" : "", cfg->msi.msi_msgnum);
1914 if (start_cpuid < 0)
1915 start_cpuid = atomic_fetchadd_int(&pci_msi_cpuid, 1) % ncpus;
1918 for (i = 0; i < ncpus; ++i) {
1919 cpuid = (start_cpuid + i) % ncpus;
1921 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, count,
1922 cfg->msi.msi_msgnum, irqs, cpuid);
1925 else if (error != EMSGSIZE)
1932 * We now have N messages mapped onto SYS_RES_IRQ resources in
1933 * the irqs[] array, so add new resources starting at rid 1.
1935 for (i = 0; i < count; i++) {
1937 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1938 irqs[i], irqs[i], 1, cpuid);
1943 device_printf(child, "using IRQ %d on cpu%d for MSI\n",
1949 * Be fancy and try to print contiguous runs
1950 * of IRQ values as ranges. 'run' is true if
1951 * we are in a range.
1953 device_printf(child, "using IRQs %d", irqs[0]);
1955 for (i = 1; i < count; i++) {
1957 /* Still in a run? */
1958 if (irqs[i] == irqs[i - 1] + 1) {
1963 /* Finish previous range. */
1965 kprintf("-%d", irqs[i - 1]);
1969 /* Start new range. */
1970 kprintf(",%d", irqs[i]);
1973 /* Unfinished range? */
1975 kprintf("-%d", irqs[count - 1]);
1976 kprintf(" for MSI on cpu%d\n", cpuid);
1980 /* Update control register with count. */
1981 ctrl = cfg->msi.msi_ctrl;
1982 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1983 ctrl |= (ffs(count) - 1) << 4;
1984 cfg->msi.msi_ctrl = ctrl;
1985 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1987 /* Update counts of alloc'd messages. */
1988 cfg->msi.msi_alloc = count;
1989 cfg->msi.msi_handlers = 0;
1993 /* Release the MSI messages associated with this device. */
1995 pci_release_msi_method(device_t dev, device_t child)
1997 struct pci_devinfo *dinfo = device_get_ivars(child);
1998 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1999 struct resource_list_entry *rle;
2000 int i, irqs[32], cpuid = -1;
2002 /* Do we have any messages to release? */
2003 if (msi->msi_alloc == 0)
2005 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2007 /* Make sure none of the resources are allocated. */
2008 if (msi->msi_handlers > 0)
2010 for (i = 0; i < msi->msi_alloc; i++) {
2011 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2012 KASSERT(rle != NULL, ("missing MSI resource"));
2013 if (rle->res != NULL)
2017 KASSERT(cpuid >= 0 && cpuid < ncpus,
2018 ("invalid MSI target cpuid %d", cpuid));
2020 KASSERT(rle->cpuid == cpuid,
2021 ("MSI targets different cpus, "
2022 "was cpu%d, now cpu%d", cpuid, rle->cpuid));
2024 irqs[i] = rle->start;
2027 /* Update control register with 0 count. */
2028 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2029 ("%s: MSI still enabled", __func__));
2030 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2031 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2034 /* Release the messages. */
2035 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs,
2037 for (i = 0; i < msi->msi_alloc; i++)
2038 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2040 /* Update alloc count. */
2048 * Return the max supported MSI messages this device supports.
2049 * Basically, assuming the MD code can alloc messages, this function
2050 * should return the maximum value that pci_alloc_msi() can return.
2051 * Thus, it is subject to the tunables, etc.
2054 pci_msi_count_method(device_t dev, device_t child)
2056 struct pci_devinfo *dinfo = device_get_ivars(child);
2057 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2059 if (pci_do_msi && msi->msi_location != 0)
2060 return (msi->msi_msgnum);
2064 /* kfree pcicfgregs structure and all depending data structures */
2067 pci_freecfg(struct pci_devinfo *dinfo)
2069 struct devlist *devlist_head;
2072 devlist_head = &pci_devq;
2074 if (dinfo->cfg.vpd.vpd_reg) {
2075 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2076 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2077 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2078 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2079 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2080 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2081 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2083 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2084 kfree(dinfo, M_DEVBUF);
2086 /* increment the generation count */
2089 /* we're losing one device */
2095 * PCI power manangement
2098 pci_set_powerstate_method(device_t dev, device_t child, int state)
2100 struct pci_devinfo *dinfo = device_get_ivars(child);
2101 pcicfgregs *cfg = &dinfo->cfg;
2103 int result, oldstate, highest, delay;
2105 if (cfg->pp.pp_cap == 0)
2106 return (EOPNOTSUPP);
2109 * Optimize a no state change request away. While it would be OK to
2110 * write to the hardware in theory, some devices have shown odd
2111 * behavior when going from D3 -> D3.
2113 oldstate = pci_get_powerstate(child);
2114 if (oldstate == state)
2118 * The PCI power management specification states that after a state
2119 * transition between PCI power states, system software must
2120 * guarantee a minimal delay before the function accesses the device.
2121 * Compute the worst case delay that we need to guarantee before we
2122 * access the device. Many devices will be responsive much more
2123 * quickly than this delay, but there are some that don't respond
2124 * instantly to state changes. Transitions to/from D3 state require
2125 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2126 * is done below with DELAY rather than a sleeper function because
2127 * this function can be called from contexts where we cannot sleep.
2129 highest = (oldstate > state) ? oldstate : state;
2130 if (highest == PCI_POWERSTATE_D3)
2132 else if (highest == PCI_POWERSTATE_D2)
2136 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2137 & ~PCIM_PSTAT_DMASK;
2140 case PCI_POWERSTATE_D0:
2141 status |= PCIM_PSTAT_D0;
2143 case PCI_POWERSTATE_D1:
2144 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2145 return (EOPNOTSUPP);
2146 status |= PCIM_PSTAT_D1;
2148 case PCI_POWERSTATE_D2:
2149 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2150 return (EOPNOTSUPP);
2151 status |= PCIM_PSTAT_D2;
2153 case PCI_POWERSTATE_D3:
2154 status |= PCIM_PSTAT_D3;
2162 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2163 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2164 dinfo->cfg.func, oldstate, state);
2166 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2173 pci_get_powerstate_method(device_t dev, device_t child)
2175 struct pci_devinfo *dinfo = device_get_ivars(child);
2176 pcicfgregs *cfg = &dinfo->cfg;
2180 if (cfg->pp.pp_cap != 0) {
2181 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2182 switch (status & PCIM_PSTAT_DMASK) {
2184 result = PCI_POWERSTATE_D0;
2187 result = PCI_POWERSTATE_D1;
2190 result = PCI_POWERSTATE_D2;
2193 result = PCI_POWERSTATE_D3;
2196 result = PCI_POWERSTATE_UNKNOWN;
2200 /* No support, device is always at D0 */
2201 result = PCI_POWERSTATE_D0;
2207 * Some convenience functions for PCI device drivers.
2210 static __inline void
2211 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2215 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2217 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2220 static __inline void
2221 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2225 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2227 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2231 pci_enable_busmaster_method(device_t dev, device_t child)
2233 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2238 pci_disable_busmaster_method(device_t dev, device_t child)
2240 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2245 pci_enable_io_method(device_t dev, device_t child, int space)
2255 case SYS_RES_IOPORT:
2256 bit = PCIM_CMD_PORTEN;
2259 case SYS_RES_MEMORY:
2260 bit = PCIM_CMD_MEMEN;
2266 pci_set_command_bit(dev, child, bit);
2267 /* Some devices seem to need a brief stall here, what do to? */
2268 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2271 device_printf(child, "failed to enable %s mapping!\n", error);
2276 pci_disable_io_method(device_t dev, device_t child, int space)
2286 case SYS_RES_IOPORT:
2287 bit = PCIM_CMD_PORTEN;
2290 case SYS_RES_MEMORY:
2291 bit = PCIM_CMD_MEMEN;
2297 pci_clear_command_bit(dev, child, bit);
2298 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2299 if (command & bit) {
2300 device_printf(child, "failed to disable %s mapping!\n", error);
2307 * New style pci driver. Parent device is either a pci-host-bridge or a
2308 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2312 pci_print_verbose(struct pci_devinfo *dinfo)
2316 pcicfgregs *cfg = &dinfo->cfg;
2318 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2319 cfg->vendor, cfg->device, cfg->revid);
2320 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2321 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2322 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2323 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2325 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2326 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2327 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2328 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2329 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2330 if (cfg->intpin > 0)
2331 kprintf("\tintpin=%c, irq=%d\n",
2332 cfg->intpin +'a' -1, cfg->intline);
2333 if (cfg->pp.pp_cap) {
2336 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2337 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2338 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2339 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2340 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2341 status & PCIM_PSTAT_DMASK);
2343 if (cfg->msi.msi_location) {
2346 ctrl = cfg->msi.msi_ctrl;
2347 kprintf("\tMSI supports %d message%s%s%s\n",
2348 cfg->msi.msi_msgnum,
2349 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2350 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2351 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2353 if (cfg->msix.msix_location) {
2354 kprintf("\tMSI-X supports %d message%s ",
2355 cfg->msix.msix_msgnum,
2356 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2357 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2358 kprintf("in map 0x%x\n",
2359 cfg->msix.msix_table_bar);
2361 kprintf("in maps 0x%x and 0x%x\n",
2362 cfg->msix.msix_table_bar,
2363 cfg->msix.msix_pba_bar);
2365 pci_print_verbose_expr(cfg);
2370 pci_print_verbose_expr(const pcicfgregs *cfg)
2372 const struct pcicfg_expr *expr = &cfg->expr;
2373 const char *port_name;
2379 if (expr->expr_ptr == 0) /* No PCI Express capability */
2382 kprintf("\tPCI Express ver.%d cap=0x%04x",
2383 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2385 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2387 switch (port_type) {
2388 case PCIE_END_POINT:
2389 port_name = "DEVICE";
2391 case PCIE_LEG_END_POINT:
2392 port_name = "LEGDEV";
2394 case PCIE_ROOT_PORT:
2397 case PCIE_UP_STREAM_PORT:
2398 port_name = "UPSTREAM";
2400 case PCIE_DOWN_STREAM_PORT:
2401 port_name = "DOWNSTRM";
2403 case PCIE_PCIE2PCI_BRIDGE:
2404 port_name = "PCIE2PCI";
2406 case PCIE_PCI2PCIE_BRIDGE:
2407 port_name = "PCI2PCIE";
2409 case PCIE_ROOT_END_POINT:
2410 port_name = "ROOTDEV";
2412 case PCIE_ROOT_EVT_COLL:
2413 port_name = "ROOTEVTC";
2419 if ((port_type == PCIE_ROOT_PORT ||
2420 port_type == PCIE_DOWN_STREAM_PORT) &&
2421 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2423 if (port_name != NULL)
2424 kprintf("[%s]", port_name);
2426 if (pcie_slotimpl(cfg)) {
2427 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2428 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2429 kprintf("[HOTPLUG]");
2435 pci_porten(device_t pcib, int b, int s, int f)
2437 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2438 & PCIM_CMD_PORTEN) != 0;
2442 pci_memen(device_t pcib, int b, int s, int f)
2444 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2445 & PCIM_CMD_MEMEN) != 0;
2449 * Add a resource based on a pci map register. Return 1 if the map
2450 * register is a 32bit map register or 2 if it is a 64bit register.
2453 pci_add_map(device_t pcib, device_t bus, device_t dev,
2454 int b, int s, int f, int reg, struct resource_list *rl, int force,
2460 pci_addr_t start, end, count;
2467 struct resource *res;
2469 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2471 /* Disable access to device memory */
2473 if (PCI_BAR_MEM(map)) {
2474 old_cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2475 cmd = old_cmd & ~PCIM_CMD_MEMEN;
2476 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2479 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2480 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2481 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2483 /* Restore memory access mode */
2484 if (PCI_BAR_MEM(map)) {
2485 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, old_cmd, 2);
2488 if (PCI_BAR_MEM(map)) {
2489 type = SYS_RES_MEMORY;
2490 if (map & PCIM_BAR_MEM_PREFETCH)
2493 type = SYS_RES_IOPORT;
2494 ln2size = pci_mapsize(testval);
2495 ln2range = pci_maprange(testval);
2496 base = pci_mapbase(map);
2497 barlen = ln2range == 64 ? 2 : 1;
2500 * For I/O registers, if bottom bit is set, and the next bit up
2501 * isn't clear, we know we have a BAR that doesn't conform to the
2502 * spec, so ignore it. Also, sanity check the size of the data
2503 * areas to the type of memory involved. Memory must be at least
2504 * 16 bytes in size, while I/O ranges must be at least 4.
2506 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2508 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2509 (type == SYS_RES_IOPORT && ln2size < 2))
2513 /* Read the other half of a 64bit map register */
2514 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2516 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2517 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2518 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2519 kprintf(", port disabled\n");
2520 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2521 kprintf(", memory disabled\n");
2523 kprintf(", enabled\n");
2527 * If base is 0, then we have problems. It is best to ignore
2528 * such entries for the moment. These will be allocated later if
2529 * the driver specifically requests them. However, some
2530 * removable busses look better when all resources are allocated,
2531 * so allow '0' to be overriden.
2533 * Similarly treat maps whose values is the same as the test value
2534 * read back. These maps have had all f's written to them by the
2535 * BIOS in an attempt to disable the resources.
2537 if (!force && (base == 0 || map == testval))
2539 if ((u_long)base != base) {
2541 "pci%d:%d:%d:%d bar %#x too many address bits",
2542 pci_get_domain(dev), b, s, f, reg);
2547 * This code theoretically does the right thing, but has
2548 * undesirable side effects in some cases where peripherals
2549 * respond oddly to having these bits enabled. Let the user
2550 * be able to turn them off (since pci_enable_io_modes is 1 by
2553 if (pci_enable_io_modes) {
2554 /* Turn on resources that have been left off by a lazy BIOS */
2555 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2556 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2557 cmd |= PCIM_CMD_PORTEN;
2558 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2560 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2561 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2562 cmd |= PCIM_CMD_MEMEN;
2563 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2566 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2568 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2572 count = 1 << ln2size;
2573 if (base == 0 || base == pci_mapbase(testval)) {
2574 start = 0; /* Let the parent decide. */
2578 end = base + (1 << ln2size) - 1;
2580 resource_list_add(rl, type, reg, start, end, count, -1);
2583 * Try to allocate the resource for this BAR from our parent
2584 * so that this resource range is already reserved. The
2585 * driver for this device will later inherit this resource in
2586 * pci_alloc_resource().
2588 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2589 prefetch ? RF_PREFETCHABLE : 0, -1);
2592 * If the allocation fails, delete the resource list
2593 * entry to force pci_alloc_resource() to allocate
2594 * resources from the parent.
2596 resource_list_delete(rl, type, reg);
2597 #ifdef PCI_BAR_CLEAR
2600 #else /* !PCI_BAR_CLEAR */
2602 * Don't clear BAR here. Some BIOS lists HPET as a
2603 * PCI function, clearing the BAR causes HPET timer
2607 kprintf("pci:%d:%d:%d: resource reservation failed "
2608 "%#jx - %#jx\n", b, s, f,
2609 (intmax_t)start, (intmax_t)end);
2612 #endif /* PCI_BAR_CLEAR */
2614 start = rman_get_start(res);
2616 pci_write_config(dev, reg, start, 4);
2618 pci_write_config(dev, reg + 4, start >> 32, 4);
2623 * For ATA devices we need to decide early what addressing mode to use.
2624 * Legacy demands that the primary and secondary ATA ports sits on the
2625 * same addresses that old ISA hardware did. This dictates that we use
2626 * those addresses and ignore the BAR's if we cannot set PCI native
2630 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2631 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2633 int rid, type, progif;
2635 /* if this device supports PCI native addressing use it */
2636 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2637 if ((progif & 0x8a) == 0x8a) {
2638 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2639 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2640 kprintf("Trying ATA native PCI addressing mode\n");
2641 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2645 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2646 type = SYS_RES_IOPORT;
2647 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2648 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2649 prefetchmask & (1 << 0));
2650 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2651 prefetchmask & (1 << 1));
2654 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8, -1);
2655 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2658 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1, -1);
2659 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2662 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2663 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2664 prefetchmask & (1 << 2));
2665 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2666 prefetchmask & (1 << 3));
2669 resource_list_add(rl, type, rid, 0x170, 0x177, 8, -1);
2670 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2673 resource_list_add(rl, type, rid, 0x376, 0x376, 1, -1);
2674 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2677 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2678 prefetchmask & (1 << 4));
2679 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2680 prefetchmask & (1 << 5));
2684 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2686 struct pci_devinfo *dinfo = device_get_ivars(dev);
2687 pcicfgregs *cfg = &dinfo->cfg;
2688 char tunable_name[64];
2691 /* Has to have an intpin to have an interrupt. */
2692 if (cfg->intpin == 0)
2695 /* Let the user override the IRQ with a tunable. */
2696 irq = PCI_INVALID_IRQ;
2697 ksnprintf(tunable_name, sizeof(tunable_name),
2698 "hw.pci%d.%d.%d.%d.INT%c.irq",
2699 cfg->domain, cfg->bus, cfg->slot, cfg->func, cfg->intpin + 'A' - 1);
2700 if (TUNABLE_INT_FETCH(tunable_name, &irq)) {
2701 if (irq >= 255 || irq <= 0) {
2702 irq = PCI_INVALID_IRQ;
2704 BUS_CONFIG_INTR(bus, dev, irq,
2705 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2710 * If we didn't get an IRQ via the tunable, then we either use the
2711 * IRQ value in the intline register or we ask the bus to route an
2712 * interrupt for us. If force_route is true, then we only use the
2713 * value in the intline register if the bus was unable to assign an
2716 if (!PCI_INTERRUPT_VALID(irq)) {
2717 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2718 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2719 if (!PCI_INTERRUPT_VALID(irq))
2723 /* If after all that we don't have an IRQ, just bail. */
2724 if (!PCI_INTERRUPT_VALID(irq))
2727 /* Update the config register if it changed. */
2728 if (irq != cfg->intline) {
2730 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2733 /* Add this IRQ as rid 0 interrupt resource. */
2734 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1,
2735 machintr_legacy_intr_cpuid(irq));
2739 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2741 struct pci_devinfo *dinfo = device_get_ivars(dev);
2742 pcicfgregs *cfg = &dinfo->cfg;
2743 struct resource_list *rl = &dinfo->resources;
2744 struct pci_quirk *q;
2751 /* ATA devices needs special map treatment */
2752 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2753 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2754 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2755 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2756 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2757 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2759 for (i = 0; i < cfg->nummaps;)
2760 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2761 rl, force, prefetchmask & (1 << i));
2764 * Add additional, quirked resources.
2766 for (q = &pci_quirks[0]; q->devid; q++) {
2767 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2768 && q->type == PCI_QUIRK_MAP_REG)
2769 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2773 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2775 * Try to re-route interrupts. Sometimes the BIOS or
2776 * firmware may leave bogus values in these registers.
2777 * If the re-route fails, then just stick with what we
2780 pci_assign_interrupt(bus, dev, 1);
2785 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2787 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2788 device_t pcib = device_get_parent(dev);
2789 struct pci_devinfo *dinfo;
2791 int s, f, pcifunchigh;
2794 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2795 ("dinfo_size too small"));
2796 maxslots = PCIB_MAXSLOTS(pcib);
2797 for (s = 0; s <= maxslots; s++) {
2801 hdrtype = REG(PCIR_HDRTYPE, 1);
2802 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2804 if (hdrtype & PCIM_MFDEV)
2805 pcifunchigh = PCI_FUNCMAX;
2806 for (f = 0; f <= pcifunchigh; f++) {
2807 dinfo = pci_read_device(pcib, domain, busno, s, f,
2809 if (dinfo != NULL) {
2810 pci_add_child(dev, dinfo);
2818 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2822 pcib = device_get_parent(bus);
2823 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2824 device_set_ivars(dinfo->cfg.dev, dinfo);
2825 resource_list_init(&dinfo->resources);
2826 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2827 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2828 pci_print_verbose(dinfo);
2829 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2833 pci_probe(device_t dev)
2835 device_set_desc(dev, "PCI bus");
2837 /* Allow other subclasses to override this driver. */
2842 pci_attach(device_t dev)
2847 * Since there can be multiple independantly numbered PCI
2848 * busses on systems with multiple PCI domains, we can't use
2849 * the unit number to decide which bus we are probing. We ask
2850 * the parent pcib what our domain and bus numbers are.
2852 domain = pcib_get_domain(dev);
2853 busno = pcib_get_bus(dev);
2855 device_printf(dev, "domain=%d, physical bus=%d\n",
2858 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2860 return (bus_generic_attach(dev));
2864 pci_suspend(device_t dev)
2866 int dstate, error, i, numdevs;
2867 device_t acpi_dev, child, *devlist;
2868 struct pci_devinfo *dinfo;
2871 * Save the PCI configuration space for each child and set the
2872 * device in the appropriate power state for this sleep state.
2875 if (pci_do_power_resume)
2876 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2877 device_get_children(dev, &devlist, &numdevs);
2878 for (i = 0; i < numdevs; i++) {
2880 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2881 pci_cfg_save(child, dinfo, 0);
2884 /* Suspend devices before potentially powering them down. */
2885 error = bus_generic_suspend(dev);
2887 kfree(devlist, M_TEMP);
2892 * Always set the device to D3. If ACPI suggests a different
2893 * power state, use it instead. If ACPI is not present, the
2894 * firmware is responsible for managing device power. Skip
2895 * children who aren't attached since they are powered down
2896 * separately. Only manage type 0 devices for now.
2898 for (i = 0; acpi_dev && i < numdevs; i++) {
2900 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2901 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2902 dstate = PCI_POWERSTATE_D3;
2903 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2904 pci_set_powerstate(child, dstate);
2907 kfree(devlist, M_TEMP);
2912 pci_resume(device_t dev)
2915 device_t acpi_dev, child, *devlist;
2916 struct pci_devinfo *dinfo;
2919 * Set each child to D0 and restore its PCI configuration space.
2922 if (pci_do_power_resume)
2923 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2924 device_get_children(dev, &devlist, &numdevs);
2925 for (i = 0; i < numdevs; i++) {
2927 * Notify ACPI we're going to D0 but ignore the result. If
2928 * ACPI is not present, the firmware is responsible for
2929 * managing device power. Only manage type 0 devices for now.
2932 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2933 if (acpi_dev && device_is_attached(child) &&
2934 dinfo->cfg.hdrtype == 0) {
2935 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2936 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2939 /* Now the device is powered up, restore its config space. */
2940 pci_cfg_restore(child, dinfo);
2942 kfree(devlist, M_TEMP);
2943 return (bus_generic_resume(dev));
2947 pci_load_vendor_data(void)
2949 caddr_t vendordata, info;
2951 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2952 info = preload_search_info(vendordata, MODINFO_ADDR);
2953 pci_vendordata = *(char **)info;
2954 info = preload_search_info(vendordata, MODINFO_SIZE);
2955 pci_vendordata_size = *(size_t *)info;
2956 /* terminate the database */
2957 pci_vendordata[pci_vendordata_size] = '\n';
2962 pci_driver_added(device_t dev, driver_t *driver)
2967 struct pci_devinfo *dinfo;
2971 device_printf(dev, "driver added\n");
2972 DEVICE_IDENTIFY(driver, dev);
2973 device_get_children(dev, &devlist, &numdevs);
2974 for (i = 0; i < numdevs; i++) {
2976 if (device_get_state(child) != DS_NOTPRESENT)
2978 dinfo = device_get_ivars(child);
2979 pci_print_verbose(dinfo);
2981 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2982 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2984 pci_cfg_restore(child, dinfo);
2985 if (device_probe_and_attach(child) != 0)
2986 pci_cfg_save(child, dinfo, 1);
2988 kfree(devlist, M_TEMP);
2992 pci_child_detached(device_t parent __unused, device_t child)
2994 /* Turn child's power off */
2995 pci_cfg_save(child, device_get_ivars(child), 1);
2999 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3000 driver_intr_t *intr, void *arg, void **cookiep,
3001 lwkt_serialize_t serializer, const char *desc)
3006 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3007 arg, &cookie, serializer, desc);
3011 /* If this is not a direct child, just bail out. */
3012 if (device_get_parent(child) != dev) {
3017 rid = rman_get_rid(irq);
3019 /* Make sure that INTx is enabled */
3020 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3022 struct pci_devinfo *dinfo = device_get_ivars(child);
3027 * Check to see if the interrupt is MSI or MSI-X.
3028 * Ask our parent to map the MSI and give
3029 * us the address and data register values.
3030 * If we fail for some reason, teardown the
3031 * interrupt handler.
3033 if (dinfo->cfg.msi.msi_alloc > 0) {
3034 struct pcicfg_msi *msi = &dinfo->cfg.msi;
3036 if (msi->msi_addr == 0) {
3037 KASSERT(msi->msi_handlers == 0,
3038 ("MSI has handlers, but vectors not mapped"));
3039 error = PCIB_MAP_MSI(device_get_parent(dev),
3040 child, rman_get_start(irq), &addr, &data,
3041 rman_get_cpuid(irq));
3044 msi->msi_addr = addr;
3045 msi->msi_data = data;
3046 pci_enable_msi(child, addr, data);
3048 msi->msi_handlers++;
3050 struct msix_vector *mv;
3053 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3054 ("No MSI-X or MSI rid %d allocated", rid));
3056 mv = pci_find_msix_vector(child, rid);
3058 ("MSI-X rid %d is not allocated", rid));
3059 KASSERT(mv->mv_address == 0,
3060 ("MSI-X rid %d has been setup", rid));
3062 error = PCIB_MAP_MSI(device_get_parent(dev),
3063 child, rman_get_start(irq), &addr, &data,
3064 rman_get_cpuid(irq));
3067 mv->mv_address = addr;
3070 vector = PCI_MSIX_RID2VEC(rid);
3071 pci_setup_msix_vector(child, vector,
3072 mv->mv_address, mv->mv_data);
3073 pci_unmask_msix_vector(child, vector);
3076 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3077 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3080 (void)bus_generic_teardown_intr(dev, child, irq,
3090 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3095 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3098 /* If this isn't a direct child, just bail out */
3099 if (device_get_parent(child) != dev)
3100 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3102 rid = rman_get_rid(irq);
3105 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3107 struct pci_devinfo *dinfo = device_get_ivars(child);
3110 * Check to see if the interrupt is MSI or MSI-X. If so,
3111 * decrement the appropriate handlers count and mask the
3112 * MSI-X message, or disable MSI messages if the count
3115 if (dinfo->cfg.msi.msi_alloc > 0) {
3116 struct pcicfg_msi *msi = &dinfo->cfg.msi;
3118 KASSERT(rid <= msi->msi_alloc,
3119 ("MSI-X index too high"));
3120 KASSERT(msi->msi_handlers > 0,
3121 ("MSI rid %d is not setup", rid));
3123 msi->msi_handlers--;
3124 if (msi->msi_handlers == 0)
3125 pci_disable_msi(child);
3127 struct msix_vector *mv;
3129 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3130 ("No MSI or MSI-X rid %d allocated", rid));
3132 mv = pci_find_msix_vector(child, rid);
3134 ("MSI-X rid %d is not allocated", rid));
3135 KASSERT(mv->mv_address != 0,
3136 ("MSI-X rid %d has not been setup", rid));
3138 pci_mask_msix_vector(child, PCI_MSIX_RID2VEC(rid));
3143 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3146 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3151 pci_print_child(device_t dev, device_t child)
3153 struct pci_devinfo *dinfo;
3154 struct resource_list *rl;
3157 dinfo = device_get_ivars(child);
3158 rl = &dinfo->resources;
3160 retval += bus_print_child_header(dev, child);
3162 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3163 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3164 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3165 if (device_get_flags(dev))
3166 retval += kprintf(" flags %#x", device_get_flags(dev));
3168 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3169 pci_get_function(child));
3171 retval += bus_print_child_footer(dev, child);
3181 } pci_nomatch_tab[] = {
3182 {PCIC_OLD, -1, "old"},
3183 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3184 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3185 {PCIC_STORAGE, -1, "mass storage"},
3186 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3187 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3188 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3189 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3190 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3191 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3192 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3193 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3194 {PCIC_NETWORK, -1, "network"},
3195 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3196 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3197 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3198 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3199 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3200 {PCIC_DISPLAY, -1, "display"},
3201 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3202 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3203 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3204 {PCIC_MULTIMEDIA, -1, "multimedia"},
3205 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3206 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3207 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3208 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3209 {PCIC_MEMORY, -1, "memory"},
3210 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3211 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3212 {PCIC_BRIDGE, -1, "bridge"},
3213 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3214 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3215 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3216 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3217 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3218 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3219 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3220 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3221 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3222 {PCIC_SIMPLECOMM, -1, "simple comms"},
3223 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3224 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3225 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3226 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3227 {PCIC_BASEPERIPH, -1, "base peripheral"},
3228 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3229 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3230 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3231 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3232 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3233 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3234 {PCIC_INPUTDEV, -1, "input device"},
3235 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3236 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3237 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3238 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3239 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3240 {PCIC_DOCKING, -1, "docking station"},
3241 {PCIC_PROCESSOR, -1, "processor"},
3242 {PCIC_SERIALBUS, -1, "serial bus"},
3243 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3244 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3245 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3246 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3247 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3248 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3249 {PCIC_WIRELESS, -1, "wireless controller"},
3250 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3251 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3252 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3253 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3254 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3255 {PCIC_SATCOM, -1, "satellite communication"},
3256 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3257 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3258 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3259 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3260 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3261 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3262 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3263 {PCIC_DASP, -1, "dasp"},
3264 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3269 pci_probe_nomatch(device_t dev, device_t child)
3272 char *cp, *scp, *device;
3275 * Look for a listing for this device in a loaded device database.
3277 if ((device = pci_describe_device(child)) != NULL) {
3278 device_printf(dev, "<%s>", device);
3279 kfree(device, M_DEVBUF);
3282 * Scan the class/subclass descriptions for a general
3287 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3288 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3289 if (pci_nomatch_tab[i].subclass == -1) {
3290 cp = pci_nomatch_tab[i].desc;
3291 } else if (pci_nomatch_tab[i].subclass ==
3292 pci_get_subclass(child)) {
3293 scp = pci_nomatch_tab[i].desc;
3297 device_printf(dev, "<%s%s%s>",
3299 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3302 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3303 pci_get_vendor(child), pci_get_device(child),
3304 pci_get_slot(child), pci_get_function(child));
3305 if (pci_get_intpin(child) > 0) {
3308 irq = pci_get_irq(child);
3309 if (PCI_INTERRUPT_VALID(irq))
3310 kprintf(" irq %d", irq);
3314 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3318 * Parse the PCI device database, if loaded, and return a pointer to a
3319 * description of the device.
3321 * The database is flat text formatted as follows:
3323 * Any line not in a valid format is ignored.
3324 * Lines are terminated with newline '\n' characters.
3326 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3329 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3330 * - devices cannot be listed without a corresponding VENDOR line.
3331 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3332 * another TAB, then the device name.
3336 * Assuming (ptr) points to the beginning of a line in the database,
3337 * return the vendor or device and description of the next entry.
3338 * The value of (vendor) or (device) inappropriate for the entry type
3339 * is set to -1. Returns nonzero at the end of the database.
3341 * Note that this is slightly unrobust in the face of corrupt data;
3342 * we attempt to safeguard against this by spamming the end of the
3343 * database with a newline when we initialise.
3346 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3355 left = pci_vendordata_size - (cp - pci_vendordata);
3363 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3367 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3370 /* skip to next line */
3371 while (*cp != '\n' && left > 0) {
3380 /* skip to next line */
3381 while (*cp != '\n' && left > 0) {
3385 if (*cp == '\n' && left > 0)
3392 pci_describe_device(device_t dev)
3395 char *desc, *vp, *dp, *line;
3397 desc = vp = dp = NULL;
3400 * If we have no vendor data, we can't do anything.
3402 if (pci_vendordata == NULL)
3406 * Scan the vendor data looking for this device
3408 line = pci_vendordata;
3409 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3412 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3414 if (vendor == pci_get_vendor(dev))
3417 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3420 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3428 if (device == pci_get_device(dev))
3432 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3433 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3435 ksprintf(desc, "%s, %s", vp, dp);
3438 kfree(vp, M_DEVBUF);
3440 kfree(dp, M_DEVBUF);
3445 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3447 struct pci_devinfo *dinfo;
3450 dinfo = device_get_ivars(child);
3454 case PCI_IVAR_ETHADDR:
3456 * The generic accessor doesn't deal with failure, so
3457 * we set the return value, then return an error.
3459 *((uint8_t **) result) = NULL;
3461 case PCI_IVAR_SUBVENDOR:
3462 *result = cfg->subvendor;
3464 case PCI_IVAR_SUBDEVICE:
3465 *result = cfg->subdevice;
3467 case PCI_IVAR_VENDOR:
3468 *result = cfg->vendor;
3470 case PCI_IVAR_DEVICE:
3471 *result = cfg->device;
3473 case PCI_IVAR_DEVID:
3474 *result = (cfg->device << 16) | cfg->vendor;
3476 case PCI_IVAR_CLASS:
3477 *result = cfg->baseclass;
3479 case PCI_IVAR_SUBCLASS:
3480 *result = cfg->subclass;
3482 case PCI_IVAR_PROGIF:
3483 *result = cfg->progif;
3485 case PCI_IVAR_REVID:
3486 *result = cfg->revid;
3488 case PCI_IVAR_INTPIN:
3489 *result = cfg->intpin;
3492 *result = cfg->intline;
3494 case PCI_IVAR_DOMAIN:
3495 *result = cfg->domain;
3501 *result = cfg->slot;
3503 case PCI_IVAR_FUNCTION:
3504 *result = cfg->func;
3506 case PCI_IVAR_CMDREG:
3507 *result = cfg->cmdreg;
3509 case PCI_IVAR_CACHELNSZ:
3510 *result = cfg->cachelnsz;
3512 case PCI_IVAR_MINGNT:
3513 *result = cfg->mingnt;
3515 case PCI_IVAR_MAXLAT:
3516 *result = cfg->maxlat;
3518 case PCI_IVAR_LATTIMER:
3519 *result = cfg->lattimer;
3521 case PCI_IVAR_PCIXCAP_PTR:
3522 *result = cfg->pcix.pcix_ptr;
3524 case PCI_IVAR_PCIECAP_PTR:
3525 *result = cfg->expr.expr_ptr;
3527 case PCI_IVAR_VPDCAP_PTR:
3528 *result = cfg->vpd.vpd_reg;
3537 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3539 struct pci_devinfo *dinfo;
3541 dinfo = device_get_ivars(child);
3544 case PCI_IVAR_INTPIN:
3545 dinfo->cfg.intpin = value;
3547 case PCI_IVAR_ETHADDR:
3548 case PCI_IVAR_SUBVENDOR:
3549 case PCI_IVAR_SUBDEVICE:
3550 case PCI_IVAR_VENDOR:
3551 case PCI_IVAR_DEVICE:
3552 case PCI_IVAR_DEVID:
3553 case PCI_IVAR_CLASS:
3554 case PCI_IVAR_SUBCLASS:
3555 case PCI_IVAR_PROGIF:
3556 case PCI_IVAR_REVID:
3558 case PCI_IVAR_DOMAIN:
3561 case PCI_IVAR_FUNCTION:
3562 return (EINVAL); /* disallow for now */
3569 #include "opt_ddb.h"
3571 #include <ddb/ddb.h>
3572 #include <sys/cons.h>
3575 * List resources based on pci map registers, used for within ddb
3578 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3580 struct pci_devinfo *dinfo;
3581 struct devlist *devlist_head;
3584 int i, error, none_count;
3587 /* get the head of the device queue */
3588 devlist_head = &pci_devq;
3591 * Go through the list of devices and print out devices
3593 for (error = 0, i = 0,
3594 dinfo = STAILQ_FIRST(devlist_head);
3595 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3596 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3598 /* Populate pd_name and pd_unit */
3601 name = device_get_name(dinfo->cfg.dev);
3604 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3605 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3606 (name && *name) ? name : "none",
3607 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3609 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3610 p->pc_sel.pc_func, (p->pc_class << 16) |
3611 (p->pc_subclass << 8) | p->pc_progif,
3612 (p->pc_subdevice << 16) | p->pc_subvendor,
3613 (p->pc_device << 16) | p->pc_vendor,
3614 p->pc_revid, p->pc_hdr);
3620 static struct resource *
3621 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3622 u_long start, u_long end, u_long count, u_int flags)
3624 struct pci_devinfo *dinfo = device_get_ivars(child);
3625 struct resource_list *rl = &dinfo->resources;
3626 struct resource_list_entry *rle;
3627 struct resource *res;
3628 pci_addr_t map, testval;
3632 * Weed out the bogons, and figure out how large the BAR/map
3633 * is. Bars that read back 0 here are bogus and unimplemented.
3634 * Note: atapci in legacy mode are special and handled elsewhere
3635 * in the code. If you have a atapci device in legacy mode and
3636 * it fails here, that other code is broken.
3639 map = pci_read_config(child, *rid, 4);
3640 pci_write_config(child, *rid, 0xffffffff, 4);
3641 testval = pci_read_config(child, *rid, 4);
3642 if (pci_maprange(testval) == 64)
3643 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3644 if (pci_mapbase(testval) == 0)
3648 * Restore the original value of the BAR. We may have reprogrammed
3649 * the BAR of the low-level console device and when booting verbose,
3650 * we need the console device addressable.
3652 pci_write_config(child, *rid, map, 4);
3654 if (PCI_BAR_MEM(testval)) {
3655 if (type != SYS_RES_MEMORY) {
3658 "child %s requested type %d for rid %#x,"
3659 " but the BAR says it is an memio\n",
3660 device_get_nameunit(child), type, *rid);
3664 if (type != SYS_RES_IOPORT) {
3667 "child %s requested type %d for rid %#x,"
3668 " but the BAR says it is an ioport\n",
3669 device_get_nameunit(child), type, *rid);
3674 * For real BARs, we need to override the size that
3675 * the driver requests, because that's what the BAR
3676 * actually uses and we would otherwise have a
3677 * situation where we might allocate the excess to
3678 * another driver, which won't work.
3680 mapsize = pci_mapsize(testval);
3681 count = 1UL << mapsize;
3682 if (RF_ALIGNMENT(flags) < mapsize)
3683 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3684 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3685 flags |= RF_PREFETCHABLE;
3688 * Allocate enough resource, and then write back the
3689 * appropriate bar for that resource.
3691 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3692 start, end, count, flags, -1);
3694 device_printf(child,
3695 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3696 count, *rid, type, start, end);
3699 resource_list_add(rl, type, *rid, start, end, count, -1);
3700 rle = resource_list_find(rl, type, *rid);
3702 panic("pci_alloc_map: unexpectedly can't find resource.");
3704 rle->start = rman_get_start(res);
3705 rle->end = rman_get_end(res);
3708 device_printf(child,
3709 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3710 count, *rid, type, rman_get_start(res));
3711 map = rman_get_start(res);
3713 pci_write_config(child, *rid, map, 4);
3714 if (pci_maprange(testval) == 64)
3715 pci_write_config(child, *rid + 4, map >> 32, 4);
3721 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3722 u_long start, u_long end, u_long count, u_int flags, int cpuid)
3724 struct pci_devinfo *dinfo = device_get_ivars(child);
3725 struct resource_list *rl = &dinfo->resources;
3726 struct resource_list_entry *rle;
3727 pcicfgregs *cfg = &dinfo->cfg;
3730 * Perform lazy resource allocation
3732 if (device_get_parent(child) == dev) {
3736 * Can't alloc legacy interrupt once MSI messages
3737 * have been allocated.
3739 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3740 cfg->msix.msix_alloc > 0))
3743 * If the child device doesn't have an
3744 * interrupt routed and is deserving of an
3745 * interrupt, try to assign it one.
3747 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3749 pci_assign_interrupt(dev, child, 0);
3751 case SYS_RES_IOPORT:
3752 case SYS_RES_MEMORY:
3753 if (*rid < PCIR_BAR(cfg->nummaps)) {
3755 * Enable the I/O mode. We should
3756 * also be assigning resources too
3757 * when none are present. The
3758 * resource_list_alloc kind of sorta does
3761 if (PCI_ENABLE_IO(dev, child, type))
3764 rle = resource_list_find(rl, type, *rid);
3766 return (pci_alloc_map(dev, child, type, rid,
3767 start, end, count, flags));
3771 * If we've already allocated the resource, then
3772 * return it now. But first we may need to activate
3773 * it, since we don't allocate the resource as active
3774 * above. Normally this would be done down in the
3775 * nexus, but since we short-circuit that path we have
3776 * to do its job here. Not sure if we should kfree the
3777 * resource if it fails to activate.
3779 rle = resource_list_find(rl, type, *rid);
3780 if (rle != NULL && rle->res != NULL) {
3782 device_printf(child,
3783 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3784 rman_get_size(rle->res), *rid, type,
3785 rman_get_start(rle->res));
3786 if ((flags & RF_ACTIVE) &&
3787 bus_generic_activate_resource(dev, child, type,
3788 *rid, rle->res) != 0)
3793 return (resource_list_alloc(rl, dev, child, type, rid,
3794 start, end, count, flags, cpuid));
3798 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3800 struct pci_devinfo *dinfo;
3801 struct resource_list *rl;
3802 struct resource_list_entry *rle;
3804 if (device_get_parent(child) != dev)
3807 dinfo = device_get_ivars(child);
3808 rl = &dinfo->resources;
3809 rle = resource_list_find(rl, type, rid);
3812 if (rman_get_device(rle->res) != dev ||
3813 rman_get_flags(rle->res) & RF_ACTIVE) {
3814 device_printf(dev, "delete_resource: "
3815 "Resource still owned by child, oops. "
3816 "(type=%d, rid=%d, addr=%lx)\n",
3817 rle->type, rle->rid,
3818 rman_get_start(rle->res));
3821 bus_release_resource(dev, type, rid, rle->res);
3823 resource_list_delete(rl, type, rid);
3826 * Why do we turn off the PCI configuration BAR when we delete a
3829 pci_write_config(child, rid, 0, 4);
3830 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3833 struct resource_list *
3834 pci_get_resource_list (device_t dev, device_t child)
3836 struct pci_devinfo *dinfo = device_get_ivars(child);
3841 return (&dinfo->resources);
3845 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3847 struct pci_devinfo *dinfo = device_get_ivars(child);
3848 pcicfgregs *cfg = &dinfo->cfg;
3850 return (PCIB_READ_CONFIG(device_get_parent(dev),
3851 cfg->bus, cfg->slot, cfg->func, reg, width));
3855 pci_write_config_method(device_t dev, device_t child, int reg,
3856 uint32_t val, int width)
3858 struct pci_devinfo *dinfo = device_get_ivars(child);
3859 pcicfgregs *cfg = &dinfo->cfg;
3861 PCIB_WRITE_CONFIG(device_get_parent(dev),
3862 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3866 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3870 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3871 pci_get_function(child));
3876 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3879 struct pci_devinfo *dinfo;
3882 dinfo = device_get_ivars(child);
3884 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3885 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3886 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3892 pci_assign_interrupt_method(device_t dev, device_t child)
3894 struct pci_devinfo *dinfo = device_get_ivars(child);
3895 pcicfgregs *cfg = &dinfo->cfg;
3897 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3902 pci_modevent(module_t mod, int what, void *arg)
3904 static struct cdev *pci_cdev;
3908 STAILQ_INIT(&pci_devq);
3910 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3912 pci_load_vendor_data();
3916 destroy_dev(pci_cdev);
3924 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3929 * Only do header type 0 devices. Type 1 devices are bridges,
3930 * which we know need special treatment. Type 2 devices are
3931 * cardbus bridges which also require special treatment.
3932 * Other types are unknown, and we err on the side of safety
3935 if (dinfo->cfg.hdrtype != 0)
3939 * Restore the device to full power mode. We must do this
3940 * before we restore the registers because moving from D3 to
3941 * D0 will cause the chip's BARs and some other registers to
3942 * be reset to some unknown power on reset values. Cut down
3943 * the noise on boot by doing nothing if we are already in
3946 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3947 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3949 for (i = 0; i < dinfo->cfg.nummaps; i++)
3950 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3951 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3952 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3953 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3954 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3955 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3956 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3957 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3958 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3959 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3960 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3962 /* Restore MSI and MSI-X configurations if they are present. */
3963 if (dinfo->cfg.msi.msi_location != 0)
3964 pci_resume_msi(dev);
3965 if (dinfo->cfg.msix.msix_location != 0)
3966 pci_resume_msix(dev);
3970 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3977 * Only do header type 0 devices. Type 1 devices are bridges, which
3978 * we know need special treatment. Type 2 devices are cardbus bridges
3979 * which also require special treatment. Other types are unknown, and
3980 * we err on the side of safety by ignoring them. Powering down
3981 * bridges should not be undertaken lightly.
3983 if (dinfo->cfg.hdrtype != 0)
3985 for (i = 0; i < dinfo->cfg.nummaps; i++)
3986 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3987 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3990 * Some drivers apparently write to these registers w/o updating our
3991 * cached copy. No harm happens if we update the copy, so do so here
3992 * so we can restore them. The COMMAND register is modified by the
3993 * bus w/o updating the cache. This should represent the normally
3994 * writable portion of the 'defined' part of type 0 headers. In
3995 * theory we also need to save/restore the PCI capability structures
3996 * we know about, but apart from power we don't know any that are
3999 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4000 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4001 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4002 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4003 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4004 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4005 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4006 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4007 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4008 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4009 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4010 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4011 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4012 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4013 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4016 * don't set the state for display devices, base peripherals and
4017 * memory devices since bad things happen when they are powered down.
4018 * We should (a) have drivers that can easily detach and (b) use
4019 * generic drivers for these devices so that some device actually
4020 * attaches. We need to make sure that when we implement (a) we don't
4021 * power the device down on a reattach.
4023 cls = pci_get_class(dev);
4026 switch (pci_do_power_nodriver)
4028 case 0: /* NO powerdown at all */
4030 case 1: /* Conservative about what to power down */
4031 if (cls == PCIC_STORAGE)
4034 case 2: /* Agressive about what to power down */
4035 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4036 cls == PCIC_BASEPERIPH)
4039 case 3: /* Power down everything */
4043 * PCI spec says we can only go into D3 state from D0 state.
4044 * Transition from D[12] into D0 before going to D3 state.
4046 ps = pci_get_powerstate(dev);
4047 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4048 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4049 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4050 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4053 #ifdef COMPAT_OLDPCI
4056 * Locate the parent of a PCI device by scanning the PCI devlist
4057 * and return the entry for the parent.
4058 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4059 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4062 pci_devlist_get_parent(pcicfgregs *cfg)
4064 struct devlist *devlist_head;
4065 struct pci_devinfo *dinfo;
4066 pcicfgregs *bridge_cfg;
4069 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4071 /* If the device is on PCI bus 0, look for the host */
4072 if (cfg->bus == 0) {
4073 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4074 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4075 bridge_cfg = &dinfo->cfg;
4076 if (bridge_cfg->baseclass == PCIC_BRIDGE
4077 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4078 && bridge_cfg->bus == cfg->bus) {
4084 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4086 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4087 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4088 bridge_cfg = &dinfo->cfg;
4089 if (bridge_cfg->baseclass == PCIC_BRIDGE
4090 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4091 && bridge_cfg->secondarybus == cfg->bus) {
4100 #endif /* COMPAT_OLDPCI */
4103 pci_alloc_1intr(device_t dev, int msi_enable, int *rid0, u_int *flags0)
4109 type = PCI_INTR_TYPE_LEGACY;
4110 flags = RF_SHAREABLE | RF_ACTIVE;
4112 msi_enable = device_getenv_int(dev, "msi.enable", msi_enable);
4116 cpu = device_getenv_int(dev, "msi.cpu", -1);
4120 if (pci_alloc_msi(dev, &rid, 1, cpu) == 0) {
4121 flags &= ~RF_SHAREABLE;
4122 type = PCI_INTR_TYPE_MSI;