2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/i386/isa/pci_cfgreg.c,v 1.1.2.7 2001/11/28 05:47:03 imp Exp $
29 * $DragonFly: src/sys/bus/pci/i386/pci_cfgreg.c,v 1.7 2004/02/08 07:10:46 hmp Exp $
33 #include <sys/param.h> /* XXX trim includes */
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/malloc.h>
39 #include <sys/sysctl.h>
42 #include <machine/md_var.h>
43 #include <machine/clock.h>
44 #include <bus/pci/pcivar.h>
45 #include <bus/pci/pcireg.h>
46 #include <bus/isa/isavar.h>
47 #include <bus/pci/i386/pci_cfgreg.h>
48 #include <machine/segments.h>
49 #include <machine/pc/bios.h>
52 #include <machine/smp.h>
55 #define PRVERB(a) do { \
60 static int pci_disable_bios_route = 0;
61 SYSCTL_INT(_hw, OID_AUTO, pci_disable_bios_route, CTLFLAG_RD,
62 &pci_disable_bios_route, 0, "disable interrupt routing via PCI-BIOS");
63 TUNABLE_INT("hw.pci_disable_bios_route", &pci_disable_bios_route);
68 static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq);
69 static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
70 static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
71 static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
72 static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
74 static void pci_print_irqmask(u_int16_t irqs);
75 static void pci_print_route_table(struct PIR_table *prt, int size);
76 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
77 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
78 static int pcireg_cfgopen(void);
80 static struct PIR_table *pci_route_table;
81 static int pci_route_count;
84 * Some BIOS writers seem to want to ignore the spec and put
85 * 0 in the intline rather than 255 to indicate none. Some use
86 * numbers in the range 128-254 to indicate something strange and
87 * apparently undocumented anywhere. Assume these are completely bogus
88 * and map them to 255, which means "none".
91 pci_i386_map_intline(int line)
93 if (line == 0 || line >= 128)
94 return (PCI_INVALID_IRQ);
99 pcibios_get_version(void)
101 struct bios_regs args;
103 if (PCIbios.ventry == 0) {
104 PRVERB(("pcibios: No call entry point\n"));
107 args.eax = PCIBIOS_BIOS_PRESENT;
108 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
109 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
112 if (args.edx != 0x20494350) {
113 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
116 return (args.ebx & 0xffff);
120 * Initialise access to PCI configuration space
125 static int opened = 0;
127 static struct PIR_table *pt;
135 if (pcireg_cfgopen() == 0)
138 v = pcibios_get_version();
140 printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
144 * Look for the interrupt routing table.
146 * We use PCI BIOS's PIR table if it's available $PIR is the
147 * standard way to do this. Sadly some machines are not
148 * standards conforming and have _PIR instead. We shrug and cope
149 * by looking for both.
151 if (pcibios_get_version() >= 0x0210 && pt == NULL) {
152 sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0);
154 sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0);
156 pt = (struct PIR_table *)(uintptr_t)
157 BIOS_PADDRTOVADDR(sigaddr);
158 for (cv = (u_int8_t *)pt, ck = 0, i = 0;
159 i < (pt->pt_header.ph_length); i++)
161 if (ck == 0 && pt->pt_header.ph_length >
162 sizeof(struct PIR_header)) {
163 pci_route_table = pt;
164 pci_route_count = (pt->pt_header.ph_length -
165 sizeof(struct PIR_header)) /
166 sizeof(struct PIR_entry);
167 printf("Using $PIR table, %d entries at %p\n",
168 pci_route_count, pci_route_table);
170 pci_print_route_table(pci_route_table,
180 * Read configuration space register
183 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
190 * If we are using the APIC, the contents of the intline
191 * register will probably be wrong (since they are set up for
192 * use with the PIC. Rather than rewrite these registers
193 * (maybe that would be smarter) we trap attempts to read them
194 * and translate to our private vector numbers.
196 if ((reg == PCIR_INTLINE) && (bytes == 1)) {
198 pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1);
199 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
204 airq = pci_apic_irq(bus, slot, pin);
206 /* PCI specific entry found in MP table */
208 undirect_pci_irq(line);
212 * PCI interrupts might be redirected to the
213 * ISA bus according to some MP tables. Use the
214 * same methods as used by the ISA devices
215 * devices to find the proper IOAPIC int pin.
217 airq = isa_apic_irq(line);
218 if ((airq >= 0) && (airq != line)) {
219 /* XXX: undirect_pci_irq() ? */
220 undirect_isa_irq(line);
229 * Some BIOS writers seem to want to ignore the spec and put
230 * 0 in the intline rather than 255 to indicate none. The rest of
231 * the code uses 255 as an invalid IRQ.
233 if (reg == PCIR_INTLINE && bytes == 1) {
234 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
235 return pci_i386_map_intline(line);
238 return (pcireg_cfgread(bus, slot, func, reg, bytes));
242 * Write configuration space register
245 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
247 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
251 pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
253 return (pci_cfgregread(cfg->bus, cfg->slot, cfg->func, reg, bytes));
257 pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
259 pci_cfgregwrite(cfg->bus, cfg->slot, cfg->func, reg, data, bytes);
264 * Route a PCI interrupt
267 pci_cfgintr(int bus, int device, int pin, int oldirq)
269 struct PIR_entry *pe;
271 struct bios_regs args;
277 v = pcibios_get_version();
280 "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n",
281 (v & 0xff00) >> 8, v & 0xff));
282 return (PCI_INVALID_IRQ);
284 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
285 (pin < 1) || (pin > 4))
286 return (PCI_INVALID_IRQ);
289 * Scan the entry table for a contender
291 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count;
293 if ((bus != pe->pe_bus) || (device != pe->pe_device))
297 * A link of 0 means that this intpin is not connected to
298 * any other device's interrupt pins and is not connected to
299 * any of the Interrupt Router's interrupt pins, so we can't
302 if (pe->pe_intpin[pin - 1].link == 0)
305 if (pci_cfgintr_valid(pe, pin, oldirq)) {
306 printf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus,
307 device, 'A' + pin - 1, oldirq);
312 * We try to find a linked interrupt, then we look to see
313 * if the interrupt is uniquely routed, then we look for
314 * a virgin interrupt. The virgin interrupt should return
315 * an interrupt we can route, but if that fails, maybe we
316 * should try harder to route a different interrupt.
317 * However, experience has shown that that's rarely the
318 * failure mode we see.
320 irq = pci_cfgintr_linked(pe, pin);
321 if (irq != PCI_INVALID_IRQ)
323 if (irq == PCI_INVALID_IRQ) {
324 irq = pci_cfgintr_unique(pe, pin);
325 if (irq != PCI_INVALID_IRQ)
328 if (irq == PCI_INVALID_IRQ)
329 irq = pci_cfgintr_virgin(pe, pin);
331 if (irq == PCI_INVALID_IRQ)
334 if (pci_disable_bios_route != 0)
337 * Ask the BIOS to route the interrupt. If we picked an
338 * interrupt that failed, we should really try other
339 * choices that the BIOS offers us.
341 * For uniquely routed interrupts, we need to try
342 * to route them on some machines. Yet other machines
343 * fail to route, so we have to pretend that in that
344 * case it worked. Isn't PC hardware fun?
346 * NOTE: if we want to whack hardware to do this, then
347 * I think the right way to do that would be to have
348 * bridge drivers that do this. I'm not sure that the
349 * $PIR table would be valid for those interrupt
352 args.eax = PCIBIOS_ROUTE_INTERRUPT;
353 args.ebx = (bus << 8) | (device << 3);
354 /* pin value is 0xa - 0xd */
355 args.ecx = (irq << 8) | (0xa + pin -1);
357 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)) &&
359 PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n"));
360 return (PCI_INVALID_IRQ);
362 printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus,
363 device, 'A' + pin - 1, irq);
367 PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus,
368 device, 'A' + pin - 1));
369 return (PCI_INVALID_IRQ);
373 * Check to see if an existing IRQ setting is valid.
376 pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq)
380 if (!PCI_INTERRUPT_VALID(irq))
382 irqmask = pe->pe_intpin[pin - 1].irqs;
383 if (irqmask & (1 << irq)) {
384 PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq));
391 * Look to see if the routing table claims this pin is uniquely routed.
394 pci_cfgintr_unique(struct PIR_entry *pe, int pin)
399 irqmask = pe->pe_intpin[pin - 1].irqs;
400 if(irqmask != 0 && powerof2(irqmask)) {
401 irq = ffs(irqmask) - 1;
402 PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
405 return (PCI_INVALID_IRQ);
409 * Look for another device which shares the same link byte and
410 * already has a unique IRQ, or which has had one routed already.
413 pci_cfgintr_linked(struct PIR_entry *pe, int pin)
415 struct PIR_entry *oe;
416 struct PIR_intpin *pi;
422 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count;
424 /* scan interrupt pins */
425 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
427 /* don't look at the entry we're trying to match */
428 if ((pe == oe) && (i == (pin - 1)))
430 /* compare link bytes */
431 if (pi->link != pe->pe_intpin[pin - 1].link)
433 /* link destination mapped to a unique interrupt? */
434 if (pi->irqs != 0 && powerof2(pi->irqs)) {
435 irq = ffs(pi->irqs) - 1;
436 PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
442 * look for the real PCI device that matches this
445 irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device,
447 if (irq != PCI_INVALID_IRQ)
451 return (PCI_INVALID_IRQ);
455 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
456 * see if it has already been assigned an interrupt.
459 pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
461 devclass_t pci_devclass;
462 device_t *pci_devices;
464 device_t *pci_children;
466 device_t *busp, *childp;
470 * Find all the PCI busses.
473 if ((pci_devclass = devclass_find("pci")) != NULL)
474 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
477 * Scan all the PCI busses/devices looking for this one.
479 irq = PCI_INVALID_IRQ;
480 for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ);
483 device_get_children(*busp, &pci_children, &pci_childcount);
485 for (j = 0, childp = pci_children; j < pci_childcount; j++,
487 if ((pci_get_bus(*childp) == bus) &&
488 (pci_get_slot(*childp) == device) &&
489 (pci_get_intpin(*childp) == matchpin)) {
490 irq = pci_i386_map_intline(pci_get_irq(*childp));
491 if (irq != PCI_INVALID_IRQ)
492 PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
493 pe->pe_intpin[pin - 1].link, irq,
494 pci_get_bus(*childp),
495 pci_get_slot(*childp),
496 pci_get_function(*childp)));
500 if (pci_children != NULL)
501 free(pci_children, M_TEMP);
503 if (pci_devices != NULL)
504 free(pci_devices, M_TEMP);
509 * Pick a suitable IRQ from those listed as routable to this device.
512 pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
517 * first scan the set of PCI-only interrupts and see if any of these
520 for (irq = 0; irq < 16; irq++) {
523 /* can we use this interrupt? */
524 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
525 (pe->pe_intpin[pin - 1].irqs & ibit)) {
526 PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq));
531 /* life is tough, so just pick an interrupt */
532 for (irq = 0; irq < 16; irq++) {
535 if (pe->pe_intpin[pin - 1].irqs & ibit) {
536 PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq));
540 return (PCI_INVALID_IRQ);
544 pci_print_irqmask(u_int16_t irqs)
553 for (i = 0; i < 16; i++, irqs >>= 1)
564 * Dump the contents of a PCI BIOS Interrupt Routing Table to the console.
567 pci_print_route_table(struct PIR_table *ptr, int size)
569 struct PIR_entry *entry;
570 struct PIR_intpin *intpin;
573 printf("PCI-Only Interrupts: ");
574 pci_print_irqmask(ptr->pt_header.ph_pci_irqs);
575 printf("\nLocation Bus Device Pin Link IRQs\n");
576 entry = &ptr->pt_entry[0];
577 for (i = 0; i < size; i++, entry++) {
578 intpin = &entry->pe_intpin[0];
579 for (pin = 0; pin < 4; pin++, intpin++)
580 if (intpin->link != 0) {
581 if (entry->pe_slot == 0)
584 printf("slot %-3d ", entry->pe_slot);
585 printf(" %3d %3d %c 0x%02x ",
586 entry->pe_bus, entry->pe_device,
587 'A' + pin, intpin->link);
588 pci_print_irqmask(intpin->irqs);
595 * See if any interrupts for a given PCI bus are routed in the PIR. Don't
596 * even bother looking if the BIOS doesn't support routing anyways.
599 pci_probe_route_table(int bus)
604 v = pcibios_get_version();
607 for (i = 0; i < pci_route_count; i++)
608 if (pci_route_table->pt_entry[i].pe_bus == bus)
614 * Configuration space access using direct register operations
617 /* enable configuration space accesses and return data port address */
619 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
623 if (bus <= PCI_BUSMAX
625 && func <= PCI_FUNCMAX
628 && (unsigned) bytes <= 4
629 && (reg & (bytes - 1)) == 0) {
632 outl(CONF1_ADDR_PORT, (1 << 31)
633 | (bus << 16) | (slot << 11)
634 | (func << 8) | (reg & ~0x03));
635 dataport = CONF1_DATA_PORT + (reg & 0x03);
638 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
639 outb(CONF2_FORWARD_PORT, bus);
640 dataport = 0xc000 | (slot << 8) | reg;
647 /* disable configuration space accesses */
653 outl(CONF1_ADDR_PORT, 0);
656 outb(CONF2_ENABLE_PORT, 0);
657 outb(CONF2_FORWARD_PORT, 0);
663 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
668 port = pci_cfgenable(bus, slot, func, reg, bytes);
687 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
691 port = pci_cfgenable(bus, slot, func, reg, bytes);
708 /* check whether the configuration mechanism has been correctly identified */
710 pci_cfgcheck(int maxdev)
718 printf("pci_cfgcheck:\tdevice ");
720 for (device = 0; device < maxdev; device++) {
722 printf("%d ", device);
724 port = pci_cfgenable(0, device, 0, 0, 4);
726 if (id == 0 || id == 0xffffffff)
729 port = pci_cfgenable(0, device, 0, 8, 4);
730 class = inl(port) >> 8;
732 printf("[class=%06x] ", class);
733 if (class == 0 || (class & 0xf870ff) != 0)
736 port = pci_cfgenable(0, device, 0, 14, 1);
739 printf("[hdr=%02x] ", header);
740 if ((header & 0x7e) != 0)
744 printf("is there (id=%08x)\n", id);
750 printf("-- nothing found\n");
759 uint32_t mode1res,oldval1;
760 uint8_t mode2res,oldval2;
762 oldval1 = inl(CONF1_ADDR_PORT);
765 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
769 if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
774 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
776 mode1res = inl(CONF1_ADDR_PORT);
777 outl(CONF1_ADDR_PORT, oldval1);
780 printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
781 mode1res, CONF1_ENABLE_CHK);
784 if (pci_cfgcheck(32))
788 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
789 mode1res = inl(CONF1_ADDR_PORT);
790 outl(CONF1_ADDR_PORT, oldval1);
793 printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
794 mode1res, CONF1_ENABLE_CHK1);
796 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
797 if (pci_cfgcheck(32))
802 oldval2 = inb(CONF2_ENABLE_PORT);
805 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
809 if ((oldval2 & 0xf0) == 0) {
814 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
815 mode2res = inb(CONF2_ENABLE_PORT);
816 outb(CONF2_ENABLE_PORT, oldval2);
819 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
820 mode2res, CONF2_ENABLE_CHK);
822 if (mode2res == CONF2_ENABLE_RES) {
824 printf("pci_open(2a):\tnow trying mechanism 2\n");
826 if (pci_cfgcheck(16))