sys/platform/pc64/amd64/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * Copyright (c) 2008 The DragonFly Project.
   6  * All rights reserved.
   7  *
   8  * This code is derived from software contributed to Berkeley by
   9  * William Jolitz.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. All advertising materials mentioning features or use of this software
  20  *    must display the following acknowledgement:
  21  *      This product includes software developed by the University of
  22  *      California, Berkeley and its contributors.
  23  * 4. Neither the name of the University nor the names of its contributors
  24  *    may be used to endorse or promote products derived from this software
  25  *    without specific prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  29  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  30  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  31  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  35  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  36  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  37  * SUCH DAMAGE.
  38  *
  39  * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  40  * $DragonFly: src/sys/platform/pc64/amd64/identcpu.c,v 1.2 2008/11/24 13:14:21 swildner Exp $
  41  */
  42
  43 #include "opt_cpu.h"
  44
  45 #include <sys/param.h>
  46 #include <sys/bus.h>
  47 #include <sys/eventhandler.h>
  48 #include <sys/systm.h>
  49 #include <sys/kernel.h>
  50 #include <sys/sysctl.h>
  51 #include <sys/power.h>
  52
  53 #include <machine/asmacros.h>
  54 #include <machine/clock.h>
  55 #include <machine/cputypes.h>
  56 #include <machine/frame.h>
  57 #include <machine_base/isa/intr_machdep.h>
  58 #include <machine/segments.h>
  59 #include <machine/specialreg.h>
  60 #include <machine/md_var.h>
  61
  62 /* XXX - should be in header file: */
  63 void printcpuinfo(void);
  64 void identify_cpu(void);
  65 void earlysetcpuclass(void);
  66 void panicifcpuunsupported(void);
  67
  68 static u_int find_cpu_vendor_id(void);
  69 static void print_AMD_info(void);
  70 static void print_AMD_assoc(int i);
  71 static void print_via_padlock_info(void);
  72
  73 int     cpu_class;
  74 char machine[] = "amd64";
  75 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  76     machine, 0, "Machine class");
  77
  78 static char cpu_model[128];
  79 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
  80     cpu_model, 0, "Machine model");
  81
  82 static int hw_clockrate;
  83 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
  84     &hw_clockrate, 0, "CPU instruction clock rate");
  85
  86 static char cpu_brand[48];
  87
  88 static struct {
  89         char    *cpu_name;
  90         int     cpu_class;
  91 } amd64_cpus[] = {
  92         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
  93         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
  94 };
  95
  96 static struct {
  97         char    *vendor;
  98         u_int   vendor_id;
  99 } cpu_vendors[] = {
 100         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 101         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 102         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 103 };
 104
 105 int cpu_cores;
 106 int cpu_logical;
 107
 108
 109 extern int pq_l2size;
 110 extern int pq_l2nways;
 111
 112 void
 113 printcpuinfo(void)
 114 {
 115         u_int regs[4], i;
 116         char *brand;
 117
 118         cpu_class = amd64_cpus[cpu].cpu_class;
 119         kprintf("CPU: ");
 120         strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
 121
 122         /* Check for extended CPUID information and a processor name. */
 123         if (cpu_exthigh >= 0x80000004) {
 124                 brand = cpu_brand;
 125                 for (i = 0x80000002; i < 0x80000005; i++) {
 126                         do_cpuid(i, regs);
 127                         memcpy(brand, regs, sizeof(regs));
 128                         brand += sizeof(regs);
 129                 }
 130         }
 131
 132         switch (cpu_vendor_id) {
 133         case CPU_VENDOR_INTEL:
 134                 /* Please make up your mind folks! */
 135                 strcat(cpu_model, "EM64T");
 136                 break;
 137         case CPU_VENDOR_AMD:
 138                 /*
 139                  * Values taken from AMD Processor Recognition
 140                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 141                  * (also describes ``Features'' encodings.
 142                  */
 143                 strcpy(cpu_model, "AMD ");
 144                 if ((cpu_id & 0xf00) == 0xf00)
 145                         strcat(cpu_model, "AMD64 Processor");
 146                 else
 147                         strcat(cpu_model, "Unknown");
 148                 break;
 149         case CPU_VENDOR_CENTAUR:
 150                 strcpy(cpu_model, "VIA ");
 151                 if ((cpu_id & 0xff0) == 0x6f0)
 152                         strcat(cpu_model, "Nano Processor");
 153                 else
 154                         strcat(cpu_model, "Unknown");
 155                 break;
 156         default:
 157                 strcat(cpu_model, "Unknown");
 158                 break;
 159         }
 160
 161         /*
 162          * Replace cpu_model with cpu_brand minus leading spaces if
 163          * we have one.
 164          */
 165         brand = cpu_brand;
 166         while (*brand == ' ')
 167                 ++brand;
 168         if (*brand != '\0')
 169                 strcpy(cpu_model, brand);
 170
 171         kprintf("%s (", cpu_model);
 172         switch(cpu_class) {
 173         case CPUCLASS_K8:
 174                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
 175                 kprintf("%jd.%02d-MHz ",
 176                        (intmax_t)(tsc_frequency + 4999) / 1000000,
 177                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
 178                 kprintf("K8");
 179                 break;
 180         default:
 181                 kprintf("Unknown");     /* will panic below... */
 182         }
 183         kprintf("-class CPU)\n");
 184         if (*cpu_vendor)
 185                 kprintf("  Origin = \"%s\"", cpu_vendor);
 186         if (cpu_id)
 187                 kprintf("  Id = 0x%x", cpu_id);
 188
 189         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 190             cpu_vendor_id == CPU_VENDOR_AMD ||
 191             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 192                 kprintf("  Stepping = %u", cpu_id & 0xf);
 193                 if (cpu_high > 0) {
 194                         u_int cmp = 1, htt = 1;
 195
 196                         /*
 197                          * Here we should probably set up flags indicating
 198                          * whether or not various features are available.
 199                          * The interesting ones are probably VME, PSE, PAE,
 200                          * and PGE.  The code already assumes without bothering
 201                          * to check that all CPUs >= Pentium have a TSC and
 202                          * MSRs.
 203                          */
 204                         kprintf("\n  Features=0x%b", cpu_feature,
 205                         "\020"
 206                         "\001FPU"       /* Integral FPU */
 207                         "\002VME"       /* Extended VM86 mode support */
 208                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 209                         "\004PSE"       /* 4MByte page tables */
 210                         "\005TSC"       /* Timestamp counter */
 211                         "\006MSR"       /* Machine specific registers */
 212                         "\007PAE"       /* Physical address extension */
 213                         "\010MCE"       /* Machine Check support */
 214                         "\011CX8"       /* CMPEXCH8 instruction */
 215                         "\012APIC"      /* SMP local APIC */
 216                         "\013oldMTRR"   /* Previous implementation of MTRR */
 217                         "\014SEP"       /* Fast System Call */
 218                         "\015MTRR"      /* Memory Type Range Registers */
 219                         "\016PGE"       /* PG_G (global bit) support */
 220                         "\017MCA"       /* Machine Check Architecture */
 221                         "\020CMOV"      /* CMOV instruction */
 222                         "\021PAT"       /* Page attributes table */
 223                         "\022PSE36"     /* 36 bit address space support */
 224                         "\023PN"        /* Processor Serial number */
 225                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 226                         "\025<b20>"
 227                         "\026DTS"       /* Debug Trace Store */
 228                         "\027ACPI"      /* ACPI support */
 229                         "\030MMX"       /* MMX instructions */
 230                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 231                         "\032SSE"       /* Streaming SIMD Extensions */
 232                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 233                         "\034SS"        /* Self snoop */
 234                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 235                         "\036TM"        /* Thermal Monitor clock slowdown */
 236                         "\037IA64"      /* CPU can execute IA64 instructions */
 237                         "\040PBE"       /* Pending Break Enable */
 238                         );
 239
 240                         if (cpu_feature2 != 0) {
 241                                 kprintf("\n  Features2=0x%b", cpu_feature2,
 242                                 "\020"
 243                                 "\001SSE3"      /* SSE3 */
 244                                 "\002<b1>"
 245                                 "\003DTES64"    /* 64-bit Debug Trace */
 246                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 247                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 248                                 "\006VMX"       /* Virtual Machine Extensions */
 249                                 "\007SMX"       /* Safer Mode Extensions */
 250                                 "\010EST"       /* Enhanced SpeedStep */
 251                                 "\011TM2"       /* Thermal Monitor 2 */
 252                                 "\012SSSE3"     /* SSSE3 */
 253                                 "\013CNXT-ID"   /* L1 context ID available */
 254                                 "\014<b11>"
 255                                 "\015<b12>"
 256                                 "\016CX16"      /* CMPXCHG16B Instruction */
 257                                 "\017xTPR"      /* Send Task Priority Messages*/
 258                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 259                                 "\021<b16>"
 260                                 "\022<b17>"
 261                                 "\023DCA"       /* Direct Cache Access */
 262                                 "\024SSE4.1"
 263                                 "\025SSE4.2"
 264                                 "\026x2APIC"    /* xAPIC Extensions */
 265                                 "\027MOVBE"     /* MOVBE instruction */
 266                                 "\030POPCNT"
 267                                 "\031<b24>"
 268                                 "\032<b25>"
 269                                 "\033XSAVE"
 270                                 "\034OSXSAVE"
 271                                 "\035<b28>"
 272                                 "\036<b29>"
 273                                 "\037<b30>"
 274                                 "\040<b31>"
 275                                 );
 276                         }
 277
 278                         /*
 279                          * AMD64 Architecture Programmer's Manual Volume 3:
 280                          * General-Purpose and System Instructions
 281                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
 282                          *
 283                          * IA-32 Intel Architecture Software Developer's Manual,
 284                          * Volume 2A: Instruction Set Reference, A-M
 285                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
 286                          */
 287                         if (amd_feature != 0) {
 288                                 kprintf("\n  AMD Features=0x%b", amd_feature,
 289                                 "\020"          /* in hex */
 290                                 "\001<s0>"      /* Same */
 291                                 "\002<s1>"      /* Same */
 292                                 "\003<s2>"      /* Same */
 293                                 "\004<s3>"      /* Same */
 294                                 "\005<s4>"      /* Same */
 295                                 "\006<s5>"      /* Same */
 296                                 "\007<s6>"      /* Same */
 297                                 "\010<s7>"      /* Same */
 298                                 "\011<s8>"      /* Same */
 299                                 "\012<s9>"      /* Same */
 300                                 "\013<b10>"     /* Undefined */
 301                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 302                                 "\015<s12>"     /* Same */
 303                                 "\016<s13>"     /* Same */
 304                                 "\017<s14>"     /* Same */
 305                                 "\020<s15>"     /* Same */
 306                                 "\021<s16>"     /* Same */
 307                                 "\022<s17>"     /* Same */
 308                                 "\023<b18>"     /* Reserved, unknown */
 309                                 "\024MP"        /* Multiprocessor Capable */
 310                                 "\025NX"        /* Has EFER.NXE, NX */
 311                                 "\026<b21>"     /* Undefined */
 312                                 "\027MMX+"      /* AMD MMX Extensions */
 313                                 "\030<s23>"     /* Same */
 314                                 "\031<s24>"     /* Same */
 315                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 316                                 "\033Page1GB"   /* 1-GB large page support */
 317                                 "\034RDTSCP"    /* RDTSCP */
 318                                 "\035<b28>"     /* Undefined */
 319                                 "\036LM"        /* 64 bit long mode */
 320                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 321                                 "\0403DNow!"    /* AMD 3DNow! */
 322                                 );
 323                         }
 324
 325                         if (amd_feature2 != 0) {
 326                                 kprintf("\n  AMD Features2=0x%b", amd_feature2,
 327                                 "\020"
 328                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 329                                 "\002CMP"       /* CMP legacy */
 330                                 "\003SVM"       /* Secure Virtual Mode */
 331                                 "\004ExtAPIC"   /* Extended APIC register */
 332                                 "\005CR8"       /* CR8 in legacy mode */
 333                                 "\006ABM"       /* LZCNT instruction */
 334                                 "\007SSE4A"     /* SSE4A */
 335                                 "\010MAS"       /* Misaligned SSE mode */
 336                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 337                                 "\012OSVW"      /* OS visible workaround */
 338                                 "\013IBS"       /* Instruction based sampling */
 339                                 "\014SSE5"      /* SSE5 */
 340                                 "\015SKINIT"    /* SKINIT/STGI */
 341                                 "\016WDT"       /* Watchdog timer */
 342                                 "\017<b14>"
 343                                 "\020<b15>"
 344                                 "\021<b16>"
 345                                 "\022<b17>"
 346                                 "\023<b18>"
 347                                 "\024<b19>"
 348                                 "\025<b20>"
 349                                 "\026<b21>"
 350                                 "\027<b22>"
 351                                 "\030<b23>"
 352                                 "\031<b24>"
 353                                 "\032<b25>"
 354                                 "\033<b26>"
 355                                 "\034<b27>"
 356                                 "\035<b28>"
 357                                 "\036<b29>"
 358                                 "\037<b30>"
 359                                 "\040<b31>"
 360                                 );
 361                         }
 362
 363                         if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
 364                                 print_via_padlock_info();
 365
 366                         if ((cpu_feature & CPUID_HTT) &&
 367                             cpu_vendor_id == CPU_VENDOR_AMD)
 368                                 cpu_feature &= ~CPUID_HTT;
 369
 370                         /*
 371                          * If this CPU supports HTT or CMP then mention the
 372                          * number of physical/logical cores it contains.
 373                          */
 374                         if (cpu_feature & CPUID_HTT)
 375                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
 376                         if (cpu_vendor_id == CPU_VENDOR_AMD &&
 377                             (amd_feature2 & AMDID2_CMP))
 378                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
 379                         else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
 380                             (cpu_high >= 4)) {
 381                                 cpuid_count(4, 0, regs);
 382                                 if ((regs[0] & 0x1f) != 0)
 383                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
 384                         }
 385                         cpu_cores = cmp;
 386                         cpu_logical = htt / cmp;
 387                         if (cmp > 1)
 388                                 kprintf("\n  Cores per package: %d", cmp);
 389                         if ((htt / cmp) > 1)
 390                                 kprintf("\n  Logical CPUs per core: %d",
 391                                     cpu_logical);
 392                 }
 393         }
 394         /* Avoid ugly blank lines: only print newline when we have to. */
 395         if (*cpu_vendor || cpu_id)
 396                 kprintf("\n");
 397
 398         if (!bootverbose)
 399                 return;
 400
 401         if (cpu_vendor_id == CPU_VENDOR_AMD)
 402                 print_AMD_info();
 403 }
 404
 405 void
 406 panicifcpuunsupported(void)
 407 {
 408
 409 #ifndef HAMMER_CPU
 410 #error "You need to specify a cpu type"
 411 #endif
 412         /*
 413          * Now that we have told the user what they have,
 414          * let them know if that machine type isn't configured.
 415          */
 416         switch (cpu_class) {
 417         case CPUCLASS_X86:
 418 #ifndef HAMMER_CPU
 419         case CPUCLASS_K8:
 420 #endif
 421                 panic("CPU class not configured");
 422         default:
 423                 break;
 424         }
 425 }
 426
 427
 428 #if JG
 429 /* Update TSC freq with the value indicated by the caller. */
 430 static void
 431 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
 432 {
 433         /* If there was an error during the transition, don't do anything. */
 434         if (status != 0)
 435                 return;
 436
 437         /* Total setting for this level gives the new frequency in MHz. */
 438         hw_clockrate = level->total_set.freq;
 439 }
 440
 441 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
 442     EVENTHANDLER_PRI_ANY);
 443 #endif
 444
 445 /*
 446  * Final stage of CPU identification.
 447  */
 448 void
 449 identify_cpu(void)
 450 {
 451         u_int regs[4];
 452
 453         do_cpuid(0, regs);
 454         cpu_high = regs[0];
 455         ((u_int *)&cpu_vendor)[0] = regs[1];
 456         ((u_int *)&cpu_vendor)[1] = regs[3];
 457         ((u_int *)&cpu_vendor)[2] = regs[2];
 458         cpu_vendor[12] = '\0';
 459         cpu_vendor_id = find_cpu_vendor_id();
 460
 461         do_cpuid(1, regs);
 462         cpu_id = regs[0];
 463         cpu_procinfo = regs[1];
 464         cpu_feature = regs[3];
 465         cpu_feature2 = regs[2];
 466
 467         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 468             cpu_vendor_id == CPU_VENDOR_AMD ||
 469             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 470                 do_cpuid(0x80000000, regs);
 471                 cpu_exthigh = regs[0];
 472         }
 473         if (cpu_exthigh >= 0x80000001) {
 474                 do_cpuid(0x80000001, regs);
 475                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
 476                 amd_feature2 = regs[2];
 477         }
 478         if (cpu_exthigh >= 0x80000008) {
 479                 do_cpuid(0x80000008, regs);
 480                 cpu_procinfo2 = regs[2];
 481         }
 482
 483         /* XXX */
 484         cpu = CPU_CLAWHAMMER;
 485 }
 486
 487 static u_int
 488 find_cpu_vendor_id(void)
 489 {
 490         int     i;
 491
 492         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
 493                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
 494                         return (cpu_vendors[i].vendor_id);
 495         return (0);
 496 }
 497
 498 static void
 499 print_AMD_assoc(int i)
 500 {
 501         if (i == 255)
 502                 kprintf(", fully associative\n");
 503         else
 504                 kprintf(", %d-way associative\n", i);
 505 }
 506
 507 static void
 508 print_AMD_l2_assoc(int i)
 509 {
 510         switch (i & 0x0f) {
 511         case 0: kprintf(", disabled/not present\n"); break;
 512         case 1: kprintf(", direct mapped\n"); break;
 513         case 2: kprintf(", 2-way associative\n"); break;
 514         case 4: kprintf(", 4-way associative\n"); break;
 515         case 6: kprintf(", 8-way associative\n"); break;
 516         case 8: kprintf(", 16-way associative\n"); break;
 517         case 15: kprintf(", fully associative\n"); break;
 518         default: kprintf(", reserved configuration\n"); break;
 519         }
 520 }
 521
 522 static void
 523 print_AMD_info(void)
 524 {
 525         u_int regs[4];
 526
 527         if (cpu_exthigh < 0x80000005)
 528                 return;
 529
 530         do_cpuid(0x80000005, regs);
 531         kprintf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
 532         print_AMD_assoc(regs[0] >> 24);
 533
 534         kprintf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
 535         print_AMD_assoc((regs[0] >> 8) & 0xff);
 536
 537         kprintf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
 538         print_AMD_assoc(regs[1] >> 24);
 539
 540         kprintf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
 541         print_AMD_assoc((regs[1] >> 8) & 0xff);
 542
 543         kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
 544         kprintf(", %d bytes/line", regs[2] & 0xff);
 545         kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
 546         print_AMD_assoc((regs[2] >> 16) & 0xff);
 547
 548         kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
 549         kprintf(", %d bytes/line", regs[3] & 0xff);
 550         kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
 551         print_AMD_assoc((regs[3] >> 16) & 0xff);
 552
 553         if (cpu_exthigh >= 0x80000006) {
 554                 do_cpuid(0x80000006, regs);
 555                 if ((regs[0] >> 16) != 0) {
 556                         kprintf("L2 2MB data TLB: %d entries",
 557                             (regs[0] >> 16) & 0xfff);
 558                         print_AMD_l2_assoc(regs[0] >> 28);
 559                         kprintf("L2 2MB instruction TLB: %d entries",
 560                             regs[0] & 0xfff);
 561                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
 562                 } else {
 563                         kprintf("L2 2MB unified TLB: %d entries",
 564                             regs[0] & 0xfff);
 565                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
 566                 }
 567                 if ((regs[1] >> 16) != 0) {
 568                         kprintf("L2 4KB data TLB: %d entries",
 569                             (regs[1] >> 16) & 0xfff);
 570                         print_AMD_l2_assoc(regs[1] >> 28);
 571
 572                         kprintf("L2 4KB instruction TLB: %d entries",
 573                             (regs[1] >> 16) & 0xfff);
 574                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
 575                 } else {
 576                         kprintf("L2 4KB unified TLB: %d entries",
 577                             (regs[1] >> 16) & 0xfff);
 578                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
 579                 }
 580                 kprintf("L2 unified cache: %d kbytes", regs[2] >> 16);
 581                 kprintf(", %d bytes/line", regs[2] & 0xff);
 582                 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
 583                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
 584         }
 585 }
 586
 587 static void
 588 print_via_padlock_info(void)
 589 {
 590         u_int regs[4];
 591
 592         /* Check for supported models. */
 593         switch (cpu_id & 0xff0) {
 594         case 0x690:
 595                 if ((cpu_id & 0xf) < 3)
 596                         return;
 597         case 0x6a0:
 598         case 0x6d0:
 599         case 0x6f0:
 600                 break;
 601         default:
 602                 return;
 603         }
 604
 605         do_cpuid(0xc0000000, regs);
 606         if (regs[0] >= 0xc0000001)
 607                 do_cpuid(0xc0000001, regs);
 608         else
 609                 return;
 610
 611         kprintf("\n  VIA Padlock Features=0x%b", regs[3],
 612         "\020"
 613         "\003RNG"               /* RNG */
 614         "\007AES"               /* ACE */
 615         "\011AES-CTR"           /* ACE2 */
 616         "\013SHA1,SHA256"       /* PHE */
 617         "\015RSA"               /* PMM */
 618         );
 619 }