sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  * $DragonFly: src/sys/dev/netif/bce/if_bce.c,v 1.21 2008/11/19 13:57:49 sephe Exp $
  32  */
  33
  34 /*
  35  * The following controllers are supported by this driver:
  36  *   BCM5706C A2, A3
  37  *   BCM5708C B1, B2
  38  *
  39  * The following controllers are not supported by this driver:
  40  *   BCM5706C A0, A1
  41  *   BCM5706S A0, A1, A2, A3
  42  *   BCM5708C A0, B0
  43  *   BCM5708S A0, B0, B1, B2
  44  */
  45
  46 #include "opt_bce.h"
  47 #include "opt_polling.h"
  48
  49 #include <sys/param.h>
  50 #include <sys/bus.h>
  51 #include <sys/endian.h>
  52 #include <sys/kernel.h>
  53 #include <sys/interrupt.h>
  54 #include <sys/mbuf.h>
  55 #include <sys/malloc.h>
  56 #include <sys/queue.h>
  57 #ifdef BCE_DEBUG
  58 #include <sys/random.h>
  59 #endif
  60 #include <sys/rman.h>
  61 #include <sys/serialize.h>
  62 #include <sys/socket.h>
  63 #include <sys/sockio.h>
  64 #include <sys/sysctl.h>
  65
  66 #include <net/bpf.h>
  67 #include <net/ethernet.h>
  68 #include <net/if.h>
  69 #include <net/if_arp.h>
  70 #include <net/if_dl.h>
  71 #include <net/if_media.h>
  72 #include <net/if_types.h>
  73 #include <net/ifq_var.h>
  74 #include <net/vlan/if_vlan_var.h>
  75 #include <net/vlan/if_vlan_ether.h>
  76
  77 #include <dev/netif/mii_layer/mii.h>
  78 #include <dev/netif/mii_layer/miivar.h>
  79
  80 #include <bus/pci/pcireg.h>
  81 #include <bus/pci/pcivar.h>
  82
  83 #include "miibus_if.h"
  84
  85 #include <dev/netif/bce/if_bcereg.h>
  86 #include <dev/netif/bce/if_bcefw.h>
  87
  88 /****************************************************************************/
  89 /* BCE Debug Options                                                        */
  90 /****************************************************************************/
  91 #ifdef BCE_DEBUG
  92
  93 static uint32_t bce_debug = BCE_WARN;
  94
  95 /*
  96  *          0 = Never
  97  *          1 = 1 in 2,147,483,648
  98  *        256 = 1 in     8,388,608
  99  *       2048 = 1 in     1,048,576
 100  *      65536 = 1 in        32,768
 101  *    1048576 = 1 in         2,048
 102  *  268435456 = 1 in             8
 103  *  536870912 = 1 in             4
 104  * 1073741824 = 1 in             2
 105  *
 106  * bce_debug_l2fhdr_status_check:
 107  *     How often the l2_fhdr frame error check will fail.
 108  *
 109  * bce_debug_unexpected_attention:
 110  *     How often the unexpected attention check will fail.
 111  *
 112  * bce_debug_mbuf_allocation_failure:
 113  *     How often to simulate an mbuf allocation failure.
 114  *
 115  * bce_debug_dma_map_addr_failure:
 116  *     How often to simulate a DMA mapping failure.
 117  *
 118  * bce_debug_bootcode_running_failure:
 119  *     How often to simulate a bootcode failure.
 120  */
 121 static int      bce_debug_l2fhdr_status_check = 0;
 122 static int      bce_debug_unexpected_attention = 0;
 123 static int      bce_debug_mbuf_allocation_failure = 0;
 124 static int      bce_debug_dma_map_addr_failure = 0;
 125 static int      bce_debug_bootcode_running_failure = 0;
 126
 127 #endif  /* BCE_DEBUG */
 128
 129
 130 /****************************************************************************/
 131 /* PCI Device ID Table                                                      */
 132 /*                                                                          */
 133 /* Used by bce_probe() to identify the devices supported by this driver.    */
 134 /****************************************************************************/
 135 #define BCE_DEVDESC_MAX         64
 136
 137 static struct bce_type bce_devs[] = {
 138         /* BCM5706C Controllers and OEM boards. */
 139         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 140                 "HP NC370T Multifunction Gigabit Server Adapter" },
 141         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 142                 "HP NC370i Multifunction Gigabit Server Adapter" },
 143         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 144                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 145
 146         /* BCM5706S controllers and OEM boards. */
 147         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 148                 "HP NC370F Multifunction Gigabit Server Adapter" },
 149         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 150                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 151
 152         /* BCM5708C controllers and OEM boards. */
 153         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 154                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 155
 156         /* BCM5708S controllers and OEM boards. */
 157         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 158                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 159         { 0, 0, 0, 0, NULL }
 160 };
 161
 162
 163 /****************************************************************************/
 164 /* Supported Flash NVRAM device data.                                       */
 165 /****************************************************************************/
 166 static const struct flash_spec flash_table[] =
 167 {
 168         /* Slow EEPROM */
 169         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 170          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 171          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 172          "EEPROM - slow"},
 173         /* Expansion entry 0001 */
 174         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 175          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 176          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 177          "Entry 0001"},
 178         /* Saifun SA25F010 (non-buffered flash) */
 179         /* strap, cfg1, & write1 need updates */
 180         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 181          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 182          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 183          "Non-buffered flash (128kB)"},
 184         /* Saifun SA25F020 (non-buffered flash) */
 185         /* strap, cfg1, & write1 need updates */
 186         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 187          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 188          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 189          "Non-buffered flash (256kB)"},
 190         /* Expansion entry 0100 */
 191         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 192          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 193          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 194          "Entry 0100"},
 195         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 196         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 197          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 198          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 199          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 200         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 201         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 202          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 203          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 204          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 205         /* Saifun SA25F005 (non-buffered flash) */
 206         /* strap, cfg1, & write1 need updates */
 207         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 208          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 209          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 210          "Non-buffered flash (64kB)"},
 211         /* Fast EEPROM */
 212         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 213          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 214          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 215          "EEPROM - fast"},
 216         /* Expansion entry 1001 */
 217         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 218          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 219          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 220          "Entry 1001"},
 221         /* Expansion entry 1010 */
 222         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 223          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 224          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 225          "Entry 1010"},
 226         /* ATMEL AT45DB011B (buffered flash) */
 227         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 228          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 229          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 230          "Buffered flash (128kB)"},
 231         /* Expansion entry 1100 */
 232         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 233          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 234          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 235          "Entry 1100"},
 236         /* Expansion entry 1101 */
 237         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 238          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 239          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 240          "Entry 1101"},
 241         /* Ateml Expansion entry 1110 */
 242         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 243          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 244          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 245          "Entry 1110 (Atmel)"},
 246         /* ATMEL AT45DB021B (buffered flash) */
 247         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 248          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 249          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 250          "Buffered flash (256kB)"},
 251 };
 252
 253
 254 /****************************************************************************/
 255 /* DragonFly device entry points.                                           */
 256 /****************************************************************************/
 257 static int      bce_probe(device_t);
 258 static int      bce_attach(device_t);
 259 static int      bce_detach(device_t);
 260 static void     bce_shutdown(device_t);
 261
 262 /****************************************************************************/
 263 /* BCE Debug Data Structure Dump Routines                                   */
 264 /****************************************************************************/
 265 #ifdef BCE_DEBUG
 266 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 267 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 268 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 269 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 270 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 271 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 272                                 struct l2_fhdr *) __unused;
 273 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 274 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 275 static void     bce_dump_status_block(struct bce_softc *);
 276 static void     bce_dump_driver_state(struct bce_softc *);
 277 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 278 static void     bce_dump_hw_state(struct bce_softc *);
 279 static void     bce_dump_txp_state(struct bce_softc *);
 280 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 281 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 282 static void     bce_freeze_controller(struct bce_softc *) __unused;
 283 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 284 static void     bce_breakpoint(struct bce_softc *);
 285 #endif  /* BCE_DEBUG */
 286
 287
 288 /****************************************************************************/
 289 /* BCE Register/Memory Access Routines                                      */
 290 /****************************************************************************/
 291 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 292 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 293 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 294 static int      bce_miibus_read_reg(device_t, int, int);
 295 static int      bce_miibus_write_reg(device_t, int, int, int);
 296 static void     bce_miibus_statchg(device_t);
 297
 298
 299 /****************************************************************************/
 300 /* BCE NVRAM Access Routines                                                */
 301 /****************************************************************************/
 302 static int      bce_acquire_nvram_lock(struct bce_softc *);
 303 static int      bce_release_nvram_lock(struct bce_softc *);
 304 static void     bce_enable_nvram_access(struct bce_softc *);
 305 static void     bce_disable_nvram_access(struct bce_softc *);
 306 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 307                                      uint32_t);
 308 static int      bce_init_nvram(struct bce_softc *);
 309 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 310 static int      bce_nvram_test(struct bce_softc *);
 311 #ifdef BCE_NVRAM_WRITE_SUPPORT
 312 static int      bce_enable_nvram_write(struct bce_softc *);
 313 static void     bce_disable_nvram_write(struct bce_softc *);
 314 static int      bce_nvram_erase_page(struct bce_softc *, uint32_t);
 315 static int      bce_nvram_write_dword(struct bce_softc *, uint32_t, uint8_t *,
 316                                       uint32_t);
 317 static int      bce_nvram_write(struct bce_softc *, uint32_t, uint8_t *,
 318                                 int) __unused;
 319 #endif
 320
 321 /****************************************************************************/
 322 /* BCE DMA Allocate/Free Routines                                           */
 323 /****************************************************************************/
 324 static int      bce_dma_alloc(struct bce_softc *);
 325 static void     bce_dma_free(struct bce_softc *);
 326 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 327 static void     bce_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 328                                  bus_size_t, int);
 329
 330 /****************************************************************************/
 331 /* BCE Firmware Synchronization and Load                                    */
 332 /****************************************************************************/
 333 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 334 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 335                                  uint32_t, uint32_t);
 336 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 337                                 struct fw_info *);
 338 static void     bce_init_cpus(struct bce_softc *);
 339
 340 static void     bce_stop(struct bce_softc *);
 341 static int      bce_reset(struct bce_softc *, uint32_t);
 342 static int      bce_chipinit(struct bce_softc *);
 343 static int      bce_blockinit(struct bce_softc *);
 344 static int      bce_newbuf_std(struct bce_softc *, struct mbuf *,
 345                                uint16_t *, uint16_t *, uint32_t *);
 346
 347 static int      bce_init_tx_chain(struct bce_softc *);
 348 static int      bce_init_rx_chain(struct bce_softc *);
 349 static void     bce_free_rx_chain(struct bce_softc *);
 350 static void     bce_free_tx_chain(struct bce_softc *);
 351
 352 static int      bce_encap(struct bce_softc *, struct mbuf **);
 353 static void     bce_start(struct ifnet *);
 354 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 355 static void     bce_watchdog(struct ifnet *);
 356 static int      bce_ifmedia_upd(struct ifnet *);
 357 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 358 static void     bce_init(void *);
 359 static void     bce_mgmt_init(struct bce_softc *);
 360
 361 static void     bce_init_ctx(struct bce_softc *);
 362 static void     bce_get_mac_addr(struct bce_softc *);
 363 static void     bce_set_mac_addr(struct bce_softc *);
 364 static void     bce_phy_intr(struct bce_softc *);
 365 static void     bce_rx_intr(struct bce_softc *, int);
 366 static void     bce_tx_intr(struct bce_softc *);
 367 static void     bce_disable_intr(struct bce_softc *);
 368 static void     bce_enable_intr(struct bce_softc *);
 369
 370 #ifdef DEVICE_POLLING
 371 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 372 #endif
 373 static void     bce_intr(void *);
 374 static void     bce_set_rx_mode(struct bce_softc *);
 375 static void     bce_stats_update(struct bce_softc *);
 376 static void     bce_tick(void *);
 377 static void     bce_tick_serialized(struct bce_softc *);
 378 static void     bce_add_sysctls(struct bce_softc *);
 379
 380 static void     bce_coal_change(struct bce_softc *);
 381 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 382 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 383 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 384 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 385 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 386 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 387 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 388 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 389 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 390                                        uint32_t *, uint32_t);
 391
 392 /*
 393  * NOTE:
 394  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 395  * takes 1023 as the TX ticks limit.  However, using 1023 will
 396  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 397  * there is _no_ network activity on the NIC.
 398  */
 399 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 400 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 401 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 402 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 403 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 404 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 405 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
 406 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
 407
 408 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 409 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 410 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 411 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 412 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 413 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 414 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 415 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 416
 417 /****************************************************************************/
 418 /* DragonFly device dispatch table.                                         */
 419 /****************************************************************************/
 420 static device_method_t bce_methods[] = {
 421         /* Device interface */
 422         DEVMETHOD(device_probe,         bce_probe),
 423         DEVMETHOD(device_attach,        bce_attach),
 424         DEVMETHOD(device_detach,        bce_detach),
 425         DEVMETHOD(device_shutdown,      bce_shutdown),
 426
 427         /* bus interface */
 428         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 429         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 430
 431         /* MII interface */
 432         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 433         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 434         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 435
 436         { 0, 0 }
 437 };
 438
 439 static driver_t bce_driver = {
 440         "bce",
 441         bce_methods,
 442         sizeof(struct bce_softc)
 443 };
 444
 445 static devclass_t bce_devclass;
 446
 447
 448 DECLARE_DUMMY_MODULE(if_xl);
 449 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 450 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, 0, 0);
 451 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
 452
 453
 454 /****************************************************************************/
 455 /* Device probe function.                                                   */
 456 /*                                                                          */
 457 /* Compares the device to the driver's list of supported devices and        */
 458 /* reports back to the OS whether this is the right driver for the device.  */
 459 /*                                                                          */
 460 /* Returns:                                                                 */
 461 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 462 /****************************************************************************/
 463 static int
 464 bce_probe(device_t dev)
 465 {
 466         struct bce_type *t;
 467         uint16_t vid, did, svid, sdid;
 468
 469         /* Get the data for the device to be probed. */
 470         vid  = pci_get_vendor(dev);
 471         did  = pci_get_device(dev);
 472         svid = pci_get_subvendor(dev);
 473         sdid = pci_get_subdevice(dev);
 474
 475         /* Look through the list of known devices for a match. */
 476         for (t = bce_devs; t->bce_name != NULL; ++t) {
 477                 if (vid == t->bce_vid && did == t->bce_did &&
 478                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 479                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 480                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 481                         char *descbuf;
 482
 483                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 484
 485                         /* Print out the device identity. */
 486                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 487                                   t->bce_name,
 488                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 489
 490                         device_set_desc_copy(dev, descbuf);
 491                         kfree(descbuf, M_TEMP);
 492                         return 0;
 493                 }
 494         }
 495         return ENXIO;
 496 }
 497
 498
 499 /****************************************************************************/
 500 /* Device attach function.                                                  */
 501 /*                                                                          */
 502 /* Allocates device resources, performs secondary chip identification,      */
 503 /* resets and initializes the hardware, and initializes driver instance     */
 504 /* variables.                                                               */
 505 /*                                                                          */
 506 /* Returns:                                                                 */
 507 /*   0 on success, positive value on failure.                               */
 508 /****************************************************************************/
 509 static int
 510 bce_attach(device_t dev)
 511 {
 512         struct bce_softc *sc = device_get_softc(dev);
 513         struct ifnet *ifp = &sc->arpcom.ac_if;
 514         uint32_t val;
 515         int rid, rc = 0;
 516 #ifdef notyet
 517         int count;
 518 #endif
 519
 520         sc->bce_dev = dev;
 521         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 522
 523         pci_enable_busmaster(dev);
 524
 525         /* Allocate PCI memory resources. */
 526         rid = PCIR_BAR(0);
 527         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 528                                                  RF_ACTIVE | PCI_RF_DENSE);
 529         if (sc->bce_res_mem == NULL) {
 530                 device_printf(dev, "PCI memory allocation failed\n");
 531                 return ENXIO;
 532         }
 533         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 534         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 535
 536         /* Allocate PCI IRQ resources. */
 537 #ifdef notyet
 538         count = pci_msi_count(dev);
 539         if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
 540                 rid = 1;
 541                 sc->bce_flags |= BCE_USING_MSI_FLAG;
 542         } else
 543 #endif
 544         rid = 0;
 545         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 546                                                  RF_SHAREABLE | RF_ACTIVE);
 547         if (sc->bce_res_irq == NULL) {
 548                 device_printf(dev, "PCI map interrupt failed\n");
 549                 rc = ENXIO;
 550                 goto fail;
 551         }
 552
 553         /*
 554          * Configure byte swap and enable indirect register access.
 555          * Rely on CPU to do target byte swapping on big endian systems.
 556          * Access to registers outside of PCI configurtion space are not
 557          * valid until this is done.
 558          */
 559         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 560                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 561                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 562
 563         /* Save ASIC revsion info. */
 564         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 565
 566         /* Weed out any non-production controller revisions. */
 567         switch(BCE_CHIP_ID(sc)) {
 568         case BCE_CHIP_ID_5706_A0:
 569         case BCE_CHIP_ID_5706_A1:
 570         case BCE_CHIP_ID_5708_A0:
 571         case BCE_CHIP_ID_5708_B0:
 572                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 573                               BCE_CHIP_ID(sc));
 574                 rc = ENODEV;
 575                 goto fail;
 576         }
 577
 578         /*
 579          * The embedded PCIe to PCI-X bridge (EPB)
 580          * in the 5708 cannot address memory above
 581          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
 582          */
 583         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
 584                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
 585         else
 586                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
 587
 588         /*
 589          * Find the base address for shared memory access.
 590          * Newer versions of bootcode use a signature and offset
 591          * while older versions use a fixed address.
 592          */
 593         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 594         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
 595                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0);
 596         else
 597                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 598
 599         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 600
 601         /* Get PCI bus information (speed and type). */
 602         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 603         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 604                 uint32_t clkreg;
 605
 606                 sc->bce_flags |= BCE_PCIX_FLAG;
 607
 608                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 609                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 610                 switch (clkreg) {
 611                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 612                         sc->bus_speed_mhz = 133;
 613                         break;
 614
 615                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 616                         sc->bus_speed_mhz = 100;
 617                         break;
 618
 619                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 620                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 621                         sc->bus_speed_mhz = 66;
 622                         break;
 623
 624                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 625                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 626                         sc->bus_speed_mhz = 50;
 627                         break;
 628
 629                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 630                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 631                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 632                         sc->bus_speed_mhz = 33;
 633                         break;
 634                 }
 635         } else {
 636                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 637                         sc->bus_speed_mhz = 66;
 638                 else
 639                         sc->bus_speed_mhz = 33;
 640         }
 641
 642         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 643                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 644
 645         device_printf(dev, "ASIC ID 0x%08X; Revision (%c%d); PCI%s %s %dMHz\n",
 646                       sc->bce_chipid,
 647                       ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 648                       (BCE_CHIP_ID(sc) & 0x0ff0) >> 4,
 649                       (sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : "",
 650                       (sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 651                       "32-bit" : "64-bit", sc->bus_speed_mhz);
 652
 653         /* Reset the controller. */
 654         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 655         if (rc != 0)
 656                 goto fail;
 657
 658         /* Initialize the controller. */
 659         rc = bce_chipinit(sc);
 660         if (rc != 0) {
 661                 device_printf(dev, "Controller initialization failed!\n");
 662                 goto fail;
 663         }
 664
 665         /* Perform NVRAM test. */
 666         rc = bce_nvram_test(sc);
 667         if (rc != 0) {
 668                 device_printf(dev, "NVRAM test failed!\n");
 669                 goto fail;
 670         }
 671
 672         /* Fetch the permanent Ethernet MAC address. */
 673         bce_get_mac_addr(sc);
 674
 675         /*
 676          * Trip points control how many BDs
 677          * should be ready before generating an
 678          * interrupt while ticks control how long
 679          * a BD can sit in the chain before
 680          * generating an interrupt.  Set the default
 681          * values for the RX and TX rings.
 682          */
 683
 684 #ifdef BCE_DRBUG
 685         /* Force more frequent interrupts. */
 686         sc->bce_tx_quick_cons_trip_int = 1;
 687         sc->bce_tx_quick_cons_trip     = 1;
 688         sc->bce_tx_ticks_int           = 0;
 689         sc->bce_tx_ticks               = 0;
 690
 691         sc->bce_rx_quick_cons_trip_int = 1;
 692         sc->bce_rx_quick_cons_trip     = 1;
 693         sc->bce_rx_ticks_int           = 0;
 694         sc->bce_rx_ticks               = 0;
 695 #else
 696         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 697         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 698         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 699         sc->bce_tx_ticks               = bce_tx_ticks;
 700
 701         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 702         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 703         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 704         sc->bce_rx_ticks               = bce_rx_ticks;
 705 #endif
 706
 707         /* Update statistics once every second. */
 708         sc->bce_stats_ticks = 1000000 & 0xffff00;
 709
 710         /*
 711          * The copper based NetXtreme II controllers
 712          * use an integrated PHY at address 1 while
 713          * the SerDes controllers use a PHY at
 714          * address 2.
 715          */
 716         sc->bce_phy_addr = 1;
 717
 718         if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
 719                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
 720                 sc->bce_flags |= BCE_NO_WOL_FLAG;
 721                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) {
 722                         sc->bce_phy_addr = 2;
 723                         val = REG_RD_IND(sc, sc->bce_shmem_base +
 724                                          BCE_SHARED_HW_CFG_CONFIG);
 725                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
 726                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
 727                 }
 728         }
 729
 730         /* Allocate DMA memory resources. */
 731         rc = bce_dma_alloc(sc);
 732         if (rc != 0) {
 733                 device_printf(dev, "DMA resource allocation failed!\n");
 734                 goto fail;
 735         }
 736
 737         /* Initialize the ifnet interface. */
 738         ifp->if_softc = sc;
 739         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 740         ifp->if_ioctl = bce_ioctl;
 741         ifp->if_start = bce_start;
 742         ifp->if_init = bce_init;
 743         ifp->if_watchdog = bce_watchdog;
 744 #ifdef DEVICE_POLLING
 745         ifp->if_poll = bce_poll;
 746 #endif
 747         ifp->if_mtu = ETHERMTU;
 748         ifp->if_hwassist = BCE_IF_HWASSIST;
 749         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 750         ifp->if_capenable = ifp->if_capabilities;
 751         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 752         ifq_set_ready(&ifp->if_snd);
 753
 754         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 755                 ifp->if_baudrate = IF_Gbps(2.5);
 756         else
 757                 ifp->if_baudrate = IF_Gbps(1);
 758
 759         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 760         sc->mbuf_alloc_size  = MCLBYTES;
 761
 762         /* Look for our PHY. */
 763         rc = mii_phy_probe(dev, &sc->bce_miibus,
 764                            bce_ifmedia_upd, bce_ifmedia_sts);
 765         if (rc != 0) {
 766                 device_printf(dev, "PHY probe failed!\n");
 767                 goto fail;
 768         }
 769
 770         /* Attach to the Ethernet interface list. */
 771         ether_ifattach(ifp, sc->eaddr, NULL);
 772
 773         callout_init(&sc->bce_stat_ch);
 774
 775         /* Hookup IRQ last. */
 776         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
 777                             &sc->bce_intrhand, ifp->if_serializer);
 778         if (rc != 0) {
 779                 device_printf(dev, "Failed to setup IRQ!\n");
 780                 ether_ifdetach(ifp);
 781                 goto fail;
 782         }
 783
 784         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
 785         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 786
 787         /* Print some important debugging info. */
 788         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 789
 790         /* Add the supported sysctls to the kernel. */
 791         bce_add_sysctls(sc);
 792
 793         /* Get the firmware running so IPMI still works */
 794         bce_mgmt_init(sc);
 795
 796         return 0;
 797 fail:
 798         bce_detach(dev);
 799         return(rc);
 800 }
 801
 802
 803 /****************************************************************************/
 804 /* Device detach function.                                                  */
 805 /*                                                                          */
 806 /* Stops the controller, resets the controller, and releases resources.     */
 807 /*                                                                          */
 808 /* Returns:                                                                 */
 809 /*   0 on success, positive value on failure.                               */
 810 /****************************************************************************/
 811 static int
 812 bce_detach(device_t dev)
 813 {
 814         struct bce_softc *sc = device_get_softc(dev);
 815
 816         if (device_is_attached(dev)) {
 817                 struct ifnet *ifp = &sc->arpcom.ac_if;
 818
 819                 /* Stop and reset the controller. */
 820                 lwkt_serialize_enter(ifp->if_serializer);
 821                 bce_stop(sc);
 822                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 823                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
 824                 lwkt_serialize_exit(ifp->if_serializer);
 825
 826                 ether_ifdetach(ifp);
 827         }
 828
 829         /* If we have a child device on the MII bus remove it too. */
 830         if (sc->bce_miibus)
 831                 device_delete_child(dev, sc->bce_miibus);
 832         bus_generic_detach(dev);
 833
 834         if (sc->bce_res_irq != NULL) {
 835                 bus_release_resource(dev, SYS_RES_IRQ,
 836                         sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
 837                         sc->bce_res_irq);
 838         }
 839
 840 #ifdef notyet
 841         if (sc->bce_flags & BCE_USING_MSI_FLAG)
 842                 pci_release_msi(dev);
 843 #endif
 844
 845         if (sc->bce_res_mem != NULL) {
 846                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
 847                                      sc->bce_res_mem);
 848         }
 849
 850         bce_dma_free(sc);
 851
 852         if (sc->bce_sysctl_tree != NULL)
 853                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
 854
 855         return 0;
 856 }
 857
 858
 859 /****************************************************************************/
 860 /* Device shutdown function.                                                */
 861 /*                                                                          */
 862 /* Stops and resets the controller.                                         */
 863 /*                                                                          */
 864 /* Returns:                                                                 */
 865 /*   Nothing                                                                */
 866 /****************************************************************************/
 867 static void
 868 bce_shutdown(device_t dev)
 869 {
 870         struct bce_softc *sc = device_get_softc(dev);
 871         struct ifnet *ifp = &sc->arpcom.ac_if;
 872
 873         lwkt_serialize_enter(ifp->if_serializer);
 874         bce_stop(sc);
 875         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 876         lwkt_serialize_exit(ifp->if_serializer);
 877 }
 878
 879
 880 /****************************************************************************/
 881 /* Indirect register read.                                                  */
 882 /*                                                                          */
 883 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
 884 /* configuration space.  Using this mechanism avoids issues with posted     */
 885 /* reads but is much slower than memory-mapped I/O.                         */
 886 /*                                                                          */
 887 /* Returns:                                                                 */
 888 /*   The value of the register.                                             */
 889 /****************************************************************************/
 890 static uint32_t
 891 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
 892 {
 893         device_t dev = sc->bce_dev;
 894
 895         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
 896 #ifdef BCE_DEBUG
 897         {
 898                 uint32_t val;
 899                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
 900                 DBPRINT(sc, BCE_EXCESSIVE,
 901                         "%s(); offset = 0x%08X, val = 0x%08X\n",
 902                         __func__, offset, val);
 903                 return val;
 904         }
 905 #else
 906         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
 907 #endif
 908 }
 909
 910
 911 /****************************************************************************/
 912 /* Indirect register write.                                                 */
 913 /*                                                                          */
 914 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
 915 /* configuration space.  Using this mechanism avoids issues with posted     */
 916 /* writes but is muchh slower than memory-mapped I/O.                       */
 917 /*                                                                          */
 918 /* Returns:                                                                 */
 919 /*   Nothing.                                                               */
 920 /****************************************************************************/
 921 static void
 922 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
 923 {
 924         device_t dev = sc->bce_dev;
 925
 926         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
 927                 __func__, offset, val);
 928
 929         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
 930         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
 931 }
 932
 933
 934 /****************************************************************************/
 935 /* Context memory write.                                                    */
 936 /*                                                                          */
 937 /* The NetXtreme II controller uses context memory to track connection      */
 938 /* information for L2 and higher network protocols.                         */
 939 /*                                                                          */
 940 /* Returns:                                                                 */
 941 /*   Nothing.                                                               */
 942 /****************************************************************************/
 943 static void
 944 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t offset,
 945            uint32_t val)
 946 {
 947         DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
 948                 "val = 0x%08X\n", __func__, cid_addr, offset, val);
 949
 950         offset += cid_addr;
 951         REG_WR(sc, BCE_CTX_DATA_ADR, offset);
 952         REG_WR(sc, BCE_CTX_DATA, val);
 953 }
 954
 955
 956 /****************************************************************************/
 957 /* PHY register read.                                                       */
 958 /*                                                                          */
 959 /* Implements register reads on the MII bus.                                */
 960 /*                                                                          */
 961 /* Returns:                                                                 */
 962 /*   The value of the register.                                             */
 963 /****************************************************************************/
 964 static int
 965 bce_miibus_read_reg(device_t dev, int phy, int reg)
 966 {
 967         struct bce_softc *sc = device_get_softc(dev);
 968         uint32_t val;
 969         int i;
 970
 971         /* Make sure we are accessing the correct PHY address. */
 972         if (phy != sc->bce_phy_addr) {
 973                 DBPRINT(sc, BCE_VERBOSE,
 974                         "Invalid PHY address %d for PHY read!\n", phy);
 975                 return 0;
 976         }
 977
 978         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
 979                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
 980                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
 981
 982                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
 983                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
 984
 985                 DELAY(40);
 986         }
 987
 988         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
 989               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
 990               BCE_EMAC_MDIO_COMM_START_BUSY;
 991         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
 992
 993         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
 994                 DELAY(10);
 995
 996                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
 997                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
 998                         DELAY(5);
 999
1000                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1001                         val &= BCE_EMAC_MDIO_COMM_DATA;
1002                         break;
1003                 }
1004         }
1005
1006         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1007                 if_printf(&sc->arpcom.ac_if,
1008                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1009                           phy, reg);
1010                 val = 0x0;
1011         } else {
1012                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1013         }
1014
1015         DBPRINT(sc, BCE_EXCESSIVE,
1016                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1017                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1018
1019         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1020                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1021                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1022
1023                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1024                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1025
1026                 DELAY(40);
1027         }
1028         return (val & 0xffff);
1029 }
1030
1031
1032 /****************************************************************************/
1033 /* PHY register write.                                                      */
1034 /*                                                                          */
1035 /* Implements register writes on the MII bus.                               */
1036 /*                                                                          */
1037 /* Returns:                                                                 */
1038 /*   The value of the register.                                             */
1039 /****************************************************************************/
1040 static int
1041 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1042 {
1043         struct bce_softc *sc = device_get_softc(dev);
1044         uint32_t val1;
1045         int i;
1046
1047         /* Make sure we are accessing the correct PHY address. */
1048         if (phy != sc->bce_phy_addr) {
1049                 DBPRINT(sc, BCE_WARN,
1050                         "Invalid PHY address %d for PHY write!\n", phy);
1051                 return(0);
1052         }
1053
1054         DBPRINT(sc, BCE_EXCESSIVE,
1055                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1056                 __func__, phy, (uint16_t)(reg & 0xffff),
1057                 (uint16_t)(val & 0xffff));
1058
1059         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1060                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1061                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1062
1063                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1064                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1065
1066                 DELAY(40);
1067         }
1068
1069         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1070                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1071                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1072         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1073
1074         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1075                 DELAY(10);
1076
1077                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1078                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1079                         DELAY(5);
1080                         break;
1081                 }
1082         }
1083
1084         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1085                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1086
1087         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1088                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1089                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1090
1091                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1092                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1093
1094                 DELAY(40);
1095         }
1096         return 0;
1097 }
1098
1099
1100 /****************************************************************************/
1101 /* MII bus status change.                                                   */
1102 /*                                                                          */
1103 /* Called by the MII bus driver when the PHY establishes link to set the    */
1104 /* MAC interface registers.                                                 */
1105 /*                                                                          */
1106 /* Returns:                                                                 */
1107 /*   Nothing.                                                               */
1108 /****************************************************************************/
1109 static void
1110 bce_miibus_statchg(device_t dev)
1111 {
1112         struct bce_softc *sc = device_get_softc(dev);
1113         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1114
1115         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1116                 mii->mii_media_active);
1117
1118 #ifdef BCE_DEBUG
1119         /* Decode the interface media flags. */
1120         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1121         switch(IFM_TYPE(mii->mii_media_active)) {
1122         case IFM_ETHER:
1123                 kprintf("Ethernet )");
1124                 break;
1125         default:
1126                 kprintf("Unknown )");
1127                 break;
1128         }
1129
1130         kprintf(" Media Options: ( ");
1131         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1132         case IFM_AUTO:
1133                 kprintf("Autoselect )");
1134                 break;
1135         case IFM_MANUAL:
1136                 kprintf("Manual )");
1137                 break;
1138         case IFM_NONE:
1139                 kprintf("None )");
1140                 break;
1141         case IFM_10_T:
1142                 kprintf("10Base-T )");
1143                 break;
1144         case IFM_100_TX:
1145                 kprintf("100Base-TX )");
1146                 break;
1147         case IFM_1000_SX:
1148                 kprintf("1000Base-SX )");
1149                 break;
1150         case IFM_1000_T:
1151                 kprintf("1000Base-T )");
1152                 break;
1153         default:
1154                 kprintf("Other )");
1155                 break;
1156         }
1157
1158         kprintf(" Global Options: (");
1159         if (mii->mii_media_active & IFM_FDX)
1160                 kprintf(" FullDuplex");
1161         if (mii->mii_media_active & IFM_HDX)
1162                 kprintf(" HalfDuplex");
1163         if (mii->mii_media_active & IFM_LOOP)
1164                 kprintf(" Loopback");
1165         if (mii->mii_media_active & IFM_FLAG0)
1166                 kprintf(" Flag0");
1167         if (mii->mii_media_active & IFM_FLAG1)
1168                 kprintf(" Flag1");
1169         if (mii->mii_media_active & IFM_FLAG2)
1170                 kprintf(" Flag2");
1171         kprintf(" )\n");
1172 #endif
1173
1174         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1175
1176         /*
1177          * Set MII or GMII interface based on the speed negotiated
1178          * by the PHY.
1179          */
1180         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1181             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1182                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1183                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1184         } else {
1185                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1186                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1187         }
1188
1189         /*
1190          * Set half or full duplex based on the duplicity negotiated
1191          * by the PHY.
1192          */
1193         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1194                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1195                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1196         } else {
1197                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1198                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1199         }
1200 }
1201
1202
1203 /****************************************************************************/
1204 /* Acquire NVRAM lock.                                                      */
1205 /*                                                                          */
1206 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1207 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1208 /* for use by the driver.                                                   */
1209 /*                                                                          */
1210 /* Returns:                                                                 */
1211 /*   0 on success, positive value on failure.                               */
1212 /****************************************************************************/
1213 static int
1214 bce_acquire_nvram_lock(struct bce_softc *sc)
1215 {
1216         uint32_t val;
1217         int j;
1218
1219         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1220
1221         /* Request access to the flash interface. */
1222         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1223         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1224                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1225                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1226                         break;
1227
1228                 DELAY(5);
1229         }
1230
1231         if (j >= NVRAM_TIMEOUT_COUNT) {
1232                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1233                 return EBUSY;
1234         }
1235         return 0;
1236 }
1237
1238
1239 /****************************************************************************/
1240 /* Release NVRAM lock.                                                      */
1241 /*                                                                          */
1242 /* When the caller is finished accessing NVRAM the lock must be released.   */
1243 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1244 /* for use by the driver.                                                   */
1245 /*                                                                          */
1246 /* Returns:                                                                 */
1247 /*   0 on success, positive value on failure.                               */
1248 /****************************************************************************/
1249 static int
1250 bce_release_nvram_lock(struct bce_softc *sc)
1251 {
1252         int j;
1253         uint32_t val;
1254
1255         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1256
1257         /*
1258          * Relinquish nvram interface.
1259          */
1260         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1261
1262         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1263                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1264                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1265                         break;
1266
1267                 DELAY(5);
1268         }
1269
1270         if (j >= NVRAM_TIMEOUT_COUNT) {
1271                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1272                 return EBUSY;
1273         }
1274         return 0;
1275 }
1276
1277
1278 #ifdef BCE_NVRAM_WRITE_SUPPORT
1279 /****************************************************************************/
1280 /* Enable NVRAM write access.                                               */
1281 /*                                                                          */
1282 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
1283 /*                                                                          */
1284 /* Returns:                                                                 */
1285 /*   0 on success, positive value on failure.                               */
1286 /****************************************************************************/
1287 static int
1288 bce_enable_nvram_write(struct bce_softc *sc)
1289 {
1290         uint32_t val;
1291
1292         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM write.\n");
1293
1294         val = REG_RD(sc, BCE_MISC_CFG);
1295         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1296
1297         if (!sc->bce_flash_info->buffered) {
1298                 int j;
1299
1300                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1301                 REG_WR(sc, BCE_NVM_COMMAND,
1302                        BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1303
1304                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1305                         DELAY(5);
1306
1307                         val = REG_RD(sc, BCE_NVM_COMMAND);
1308                         if (val & BCE_NVM_COMMAND_DONE)
1309                                 break;
1310                 }
1311
1312                 if (j >= NVRAM_TIMEOUT_COUNT) {
1313                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1314                         return EBUSY;
1315                 }
1316         }
1317         return 0;
1318 }
1319
1320
1321 /****************************************************************************/
1322 /* Disable NVRAM write access.                                              */
1323 /*                                                                          */
1324 /* When the caller is finished writing to NVRAM write access must be        */
1325 /* disabled.                                                                */
1326 /*                                                                          */
1327 /* Returns:                                                                 */
1328 /*   Nothing.                                                               */
1329 /****************************************************************************/
1330 static void
1331 bce_disable_nvram_write(struct bce_softc *sc)
1332 {
1333         uint32_t val;
1334
1335         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM write.\n");
1336
1337         val = REG_RD(sc, BCE_MISC_CFG);
1338         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1339 }
1340 #endif  /* BCE_NVRAM_WRITE_SUPPORT */
1341
1342
1343 /****************************************************************************/
1344 /* Enable NVRAM access.                                                     */
1345 /*                                                                          */
1346 /* Before accessing NVRAM for read or write operations the caller must      */
1347 /* enabled NVRAM access.                                                    */
1348 /*                                                                          */
1349 /* Returns:                                                                 */
1350 /*   Nothing.                                                               */
1351 /****************************************************************************/
1352 static void
1353 bce_enable_nvram_access(struct bce_softc *sc)
1354 {
1355         uint32_t val;
1356
1357         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1358
1359         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1360         /* Enable both bits, even on read. */
1361         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1362                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1363 }
1364
1365
1366 /****************************************************************************/
1367 /* Disable NVRAM access.                                                    */
1368 /*                                                                          */
1369 /* When the caller is finished accessing NVRAM access must be disabled.     */
1370 /*                                                                          */
1371 /* Returns:                                                                 */
1372 /*   Nothing.                                                               */
1373 /****************************************************************************/
1374 static void
1375 bce_disable_nvram_access(struct bce_softc *sc)
1376 {
1377         uint32_t val;
1378
1379         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1380
1381         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1382
1383         /* Disable both bits, even after read. */
1384         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1385                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1386 }
1387
1388
1389 #ifdef BCE_NVRAM_WRITE_SUPPORT
1390 /****************************************************************************/
1391 /* Erase NVRAM page before writing.                                         */
1392 /*                                                                          */
1393 /* Non-buffered flash parts require that a page be erased before it is      */
1394 /* written.                                                                 */
1395 /*                                                                          */
1396 /* Returns:                                                                 */
1397 /*   0 on success, positive value on failure.                               */
1398 /****************************************************************************/
1399 static int
1400 bce_nvram_erase_page(struct bce_softc *sc, uint32_t offset)
1401 {
1402         uint32_t cmd;
1403         int j;
1404
1405         /* Buffered flash doesn't require an erase. */
1406         if (sc->bce_flash_info->buffered)
1407                 return 0;
1408
1409         DBPRINT(sc, BCE_VERBOSE, "Erasing NVRAM page.\n");
1410
1411         /* Build an erase command. */
1412         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
1413               BCE_NVM_COMMAND_DOIT;
1414
1415         /*
1416          * Clear the DONE bit separately, set the NVRAM adress to erase,
1417          * and issue the erase command.
1418          */
1419         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1420         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1421         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1422
1423         /* Wait for completion. */
1424         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1425                 uint32_t val;
1426
1427                 DELAY(5);
1428
1429                 val = REG_RD(sc, BCE_NVM_COMMAND);
1430                 if (val & BCE_NVM_COMMAND_DONE)
1431                         break;
1432         }
1433
1434         if (j >= NVRAM_TIMEOUT_COUNT) {
1435                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
1436                 return EBUSY;
1437         }
1438         return 0;
1439 }
1440 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1441
1442
1443 /****************************************************************************/
1444 /* Read a dword (32 bits) from NVRAM.                                       */
1445 /*                                                                          */
1446 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1447 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1448 /*                                                                          */
1449 /* Returns:                                                                 */
1450 /*   0 on success and the 32 bit value read, positive value on failure.     */
1451 /****************************************************************************/
1452 static int
1453 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1454                      uint32_t cmd_flags)
1455 {
1456         uint32_t cmd;
1457         int i, rc = 0;
1458
1459         /* Build the command word. */
1460         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1461
1462         /* Calculate the offset for buffered flash. */
1463         if (sc->bce_flash_info->buffered) {
1464                 offset = ((offset / sc->bce_flash_info->page_size) <<
1465                           sc->bce_flash_info->page_bits) +
1466                          (offset % sc->bce_flash_info->page_size);
1467         }
1468
1469         /*
1470          * Clear the DONE bit separately, set the address to read,
1471          * and issue the read.
1472          */
1473         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1474         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1475         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1476
1477         /* Wait for completion. */
1478         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1479                 uint32_t val;
1480
1481                 DELAY(5);
1482
1483                 val = REG_RD(sc, BCE_NVM_COMMAND);
1484                 if (val & BCE_NVM_COMMAND_DONE) {
1485                         val = REG_RD(sc, BCE_NVM_READ);
1486
1487                         val = be32toh(val);
1488                         memcpy(ret_val, &val, 4);
1489                         break;
1490                 }
1491         }
1492
1493         /* Check for errors. */
1494         if (i >= NVRAM_TIMEOUT_COUNT) {
1495                 if_printf(&sc->arpcom.ac_if,
1496                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1497                           offset);
1498                 rc = EBUSY;
1499         }
1500         return rc;
1501 }
1502
1503
1504 #ifdef BCE_NVRAM_WRITE_SUPPORT
1505 /****************************************************************************/
1506 /* Write a dword (32 bits) to NVRAM.                                        */
1507 /*                                                                          */
1508 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
1509 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
1510 /* enabled NVRAM write access.                                              */
1511 /*                                                                          */
1512 /* Returns:                                                                 */
1513 /*   0 on success, positive value on failure.                               */
1514 /****************************************************************************/
1515 static int
1516 bce_nvram_write_dword(struct bce_softc *sc, uint32_t offset, uint8_t *val,
1517                       uint32_t cmd_flags)
1518 {
1519         uint32_t cmd, val32;
1520         int j;
1521
1522         /* Build the command word. */
1523         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
1524
1525         /* Calculate the offset for buffered flash. */
1526         if (sc->bce_flash_info->buffered) {
1527                 offset = ((offset / sc->bce_flash_info->page_size) <<
1528                           sc->bce_flash_info->page_bits) +
1529                          (offset % sc->bce_flash_info->page_size);
1530         }
1531
1532         /*
1533          * Clear the DONE bit separately, convert NVRAM data to big-endian,
1534          * set the NVRAM address to write, and issue the write command
1535          */
1536         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1537         memcpy(&val32, val, 4);
1538         val32 = htobe32(val32);
1539         REG_WR(sc, BCE_NVM_WRITE, val32);
1540         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1541         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1542
1543         /* Wait for completion. */
1544         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1545                 DELAY(5);
1546
1547                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
1548                         break;
1549         }
1550         if (j >= NVRAM_TIMEOUT_COUNT) {
1551                 if_printf(&sc->arpcom.ac_if,
1552                           "Timeout error writing NVRAM at offset 0x%08X\n",
1553                           offset);
1554                 return EBUSY;
1555         }
1556         return 0;
1557 }
1558 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1559
1560
1561 /****************************************************************************/
1562 /* Initialize NVRAM access.                                                 */
1563 /*                                                                          */
1564 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1565 /* access that device.                                                      */
1566 /*                                                                          */
1567 /* Returns:                                                                 */
1568 /*   0 on success, positive value on failure.                               */
1569 /****************************************************************************/
1570 static int
1571 bce_init_nvram(struct bce_softc *sc)
1572 {
1573         uint32_t val;
1574         int j, entry_count, rc = 0;
1575         const struct flash_spec *flash;
1576
1577         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1578
1579         /* Determine the selected interface. */
1580         val = REG_RD(sc, BCE_NVM_CFG1);
1581
1582         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1583
1584         /*
1585          * Flash reconfiguration is required to support additional
1586          * NVRAM devices not directly supported in hardware.
1587          * Check if the flash interface was reconfigured
1588          * by the bootcode.
1589          */
1590
1591         if (val & 0x40000000) {
1592                 /* Flash interface reconfigured by bootcode. */
1593
1594                 DBPRINT(sc, BCE_INFO_LOAD,
1595                         "%s(): Flash WAS reconfigured.\n", __func__);
1596
1597                 for (j = 0, flash = flash_table; j < entry_count;
1598                      j++, flash++) {
1599                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1600                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1601                                 sc->bce_flash_info = flash;
1602                                 break;
1603                         }
1604                 }
1605         } else {
1606                 /* Flash interface not yet reconfigured. */
1607                 uint32_t mask;
1608
1609                 DBPRINT(sc, BCE_INFO_LOAD,
1610                         "%s(): Flash was NOT reconfigured.\n", __func__);
1611
1612                 if (val & (1 << 23))
1613                         mask = FLASH_BACKUP_STRAP_MASK;
1614                 else
1615                         mask = FLASH_STRAP_MASK;
1616
1617                 /* Look for the matching NVRAM device configuration data. */
1618                 for (j = 0, flash = flash_table; j < entry_count;
1619                      j++, flash++) {
1620                         /* Check if the device matches any of the known devices. */
1621                         if ((val & mask) == (flash->strapping & mask)) {
1622                                 /* Found a device match. */
1623                                 sc->bce_flash_info = flash;
1624
1625                                 /* Request access to the flash interface. */
1626                                 rc = bce_acquire_nvram_lock(sc);
1627                                 if (rc != 0)
1628                                         return rc;
1629
1630                                 /* Reconfigure the flash interface. */
1631                                 bce_enable_nvram_access(sc);
1632                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1633                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1634                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1635                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1636                                 bce_disable_nvram_access(sc);
1637                                 bce_release_nvram_lock(sc);
1638                                 break;
1639                         }
1640                 }
1641         }
1642
1643         /* Check if a matching device was found. */
1644         if (j == entry_count) {
1645                 sc->bce_flash_info = NULL;
1646                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1647                 rc = ENODEV;
1648         }
1649
1650         /* Write the flash config data to the shared memory interface. */
1651         val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) &
1652               BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1653         if (val)
1654                 sc->bce_flash_size = val;
1655         else
1656                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1657
1658         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1659                 __func__, sc->bce_flash_info->total_size);
1660
1661         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1662
1663         return rc;
1664 }
1665
1666
1667 /****************************************************************************/
1668 /* Read an arbitrary range of data from NVRAM.                              */
1669 /*                                                                          */
1670 /* Prepares the NVRAM interface for access and reads the requested data     */
1671 /* into the supplied buffer.                                                */
1672 /*                                                                          */
1673 /* Returns:                                                                 */
1674 /*   0 on success and the data read, positive value on failure.             */
1675 /****************************************************************************/
1676 static int
1677 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1678                int buf_size)
1679 {
1680         uint32_t cmd_flags, offset32, len32, extra;
1681         int rc = 0;
1682
1683         if (buf_size == 0)
1684                 return 0;
1685
1686         /* Request access to the flash interface. */
1687         rc = bce_acquire_nvram_lock(sc);
1688         if (rc != 0)
1689                 return rc;
1690
1691         /* Enable access to flash interface */
1692         bce_enable_nvram_access(sc);
1693
1694         len32 = buf_size;
1695         offset32 = offset;
1696         extra = 0;
1697
1698         cmd_flags = 0;
1699
1700         /* XXX should we release nvram lock if read_dword() fails? */
1701         if (offset32 & 3) {
1702                 uint8_t buf[4];
1703                 uint32_t pre_len;
1704
1705                 offset32 &= ~3;
1706                 pre_len = 4 - (offset & 3);
1707
1708                 if (pre_len >= len32) {
1709                         pre_len = len32;
1710                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1711                 } else {
1712                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1713                 }
1714
1715                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1716                 if (rc)
1717                         return rc;
1718
1719                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1720
1721                 offset32 += 4;
1722                 ret_buf += pre_len;
1723                 len32 -= pre_len;
1724         }
1725
1726         if (len32 & 3) {
1727                 extra = 4 - (len32 & 3);
1728                 len32 = (len32 + 4) & ~3;
1729         }
1730
1731         if (len32 == 4) {
1732                 uint8_t buf[4];
1733
1734                 if (cmd_flags)
1735                         cmd_flags = BCE_NVM_COMMAND_LAST;
1736                 else
1737                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1738                                     BCE_NVM_COMMAND_LAST;
1739
1740                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1741
1742                 memcpy(ret_buf, buf, 4 - extra);
1743         } else if (len32 > 0) {
1744                 uint8_t buf[4];
1745
1746                 /* Read the first word. */
1747                 if (cmd_flags)
1748                         cmd_flags = 0;
1749                 else
1750                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1751
1752                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1753
1754                 /* Advance to the next dword. */
1755                 offset32 += 4;
1756                 ret_buf += 4;
1757                 len32 -= 4;
1758
1759                 while (len32 > 4 && rc == 0) {
1760                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1761
1762                         /* Advance to the next dword. */
1763                         offset32 += 4;
1764                         ret_buf += 4;
1765                         len32 -= 4;
1766                 }
1767
1768                 if (rc)
1769                         return rc;
1770
1771                 cmd_flags = BCE_NVM_COMMAND_LAST;
1772                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1773
1774                 memcpy(ret_buf, buf, 4 - extra);
1775         }
1776
1777         /* Disable access to flash interface and release the lock. */
1778         bce_disable_nvram_access(sc);
1779         bce_release_nvram_lock(sc);
1780
1781         return rc;
1782 }
1783
1784
1785 #ifdef BCE_NVRAM_WRITE_SUPPORT
1786 /****************************************************************************/
1787 /* Write an arbitrary range of data from NVRAM.                             */
1788 /*                                                                          */
1789 /* Prepares the NVRAM interface for write access and writes the requested   */
1790 /* data from the supplied buffer.  The caller is responsible for            */
1791 /* calculating any appropriate CRCs.                                        */
1792 /*                                                                          */
1793 /* Returns:                                                                 */
1794 /*   0 on success, positive value on failure.                               */
1795 /****************************************************************************/
1796 static int
1797 bce_nvram_write(struct bce_softc *sc, uint32_t offset, uint8_t *data_buf,
1798                 int buf_size)
1799 {
1800         uint32_t written, offset32, len32;
1801         uint8_t *buf, start[4], end[4];
1802         int rc = 0;
1803         int align_start, align_end;
1804
1805         buf = data_buf;
1806         offset32 = offset;
1807         len32 = buf_size;
1808         align_end = 0;
1809         align_start = (offset32 & 3);
1810
1811         if (align_start) {
1812                 offset32 &= ~3;
1813                 len32 += align_start;
1814                 rc = bce_nvram_read(sc, offset32, start, 4);
1815                 if (rc)
1816                         return rc;
1817         }
1818
1819         if (len32 & 3) {
1820                 if (len32 > 4 || !align_start) {
1821                         align_end = 4 - (len32 & 3);
1822                         len32 += align_end;
1823                         rc = bce_nvram_read(sc, offset32 + len32 - 4, end, 4);
1824                         if (rc)
1825                                 return rc;
1826                 }
1827         }
1828
1829         if (align_start || align_end) {
1830                 buf = kmalloc(len32, M_DEVBUF, M_NOWAIT);
1831                 if (buf == NULL)
1832                         return ENOMEM;
1833                 if (align_start)
1834                         memcpy(buf, start, 4);
1835                 if (align_end)
1836                         memcpy(buf + len32 - 4, end, 4);
1837                 memcpy(buf + align_start, data_buf, buf_size);
1838         }
1839
1840         written = 0;
1841         while (written < len32 && rc == 0) {
1842                 uint32_t page_start, page_end, data_start, data_end;
1843                 uint32_t addr, cmd_flags;
1844                 int i;
1845                 uint8_t flash_buffer[264];
1846
1847                 /* Find the page_start addr */
1848                 page_start = offset32 + written;
1849                 page_start -= (page_start % sc->bce_flash_info->page_size);
1850                 /* Find the page_end addr */
1851                 page_end = page_start + sc->bce_flash_info->page_size;
1852                 /* Find the data_start addr */
1853                 data_start = (written == 0) ? offset32 : page_start;
1854                 /* Find the data_end addr */
1855                 data_end = (page_end > offset32 + len32) ? (offset32 + len32)
1856                                                          : page_end;
1857
1858                 /* Request access to the flash interface. */
1859                 rc = bce_acquire_nvram_lock(sc);
1860                 if (rc != 0)
1861                         goto nvram_write_end;
1862
1863                 /* Enable access to flash interface */
1864                 bce_enable_nvram_access(sc);
1865
1866                 cmd_flags = BCE_NVM_COMMAND_FIRST;
1867                 if (sc->bce_flash_info->buffered == 0) {
1868                         int j;
1869
1870                         /*
1871                          * Read the whole page into the buffer
1872                          * (non-buffer flash only)
1873                          */
1874                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
1875                                 if (j == (sc->bce_flash_info->page_size - 4))
1876                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
1877
1878                                 rc = bce_nvram_read_dword(sc, page_start + j,
1879                                                           &flash_buffer[j],
1880                                                           cmd_flags);
1881                                 if (rc)
1882                                         goto nvram_write_end;
1883
1884                                 cmd_flags = 0;
1885                         }
1886                 }
1887
1888                 /* Enable writes to flash interface (unlock write-protect) */
1889                 rc = bce_enable_nvram_write(sc);
1890                 if (rc != 0)
1891                         goto nvram_write_end;
1892
1893                 /* Erase the page */
1894                 rc = bce_nvram_erase_page(sc, page_start);
1895                 if (rc != 0)
1896                         goto nvram_write_end;
1897
1898                 /* Re-enable the write again for the actual write */
1899                 bce_enable_nvram_write(sc);
1900
1901                 /* Loop to write back the buffer data from page_start to
1902                  * data_start */
1903                 i = 0;
1904                 if (sc->bce_flash_info->buffered == 0) {
1905                         for (addr = page_start; addr < data_start;
1906                              addr += 4, i += 4) {
1907                                 rc = bce_nvram_write_dword(sc, addr,
1908                                                            &flash_buffer[i],
1909                                                            cmd_flags);
1910                                 if (rc != 0)
1911                                         goto nvram_write_end;
1912
1913                                 cmd_flags = 0;
1914                         }
1915                 }
1916
1917                 /* Loop to write the new data from data_start to data_end */
1918                 for (addr = data_start; addr < data_end; addr += 4, i++) {
1919                         if (addr == page_end - 4 ||
1920                             (sc->bce_flash_info->buffered &&
1921                              addr == data_end - 4))
1922                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
1923
1924                         rc = bce_nvram_write_dword(sc, addr, buf, cmd_flags);
1925                         if (rc != 0)
1926                                 goto nvram_write_end;
1927
1928                         cmd_flags = 0;
1929                         buf += 4;
1930                 }
1931
1932                 /* Loop to write back the buffer data from data_end
1933                  * to page_end */
1934                 if (sc->bce_flash_info->buffered == 0) {
1935                         for (addr = data_end; addr < page_end;
1936                              addr += 4, i += 4) {
1937                                 if (addr == page_end-4)
1938                                         cmd_flags = BCE_NVM_COMMAND_LAST;
1939
1940                                 rc = bce_nvram_write_dword(sc, addr,
1941                                         &flash_buffer[i], cmd_flags);
1942                                 if (rc != 0)
1943                                         goto nvram_write_end;
1944
1945                                 cmd_flags = 0;
1946                         }
1947                 }
1948
1949                 /* Disable writes to flash interface (lock write-protect) */
1950                 bce_disable_nvram_write(sc);
1951
1952                 /* Disable access to flash interface */
1953                 bce_disable_nvram_access(sc);
1954                 bce_release_nvram_lock(sc);
1955
1956                 /* Increment written */
1957                 written += data_end - data_start;
1958         }
1959
1960 nvram_write_end:
1961         if (align_start || align_end)
1962                 kfree(buf, M_DEVBUF);
1963         return rc;
1964 }
1965 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1966
1967
1968 /****************************************************************************/
1969 /* Verifies that NVRAM is accessible and contains valid data.               */
1970 /*                                                                          */
1971 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1972 /* correct.                                                                 */
1973 /*                                                                          */
1974 /* Returns:                                                                 */
1975 /*   0 on success, positive value on failure.                               */
1976 /****************************************************************************/
1977 static int
1978 bce_nvram_test(struct bce_softc *sc)
1979 {
1980         uint32_t buf[BCE_NVRAM_SIZE / 4];
1981         uint32_t magic, csum;
1982         uint8_t *data = (uint8_t *)buf;
1983         int rc = 0;
1984
1985         /*
1986          * Check that the device NVRAM is valid by reading
1987          * the magic value at offset 0.
1988          */
1989         rc = bce_nvram_read(sc, 0, data, 4);
1990         if (rc != 0)
1991                 return rc;
1992
1993         magic = be32toh(buf[0]);
1994         if (magic != BCE_NVRAM_MAGIC) {
1995                 if_printf(&sc->arpcom.ac_if,
1996                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1997                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1998                 return ENODEV;
1999         }
2000
2001         /*
2002          * Verify that the device NVRAM includes valid
2003          * configuration data.
2004          */
2005         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
2006         if (rc != 0)
2007                 return rc;
2008
2009         csum = ether_crc32_le(data, 0x100);
2010         if (csum != BCE_CRC32_RESIDUAL) {
2011                 if_printf(&sc->arpcom.ac_if,
2012                           "Invalid Manufacturing Information NVRAM CRC! "
2013                           "Expected: 0x%08X, Found: 0x%08X\n",
2014                           BCE_CRC32_RESIDUAL, csum);
2015                 return ENODEV;
2016         }
2017
2018         csum = ether_crc32_le(data + 0x100, 0x100);
2019         if (csum != BCE_CRC32_RESIDUAL) {
2020                 if_printf(&sc->arpcom.ac_if,
2021                           "Invalid Feature Configuration Information "
2022                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
2023                           BCE_CRC32_RESIDUAL, csum);
2024                 rc = ENODEV;
2025         }
2026         return rc;
2027 }
2028
2029
2030 /****************************************************************************/
2031 /* Free any DMA memory owned by the driver.                                 */
2032 /*                                                                          */
2033 /* Scans through each data structre that requires DMA memory and frees      */
2034 /* the memory if allocated.                                                 */
2035 /*                                                                          */
2036 /* Returns:                                                                 */
2037 /*   Nothing.                                                               */
2038 /****************************************************************************/
2039 static void
2040 bce_dma_free(struct bce_softc *sc)
2041 {
2042         int i;
2043
2044         /* Destroy the status block. */
2045         if (sc->status_tag != NULL) {
2046                 if (sc->status_block != NULL) {
2047                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2048                         bus_dmamem_free(sc->status_tag, sc->status_block,
2049                                         sc->status_map);
2050                 }
2051                 bus_dma_tag_destroy(sc->status_tag);
2052         }
2053
2054
2055         /* Destroy the statistics block. */
2056         if (sc->stats_tag != NULL) {
2057                 if (sc->stats_block != NULL) {
2058                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2059                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2060                                         sc->stats_map);
2061                 }
2062                 bus_dma_tag_destroy(sc->stats_tag);
2063         }
2064
2065         /* Destroy the TX buffer descriptor DMA stuffs. */
2066         if (sc->tx_bd_chain_tag != NULL) {
2067                 for (i = 0; i < TX_PAGES; i++) {
2068                         if (sc->tx_bd_chain[i] != NULL) {
2069                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2070                                                   sc->tx_bd_chain_map[i]);
2071                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2072                                                 sc->tx_bd_chain[i],
2073                                                 sc->tx_bd_chain_map[i]);
2074                         }
2075                 }
2076                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2077         }
2078
2079         /* Destroy the RX buffer descriptor DMA stuffs. */
2080         if (sc->rx_bd_chain_tag != NULL) {
2081                 for (i = 0; i < RX_PAGES; i++) {
2082                         if (sc->rx_bd_chain[i] != NULL) {
2083                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2084                                                   sc->rx_bd_chain_map[i]);
2085                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2086                                                 sc->rx_bd_chain[i],
2087                                                 sc->rx_bd_chain_map[i]);
2088                         }
2089                 }
2090                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2091         }
2092
2093         /* Destroy the TX mbuf DMA stuffs. */
2094         if (sc->tx_mbuf_tag != NULL) {
2095                 for (i = 0; i < TOTAL_TX_BD; i++) {
2096                         /* Must have been unloaded in bce_stop() */
2097                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2098                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2099                                            sc->tx_mbuf_map[i]);
2100                 }
2101                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2102         }
2103
2104         /* Destroy the RX mbuf DMA stuffs. */
2105         if (sc->rx_mbuf_tag != NULL) {
2106                 for (i = 0; i < TOTAL_RX_BD; i++) {
2107                         /* Must have been unloaded in bce_stop() */
2108                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2109                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2110                                            sc->rx_mbuf_map[i]);
2111                 }
2112                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2113         }
2114
2115         /* Destroy the parent tag */
2116         if (sc->parent_tag != NULL)
2117                 bus_dma_tag_destroy(sc->parent_tag);
2118 }
2119
2120
2121 /****************************************************************************/
2122 /* Get DMA memory from the OS.                                              */
2123 /*                                                                          */
2124 /* Validates that the OS has provided DMA buffers in response to a          */
2125 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2126 /* When the callback is used the OS will return 0 for the mapping function  */
2127 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2128 /* failures back to the caller.                                             */
2129 /*                                                                          */
2130 /* Returns:                                                                 */
2131 /*   Nothing.                                                               */
2132 /****************************************************************************/
2133 static void
2134 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2135 {
2136         bus_addr_t *busaddr = arg;
2137
2138         /*
2139          * Simulate a mapping failure.
2140          * XXX not correct.
2141          */
2142         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2143                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2144                         __FILE__, __LINE__);
2145                 error = ENOMEM);
2146
2147         /* Check for an error and signal the caller that an error occurred. */
2148         if (error)
2149                 return;
2150
2151         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2152         *busaddr = segs->ds_addr;
2153 }
2154
2155
2156 static void
2157 bce_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
2158                  bus_size_t mapsz __unused, int error)
2159 {
2160         struct bce_dmamap_arg *ctx = arg;
2161         int i;
2162
2163         if (error)
2164                 return;
2165
2166         if (nsegs > ctx->bce_maxsegs) {
2167                 ctx->bce_maxsegs = 0;
2168                 return;
2169         }
2170
2171         ctx->bce_maxsegs = nsegs;
2172         for (i = 0; i < nsegs; ++i)
2173                 ctx->bce_segs[i] = segs[i];
2174 }
2175
2176
2177 /****************************************************************************/
2178 /* Allocate any DMA memory needed by the driver.                            */
2179 /*                                                                          */
2180 /* Allocates DMA memory needed for the various global structures needed by  */
2181 /* hardware.                                                                */
2182 /*                                                                          */
2183 /* Returns:                                                                 */
2184 /*   0 for success, positive value for failure.                             */
2185 /****************************************************************************/
2186 static int
2187 bce_dma_alloc(struct bce_softc *sc)
2188 {
2189         struct ifnet *ifp = &sc->arpcom.ac_if;
2190         int i, j, rc = 0;
2191         bus_addr_t busaddr;
2192
2193         /*
2194          * Allocate the parent bus DMA tag appropriate for PCI.
2195          */
2196         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2197                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2198                                 NULL, NULL,
2199                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2200                                 BUS_SPACE_MAXSIZE_32BIT,
2201                                 0, &sc->parent_tag);
2202         if (rc != 0) {
2203                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2204                 return rc;
2205         }
2206
2207         /*
2208          * Create a DMA tag for the status block, allocate and clear the
2209          * memory, map the memory into DMA space, and fetch the physical
2210          * address of the block.
2211          */
2212         rc = bus_dma_tag_create(sc->parent_tag,
2213                                 BCE_DMA_ALIGN, BCE_DMA_BOUNDARY,
2214                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2215                                 NULL, NULL,
2216                                 BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
2217                                 0, &sc->status_tag);
2218         if (rc != 0) {
2219                 if_printf(ifp, "Could not allocate status block DMA tag!\n");
2220                 return rc;
2221         }
2222
2223         rc = bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
2224                               BUS_DMA_WAITOK | BUS_DMA_ZERO,
2225                               &sc->status_map);
2226         if (rc != 0) {
2227                 if_printf(ifp, "Could not allocate status block DMA memory!\n");
2228                 return rc;
2229         }
2230
2231         rc = bus_dmamap_load(sc->status_tag, sc->status_map,
2232                              sc->status_block, BCE_STATUS_BLK_SZ,
2233                              bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK);
2234         if (rc != 0) {
2235                 if_printf(ifp, "Could not map status block DMA memory!\n");
2236                 bus_dmamem_free(sc->status_tag, sc->status_block,
2237                                 sc->status_map);
2238                 sc->status_block = NULL;
2239                 return rc;
2240         }
2241
2242         sc->status_block_paddr = busaddr;
2243         /* DRC - Fix for 64 bit addresses. */
2244         DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n",
2245                 (uint32_t)sc->status_block_paddr);
2246
2247         /*
2248          * Create a DMA tag for the statistics block, allocate and clear the
2249          * memory, map the memory into DMA space, and fetch the physical
2250          * address of the block.
2251          */
2252         rc = bus_dma_tag_create(sc->parent_tag,
2253                                 BCE_DMA_ALIGN, BCE_DMA_BOUNDARY,
2254                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2255                                 NULL, NULL,
2256                                 BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
2257                                 0, &sc->stats_tag);
2258         if (rc != 0) {
2259                 if_printf(ifp, "Could not allocate "
2260                           "statistics block DMA tag!\n");
2261                 return rc;
2262         }
2263
2264         rc = bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
2265                               BUS_DMA_WAITOK | BUS_DMA_ZERO,
2266                               &sc->stats_map);
2267         if (rc != 0) {
2268                 if_printf(ifp, "Could not allocate "
2269                           "statistics block DMA memory!\n");
2270                 return rc;
2271         }
2272
2273         rc = bus_dmamap_load(sc->stats_tag, sc->stats_map,
2274                              sc->stats_block, BCE_STATS_BLK_SZ,
2275                              bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK);
2276         if (rc != 0) {
2277                 if_printf(ifp, "Could not map statistics block DMA memory!\n");
2278                 bus_dmamem_free(sc->stats_tag, sc->stats_block, sc->stats_map);
2279                 sc->stats_block = NULL;
2280                 return rc;
2281         }
2282
2283         sc->stats_block_paddr = busaddr;
2284         /* DRC - Fix for 64 bit address. */
2285         DBPRINT(sc, BCE_INFO, "stats_block_paddr = 0x%08X\n",
2286                 (uint32_t)sc->stats_block_paddr);
2287
2288         /*
2289          * Create a DMA tag for the TX buffer descriptor chain,
2290          * allocate and clear the  memory, and fetch the
2291          * physical address of the block.
2292          */
2293         rc = bus_dma_tag_create(sc->parent_tag,
2294                                 BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
2295                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2296                                 NULL, NULL,
2297                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2298                                 0, &sc->tx_bd_chain_tag);
2299         if (rc != 0) {
2300                 if_printf(ifp, "Could not allocate "
2301                           "TX descriptor chain DMA tag!\n");
2302                 return rc;
2303         }
2304
2305         for (i = 0; i < TX_PAGES; i++) {
2306                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2307                                       (void **)&sc->tx_bd_chain[i],
2308                                       BUS_DMA_WAITOK, &sc->tx_bd_chain_map[i]);
2309                 if (rc != 0) {
2310                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2311                                   "chain DMA memory!\n", i);
2312                         return rc;
2313                 }
2314
2315                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2316                                      sc->tx_bd_chain_map[i],
2317                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2318                                      bce_dma_map_addr, &busaddr,
2319                                      BUS_DMA_WAITOK);
2320                 if (rc != 0) {
2321                         if_printf(ifp, "Could not map %dth TX descriptor "
2322                                   "chain DMA memory!\n", i);
2323                         bus_dmamem_free(sc->tx_bd_chain_tag,
2324                                         sc->tx_bd_chain[i],
2325                                         sc->tx_bd_chain_map[i]);
2326                         sc->tx_bd_chain[i] = NULL;
2327                         return rc;
2328                 }
2329
2330                 sc->tx_bd_chain_paddr[i] = busaddr;
2331                 /* DRC - Fix for 64 bit systems. */
2332                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2333                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2334         }
2335
2336         /* Create a DMA tag for TX mbufs. */
2337         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2338                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2339                                 NULL, NULL,
2340                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2341                                 BCE_MAX_SEGMENTS, MCLBYTES,
2342                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2343                                 BUS_DMA_ONEBPAGE,
2344                                 &sc->tx_mbuf_tag);
2345         if (rc != 0) {
2346                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2347                 return rc;
2348         }
2349
2350         /* Create DMA maps for the TX mbufs clusters. */
2351         for (i = 0; i < TOTAL_TX_BD; i++) {
2352                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2353                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2354                                        &sc->tx_mbuf_map[i]);
2355                 if (rc != 0) {
2356                         for (j = 0; j < i; ++j) {
2357                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2358                                                    sc->tx_mbuf_map[i]);
2359                         }
2360                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2361                         sc->tx_mbuf_tag = NULL;
2362
2363                         if_printf(ifp, "Unable to create "
2364                                   "%dth TX mbuf DMA map!\n", i);
2365                         return rc;
2366                 }
2367         }
2368
2369         /*
2370          * Create a DMA tag for the RX buffer descriptor chain,
2371          * allocate and clear the  memory, and fetch the physical
2372          * address of the blocks.
2373          */
2374         rc = bus_dma_tag_create(sc->parent_tag,
2375                                 BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
2376                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2377                                 NULL, NULL,
2378                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2379                                 0, &sc->rx_bd_chain_tag);
2380         if (rc != 0) {
2381                 if_printf(ifp, "Could not allocate "
2382                           "RX descriptor chain DMA tag!\n");
2383                 return rc;
2384         }
2385
2386         for (i = 0; i < RX_PAGES; i++) {
2387                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2388                                       (void **)&sc->rx_bd_chain[i],
2389                                       BUS_DMA_WAITOK | BUS_DMA_ZERO,
2390                                       &sc->rx_bd_chain_map[i]);
2391                 if (rc != 0) {
2392                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2393                                   "chain DMA memory!\n", i);
2394                         return rc;
2395                 }
2396
2397                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2398                                      sc->rx_bd_chain_map[i],
2399                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2400                                      bce_dma_map_addr, &busaddr,
2401                                      BUS_DMA_WAITOK);
2402                 if (rc != 0) {
2403                         if_printf(ifp, "Could not map %dth RX descriptor "
2404                                   "chain DMA memory!\n", i);
2405                         bus_dmamem_free(sc->rx_bd_chain_tag,
2406                                         sc->rx_bd_chain[i],
2407                                         sc->rx_bd_chain_map[i]);
2408                         sc->rx_bd_chain[i] = NULL;
2409                         return rc;
2410                 }
2411
2412                 sc->rx_bd_chain_paddr[i] = busaddr;
2413                 /* DRC - Fix for 64 bit systems. */
2414                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2415                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2416         }
2417
2418         /* Create a DMA tag for RX mbufs. */
2419         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2420                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2421                                 NULL, NULL,
2422                                 MCLBYTES, 1, MCLBYTES,
2423                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
2424                                 &sc->rx_mbuf_tag);
2425         if (rc != 0) {
2426                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2427                 return rc;
2428         }
2429
2430         /* Create DMA maps for the RX mbuf clusters. */
2431         for (i = 0; i < TOTAL_RX_BD; i++) {
2432                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2433                                        &sc->rx_mbuf_map[i]);
2434                 if (rc != 0) {
2435                         for (j = 0; j < i; ++j) {
2436                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2437                                                    sc->rx_mbuf_map[j]);
2438                         }
2439                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2440                         sc->rx_mbuf_tag = NULL;
2441
2442                         if_printf(ifp, "Unable to create "
2443                                   "%dth RX mbuf DMA map!\n", i);
2444                         return rc;
2445                 }
2446         }
2447         return 0;
2448 }
2449
2450
2451 /****************************************************************************/
2452 /* Firmware synchronization.                                                */
2453 /*                                                                          */
2454 /* Before performing certain events such as a chip reset, synchronize with  */
2455 /* the firmware first.                                                      */
2456 /*                                                                          */
2457 /* Returns:                                                                 */
2458 /*   0 for success, positive value for failure.                             */
2459 /****************************************************************************/
2460 static int
2461 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2462 {
2463         int i, rc = 0;
2464         uint32_t val;
2465
2466         /* Don't waste any time if we've timed out before. */
2467         if (sc->bce_fw_timed_out)
2468                 return EBUSY;
2469
2470         /* Increment the message sequence number. */
2471         sc->bce_fw_wr_seq++;
2472         msg_data |= sc->bce_fw_wr_seq;
2473
2474         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2475
2476         /* Send the message to the bootcode driver mailbox. */
2477         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2478
2479         /* Wait for the bootcode to acknowledge the message. */
2480         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2481                 /* Check for a response in the bootcode firmware mailbox. */
2482                 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
2483                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2484                         break;
2485                 DELAY(1000);
2486         }
2487
2488         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2489         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2490             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2491                 if_printf(&sc->arpcom.ac_if,
2492                           "Firmware synchronization timeout! "
2493                           "msg_data = 0x%08X\n", msg_data);
2494
2495                 msg_data &= ~BCE_DRV_MSG_CODE;
2496                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2497
2498                 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2499
2500                 sc->bce_fw_timed_out = 1;
2501                 rc = EBUSY;
2502         }
2503         return rc;
2504 }
2505
2506
2507 /****************************************************************************/
2508 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2509 /*                                                                          */
2510 /* Returns:                                                                 */
2511 /*   Nothing.                                                               */
2512 /****************************************************************************/
2513 static void
2514 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2515                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2516 {
2517         int i;
2518         uint32_t val;
2519
2520         for (i = 0; i < rv2p_code_len; i += 8) {
2521                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2522                 rv2p_code++;
2523                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2524                 rv2p_code++;
2525
2526                 if (rv2p_proc == RV2P_PROC1) {
2527                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2528                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2529                 } else {
2530                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2531                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2532                 }
2533         }
2534
2535         /* Reset the processor, un-stall is done later. */
2536         if (rv2p_proc == RV2P_PROC1)
2537                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2538         else
2539                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2540 }
2541
2542
2543 /****************************************************************************/
2544 /* Load RISC processor firmware.                                            */
2545 /*                                                                          */
2546 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2547 /* associated with a particular processor.                                  */
2548 /*                                                                          */
2549 /* Returns:                                                                 */
2550 /*   Nothing.                                                               */
2551 /****************************************************************************/
2552 static void
2553 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2554                 struct fw_info *fw)
2555 {
2556         uint32_t offset, val;
2557         int j;
2558
2559         /* Halt the CPU. */
2560         val = REG_RD_IND(sc, cpu_reg->mode);
2561         val |= cpu_reg->mode_value_halt;
2562         REG_WR_IND(sc, cpu_reg->mode, val);
2563         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2564
2565         /* Load the Text area. */
2566         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2567         if (fw->text) {
2568                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2569                         REG_WR_IND(sc, offset, fw->text[j]);
2570         }
2571
2572         /* Load the Data area. */
2573         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2574         if (fw->data) {
2575                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2576                         REG_WR_IND(sc, offset, fw->data[j]);
2577         }
2578
2579         /* Load the SBSS area. */
2580         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2581         if (fw->sbss) {
2582                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2583                         REG_WR_IND(sc, offset, fw->sbss[j]);
2584         }
2585
2586         /* Load the BSS area. */
2587         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2588         if (fw->bss) {
2589                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2590                         REG_WR_IND(sc, offset, fw->bss[j]);
2591         }
2592
2593         /* Load the Read-Only area. */
2594         offset = cpu_reg->spad_base +
2595                 (fw->rodata_addr - cpu_reg->mips_view_base);
2596         if (fw->rodata) {
2597                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2598                         REG_WR_IND(sc, offset, fw->rodata[j]);
2599         }
2600
2601         /* Clear the pre-fetch instruction. */
2602         REG_WR_IND(sc, cpu_reg->inst, 0);
2603         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2604
2605         /* Start the CPU. */
2606         val = REG_RD_IND(sc, cpu_reg->mode);
2607         val &= ~cpu_reg->mode_value_halt;
2608         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2609         REG_WR_IND(sc, cpu_reg->mode, val);
2610 }
2611
2612
2613 /****************************************************************************/
2614 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs.                         */
2615 /*                                                                          */
2616 /* Loads the firmware for each CPU and starts the CPU.                      */
2617 /*                                                                          */
2618 /* Returns:                                                                 */
2619 /*   Nothing.                                                               */
2620 /****************************************************************************/
2621 static void
2622 bce_init_cpus(struct bce_softc *sc)
2623 {
2624         struct cpu_reg cpu_reg;
2625         struct fw_info fw;
2626
2627         /* Initialize the RV2P processor. */
2628         bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1);
2629         bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2);
2630
2631         /* Initialize the RX Processor. */
2632         cpu_reg.mode = BCE_RXP_CPU_MODE;
2633         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2634         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2635         cpu_reg.state = BCE_RXP_CPU_STATE;
2636         cpu_reg.state_value_clear = 0xffffff;
2637         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2638         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2639         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2640         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2641         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2642         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2643         cpu_reg.mips_view_base = 0x8000000;
2644
2645         fw.ver_major = bce_RXP_b06FwReleaseMajor;
2646         fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2647         fw.ver_fix = bce_RXP_b06FwReleaseFix;
2648         fw.start_addr = bce_RXP_b06FwStartAddr;
2649
2650         fw.text_addr = bce_RXP_b06FwTextAddr;
2651         fw.text_len = bce_RXP_b06FwTextLen;
2652         fw.text_index = 0;
2653         fw.text = bce_RXP_b06FwText;
2654
2655         fw.data_addr = bce_RXP_b06FwDataAddr;
2656         fw.data_len = bce_RXP_b06FwDataLen;
2657         fw.data_index = 0;
2658         fw.data = bce_RXP_b06FwData;
2659
2660         fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2661         fw.sbss_len = bce_RXP_b06FwSbssLen;
2662         fw.sbss_index = 0;
2663         fw.sbss = bce_RXP_b06FwSbss;
2664
2665         fw.bss_addr = bce_RXP_b06FwBssAddr;
2666         fw.bss_len = bce_RXP_b06FwBssLen;
2667         fw.bss_index = 0;
2668         fw.bss = bce_RXP_b06FwBss;
2669
2670         fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2671         fw.rodata_len = bce_RXP_b06FwRodataLen;
2672         fw.rodata_index = 0;
2673         fw.rodata = bce_RXP_b06FwRodata;
2674
2675         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2676         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2677
2678         /* Initialize the TX Processor. */
2679         cpu_reg.mode = BCE_TXP_CPU_MODE;
2680         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2681         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2682         cpu_reg.state = BCE_TXP_CPU_STATE;
2683         cpu_reg.state_value_clear = 0xffffff;
2684         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2685         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2686         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2687         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2688         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2689         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2690         cpu_reg.mips_view_base = 0x8000000;
2691
2692         fw.ver_major = bce_TXP_b06FwReleaseMajor;
2693         fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2694         fw.ver_fix = bce_TXP_b06FwReleaseFix;
2695         fw.start_addr = bce_TXP_b06FwStartAddr;
2696
2697         fw.text_addr = bce_TXP_b06FwTextAddr;
2698         fw.text_len = bce_TXP_b06FwTextLen;
2699         fw.text_index = 0;
2700         fw.text = bce_TXP_b06FwText;
2701
2702         fw.data_addr = bce_TXP_b06FwDataAddr;
2703         fw.data_len = bce_TXP_b06FwDataLen;
2704         fw.data_index = 0;
2705         fw.data = bce_TXP_b06FwData;
2706
2707         fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2708         fw.sbss_len = bce_TXP_b06FwSbssLen;
2709         fw.sbss_index = 0;
2710         fw.sbss = bce_TXP_b06FwSbss;
2711
2712         fw.bss_addr = bce_TXP_b06FwBssAddr;
2713         fw.bss_len = bce_TXP_b06FwBssLen;
2714         fw.bss_index = 0;
2715         fw.bss = bce_TXP_b06FwBss;
2716
2717         fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2718         fw.rodata_len = bce_TXP_b06FwRodataLen;
2719         fw.rodata_index = 0;
2720         fw.rodata = bce_TXP_b06FwRodata;
2721
2722         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2723         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2724
2725         /* Initialize the TX Patch-up Processor. */
2726         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2727         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2728         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2729         cpu_reg.state = BCE_TPAT_CPU_STATE;
2730         cpu_reg.state_value_clear = 0xffffff;
2731         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2732         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2733         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2734         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2735         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2736         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2737         cpu_reg.mips_view_base = 0x8000000;
2738
2739         fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2740         fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2741         fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2742         fw.start_addr = bce_TPAT_b06FwStartAddr;
2743
2744         fw.text_addr = bce_TPAT_b06FwTextAddr;
2745         fw.text_len = bce_TPAT_b06FwTextLen;
2746         fw.text_index = 0;
2747         fw.text = bce_TPAT_b06FwText;
2748
2749         fw.data_addr = bce_TPAT_b06FwDataAddr;
2750         fw.data_len = bce_TPAT_b06FwDataLen;
2751         fw.data_index = 0;
2752         fw.data = bce_TPAT_b06FwData;
2753
2754         fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2755         fw.sbss_len = bce_TPAT_b06FwSbssLen;
2756         fw.sbss_index = 0;
2757         fw.sbss = bce_TPAT_b06FwSbss;
2758
2759         fw.bss_addr = bce_TPAT_b06FwBssAddr;
2760         fw.bss_len = bce_TPAT_b06FwBssLen;
2761         fw.bss_index = 0;
2762         fw.bss = bce_TPAT_b06FwBss;
2763
2764         fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2765         fw.rodata_len = bce_TPAT_b06FwRodataLen;
2766         fw.rodata_index = 0;
2767         fw.rodata = bce_TPAT_b06FwRodata;
2768
2769         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2770         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2771
2772         /* Initialize the Completion Processor. */
2773         cpu_reg.mode = BCE_COM_CPU_MODE;
2774         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
2775         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
2776         cpu_reg.state = BCE_COM_CPU_STATE;
2777         cpu_reg.state_value_clear = 0xffffff;
2778         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
2779         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
2780         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
2781         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
2782         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
2783         cpu_reg.spad_base = BCE_COM_SCRATCH;
2784         cpu_reg.mips_view_base = 0x8000000;
2785
2786         fw.ver_major = bce_COM_b06FwReleaseMajor;
2787         fw.ver_minor = bce_COM_b06FwReleaseMinor;
2788         fw.ver_fix = bce_COM_b06FwReleaseFix;
2789         fw.start_addr = bce_COM_b06FwStartAddr;
2790
2791         fw.text_addr = bce_COM_b06FwTextAddr;
2792         fw.text_len = bce_COM_b06FwTextLen;
2793         fw.text_index = 0;
2794         fw.text = bce_COM_b06FwText;
2795
2796         fw.data_addr = bce_COM_b06FwDataAddr;
2797         fw.data_len = bce_COM_b06FwDataLen;
2798         fw.data_index = 0;
2799         fw.data = bce_COM_b06FwData;
2800
2801         fw.sbss_addr = bce_COM_b06FwSbssAddr;
2802         fw.sbss_len = bce_COM_b06FwSbssLen;
2803         fw.sbss_index = 0;
2804         fw.sbss = bce_COM_b06FwSbss;
2805
2806         fw.bss_addr = bce_COM_b06FwBssAddr;
2807         fw.bss_len = bce_COM_b06FwBssLen;
2808         fw.bss_index = 0;
2809         fw.bss = bce_COM_b06FwBss;
2810
2811         fw.rodata_addr = bce_COM_b06FwRodataAddr;
2812         fw.rodata_len = bce_COM_b06FwRodataLen;
2813         fw.rodata_index = 0;
2814         fw.rodata = bce_COM_b06FwRodata;
2815
2816         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
2817         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2818 }
2819
2820
2821 /****************************************************************************/
2822 /* Initialize context memory.                                               */
2823 /*                                                                          */
2824 /* Clears the memory associated with each Context ID (CID).                 */
2825 /*                                                                          */
2826 /* Returns:                                                                 */
2827 /*   Nothing.                                                               */
2828 /****************************************************************************/
2829 static void
2830 bce_init_ctx(struct bce_softc *sc)
2831 {
2832         uint32_t vcid = 96;
2833
2834         while (vcid) {
2835                 uint32_t vcid_addr, pcid_addr, offset;
2836                 int i;
2837
2838                 vcid--;
2839
2840                 vcid_addr = GET_CID_ADDR(vcid);
2841                 pcid_addr = vcid_addr;
2842
2843                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2844                         vcid_addr += (i << PHY_CTX_SHIFT);
2845                         pcid_addr += (i << PHY_CTX_SHIFT);
2846
2847                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
2848                         REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr);
2849
2850                         /* Zero out the context. */
2851                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2852                                 CTX_WR(sc, vcid_addr, offset, 0);
2853                 }
2854         }
2855 }
2856
2857
2858 /****************************************************************************/
2859 /* Fetch the permanent MAC address of the controller.                       */
2860 /*                                                                          */
2861 /* Returns:                                                                 */
2862 /*   Nothing.                                                               */
2863 /****************************************************************************/
2864 static void
2865 bce_get_mac_addr(struct bce_softc *sc)
2866 {
2867         uint32_t mac_lo = 0, mac_hi = 0;
2868
2869         /*
2870          * The NetXtreme II bootcode populates various NIC
2871          * power-on and runtime configuration items in a
2872          * shared memory area.  The factory configured MAC
2873          * address is available from both NVRAM and the
2874          * shared memory area so we'll read the value from
2875          * shared memory for speed.
2876          */
2877
2878         mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER);
2879         mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER);
2880
2881         if (mac_lo == 0 && mac_hi == 0) {
2882                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
2883         } else {
2884                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
2885                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
2886                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
2887                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
2888                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
2889                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
2890         }
2891
2892         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
2893 }
2894
2895
2896 /****************************************************************************/
2897 /* Program the MAC address.                                                 */
2898 /*                                                                          */
2899 /* Returns:                                                                 */
2900 /*   Nothing.                                                               */
2901 /****************************************************************************/
2902 static void
2903 bce_set_mac_addr(struct bce_softc *sc)
2904 {
2905         const uint8_t *mac_addr = sc->eaddr;
2906         uint32_t val;
2907
2908         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
2909                 sc->eaddr, ":");
2910
2911         val = (mac_addr[0] << 8) | mac_addr[1];
2912         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
2913
2914         val = (mac_addr[2] << 24) |
2915               (mac_addr[3] << 16) |
2916               (mac_addr[4] << 8) |
2917               mac_addr[5];
2918         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
2919 }
2920
2921
2922 /****************************************************************************/
2923 /* Stop the controller.                                                     */
2924 /*                                                                          */
2925 /* Returns:                                                                 */
2926 /*   Nothing.                                                               */
2927 /****************************************************************************/
2928 static void
2929 bce_stop(struct bce_softc *sc)
2930 {
2931         struct ifnet *ifp = &sc->arpcom.ac_if;
2932         struct mii_data *mii = device_get_softc(sc->bce_miibus);
2933         struct ifmedia_entry *ifm;
2934         int mtmp, itmp;
2935
2936         ASSERT_SERIALIZED(ifp->if_serializer);
2937
2938         callout_stop(&sc->bce_stat_ch);
2939
2940         /* Disable the transmit/receive blocks. */
2941         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff);
2942         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2943         DELAY(20);
2944
2945         bce_disable_intr(sc);
2946
2947         /* Tell firmware that the driver is going away. */
2948         bce_reset(sc, BCE_DRV_MSG_CODE_SUSPEND_NO_WOL);
2949
2950         /* Free the RX lists. */
2951         bce_free_rx_chain(sc);
2952
2953         /* Free TX buffers. */
2954         bce_free_tx_chain(sc);
2955
2956         /*
2957          * Isolate/power down the PHY, but leave the media selection
2958          * unchanged so that things will be put back to normal when
2959          * we bring the interface back up.
2960          *
2961          * 'mii' may be NULL if bce_stop() is called by bce_detach().
2962          */
2963         if (mii != NULL) {
2964                 itmp = ifp->if_flags;
2965                 ifp->if_flags |= IFF_UP;
2966                 ifm = mii->mii_media.ifm_cur;
2967                 mtmp = ifm->ifm_media;
2968                 ifm->ifm_media = IFM_ETHER | IFM_NONE;
2969                 mii_mediachg(mii);
2970                 ifm->ifm_media = mtmp;
2971                 ifp->if_flags = itmp;
2972         }
2973
2974         sc->bce_link = 0;
2975         sc->bce_coalchg_mask = 0;
2976
2977         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2978         ifp->if_timer = 0;
2979
2980         bce_mgmt_init(sc);
2981 }
2982
2983
2984 static int
2985 bce_reset(struct bce_softc *sc, uint32_t reset_code)
2986 {
2987         uint32_t val;
2988         int i, rc = 0;
2989
2990         /* Wait for pending PCI transactions to complete. */
2991         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
2992                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2993                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2994                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2995                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2996         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2997         DELAY(5);
2998
2999         /* Assume bootcode is running. */
3000         sc->bce_fw_timed_out = 0;
3001
3002         /* Give the firmware a chance to prepare for the reset. */
3003         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3004         if (rc) {
3005                 if_printf(&sc->arpcom.ac_if,
3006                           "Firmware is not ready for reset\n");
3007                 return rc;
3008         }
3009
3010         /* Set a firmware reminder that this is a soft reset. */
3011         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
3012                    BCE_DRV_RESET_SIGNATURE_MAGIC);
3013
3014         /* Dummy read to force the chip to complete all current transactions. */
3015         val = REG_RD(sc, BCE_MISC_ID);
3016
3017         /* Chip reset. */
3018         val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3019               BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3020               BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3021         REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3022
3023         /* Allow up to 30us for reset to complete. */
3024         for (i = 0; i < 10; i++) {
3025                 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3026                 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3027                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3028                         break;
3029                 }
3030                 DELAY(10);
3031         }
3032
3033         /* Check that reset completed successfully. */
3034         if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3035                    BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3036                 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3037                 return EBUSY;
3038         }
3039
3040         /* Make sure byte swapping is properly configured. */
3041         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3042         if (val != 0x01020304) {
3043                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3044                 return ENODEV;
3045         }
3046
3047         /* Just completed a reset, assume that firmware is running again. */
3048         sc->bce_fw_timed_out = 0;
3049
3050         /* Wait for the firmware to finish its initialization. */
3051         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3052         if (rc) {
3053                 if_printf(&sc->arpcom.ac_if,
3054                           "Firmware did not complete initialization!\n");
3055         }
3056         return rc;
3057 }
3058
3059
3060 static int
3061 bce_chipinit(struct bce_softc *sc)
3062 {
3063         uint32_t val;
3064         int rc = 0;
3065
3066         /* Make sure the interrupt is not active. */
3067         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3068
3069         /*
3070          * Initialize DMA byte/word swapping, configure the number of DMA
3071          * channels and PCI clock compensation delay.
3072          */
3073         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3074               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3075 #if BYTE_ORDER == BIG_ENDIAN
3076               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3077 #endif
3078               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3079               DMA_READ_CHANS << 12 |
3080               DMA_WRITE_CHANS << 16;
3081
3082         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3083
3084         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3085                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3086
3087         /*
3088          * This setting resolves a problem observed on certain Intel PCI
3089          * chipsets that cannot handle multiple outstanding DMA operations.
3090          * See errata E9_5706A1_65.
3091          */
3092         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3093             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3094             !(sc->bce_flags & BCE_PCIX_FLAG))
3095                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3096
3097         REG_WR(sc, BCE_DMA_CONFIG, val);
3098
3099         /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */
3100         if (sc->bce_flags & BCE_PCIX_FLAG) {
3101                 uint16_t cmd;
3102
3103                 cmd = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2);
3104                 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, cmd & ~0x2, 2);
3105         }
3106
3107         /* Enable the RX_V2P and Context state machines before access. */
3108         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3109                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3110                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3111                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3112
3113         /* Initialize context mapping and zero out the quick contexts. */
3114         bce_init_ctx(sc);
3115
3116         /* Initialize the on-boards CPUs */
3117         bce_init_cpus(sc);
3118
3119         /* Prepare NVRAM for access. */
3120         rc = bce_init_nvram(sc);
3121         if (rc != 0)
3122                 return rc;
3123
3124         /* Set the kernel bypass block size */
3125         val = REG_RD(sc, BCE_MQ_CONFIG);
3126         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3127         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3128         REG_WR(sc, BCE_MQ_CONFIG, val);
3129
3130         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3131         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3132         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3133
3134         /* Set the page size and clear the RV2P processor stall bits. */
3135         val = (BCM_PAGE_BITS - 8) << 24;
3136         REG_WR(sc, BCE_RV2P_CONFIG, val);
3137
3138         /* Configure page size. */
3139         val = REG_RD(sc, BCE_TBDR_CONFIG);
3140         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3141         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3142         REG_WR(sc, BCE_TBDR_CONFIG, val);
3143
3144         return 0;
3145 }
3146
3147
3148 /****************************************************************************/
3149 /* Initialize the controller in preparation to send/receive traffic.        */
3150 /*                                                                          */
3151 /* Returns:                                                                 */
3152 /*   0 for success, positive value for failure.                             */
3153 /****************************************************************************/
3154 static int
3155 bce_blockinit(struct bce_softc *sc)
3156 {
3157         uint32_t reg, val;
3158         int rc = 0;
3159
3160         /* Load the hardware default MAC address. */
3161         bce_set_mac_addr(sc);
3162
3163         /* Set the Ethernet backoff seed value */
3164         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3165               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3166         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3167
3168         sc->last_status_idx = 0;
3169         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3170
3171         /* Set up link change interrupt generation. */
3172         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3173
3174         /* Program the physical address of the status block. */
3175         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3176         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3177
3178         /* Program the physical address of the statistics block. */
3179         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3180                BCE_ADDR_LO(sc->stats_block_paddr));
3181         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3182                BCE_ADDR_HI(sc->stats_block_paddr));
3183
3184         /* Program various host coalescing parameters. */
3185         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3186                (sc->bce_tx_quick_cons_trip_int << 16) |
3187                sc->bce_tx_quick_cons_trip);
3188         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3189                (sc->bce_rx_quick_cons_trip_int << 16) |
3190                sc->bce_rx_quick_cons_trip);
3191         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3192                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3193         REG_WR(sc, BCE_HC_TX_TICKS,
3194                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3195         REG_WR(sc, BCE_HC_RX_TICKS,
3196                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3197         REG_WR(sc, BCE_HC_COM_TICKS,
3198                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3199         REG_WR(sc, BCE_HC_CMD_TICKS,
3200                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3201         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3202         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3203         REG_WR(sc, BCE_HC_CONFIG,
3204                BCE_HC_CONFIG_TX_TMR_MODE |
3205                BCE_HC_CONFIG_COLLECT_STATS);
3206
3207         /* Clear the internal statistics counters. */
3208         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3209
3210         /* Verify that bootcode is running. */
3211         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3212
3213         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3214                 if_printf(&sc->arpcom.ac_if,
3215                           "%s(%d): Simulating bootcode failure.\n",
3216                           __FILE__, __LINE__);
3217                 reg = 0);
3218
3219         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3220             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3221                 if_printf(&sc->arpcom.ac_if,
3222                           "Bootcode not running! Found: 0x%08X, "
3223                           "Expected: 08%08X\n",
3224                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3225                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3226                 return ENODEV;
3227         }
3228
3229         /* Check if any management firmware is running. */
3230         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
3231         if (reg & (BCE_PORT_FEATURE_ASF_ENABLED |
3232                    BCE_PORT_FEATURE_IMD_ENABLED)) {
3233                 DBPRINT(sc, BCE_INFO, "Management F/W Enabled.\n");
3234                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
3235         }
3236
3237         sc->bce_fw_ver =
3238                 REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_BC_REV);
3239         DBPRINT(sc, BCE_INFO, "bootcode rev = 0x%08X\n", sc->bce_fw_ver);
3240
3241         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3242         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3243
3244         /* Enable link state change interrupt generation. */
3245         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3246
3247         /* Enable all remaining blocks in the MAC. */
3248         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff);
3249         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3250         DELAY(20);
3251
3252         return 0;
3253 }
3254
3255
3256 /****************************************************************************/
3257 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3258 /*                                                                          */
3259 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3260 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3261 /* necessary.                                                               */
3262 /*                                                                          */
3263 /* Returns:                                                                 */
3264 /*   0 for success, positive value for failure.                             */
3265 /****************************************************************************/
3266 static int
3267 bce_newbuf_std(struct bce_softc *sc, struct mbuf *m,
3268                uint16_t *prod, uint16_t *chain_prod, uint32_t *prod_bseq)
3269 {
3270         bus_dmamap_t map;
3271         struct bce_dmamap_arg ctx;
3272         bus_dma_segment_t seg;
3273         struct mbuf *m_new;
3274         struct rx_bd *rxbd;
3275         int error;
3276 #ifdef BCE_DEBUG
3277         uint16_t debug_chain_prod = *chain_prod;
3278 #endif
3279
3280         /* Make sure the inputs are valid. */
3281         DBRUNIF((*chain_prod > MAX_RX_BD),
3282                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3283                           "RX producer out of range: 0x%04X > 0x%04X\n",
3284                           __FILE__, __LINE__,
3285                           *chain_prod, (uint16_t)MAX_RX_BD));
3286
3287         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3288                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3289
3290         if (m == NULL) {
3291                 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3292                         if_printf(&sc->arpcom.ac_if, "%s(%d): "
3293                                   "Simulating mbuf allocation failure.\n",
3294                                   __FILE__, __LINE__);
3295                         sc->mbuf_alloc_failed++;
3296                         return ENOBUFS);
3297
3298                 /* This is a new mbuf allocation. */
3299                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
3300                 if (m_new == NULL)
3301                         return ENOBUFS;
3302                 DBRUNIF(1, sc->rx_mbuf_alloc++);
3303         } else {
3304                 m_new = m;
3305                 m_new->m_data = m_new->m_ext.ext_buf;
3306         }
3307         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3308
3309         /* Map the mbuf cluster into device memory. */
3310         map = sc->rx_mbuf_map[*chain_prod];
3311
3312         ctx.bce_maxsegs = 1;
3313         ctx.bce_segs = &seg;
3314         error = bus_dmamap_load_mbuf(sc->rx_mbuf_tag, map, m_new,
3315                                      bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
3316         if (error || ctx.bce_maxsegs == 0) {
3317                 if_printf(&sc->arpcom.ac_if,
3318                           "Error mapping mbuf into RX chain!\n");
3319
3320                 if (m == NULL)
3321                         m_freem(m_new);
3322
3323                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3324                 return ENOBUFS;
3325         }
3326
3327         /* Watch for overflow. */
3328         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3329                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3330                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3331                           __FILE__, __LINE__, sc->free_rx_bd,
3332                           (uint16_t)USABLE_RX_BD));
3333
3334         /* Update some debug statistic counters */
3335         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3336                 sc->rx_low_watermark = sc->free_rx_bd);
3337         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3338
3339         /* Setup the rx_bd for the first segment. */
3340         rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
3341
3342         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(seg.ds_addr));
3343         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(seg.ds_addr));
3344         rxbd->rx_bd_len = htole32(seg.ds_len);
3345         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3346         *prod_bseq += seg.ds_len;
3347
3348         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3349
3350         /* Save the mbuf and update our counter. */
3351         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3352         sc->free_rx_bd--;
3353
3354         DBRUN(BCE_VERBOSE_RECV,
3355               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3356
3357         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3358                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3359
3360         return 0;
3361 }
3362
3363
3364 /****************************************************************************/
3365 /* Allocate memory and initialize the TX data structures.                   */
3366 /*                                                                          */
3367 /* Returns:                                                                 */
3368 /*   0 for success, positive value for failure.                             */
3369 /****************************************************************************/
3370 static int
3371 bce_init_tx_chain(struct bce_softc *sc)
3372 {
3373         struct tx_bd *txbd;
3374         uint32_t val;
3375         int i, rc = 0;
3376
3377         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3378
3379         /* Set the initial TX producer/consumer indices. */
3380         sc->tx_prod = 0;
3381         sc->tx_cons = 0;
3382         sc->tx_prod_bseq   = 0;
3383         sc->used_tx_bd = 0;
3384         sc->max_tx_bd = USABLE_TX_BD;
3385         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3386         DBRUNIF(1, sc->tx_full_count = 0);
3387
3388         /*
3389          * The NetXtreme II supports a linked-list structre called
3390          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3391          * consists of a series of 1 or more chain pages, each of which
3392          * consists of a fixed number of BD entries.
3393          * The last BD entry on each page is a pointer to the next page
3394          * in the chain, and the last pointer in the BD chain
3395          * points back to the beginning of the chain.
3396          */
3397
3398         /* Set the TX next pointer chain entries. */
3399         for (i = 0; i < TX_PAGES; i++) {
3400                 int j;
3401
3402                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3403
3404                 /* Check if we've reached the last page. */
3405                 if (i == (TX_PAGES - 1))
3406                         j = 0;
3407                 else
3408                         j = i + 1;
3409
3410                 txbd->tx_bd_haddr_hi =
3411                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3412                 txbd->tx_bd_haddr_lo =
3413                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3414         }
3415
3416         for (i = 0; i < TX_PAGES; ++i) {
3417                 bus_dmamap_sync(sc->tx_bd_chain_tag, sc->tx_bd_chain_map[i],
3418                                 BUS_DMASYNC_PREWRITE);
3419         }
3420
3421         /* Initialize the context ID for an L2 TX chain. */
3422         val = BCE_L2CTX_TYPE_TYPE_L2;
3423         val |= BCE_L2CTX_TYPE_SIZE_L2;
3424         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val);
3425
3426         val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3427         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val);
3428
3429         /* Point the hardware to the first page in the chain. */
3430         val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3431         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val);
3432         val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3433         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val);
3434
3435         DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
3436
3437         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3438
3439         return(rc);
3440 }
3441
3442
3443 /****************************************************************************/
3444 /* Free memory and clear the TX data structures.                            */
3445 /*                                                                          */
3446 /* Returns:                                                                 */
3447 /*   Nothing.                                                               */
3448 /****************************************************************************/
3449 static void
3450 bce_free_tx_chain(struct bce_softc *sc)
3451 {
3452         int i;
3453
3454         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3455
3456         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3457         for (i = 0; i < TOTAL_TX_BD; i++) {
3458                 if (sc->tx_mbuf_ptr[i] != NULL) {
3459                         bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i],
3460                                         BUS_DMASYNC_POSTWRITE);
3461                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3462                         m_freem(sc->tx_mbuf_ptr[i]);
3463                         sc->tx_mbuf_ptr[i] = NULL;
3464                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3465                 }
3466         }
3467
3468         /* Clear each TX chain page. */
3469         for (i = 0; i < TX_PAGES; i++)
3470                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3471         sc->used_tx_bd = 0;
3472
3473         /* Check if we lost any mbufs in the process. */
3474         DBRUNIF((sc->tx_mbuf_alloc),
3475                 if_printf(&sc->arpcom.ac_if,
3476                           "%s(%d): Memory leak! "
3477                           "Lost %d mbufs from tx chain!\n",
3478                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3479
3480         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3481 }
3482
3483
3484 /****************************************************************************/
3485 /* Allocate memory and initialize the RX data structures.                   */
3486 /*                                                                          */
3487 /* Returns:                                                                 */
3488 /*   0 for success, positive value for failure.                             */
3489 /****************************************************************************/
3490 static int
3491 bce_init_rx_chain(struct bce_softc *sc)
3492 {
3493         struct rx_bd *rxbd;
3494         int i, rc = 0;
3495         uint16_t prod, chain_prod;
3496         uint32_t prod_bseq, val;
3497
3498         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3499
3500         /* Initialize the RX producer and consumer indices. */
3501         sc->rx_prod = 0;
3502         sc->rx_cons = 0;
3503         sc->rx_prod_bseq = 0;
3504         sc->free_rx_bd = USABLE_RX_BD;
3505         sc->max_rx_bd = USABLE_RX_BD;
3506         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3507         DBRUNIF(1, sc->rx_empty_count = 0);
3508
3509         /* Initialize the RX next pointer chain entries. */
3510         for (i = 0; i < RX_PAGES; i++) {
3511                 int j;
3512
3513                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3514
3515                 /* Check if we've reached the last page. */
3516                 if (i == (RX_PAGES - 1))
3517                         j = 0;
3518                 else
3519                         j = i + 1;
3520
3521                 /* Setup the chain page pointers. */
3522                 rxbd->rx_bd_haddr_hi =
3523                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
3524                 rxbd->rx_bd_haddr_lo =
3525                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
3526         }
3527
3528         /* Initialize the context ID for an L2 RX chain. */
3529         val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3530         val |= BCE_L2CTX_CTX_TYPE_SIZE_L2;
3531         val |= 0x02 << 8;
3532         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val);
3533
3534         /* Point the hardware to the first page in the chain. */
3535         /* XXX shouldn't this after RX descriptor initialization? */
3536         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3537         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val);
3538         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3539         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val);
3540
3541         /* Allocate mbuf clusters for the rx_bd chain. */
3542         prod = prod_bseq = 0;
3543         while (prod < TOTAL_RX_BD) {
3544                 chain_prod = RX_CHAIN_IDX(prod);
3545                 if (bce_newbuf_std(sc, NULL, &prod, &chain_prod, &prod_bseq)) {
3546                         if_printf(&sc->arpcom.ac_if,
3547                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
3548                                   chain_prod);
3549                         rc = ENOBUFS;
3550                         break;
3551                 }
3552                 prod = NEXT_RX_BD(prod);
3553         }
3554
3555         /* Save the RX chain producer index. */
3556         sc->rx_prod = prod;
3557         sc->rx_prod_bseq = prod_bseq;
3558
3559         for (i = 0; i < RX_PAGES; i++) {
3560                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
3561                                 BUS_DMASYNC_PREWRITE);
3562         }
3563
3564         /* Tell the chip about the waiting rx_bd's. */
3565         REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
3566         REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3567
3568         DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD));
3569
3570         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3571
3572         return(rc);
3573 }
3574
3575
3576 /****************************************************************************/
3577 /* Free memory and clear the RX data structures.                            */
3578 /*                                                                          */
3579 /* Returns:                                                                 */
3580 /*   Nothing.                                                               */
3581 /****************************************************************************/
3582 static void
3583 bce_free_rx_chain(struct bce_softc *sc)
3584 {
3585         int i;
3586
3587         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3588
3589         /* Free any mbufs still in the RX mbuf chain. */
3590         for (i = 0; i < TOTAL_RX_BD; i++) {
3591                 if (sc->rx_mbuf_ptr[i] != NULL) {
3592                         bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i],
3593                                         BUS_DMASYNC_POSTREAD);
3594                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
3595                         m_freem(sc->rx_mbuf_ptr[i]);
3596                         sc->rx_mbuf_ptr[i] = NULL;
3597                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3598                 }
3599         }
3600
3601         /* Clear each RX chain page. */
3602         for (i = 0; i < RX_PAGES; i++)
3603                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3604
3605         /* Check if we lost any mbufs in the process. */
3606         DBRUNIF((sc->rx_mbuf_alloc),
3607                 if_printf(&sc->arpcom.ac_if,
3608                           "%s(%d): Memory leak! "
3609                           "Lost %d mbufs from rx chain!\n",
3610                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
3611
3612         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3613 }
3614
3615
3616 /****************************************************************************/
3617 /* Set media options.                                                       */
3618 /*                                                                          */
3619 /* Returns:                                                                 */
3620 /*   0 for success, positive value for failure.                             */
3621 /****************************************************************************/
3622 static int
3623 bce_ifmedia_upd(struct ifnet *ifp)
3624 {
3625         struct bce_softc *sc = ifp->if_softc;
3626         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3627
3628         /*
3629          * 'mii' will be NULL, when this function is called on following
3630          * code path: bce_attach() -> bce_mgmt_init()
3631          */
3632         if (mii != NULL) {
3633                 /* Make sure the MII bus has been enumerated. */
3634                 sc->bce_link = 0;
3635                 if (mii->mii_instance) {
3636                         struct mii_softc *miisc;
3637
3638                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3639                                 mii_phy_reset(miisc);
3640                 }
3641                 mii_mediachg(mii);
3642         }
3643         return 0;
3644 }
3645
3646
3647 /****************************************************************************/
3648 /* Reports current media status.                                            */
3649 /*                                                                          */
3650 /* Returns:                                                                 */
3651 /*   Nothing.                                                               */
3652 /****************************************************************************/
3653 static void
3654 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3655 {
3656         struct bce_softc *sc = ifp->if_softc;
3657         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3658
3659         mii_pollstat(mii);
3660         ifmr->ifm_active = mii->mii_media_active;
3661         ifmr->ifm_status = mii->mii_media_status;
3662 }
3663
3664
3665 /****************************************************************************/
3666 /* Handles PHY generated interrupt events.                                  */
3667 /*                                                                          */
3668 /* Returns:                                                                 */
3669 /*   Nothing.                                                               */
3670 /****************************************************************************/
3671 static void
3672 bce_phy_intr(struct bce_softc *sc)
3673 {
3674         uint32_t new_link_state, old_link_state;
3675         struct ifnet *ifp = &sc->arpcom.ac_if;
3676
3677         ASSERT_SERIALIZED(ifp->if_serializer);
3678
3679         new_link_state = sc->status_block->status_attn_bits &
3680                          STATUS_ATTN_BITS_LINK_STATE;
3681         old_link_state = sc->status_block->status_attn_bits_ack &
3682                          STATUS_ATTN_BITS_LINK_STATE;
3683
3684         /* Handle any changes if the link state has changed. */
3685         if (new_link_state != old_link_state) { /* XXX redundant? */
3686                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
3687
3688                 sc->bce_link = 0;
3689                 callout_stop(&sc->bce_stat_ch);
3690                 bce_tick_serialized(sc);
3691
3692                 /* Update the status_attn_bits_ack field in the status block. */
3693                 if (new_link_state) {
3694                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
3695                                STATUS_ATTN_BITS_LINK_STATE);
3696                         if (bootverbose)
3697                                 if_printf(ifp, "Link is now UP.\n");
3698                 } else {
3699                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
3700                                STATUS_ATTN_BITS_LINK_STATE);
3701                         if (bootverbose)
3702                                 if_printf(ifp, "Link is now DOWN.\n");
3703                 }
3704         }
3705
3706         /* Acknowledge the link change interrupt. */
3707         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
3708 }
3709
3710
3711 /****************************************************************************/
3712 /* Reads the receive consumer value from the status block (skipping over    */
3713 /* chain page pointer if necessary).                                        */
3714 /*                                                                          */
3715 /* Returns:                                                                 */
3716 /*   hw_cons                                                                */
3717 /****************************************************************************/
3718 static __inline uint16_t
3719 bce_get_hw_rx_cons(struct bce_softc *sc)
3720 {
3721         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
3722
3723         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
3724                 hw_cons++;
3725         return hw_cons;
3726 }
3727
3728
3729 /****************************************************************************/
3730 /* Handles received frame interrupt events.                                 */
3731 /*                                                                          */
3732 /* Returns:                                                                 */
3733 /*   Nothing.                                                               */
3734 /****************************************************************************/
3735 static void
3736 bce_rx_intr(struct bce_softc *sc, int count)
3737 {
3738         struct ifnet *ifp = &sc->arpcom.ac_if;
3739         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
3740         uint32_t sw_prod_bseq;
3741         int i;
3742         struct mbuf_chain chain[MAXCPU];
3743
3744         ASSERT_SERIALIZED(ifp->if_serializer);
3745
3746         ether_input_chain_init(chain);
3747
3748         DBRUNIF(1, sc->rx_interrupts++);
3749
3750         /* Prepare the RX chain pages to be accessed by the host CPU. */
3751         for (i = 0; i < RX_PAGES; i++) {
3752                 bus_dmamap_sync(sc->rx_bd_chain_tag,
3753                                 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
3754         }
3755
3756         /* Get the hardware's view of the RX consumer index. */
3757         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
3758
3759         /* Get working copies of the driver's view of the RX indices. */
3760         sw_cons = sc->rx_cons;
3761         sw_prod = sc->rx_prod;
3762         sw_prod_bseq = sc->rx_prod_bseq;
3763
3764         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
3765                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
3766                 __func__, sw_prod, sw_cons, sw_prod_bseq);
3767
3768         /* Prevent speculative reads from getting ahead of the status block. */
3769         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
3770                           BUS_SPACE_BARRIER_READ);
3771
3772         /* Update some debug statistics counters */
3773         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3774                 sc->rx_low_watermark = sc->free_rx_bd);
3775         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3776
3777         /* Scan through the receive chain as long as there is work to do. */
3778         while (sw_cons != hw_cons) {
3779                 struct mbuf *m = NULL;
3780                 struct l2_fhdr *l2fhdr = NULL;
3781                 struct rx_bd *rxbd;
3782                 unsigned int len;
3783                 uint32_t status = 0;
3784
3785 #ifdef DEVICE_POLLING
3786                 if (count >= 0 && count-- == 0) {
3787                         sc->hw_rx_cons = sw_cons;
3788                         break;
3789                 }
3790 #endif
3791
3792                 /*
3793                  * Convert the producer/consumer indices
3794                  * to an actual rx_bd index.
3795                  */
3796                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
3797                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
3798
3799                 /* Get the used rx_bd. */
3800                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
3801                                        [RX_IDX(sw_chain_cons)];
3802                 sc->free_rx_bd++;
3803
3804                 DBRUN(BCE_VERBOSE_RECV,
3805                       if_printf(ifp, "%s(): ", __func__);
3806                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
3807
3808                 /* The mbuf is stored with the last rx_bd entry of a packet. */
3809                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
3810                         /* Validate that this is the last rx_bd. */
3811                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
3812                                 if_printf(ifp, "%s(%d): "
3813                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
3814                                 __FILE__, __LINE__, sw_chain_cons);
3815                                 bce_breakpoint(sc));
3816
3817                         /*
3818                          * ToDo: If the received packet is small enough
3819                          * to fit into a single, non-M_EXT mbuf,
3820                          * allocate a new mbuf here, copy the data to
3821                          * that mbuf, and recycle the mapped jumbo frame.
3822                          */
3823
3824                         /* Unmap the mbuf from DMA space. */
3825                         bus_dmamap_sync(sc->rx_mbuf_tag,
3826                                         sc->rx_mbuf_map[sw_chain_cons],
3827                                         BUS_DMASYNC_POSTREAD);
3828                         bus_dmamap_unload(sc->rx_mbuf_tag,
3829                                           sc->rx_mbuf_map[sw_chain_cons]);
3830
3831                         /* Remove the mbuf from the driver's chain. */
3832                         m = sc->rx_mbuf_ptr[sw_chain_cons];
3833                         sc->rx_mbuf_ptr[sw_chain_cons] = NULL;
3834
3835                         /*
3836                          * Frames received on the NetXteme II are prepended
3837                          * with an l2_fhdr structure which provides status
3838                          * information about the received frame (including
3839                          * VLAN tags and checksum info).  The frames are also
3840                          * automatically adjusted to align the IP header
3841                          * (i.e. two null bytes are inserted before the
3842                          * Ethernet header).
3843                          */
3844                         l2fhdr = mtod(m, struct l2_fhdr *);
3845
3846                         len = l2fhdr->l2_fhdr_pkt_len;
3847                         status = l2fhdr->l2_fhdr_status;
3848
3849                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
3850                                 if_printf(ifp,
3851                                 "Simulating l2_fhdr status error.\n");
3852                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
3853
3854                         /* Watch for unusual sized frames. */
3855                         DBRUNIF((len < BCE_MIN_MTU ||
3856                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
3857                                 if_printf(ifp,
3858                                 "%s(%d): Unusual frame size found. "
3859                                 "Min(%d), Actual(%d), Max(%d)\n",
3860                                 __FILE__, __LINE__,
3861                                 (int)BCE_MIN_MTU, len,
3862                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
3863                                 bce_dump_mbuf(sc, m);
3864                                 bce_breakpoint(sc));
3865
3866                         len -= ETHER_CRC_LEN;
3867
3868                         /* Check the received frame for errors. */
3869                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
3870                                       L2_FHDR_ERRORS_PHY_DECODE |
3871                                       L2_FHDR_ERRORS_ALIGNMENT |
3872                                       L2_FHDR_ERRORS_TOO_SHORT |
3873                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
3874                                 ifp->if_ierrors++;
3875                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
3876
3877                                 /* Reuse the mbuf for a new frame. */
3878                                 if (bce_newbuf_std(sc, m, &sw_prod,
3879                                                    &sw_chain_prod,
3880                                                    &sw_prod_bseq)) {
3881                                         DBRUNIF(1, bce_breakpoint(sc));
3882                                         /* XXX */
3883                                         panic("%s: Can't reuse RX mbuf!\n",
3884                                               ifp->if_xname);
3885                                 }
3886                                 m = NULL;
3887                                 goto bce_rx_int_next_rx;
3888                         }
3889
3890                         /*
3891                          * Get a new mbuf for the rx_bd.   If no new
3892                          * mbufs are available then reuse the current mbuf,
3893                          * log an ierror on the interface, and generate
3894                          * an error in the system log.
3895                          */
3896                         if (bce_newbuf_std(sc, NULL, &sw_prod, &sw_chain_prod,
3897                                            &sw_prod_bseq)) {
3898                                 DBRUN(BCE_WARN,
3899                                       if_printf(ifp,
3900                                       "%s(%d): Failed to allocate new mbuf, "
3901                                       "incoming frame dropped!\n",
3902                                       __FILE__, __LINE__));
3903
3904                                 ifp->if_ierrors++;
3905
3906                                 /* Try and reuse the exisitng mbuf. */
3907                                 if (bce_newbuf_std(sc, m, &sw_prod,
3908                                                    &sw_chain_prod,
3909                                                    &sw_prod_bseq)) {
3910                                         DBRUNIF(1, bce_breakpoint(sc));
3911                                         /* XXX */
3912                                         panic("%s: Double mbuf allocation "
3913                                               "failure!", ifp->if_xname);
3914                                 }
3915                                 m = NULL;
3916                                 goto bce_rx_int_next_rx;
3917                         }
3918
3919                         /*
3920                          * Skip over the l2_fhdr when passing
3921                          * the data up the stack.
3922                          */
3923                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
3924
3925                         m->m_pkthdr.len = m->m_len = len;
3926                         m->m_pkthdr.rcvif = ifp;
3927
3928                         DBRUN(BCE_VERBOSE_RECV,
3929                               struct ether_header *eh;
3930                               eh = mtod(m, struct ether_header *);
3931                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
3932                                         "type: 0x%04X\n", __func__,
3933                                         eh->ether_dhost, ":",
3934                                         eh->ether_shost, ":",
3935                                         htons(eh->ether_type)));
3936
3937                         /* Validate the checksum if offload enabled. */
3938                         if (ifp->if_capenable & IFCAP_RXCSUM) {
3939                                 /* Check for an IP datagram. */
3940                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
3941                                         m->m_pkthdr.csum_flags |=
3942                                                 CSUM_IP_CHECKED;
3943
3944                                         /* Check if the IP checksum is valid. */
3945                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
3946                                              0xffff) == 0) {
3947                                                 m->m_pkthdr.csum_flags |=
3948                                                         CSUM_IP_VALID;
3949                                         } else {
3950                                                 DBPRINT(sc, BCE_WARN_RECV,
3951                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
3952                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
3953                                         }
3954                                 }
3955
3956                                 /* Check for a valid TCP/UDP frame. */
3957                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3958                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
3959
3960                                         /* Check for a good TCP/UDP checksum. */
3961                                         if ((status &
3962                                              (L2_FHDR_ERRORS_TCP_XSUM |
3963                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
3964                                                 m->m_pkthdr.csum_data =
3965                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
3966                                                 m->m_pkthdr.csum_flags |=
3967                                                         CSUM_DATA_VALID |
3968                                                         CSUM_PSEUDO_HDR;
3969                                         } else {
3970                                                 DBPRINT(sc, BCE_WARN_RECV,
3971                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
3972                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
3973                                         }
3974                                 }
3975                         }
3976
3977                         ifp->if_ipackets++;
3978 bce_rx_int_next_rx:
3979                         sw_prod = NEXT_RX_BD(sw_prod);
3980                 }
3981
3982                 sw_cons = NEXT_RX_BD(sw_cons);
3983
3984                 /* If we have a packet, pass it up the stack */
3985                 if (m) {
3986                         DBPRINT(sc, BCE_VERBOSE_RECV,
3987                                 "%s(): Passing received frame up.\n", __func__);
3988
3989                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
3990                                 m->m_flags |= M_VLANTAG;
3991                                 m->m_pkthdr.ether_vlantag =
3992                                         l2fhdr->l2_fhdr_vlan_tag;
3993                         }
3994                         ether_input_chain(ifp, m, chain);
3995
3996                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3997                 }
3998
3999                 /*
4000                  * If polling(4) is not enabled, refresh hw_cons to see
4001                  * whether there's new work.
4002                  *
4003                  * If polling(4) is enabled, i.e count >= 0, refreshing
4004                  * should not be performed, so that we would not spend
4005                  * too much time in RX processing.
4006                  */
4007                 if (count < 0 && sw_cons == hw_cons)
4008                         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4009
4010                 /*
4011                  * Prevent speculative reads from getting ahead
4012                  * of the status block.
4013                  */
4014                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4015                                   BUS_SPACE_BARRIER_READ);
4016         }
4017
4018         ether_input_dispatch(chain);
4019
4020         for (i = 0; i < RX_PAGES; i++) {
4021                 bus_dmamap_sync(sc->rx_bd_chain_tag,
4022                                 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
4023         }
4024
4025         sc->rx_cons = sw_cons;
4026         sc->rx_prod = sw_prod;
4027         sc->rx_prod_bseq = sw_prod_bseq;
4028
4029         REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
4030         REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
4031
4032         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4033                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4034                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4035 }
4036
4037
4038 /****************************************************************************/
4039 /* Reads the transmit consumer value from the status block (skipping over   */
4040 /* chain page pointer if necessary).                                        */
4041 /*                                                                          */
4042 /* Returns:                                                                 */
4043 /*   hw_cons                                                                */
4044 /****************************************************************************/
4045 static __inline uint16_t
4046 bce_get_hw_tx_cons(struct bce_softc *sc)
4047 {
4048         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4049
4050         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4051                 hw_cons++;
4052         return hw_cons;
4053 }
4054
4055
4056 /****************************************************************************/
4057 /* Handles transmit completion interrupt events.                            */
4058 /*                                                                          */
4059 /* Returns:                                                                 */
4060 /*   Nothing.                                                               */
4061 /****************************************************************************/
4062 static void
4063 bce_tx_intr(struct bce_softc *sc)
4064 {
4065         struct ifnet *ifp = &sc->arpcom.ac_if;
4066         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4067
4068         ASSERT_SERIALIZED(ifp->if_serializer);
4069
4070         DBRUNIF(1, sc->tx_interrupts++);
4071
4072         /* Get the hardware's view of the TX consumer index. */
4073         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4074         sw_tx_cons = sc->tx_cons;
4075
4076         /* Prevent speculative reads from getting ahead of the status block. */
4077         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4078                           BUS_SPACE_BARRIER_READ);
4079
4080         /* Cycle through any completed TX chain page entries. */
4081         while (sw_tx_cons != hw_tx_cons) {
4082 #ifdef BCE_DEBUG
4083                 struct tx_bd *txbd = NULL;
4084 #endif
4085                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4086
4087                 DBPRINT(sc, BCE_INFO_SEND,
4088                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4089                         "sw_tx_chain_cons = 0x%04X\n",
4090                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4091
4092                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4093                         if_printf(ifp, "%s(%d): "
4094                                   "TX chain consumer out of range! "
4095                                   " 0x%04X > 0x%04X\n",
4096                                   __FILE__, __LINE__, sw_tx_chain_cons,
4097                                   (int)MAX_TX_BD);
4098                         bce_breakpoint(sc));
4099
4100                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4101                                 [TX_IDX(sw_tx_chain_cons)]);
4102
4103                 DBRUNIF((txbd == NULL),
4104                         if_printf(ifp, "%s(%d): "
4105                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4106                                   __FILE__, __LINE__, sw_tx_chain_cons);
4107                         bce_breakpoint(sc));
4108
4109                 DBRUN(BCE_INFO_SEND,
4110                       if_printf(ifp, "%s(): ", __func__);
4111                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4112
4113                 /*
4114                  * Free the associated mbuf. Remember
4115                  * that only the last tx_bd of a packet
4116                  * has an mbuf pointer and DMA map.
4117                  */
4118                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4119                         /* Validate that this is the last tx_bd. */
4120                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4121                                 if_printf(ifp, "%s(%d): "
4122                                 "tx_bd END flag not set but "
4123                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4124                                 bce_breakpoint(sc));
4125
4126                         DBRUN(BCE_INFO_SEND,
4127                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4128                                         "from tx_bd[0x%04X]\n", __func__,
4129                                         sw_tx_chain_cons));
4130
4131                         /* Unmap the mbuf. */
4132                         bus_dmamap_unload(sc->tx_mbuf_tag,
4133                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4134
4135                         /* Free the mbuf. */
4136                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4137                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4138                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4139
4140                         ifp->if_opackets++;
4141                 }
4142
4143                 sc->used_tx_bd--;
4144                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4145
4146                 if (sw_tx_cons == hw_tx_cons) {
4147                         /* Refresh hw_cons to see if there's new work. */
4148                         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4149                 }
4150
4151                 /*
4152                  * Prevent speculative reads from getting
4153                  * ahead of the status block.
4154                  */
4155                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4156                                   BUS_SPACE_BARRIER_READ);
4157         }
4158
4159         if (sc->used_tx_bd == 0) {
4160                 /* Clear the TX timeout timer. */
4161                 ifp->if_timer = 0;
4162         }
4163
4164         /* Clear the tx hardware queue full flag. */
4165         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4166                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4167                         DBPRINT(sc, BCE_WARN_SEND,
4168                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4169                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4170                 ifp->if_flags &= ~IFF_OACTIVE;
4171         }
4172         sc->tx_cons = sw_tx_cons;
4173 }
4174
4175
4176 /****************************************************************************/
4177 /* Disables interrupt generation.                                           */
4178 /*                                                                          */
4179 /* Returns:                                                                 */
4180 /*   Nothing.                                                               */
4181 /****************************************************************************/
4182 static void
4183 bce_disable_intr(struct bce_softc *sc)
4184 {
4185         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4186         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4187         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4188 }
4189
4190
4191 /****************************************************************************/
4192 /* Enables interrupt generation.                                            */
4193 /*                                                                          */
4194 /* Returns:                                                                 */
4195 /*   Nothing.                                                               */
4196 /****************************************************************************/
4197 static void
4198 bce_enable_intr(struct bce_softc *sc)
4199 {
4200         uint32_t val;
4201
4202         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4203
4204         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4205                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4206                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4207
4208         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4209                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4210
4211         val = REG_RD(sc, BCE_HC_COMMAND);
4212         REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW);
4213 }
4214
4215
4216 /****************************************************************************/
4217 /* Handles controller initialization.                                       */
4218 /*                                                                          */
4219 /* Returns:                                                                 */
4220 /*   Nothing.                                                               */
4221 /****************************************************************************/
4222 static void
4223 bce_init(void *xsc)
4224 {
4225         struct bce_softc *sc = xsc;
4226         struct ifnet *ifp = &sc->arpcom.ac_if;
4227         uint32_t ether_mtu;
4228         int error;
4229
4230         ASSERT_SERIALIZED(ifp->if_serializer);
4231
4232         /* Check if the driver is still running and bail out if it is. */
4233         if (ifp->if_flags & IFF_RUNNING)
4234                 return;
4235
4236         bce_stop(sc);
4237
4238         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4239         if (error) {
4240                 if_printf(ifp, "Controller reset failed!\n");
4241                 goto back;
4242         }
4243
4244         error = bce_chipinit(sc);
4245         if (error) {
4246                 if_printf(ifp, "Controller initialization failed!\n");
4247                 goto back;
4248         }
4249
4250         error = bce_blockinit(sc);
4251         if (error) {
4252                 if_printf(ifp, "Block initialization failed!\n");
4253                 goto back;
4254         }
4255
4256         /* Load our MAC address. */
4257         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4258         bce_set_mac_addr(sc);
4259
4260         /* Calculate and program the Ethernet MTU size. */
4261         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4262
4263         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4264
4265         /*
4266          * Program the mtu, enabling jumbo frame
4267          * support if necessary.  Also set the mbuf
4268          * allocation count for RX frames.
4269          */
4270         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4271 #ifdef notyet
4272                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4273                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4274                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4275                 sc->mbuf_alloc_size = MJUM9BYTES;
4276 #else
4277                 panic("jumbo buffer is not supported yet\n");
4278 #endif
4279         } else {
4280                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4281                 sc->mbuf_alloc_size = MCLBYTES;
4282         }
4283
4284         /* Calculate the RX Ethernet frame size for rx_bd's. */
4285         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4286
4287         DBPRINT(sc, BCE_INFO,
4288                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4289                 "max_frame_size = %d\n",
4290                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4291                 sc->max_frame_size);
4292
4293         /* Program appropriate promiscuous/multicast filtering. */
4294         bce_set_rx_mode(sc);
4295
4296         /* Init RX buffer descriptor chain. */
4297         bce_init_rx_chain(sc);  /* XXX return value */
4298
4299         /* Init TX buffer descriptor chain. */
4300         bce_init_tx_chain(sc);  /* XXX return value */
4301
4302 #ifdef DEVICE_POLLING
4303         /* Disable interrupts if we are polling. */
4304         if (ifp->if_flags & IFF_POLLING) {
4305                 bce_disable_intr(sc);
4306
4307                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4308                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4309                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4310                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4311         } else
4312 #endif
4313         /* Enable host interrupts. */
4314         bce_enable_intr(sc);
4315
4316         bce_ifmedia_upd(ifp);
4317
4318         ifp->if_flags |= IFF_RUNNING;
4319         ifp->if_flags &= ~IFF_OACTIVE;
4320
4321         callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
4322 back:
4323         if (error)
4324                 bce_stop(sc);
4325 }
4326
4327
4328 /****************************************************************************/
4329 /* Initialize the controller just enough so that any management firmware    */
4330 /* running on the device will continue to operate corectly.                 */
4331 /*                                                                          */
4332 /* Returns:                                                                 */
4333 /*   Nothing.                                                               */
4334 /****************************************************************************/
4335 static void
4336 bce_mgmt_init(struct bce_softc *sc)
4337 {
4338         struct ifnet *ifp = &sc->arpcom.ac_if;
4339         uint32_t val;
4340
4341         /* Check if the driver is still running and bail out if it is. */
4342         if (ifp->if_flags & IFF_RUNNING)
4343                 return;
4344
4345         /* Initialize the on-boards CPUs */
4346         bce_init_cpus(sc);
4347
4348         /* Set the page size and clear the RV2P processor stall bits. */
4349         val = (BCM_PAGE_BITS - 8) << 24;
4350         REG_WR(sc, BCE_RV2P_CONFIG, val);
4351
4352         /* Enable all critical blocks in the MAC. */
4353         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4354                BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE |
4355                BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE |
4356                BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE);
4357         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4358         DELAY(20);
4359
4360         bce_ifmedia_upd(ifp);
4361 }
4362
4363
4364 /****************************************************************************/
4365 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4366 /* memory visible to the controller.                                        */
4367 /*                                                                          */
4368 /* Returns:                                                                 */
4369 /*   0 for success, positive value for failure.                             */
4370 /****************************************************************************/
4371 static int
4372 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4373 {
4374         struct bce_dmamap_arg ctx;
4375         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4376         bus_dmamap_t map, tmp_map;
4377         struct mbuf *m0 = *m_head;
4378         struct tx_bd *txbd = NULL;
4379         uint16_t vlan_tag = 0, flags = 0;
4380         uint16_t chain_prod, chain_prod_start, prod;
4381         uint32_t prod_bseq;
4382         int i, error, maxsegs;
4383 #ifdef BCE_DEBUG
4384         uint16_t debug_prod;
4385 #endif
4386
4387         /* Transfer any checksum offload flags to the bd. */
4388         if (m0->m_pkthdr.csum_flags) {
4389                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4390                         flags |= TX_BD_FLAGS_IP_CKSUM;
4391                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4392                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4393         }
4394
4395         /* Transfer any VLAN tags to the bd. */
4396         if (m0->m_flags & M_VLANTAG) {
4397                 flags |= TX_BD_FLAGS_VLAN_TAG;
4398                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4399         }
4400
4401         prod = sc->tx_prod;
4402         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4403
4404         /* Map the mbuf into DMAable memory. */
4405         map = sc->tx_mbuf_map[chain_prod_start];
4406
4407         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4408         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4409                 ("not enough segements %d\n", maxsegs));
4410         if (maxsegs > BCE_MAX_SEGMENTS)
4411                 maxsegs = BCE_MAX_SEGMENTS;
4412
4413         /* Map the mbuf into our DMA address space. */
4414         ctx.bce_maxsegs = maxsegs;
4415         ctx.bce_segs = segs;
4416         error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0,
4417                                      bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
4418         if (error == EFBIG || ctx.bce_maxsegs == 0) {
4419                 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf\n", __func__);
4420                 DBRUNIF(1, bce_dump_mbuf(sc, m0););
4421
4422                 m0 = m_defrag(*m_head, MB_DONTWAIT);
4423                 if (m0 == NULL) {
4424                         error = ENOBUFS;
4425                         goto back;
4426                 }
4427                 *m_head = m0;
4428
4429                 ctx.bce_maxsegs = maxsegs;
4430                 ctx.bce_segs = segs;
4431                 error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0,
4432                                              bce_dma_map_mbuf, &ctx,
4433                                              BUS_DMA_NOWAIT);
4434                 if (error || ctx.bce_maxsegs == 0) {
4435                         if_printf(&sc->arpcom.ac_if,
4436                                   "Error mapping mbuf into TX chain\n");
4437                         if (error == 0)
4438                                 error = EFBIG;
4439                         goto back;
4440                 }
4441         } else if (error) {
4442                 if_printf(&sc->arpcom.ac_if,
4443                           "Error mapping mbuf into TX chain\n");
4444                 goto back;
4445         }
4446
4447         /* prod points to an empty tx_bd at this point. */
4448         prod_bseq  = sc->tx_prod_bseq;
4449
4450 #ifdef BCE_DEBUG
4451         debug_prod = chain_prod;
4452 #endif
4453
4454         DBPRINT(sc, BCE_INFO_SEND,
4455                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4456                 "prod_bseq = 0x%08X\n",
4457                 __func__, prod, chain_prod, prod_bseq);
4458
4459         /*
4460          * Cycle through each mbuf segment that makes up
4461          * the outgoing frame, gathering the mapping info
4462          * for that segment and creating a tx_bd to for
4463          * the mbuf.
4464          */
4465         for (i = 0; i < ctx.bce_maxsegs; i++) {
4466                 chain_prod = TX_CHAIN_IDX(prod);
4467                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4468
4469                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4470                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4471                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4472                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4473                 txbd->tx_bd_flags = htole16(flags);
4474                 prod_bseq += segs[i].ds_len;
4475                 if (i == 0)
4476                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4477                 prod = NEXT_TX_BD(prod);
4478         }
4479
4480         /* Set the END flag on the last TX buffer descriptor. */
4481         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4482
4483         DBRUN(BCE_EXCESSIVE_SEND,
4484               bce_dump_tx_chain(sc, debug_prod, ctx.bce_maxsegs));
4485
4486         DBPRINT(sc, BCE_INFO_SEND,
4487                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4488                 "prod_bseq = 0x%08X\n",
4489                 __func__, prod, chain_prod, prod_bseq);
4490
4491         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4492
4493         /*
4494          * Ensure that the mbuf pointer for this transmission
4495          * is placed at the array index of the last
4496          * descriptor in this chain.  This is done
4497          * because a single map is used for all
4498          * segments of the mbuf and we don't want to
4499          * unload the map before all of the segments
4500          * have been freed.
4501          */
4502         sc->tx_mbuf_ptr[chain_prod] = m0;
4503
4504         tmp_map = sc->tx_mbuf_map[chain_prod];
4505         sc->tx_mbuf_map[chain_prod] = map;
4506         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4507
4508         sc->used_tx_bd += ctx.bce_maxsegs;
4509
4510         /* Update some debug statistic counters */
4511         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4512                 sc->tx_hi_watermark = sc->used_tx_bd);
4513         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4514         DBRUNIF(1, sc->tx_mbuf_alloc++);
4515
4516         DBRUN(BCE_VERBOSE_SEND,
4517               bce_dump_tx_mbuf_chain(sc, chain_prod, ctx.bce_maxsegs));
4518
4519         /* prod points to the next free tx_bd at this point. */
4520         sc->tx_prod = prod;
4521         sc->tx_prod_bseq = prod_bseq;
4522 back:
4523         if (error) {
4524                 m_freem(*m_head);
4525                 *m_head = NULL;
4526         }
4527         return error;
4528 }
4529
4530
4531 /****************************************************************************/
4532 /* Main transmit routine when called from another routine with a lock.      */
4533 /*                                                                          */
4534 /* Returns:                                                                 */
4535 /*   Nothing.                                                               */
4536 /****************************************************************************/
4537 static void
4538 bce_start(struct ifnet *ifp)
4539 {
4540         struct bce_softc *sc = ifp->if_softc;
4541         int count = 0;
4542
4543         ASSERT_SERIALIZED(ifp->if_serializer);
4544
4545         /* If there's no link or the transmit queue is empty then just exit. */
4546         if (!sc->bce_link) {
4547                 ifq_purge(&ifp->if_snd);
4548                 return;
4549         }
4550
4551         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4552                 return;
4553
4554         DBPRINT(sc, BCE_INFO_SEND,
4555                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, "
4556                 "tx_prod_bseq = 0x%08X\n",
4557                 __func__,
4558                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4559
4560         for (;;) {
4561                 struct mbuf *m_head;
4562
4563                 /*
4564                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4565                  * unlikely to fail.
4566                  */
4567                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4568                         ifp->if_flags |= IFF_OACTIVE;
4569                         break;
4570                 }
4571
4572                 /* Check for any frames to send. */
4573                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4574                 if (m_head == NULL)
4575                         break;
4576
4577                 /*
4578                  * Pack the data into the transmit ring. If we
4579                  * don't have room, place the mbuf back at the
4580                  * head of the queue and set the OACTIVE flag
4581                  * to wait for the NIC to drain the chain.
4582                  */
4583                 if (bce_encap(sc, &m_head)) {
4584                         ifp->if_flags |= IFF_OACTIVE;
4585                         DBPRINT(sc, BCE_INFO_SEND,
4586                                 "TX chain is closed for business! "
4587                                 "Total tx_bd used = %d\n",
4588                                 sc->used_tx_bd);
4589                         break;
4590                 }
4591
4592                 count++;
4593
4594                 /* Send a copy of the frame to any BPF listeners. */
4595                 ETHER_BPF_MTAP(ifp, m_head);
4596         }
4597
4598         if (count == 0) {
4599                 /* no packets were dequeued */
4600                 DBPRINT(sc, BCE_VERBOSE_SEND,
4601                         "%s(): No packets were dequeued\n", __func__);
4602                 return;
4603         }
4604
4605         DBPRINT(sc, BCE_INFO_SEND,
4606                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
4607                 "tx_prod_bseq = 0x%08X\n",
4608                 __func__,
4609                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4610
4611         /* Start the transmit. */
4612         REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4613         REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4614
4615         /* Set the tx timeout. */
4616         ifp->if_timer = BCE_TX_TIMEOUT;
4617 }
4618
4619
4620 /****************************************************************************/
4621 /* Handles any IOCTL calls from the operating system.                       */
4622 /*                                                                          */
4623 /* Returns:                                                                 */
4624 /*   0 for success, positive value for failure.                             */
4625 /****************************************************************************/
4626 static int
4627 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4628 {
4629         struct bce_softc *sc = ifp->if_softc;
4630         struct ifreq *ifr = (struct ifreq *)data;
4631         struct mii_data *mii;
4632         int mask, error = 0;
4633
4634         ASSERT_SERIALIZED(ifp->if_serializer);
4635
4636         switch(command) {
4637         case SIOCSIFMTU:
4638                 /* Check that the MTU setting is supported. */
4639                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4640 #ifdef notyet
4641                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4642 #else
4643                     ifr->ifr_mtu > ETHERMTU
4644 #endif
4645                    ) {
4646                         error = EINVAL;
4647                         break;
4648                 }
4649
4650                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
4651
4652                 ifp->if_mtu = ifr->ifr_mtu;
4653                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
4654                 bce_init(sc);
4655                 break;
4656
4657         case SIOCSIFFLAGS:
4658                 if (ifp->if_flags & IFF_UP) {
4659                         if (ifp->if_flags & IFF_RUNNING) {
4660                                 mask = ifp->if_flags ^ sc->bce_if_flags;
4661
4662                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
4663                                         bce_set_rx_mode(sc);
4664                         } else {
4665                                 bce_init(sc);
4666                         }
4667                 } else if (ifp->if_flags & IFF_RUNNING) {
4668                         bce_stop(sc);
4669                 }
4670                 sc->bce_if_flags = ifp->if_flags;
4671                 break;
4672
4673         case SIOCADDMULTI:
4674         case SIOCDELMULTI:
4675                 if (ifp->if_flags & IFF_RUNNING)
4676                         bce_set_rx_mode(sc);
4677                 break;
4678
4679         case SIOCSIFMEDIA:
4680         case SIOCGIFMEDIA:
4681                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
4682                         sc->bce_phy_flags);
4683                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
4684
4685                 mii = device_get_softc(sc->bce_miibus);
4686                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
4687                 break;
4688
4689         case SIOCSIFCAP:
4690                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4691                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
4692                         (uint32_t) mask);
4693
4694                 if (mask & IFCAP_HWCSUM) {
4695                         ifp->if_capenable ^= IFCAP_HWCSUM;
4696                         if (IFCAP_HWCSUM & ifp->if_capenable)
4697                                 ifp->if_hwassist = BCE_IF_HWASSIST;
4698                         else
4699                                 ifp->if_hwassist = 0;
4700                 }
4701                 break;
4702
4703         default:
4704                 error = ether_ioctl(ifp, command, data);
4705                 break;
4706         }
4707         return error;
4708 }
4709
4710
4711 /****************************************************************************/
4712 /* Transmit timeout handler.                                                */
4713 /*                                                                          */
4714 /* Returns:                                                                 */
4715 /*   Nothing.                                                               */
4716 /****************************************************************************/
4717 static void
4718 bce_watchdog(struct ifnet *ifp)
4719 {
4720         struct bce_softc *sc = ifp->if_softc;
4721
4722         ASSERT_SERIALIZED(ifp->if_serializer);
4723
4724         DBRUN(BCE_VERBOSE_SEND,
4725               bce_dump_driver_state(sc);
4726               bce_dump_status_block(sc));
4727
4728         /*
4729          * If we are in this routine because of pause frames, then
4730          * don't reset the hardware.
4731          */
4732         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
4733                 return;
4734
4735         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
4736
4737         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
4738
4739         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
4740         bce_init(sc);
4741
4742         ifp->if_oerrors++;
4743
4744         if (!ifq_is_empty(&ifp->if_snd))
4745                 if_devstart(ifp);
4746 }
4747
4748
4749 #ifdef DEVICE_POLLING
4750
4751 static void
4752 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4753 {
4754         struct bce_softc *sc = ifp->if_softc;
4755         struct status_block *sblk = sc->status_block;
4756         uint16_t hw_tx_cons, hw_rx_cons;
4757
4758         ASSERT_SERIALIZED(ifp->if_serializer);
4759
4760         switch (cmd) {
4761         case POLL_REGISTER:
4762                 bce_disable_intr(sc);
4763
4764                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4765                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4766                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4767                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4768                 return;
4769         case POLL_DEREGISTER:
4770                 bce_enable_intr(sc);
4771
4772                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4773                        (sc->bce_tx_quick_cons_trip_int << 16) |
4774                        sc->bce_tx_quick_cons_trip);
4775                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4776                        (sc->bce_rx_quick_cons_trip_int << 16) |
4777                        sc->bce_rx_quick_cons_trip);
4778                 return;
4779         default:
4780                 break;
4781         }
4782
4783         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
4784
4785         if (cmd == POLL_AND_CHECK_STATUS) {
4786                 uint32_t status_attn_bits;
4787
4788                 status_attn_bits = sblk->status_attn_bits;
4789
4790                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4791                         if_printf(ifp,
4792                         "Simulating unexpected status attention bit set.");
4793                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4794
4795                 /* Was it a link change interrupt? */
4796                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4797                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4798                         bce_phy_intr(sc);
4799
4800                 /*
4801                  * If any other attention is asserted then
4802                  * the chip is toast.
4803                  */
4804                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4805                      (sblk->status_attn_bits_ack &
4806                       ~STATUS_ATTN_BITS_LINK_STATE)) {
4807                         DBRUN(1, sc->unexpected_attentions++);
4808
4809                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4810                                   sblk->status_attn_bits);
4811
4812                         DBRUN(BCE_FATAL,
4813                         if (bce_debug_unexpected_attention == 0)
4814                                 bce_breakpoint(sc));
4815
4816                         bce_init(sc);
4817                         return;
4818                 }
4819         }
4820
4821         hw_rx_cons = bce_get_hw_rx_cons(sc);
4822         hw_tx_cons = bce_get_hw_tx_cons(sc);
4823
4824         /* Check for any completed RX frames. */
4825         if (hw_rx_cons != sc->hw_rx_cons)
4826                 bce_rx_intr(sc, count);
4827
4828         /* Check for any completed TX frames. */
4829         if (hw_tx_cons != sc->hw_tx_cons)
4830                 bce_tx_intr(sc);
4831
4832         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE);
4833
4834         /* Check for new frames to transmit. */
4835         if (!ifq_is_empty(&ifp->if_snd))
4836                 if_devstart(ifp);
4837 }
4838
4839 #endif  /* DEVICE_POLLING */
4840
4841
4842 /*
4843  * Interrupt handler.
4844  */
4845 /****************************************************************************/
4846 /* Main interrupt entry point.  Verifies that the controller generated the  */
4847 /* interrupt and then calls a separate routine for handle the various       */
4848 /* interrupt causes (PHY, TX, RX).                                          */
4849 /*                                                                          */
4850 /* Returns:                                                                 */
4851 /*   0 for success, positive value for failure.                             */
4852 /****************************************************************************/
4853 static void
4854 bce_intr(void *xsc)
4855 {
4856         struct bce_softc *sc = xsc;
4857         struct ifnet *ifp = &sc->arpcom.ac_if;
4858         struct status_block *sblk;
4859         uint16_t hw_rx_cons, hw_tx_cons;
4860
4861         ASSERT_SERIALIZED(ifp->if_serializer);
4862
4863         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
4864         DBRUNIF(1, sc->interrupts_generated++);
4865
4866         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
4867         sblk = sc->status_block;
4868
4869         /*
4870          * If the hardware status block index matches the last value
4871          * read by the driver and we haven't asserted our interrupt
4872          * then there's nothing to do.
4873          */
4874         if (sblk->status_idx == sc->last_status_idx &&
4875             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
4876              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
4877                 return;
4878
4879         /* Ack the interrupt and stop others from occuring. */
4880         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4881                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
4882                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4883
4884         /* Check if the hardware has finished any work. */
4885         hw_rx_cons = bce_get_hw_rx_cons(sc);
4886         hw_tx_cons = bce_get_hw_tx_cons(sc);
4887
4888         /* Keep processing data as long as there is work to do. */
4889         for (;;) {
4890                 uint32_t status_attn_bits;
4891
4892                 status_attn_bits = sblk->status_attn_bits;
4893
4894                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4895                         if_printf(ifp,
4896                         "Simulating unexpected status attention bit set.");
4897                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4898
4899                 /* Was it a link change interrupt? */
4900                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4901                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4902                         bce_phy_intr(sc);
4903
4904                 /*
4905                  * If any other attention is asserted then
4906                  * the chip is toast.
4907                  */
4908                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4909                      (sblk->status_attn_bits_ack &
4910                       ~STATUS_ATTN_BITS_LINK_STATE)) {
4911                         DBRUN(1, sc->unexpected_attentions++);
4912
4913                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4914                                   sblk->status_attn_bits);
4915
4916                         DBRUN(BCE_FATAL,
4917                         if (bce_debug_unexpected_attention == 0)
4918                                 bce_breakpoint(sc));
4919
4920                         bce_init(sc);
4921                         return;
4922                 }
4923
4924                 /* Check for any completed RX frames. */
4925                 if (hw_rx_cons != sc->hw_rx_cons)
4926                         bce_rx_intr(sc, -1);
4927
4928                 /* Check for any completed TX frames. */
4929                 if (hw_tx_cons != sc->hw_tx_cons)
4930                         bce_tx_intr(sc);
4931
4932                 /*
4933                  * Save the status block index value
4934                  * for use during the next interrupt.
4935                  */
4936                 sc->last_status_idx = sblk->status_idx;
4937
4938                 /*
4939                  * Prevent speculative reads from getting
4940                  * ahead of the status block.
4941                  */
4942                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4943                                   BUS_SPACE_BARRIER_READ);
4944
4945                 /*
4946                  * If there's no work left then exit the
4947                  * interrupt service routine.
4948                  */
4949                 hw_rx_cons = bce_get_hw_rx_cons(sc);
4950                 hw_tx_cons = bce_get_hw_tx_cons(sc);
4951                 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
4952                         break;
4953         }
4954
4955         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE);
4956
4957         /* Re-enable interrupts. */
4958         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4959                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx |
4960                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4961         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4962                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4963
4964         if (sc->bce_coalchg_mask)
4965                 bce_coal_change(sc);
4966
4967         /* Handle any frames that arrived while handling the interrupt. */
4968         if (!ifq_is_empty(&ifp->if_snd))
4969                 if_devstart(ifp);
4970 }
4971
4972
4973 /****************************************************************************/
4974 /* Programs the various packet receive modes (broadcast and multicast).     */
4975 /*                                                                          */
4976 /* Returns:                                                                 */
4977 /*   Nothing.                                                               */
4978 /****************************************************************************/
4979 static void
4980 bce_set_rx_mode(struct bce_softc *sc)
4981 {
4982         struct ifnet *ifp = &sc->arpcom.ac_if;
4983         struct ifmultiaddr *ifma;
4984         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
4985         uint32_t rx_mode, sort_mode;
4986         int h, i;
4987
4988         ASSERT_SERIALIZED(ifp->if_serializer);
4989
4990         /* Initialize receive mode default settings. */
4991         rx_mode = sc->rx_mode &
4992                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
4993                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
4994         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
4995
4996         /*
4997          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
4998          * be enbled.
4999          */
5000         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5001             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5002                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5003
5004         /*
5005          * Check for promiscuous, all multicast, or selected
5006          * multicast address filtering.
5007          */
5008         if (ifp->if_flags & IFF_PROMISC) {
5009                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5010
5011                 /* Enable promiscuous mode. */
5012                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5013                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5014         } else if (ifp->if_flags & IFF_ALLMULTI) {
5015                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5016
5017                 /* Enable all multicast addresses. */
5018                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5019                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5020                                0xffffffff);
5021                 }
5022                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5023         } else {
5024                 /* Accept one or more multicast(s). */
5025                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5026
5027                 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5028                         if (ifma->ifma_addr->sa_family != AF_LINK)
5029                                 continue;
5030                         h = ether_crc32_le(
5031                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5032                             ETHER_ADDR_LEN) & 0xFF;
5033                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5034                 }
5035
5036                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5037                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5038                                hashes[i]);
5039                 }
5040                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5041         }
5042
5043         /* Only make changes if the recive mode has actually changed. */
5044         if (rx_mode != sc->rx_mode) {
5045                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5046                         rx_mode);
5047
5048                 sc->rx_mode = rx_mode;
5049                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5050         }
5051
5052         /* Disable and clear the exisitng sort before enabling a new sort. */
5053         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5054         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5055         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5056 }
5057
5058
5059 /****************************************************************************/
5060 /* Called periodically to updates statistics from the controllers           */
5061 /* statistics block.                                                        */
5062 /*                                                                          */
5063 /* Returns:                                                                 */
5064 /*   Nothing.                                                               */
5065 /****************************************************************************/
5066 static void
5067 bce_stats_update(struct bce_softc *sc)
5068 {
5069         struct ifnet *ifp = &sc->arpcom.ac_if;
5070         struct statistics_block *stats = sc->stats_block;
5071
5072         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5073
5074         ASSERT_SERIALIZED(ifp->if_serializer);
5075
5076         /*
5077          * Update the interface statistics from the hardware statistics.
5078          */
5079         ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions;
5080
5081         ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts +
5082                           (u_long)stats->stat_EtherStatsOverrsizePkts +
5083                           (u_long)stats->stat_IfInMBUFDiscards +
5084                           (u_long)stats->stat_Dot3StatsAlignmentErrors +
5085                           (u_long)stats->stat_Dot3StatsFCSErrors;
5086
5087         ifp->if_oerrors =
5088         (u_long)stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5089         (u_long)stats->stat_Dot3StatsExcessiveCollisions +
5090         (u_long)stats->stat_Dot3StatsLateCollisions;
5091
5092         /*
5093          * Certain controllers don't report carrier sense errors correctly.
5094          * See errata E11_5708CA0_1165.
5095          */
5096         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5097             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5098                 ifp->if_oerrors +=
5099                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5100         }
5101
5102         /*
5103          * Update the sysctl statistics from the hardware statistics.
5104          */
5105         sc->stat_IfHCInOctets =
5106                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5107                  (uint64_t)stats->stat_IfHCInOctets_lo;
5108
5109         sc->stat_IfHCInBadOctets =
5110                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5111                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5112
5113         sc->stat_IfHCOutOctets =
5114                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5115                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5116
5117         sc->stat_IfHCOutBadOctets =
5118                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5119                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5120
5121         sc->stat_IfHCInUcastPkts =
5122                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5123                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5124
5125         sc->stat_IfHCInMulticastPkts =
5126                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5127                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5128
5129         sc->stat_IfHCInBroadcastPkts =
5130                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5131                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5132
5133         sc->stat_IfHCOutUcastPkts =
5134                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5135                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5136
5137         sc->stat_IfHCOutMulticastPkts =
5138                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5139                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5140
5141         sc->stat_IfHCOutBroadcastPkts =
5142                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5143                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5144
5145         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5146                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5147
5148         sc->stat_Dot3StatsCarrierSenseErrors =
5149                 stats->stat_Dot3StatsCarrierSenseErrors;
5150
5151         sc->stat_Dot3StatsFCSErrors =
5152                 stats->stat_Dot3StatsFCSErrors;
5153
5154         sc->stat_Dot3StatsAlignmentErrors =
5155                 stats->stat_Dot3StatsAlignmentErrors;
5156
5157         sc->stat_Dot3StatsSingleCollisionFrames =
5158                 stats->stat_Dot3StatsSingleCollisionFrames;
5159
5160         sc->stat_Dot3StatsMultipleCollisionFrames =
5161                 stats->stat_Dot3StatsMultipleCollisionFrames;
5162
5163         sc->stat_Dot3StatsDeferredTransmissions =
5164                 stats->stat_Dot3StatsDeferredTransmissions;
5165
5166         sc->stat_Dot3StatsExcessiveCollisions =
5167                 stats->stat_Dot3StatsExcessiveCollisions;
5168
5169         sc->stat_Dot3StatsLateCollisions =
5170                 stats->stat_Dot3StatsLateCollisions;
5171
5172         sc->stat_EtherStatsCollisions =
5173                 stats->stat_EtherStatsCollisions;
5174
5175         sc->stat_EtherStatsFragments =
5176                 stats->stat_EtherStatsFragments;
5177
5178         sc->stat_EtherStatsJabbers =
5179                 stats->stat_EtherStatsJabbers;
5180
5181         sc->stat_EtherStatsUndersizePkts =
5182                 stats->stat_EtherStatsUndersizePkts;
5183
5184         sc->stat_EtherStatsOverrsizePkts =
5185                 stats->stat_EtherStatsOverrsizePkts;
5186
5187         sc->stat_EtherStatsPktsRx64Octets =
5188                 stats->stat_EtherStatsPktsRx64Octets;
5189
5190         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5191                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5192
5193         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5194                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5195
5196         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5197                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5198
5199         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5200                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5201
5202         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5203                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5204
5205         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5206                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5207
5208         sc->stat_EtherStatsPktsTx64Octets =
5209                 stats->stat_EtherStatsPktsTx64Octets;
5210
5211         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5212                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5213
5214         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5215                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5216
5217         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5218                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5219
5220         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5221                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5222
5223         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5224                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5225
5226         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5227                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5228
5229         sc->stat_XonPauseFramesReceived =
5230                 stats->stat_XonPauseFramesReceived;
5231
5232         sc->stat_XoffPauseFramesReceived =
5233                 stats->stat_XoffPauseFramesReceived;
5234
5235         sc->stat_OutXonSent =
5236                 stats->stat_OutXonSent;
5237
5238         sc->stat_OutXoffSent =
5239                 stats->stat_OutXoffSent;
5240
5241         sc->stat_FlowControlDone =
5242                 stats->stat_FlowControlDone;
5243
5244         sc->stat_MacControlFramesReceived =
5245                 stats->stat_MacControlFramesReceived;
5246
5247         sc->stat_XoffStateEntered =
5248                 stats->stat_XoffStateEntered;
5249
5250         sc->stat_IfInFramesL2FilterDiscards =
5251                 stats->stat_IfInFramesL2FilterDiscards;
5252
5253         sc->stat_IfInRuleCheckerDiscards =
5254                 stats->stat_IfInRuleCheckerDiscards;
5255
5256         sc->stat_IfInFTQDiscards =
5257                 stats->stat_IfInFTQDiscards;
5258
5259         sc->stat_IfInMBUFDiscards =
5260                 stats->stat_IfInMBUFDiscards;
5261
5262         sc->stat_IfInRuleCheckerP4Hit =
5263                 stats->stat_IfInRuleCheckerP4Hit;
5264
5265         sc->stat_CatchupInRuleCheckerDiscards =
5266                 stats->stat_CatchupInRuleCheckerDiscards;
5267
5268         sc->stat_CatchupInFTQDiscards =
5269                 stats->stat_CatchupInFTQDiscards;
5270
5271         sc->stat_CatchupInMBUFDiscards =
5272                 stats->stat_CatchupInMBUFDiscards;
5273
5274         sc->stat_CatchupInRuleCheckerP4Hit =
5275                 stats->stat_CatchupInRuleCheckerP4Hit;
5276
5277         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5278
5279         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5280 }
5281
5282
5283 /****************************************************************************/
5284 /* Periodic function to perform maintenance tasks.                          */
5285 /*                                                                          */
5286 /* Returns:                                                                 */
5287 /*   Nothing.                                                               */
5288 /****************************************************************************/
5289 static void
5290 bce_tick_serialized(struct bce_softc *sc)
5291 {
5292         struct ifnet *ifp = &sc->arpcom.ac_if;
5293         struct mii_data *mii;
5294         uint32_t msg;
5295
5296         ASSERT_SERIALIZED(ifp->if_serializer);
5297
5298         /* Tell the firmware that the driver is still running. */
5299 #ifdef BCE_DEBUG
5300         msg = (uint32_t)BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE;
5301 #else
5302         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5303 #endif
5304         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
5305
5306         /* Update the statistics from the hardware statistics block. */
5307         bce_stats_update(sc);
5308
5309         /* Schedule the next tick. */
5310         callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
5311
5312         /* If link is up already up then we're done. */
5313         if (sc->bce_link)
5314                 return;
5315
5316         mii = device_get_softc(sc->bce_miibus);
5317         mii_tick(mii);
5318
5319         /* Check if the link has come up. */
5320         if (!sc->bce_link && (mii->mii_media_status & IFM_ACTIVE) &&
5321             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5322                 sc->bce_link++;
5323                 /* Now that link is up, handle any outstanding TX traffic. */
5324                 if (!ifq_is_empty(&ifp->if_snd))
5325                         if_devstart(ifp);
5326         }
5327 }
5328
5329
5330 static void
5331 bce_tick(void *xsc)
5332 {
5333         struct bce_softc *sc = xsc;
5334         struct ifnet *ifp = &sc->arpcom.ac_if;
5335
5336         lwkt_serialize_enter(ifp->if_serializer);
5337         bce_tick_serialized(sc);
5338         lwkt_serialize_exit(ifp->if_serializer);
5339 }
5340
5341
5342 #ifdef BCE_DEBUG
5343 /****************************************************************************/
5344 /* Allows the driver state to be dumped through the sysctl interface.       */
5345 /*                                                                          */
5346 /* Returns:                                                                 */
5347 /*   0 for success, positive value for failure.                             */
5348 /****************************************************************************/
5349 static int
5350 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5351 {
5352         int error;
5353         int result;
5354         struct bce_softc *sc;
5355
5356         result = -1;
5357         error = sysctl_handle_int(oidp, &result, 0, req);
5358
5359         if (error || !req->newptr)
5360                 return (error);
5361
5362         if (result == 1) {
5363                 sc = (struct bce_softc *)arg1;
5364                 bce_dump_driver_state(sc);
5365         }
5366
5367         return error;
5368 }
5369
5370
5371 /****************************************************************************/
5372 /* Allows the hardware state to be dumped through the sysctl interface.     */
5373 /*                                                                          */
5374 /* Returns:                                                                 */
5375 /*   0 for success, positive value for failure.                             */
5376 /****************************************************************************/
5377 static int
5378 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5379 {
5380         int error;
5381         int result;
5382         struct bce_softc *sc;
5383
5384         result = -1;
5385         error = sysctl_handle_int(oidp, &result, 0, req);
5386
5387         if (error || !req->newptr)
5388                 return (error);
5389
5390         if (result == 1) {
5391                 sc = (struct bce_softc *)arg1;
5392                 bce_dump_hw_state(sc);
5393         }
5394
5395         return error;
5396 }
5397
5398
5399 /****************************************************************************/
5400 /* Provides a sysctl interface to allows dumping the RX chain.              */
5401 /*                                                                          */
5402 /* Returns:                                                                 */
5403 /*   0 for success, positive value for failure.                             */
5404 /****************************************************************************/
5405 static int
5406 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5407 {
5408         int error;
5409         int result;
5410         struct bce_softc *sc;
5411
5412         result = -1;
5413         error = sysctl_handle_int(oidp, &result, 0, req);
5414
5415         if (error || !req->newptr)
5416                 return (error);
5417
5418         if (result == 1) {
5419                 sc = (struct bce_softc *)arg1;
5420                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5421         }
5422
5423         return error;
5424 }
5425
5426
5427 /****************************************************************************/
5428 /* Provides a sysctl interface to allows dumping the TX chain.              */
5429 /*                                                                          */
5430 /* Returns:                                                                 */
5431 /*   0 for success, positive value for failure.                             */
5432 /****************************************************************************/
5433 static int
5434 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5435 {
5436         int error;
5437         int result;
5438         struct bce_softc *sc;
5439
5440         result = -1;
5441         error = sysctl_handle_int(oidp, &result, 0, req);
5442
5443         if (error || !req->newptr)
5444                 return (error);
5445
5446         if (result == 1) {
5447                 sc = (struct bce_softc *)arg1;
5448                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5449         }
5450
5451         return error;
5452 }
5453
5454
5455 /****************************************************************************/
5456 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
5457 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
5458 /*                                                                          */
5459 /* Returns:                                                                 */
5460 /*   0 for success, positive value for failure.                             */
5461 /****************************************************************************/
5462 static int
5463 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5464 {
5465         struct bce_softc *sc;
5466         int error;
5467         uint32_t val, result;
5468
5469         result = -1;
5470         error = sysctl_handle_int(oidp, &result, 0, req);
5471         if (error || (req->newptr == NULL))
5472                 return (error);
5473
5474         /* Make sure the register is accessible. */
5475         if (result < 0x8000) {
5476                 sc = (struct bce_softc *)arg1;
5477                 val = REG_RD(sc, result);
5478                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5479                           result, val);
5480         } else if (result < 0x0280000) {
5481                 sc = (struct bce_softc *)arg1;
5482                 val = REG_RD_IND(sc, result);
5483                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5484                           result, val);
5485         }
5486         return (error);
5487 }
5488
5489
5490 /****************************************************************************/
5491 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */\r
5492 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */\r
5493 /*                                                                          */
5494 /* Returns:                                                                 */
5495 /*   0 for success, positive value for failure.                             */
5496 /****************************************************************************/
5497 static int
5498 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5499 {
5500         struct bce_softc *sc;
5501         device_t dev;
5502         int error, result;
5503         uint16_t val;
5504
5505         result = -1;
5506         error = sysctl_handle_int(oidp, &result, 0, req);
5507         if (error || (req->newptr == NULL))
5508                 return (error);
5509
5510         /* Make sure the register is accessible. */
5511         if (result < 0x20) {
5512                 sc = (struct bce_softc *)arg1;
5513                 dev = sc->bce_dev;
5514                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5515                 if_printf(&sc->arpcom.ac_if,
5516                           "phy 0x%02X = 0x%04X\n", result, val);
5517         }
5518         return (error);
5519 }
5520
5521
5522 /****************************************************************************/
5523 /* Provides a sysctl interface to forcing the driver to dump state and      */\r
5524 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
5525 /*                                                                          */
5526 /* Returns:                                                                 */
5527 /*   0 for success, positive value for failure.                             */
5528 /****************************************************************************/
5529 static int
5530 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5531 {
5532         int error;
5533         int result;
5534         struct bce_softc *sc;
5535
5536         result = -1;
5537         error = sysctl_handle_int(oidp, &result, 0, req);
5538
5539         if (error || !req->newptr)
5540                 return (error);
5541
5542         if (result == 1) {
5543                 sc = (struct bce_softc *)arg1;
5544                 bce_breakpoint(sc);
5545         }
5546
5547         return error;
5548 }
5549 #endif
5550
5551
5552 /****************************************************************************/
5553 /* Adds any sysctl parameters for tuning or debugging purposes.             */
5554 /*                                                                          */
5555 /* Returns:                                                                 */
5556 /*   0 for success, positive value for failure.                             */
5557 /****************************************************************************/
5558 static void
5559 bce_add_sysctls(struct bce_softc *sc)
5560 {
5561         struct sysctl_ctx_list *ctx;
5562         struct sysctl_oid_list *children;
5563
5564         sysctl_ctx_init(&sc->bce_sysctl_ctx);
5565         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5566                                               SYSCTL_STATIC_CHILDREN(_hw),
5567                                               OID_AUTO,
5568                                               device_get_nameunit(sc->bce_dev),
5569                                               CTLFLAG_RD, 0, "");
5570         if (sc->bce_sysctl_tree == NULL) {
5571                 device_printf(sc->bce_dev, "can't add sysctl node\n");
5572                 return;
5573         }
5574
5575         ctx = &sc->bce_sysctl_ctx;
5576         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5577
5578         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
5579                         CTLTYPE_INT | CTLFLAG_RW,
5580                         sc, 0, bce_sysctl_tx_bds_int, "I",
5581                         "Send max coalesced BD count during interrupt");
5582         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
5583                         CTLTYPE_INT | CTLFLAG_RW,
5584                         sc, 0, bce_sysctl_tx_bds, "I",
5585                         "Send max coalesced BD count");
5586         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
5587                         CTLTYPE_INT | CTLFLAG_RW,
5588                         sc, 0, bce_sysctl_tx_ticks_int, "I",
5589                         "Send coalescing ticks during interrupt");
5590         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
5591                         CTLTYPE_INT | CTLFLAG_RW,
5592                         sc, 0, bce_sysctl_tx_ticks, "I",
5593                         "Send coalescing ticks");
5594
5595         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
5596                         CTLTYPE_INT | CTLFLAG_RW,
5597                         sc, 0, bce_sysctl_rx_bds_int, "I",
5598                         "Receive max coalesced BD count during interrupt");
5599         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
5600                         CTLTYPE_INT | CTLFLAG_RW,
5601                         sc, 0, bce_sysctl_rx_bds, "I",
5602                         "Receive max coalesced BD count");
5603         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
5604                         CTLTYPE_INT | CTLFLAG_RW,
5605                         sc, 0, bce_sysctl_rx_ticks_int, "I",
5606                         "Receive coalescing ticks during interrupt");
5607         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
5608                         CTLTYPE_INT | CTLFLAG_RW,
5609                         sc, 0, bce_sysctl_rx_ticks, "I",
5610                         "Receive coalescing ticks");
5611
5612 #ifdef BCE_DEBUG
5613         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5614                 "rx_low_watermark",
5615                 CTLFLAG_RD, &sc->rx_low_watermark,
5616                 0, "Lowest level of free rx_bd's");
5617
5618         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5619                 "rx_empty_count",
5620                 CTLFLAG_RD, &sc->rx_empty_count,
5621                 0, "Number of times the RX chain was empty");
5622
5623         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5624                 "tx_hi_watermark",
5625                 CTLFLAG_RD, &sc->tx_hi_watermark,
5626                 0, "Highest level of used tx_bd's");
5627
5628         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5629                 "tx_full_count",
5630                 CTLFLAG_RD, &sc->tx_full_count,
5631                 0, "Number of times the TX chain was full");
5632
5633         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5634                 "l2fhdr_status_errors",
5635                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
5636                 0, "l2_fhdr status errors");
5637
5638         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5639                 "unexpected_attentions",
5640                 CTLFLAG_RD, &sc->unexpected_attentions,
5641                 0, "unexpected attentions");
5642
5643         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5644                 "lost_status_block_updates",
5645                 CTLFLAG_RD, &sc->lost_status_block_updates,
5646                 0, "lost status block updates");
5647
5648         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5649                 "mbuf_alloc_failed",
5650                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
5651                 0, "mbuf cluster allocation failures");
5652 #endif
5653
5654         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5655                 "stat_IfHCInOctets",
5656                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
5657                 "Bytes received");
5658
5659         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5660                 "stat_IfHCInBadOctets",
5661                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
5662                 "Bad bytes received");
5663
5664         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5665                 "stat_IfHCOutOctets",
5666                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
5667                 "Bytes sent");
5668
5669         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5670                 "stat_IfHCOutBadOctets",
5671                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
5672                 "Bad bytes sent");
5673
5674         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5675                 "stat_IfHCInUcastPkts",
5676                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
5677                 "Unicast packets received");
5678
5679         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5680                 "stat_IfHCInMulticastPkts",
5681                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
5682                 "Multicast packets received");
5683
5684         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5685                 "stat_IfHCInBroadcastPkts",
5686                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
5687                 "Broadcast packets received");
5688
5689         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5690                 "stat_IfHCOutUcastPkts",
5691                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
5692                 "Unicast packets sent");
5693
5694         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5695                 "stat_IfHCOutMulticastPkts",
5696                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
5697                 "Multicast packets sent");
5698
5699         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5700                 "stat_IfHCOutBroadcastPkts",
5701                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
5702                 "Broadcast packets sent");
5703
5704         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5705                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
5706                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
5707                 0, "Internal MAC transmit errors");
5708
5709         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5710                 "stat_Dot3StatsCarrierSenseErrors",
5711                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
5712                 0, "Carrier sense errors");
5713
5714         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5715                 "stat_Dot3StatsFCSErrors",
5716                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
5717                 0, "Frame check sequence errors");
5718
5719         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5720                 "stat_Dot3StatsAlignmentErrors",
5721                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
5722                 0, "Alignment errors");
5723
5724         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5725                 "stat_Dot3StatsSingleCollisionFrames",
5726                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
5727                 0, "Single Collision Frames");
5728
5729         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5730                 "stat_Dot3StatsMultipleCollisionFrames",
5731                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
5732                 0, "Multiple Collision Frames");
5733
5734         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5735                 "stat_Dot3StatsDeferredTransmissions",
5736                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
5737                 0, "Deferred Transmissions");
5738
5739         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5740                 "stat_Dot3StatsExcessiveCollisions",
5741                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
5742                 0, "Excessive Collisions");
5743
5744         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5745                 "stat_Dot3StatsLateCollisions",
5746                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
5747                 0, "Late Collisions");
5748
5749         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5750                 "stat_EtherStatsCollisions",
5751                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
5752                 0, "Collisions");
5753
5754         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5755                 "stat_EtherStatsFragments",
5756                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
5757                 0, "Fragments");
5758
5759         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5760                 "stat_EtherStatsJabbers",
5761                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
5762                 0, "Jabbers");
5763
5764         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5765                 "stat_EtherStatsUndersizePkts",
5766                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
5767                 0, "Undersize packets");
5768
5769         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5770                 "stat_EtherStatsOverrsizePkts",
5771                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
5772                 0, "stat_EtherStatsOverrsizePkts");
5773
5774         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5775                 "stat_EtherStatsPktsRx64Octets",
5776                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
5777                 0, "Bytes received in 64 byte packets");
5778
5779         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5780                 "stat_EtherStatsPktsRx65Octetsto127Octets",
5781                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
5782                 0, "Bytes received in 65 to 127 byte packets");
5783
5784         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5785                 "stat_EtherStatsPktsRx128Octetsto255Octets",
5786                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
5787                 0, "Bytes received in 128 to 255 byte packets");
5788
5789         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5790                 "stat_EtherStatsPktsRx256Octetsto511Octets",
5791                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
5792                 0, "Bytes received in 256 to 511 byte packets");
5793
5794         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5795                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
5796                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
5797                 0, "Bytes received in 512 to 1023 byte packets");
5798
5799         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5800                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
5801                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
5802                 0, "Bytes received in 1024 t0 1522 byte packets");
5803
5804         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5805                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
5806                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
5807                 0, "Bytes received in 1523 to 9022 byte packets");
5808
5809         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5810                 "stat_EtherStatsPktsTx64Octets",
5811                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
5812                 0, "Bytes sent in 64 byte packets");
5813
5814         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5815                 "stat_EtherStatsPktsTx65Octetsto127Octets",
5816                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
5817                 0, "Bytes sent in 65 to 127 byte packets");
5818
5819         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5820                 "stat_EtherStatsPktsTx128Octetsto255Octets",
5821                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
5822                 0, "Bytes sent in 128 to 255 byte packets");
5823
5824         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5825                 "stat_EtherStatsPktsTx256Octetsto511Octets",
5826                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
5827                 0, "Bytes sent in 256 to 511 byte packets");
5828
5829         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5830                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
5831                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
5832                 0, "Bytes sent in 512 to 1023 byte packets");
5833
5834         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5835                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
5836                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
5837                 0, "Bytes sent in 1024 to 1522 byte packets");
5838
5839         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5840                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
5841                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
5842                 0, "Bytes sent in 1523 to 9022 byte packets");
5843
5844         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5845                 "stat_XonPauseFramesReceived",
5846                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
5847                 0, "XON pause frames receved");
5848
5849         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5850                 "stat_XoffPauseFramesReceived",
5851                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
5852                 0, "XOFF pause frames received");
5853
5854         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5855                 "stat_OutXonSent",
5856                 CTLFLAG_RD, &sc->stat_OutXonSent,
5857                 0, "XON pause frames sent");
5858
5859         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5860                 "stat_OutXoffSent",
5861                 CTLFLAG_RD, &sc->stat_OutXoffSent,
5862                 0, "XOFF pause frames sent");
5863
5864         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5865                 "stat_FlowControlDone",
5866                 CTLFLAG_RD, &sc->stat_FlowControlDone,
5867                 0, "Flow control done");
5868
5869         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5870                 "stat_MacControlFramesReceived",
5871                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
5872                 0, "MAC control frames received");
5873
5874         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5875                 "stat_XoffStateEntered",
5876                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
5877                 0, "XOFF state entered");
5878
5879         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5880                 "stat_IfInFramesL2FilterDiscards",
5881                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
5882                 0, "Received L2 packets discarded");
5883
5884         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5885                 "stat_IfInRuleCheckerDiscards",
5886                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
5887                 0, "Received packets discarded by rule");
5888
5889         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5890                 "stat_IfInFTQDiscards",
5891                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
5892                 0, "Received packet FTQ discards");
5893
5894         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5895                 "stat_IfInMBUFDiscards",
5896                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
5897                 0, "Received packets discarded due to lack of controller buffer memory");
5898
5899         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5900                 "stat_IfInRuleCheckerP4Hit",
5901                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
5902                 0, "Received packets rule checker hits");
5903
5904         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5905                 "stat_CatchupInRuleCheckerDiscards",
5906                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
5907                 0, "Received packets discarded in Catchup path");
5908
5909         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5910                 "stat_CatchupInFTQDiscards",
5911                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
5912                 0, "Received packets discarded in FTQ in Catchup path");
5913
5914         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5915                 "stat_CatchupInMBUFDiscards",
5916                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
5917                 0, "Received packets discarded in controller buffer memory in Catchup path");
5918
5919         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5920                 "stat_CatchupInRuleCheckerP4Hit",
5921                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
5922                 0, "Received packets rule checker hits in Catchup path");
5923
5924         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5925                 "com_no_buffers",
5926                 CTLFLAG_RD, &sc->com_no_buffers,
5927                 0, "Valid packets received but no RX buffers available");
5928
5929 #ifdef BCE_DEBUG
5930         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5931                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
5932                 (void *)sc, 0,
5933                 bce_sysctl_driver_state, "I", "Drive state information");
5934
5935         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5936                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
5937                 (void *)sc, 0,
5938                 bce_sysctl_hw_state, "I", "Hardware state information");
5939
5940         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5941                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
5942                 (void *)sc, 0,
5943                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
5944
5945         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5946                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
5947                 (void *)sc, 0,
5948                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
5949
5950         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5951                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
5952                 (void *)sc, 0,
5953                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
5954
5955         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5956                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
5957                 (void *)sc, 0,
5958                 bce_sysctl_reg_read, "I", "Register read");
5959
5960         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, \r
5961                 "phy_read", CTLTYPE_INT | CTLFLAG_RW, \r
5962                 (void *)sc, 0, \r
5963                 bce_sysctl_phy_read, "I", "PHY register read");
5964
5965 #endif
5966
5967 }
5968
5969
5970 /****************************************************************************/
5971 /* BCE Debug Routines                                                       */
5972 /****************************************************************************/
5973 #ifdef BCE_DEBUG
5974
5975 /****************************************************************************/
5976 /* Freezes the controller to allow for a cohesive state dump.               */
5977 /*                                                                          */
5978 /* Returns:                                                                 */
5979 /*   Nothing.                                                               */
5980 /****************************************************************************/
5981 static void
5982 bce_freeze_controller(struct bce_softc *sc)
5983 {
5984         uint32_t val;
5985
5986         val = REG_RD(sc, BCE_MISC_COMMAND);
5987         val |= BCE_MISC_COMMAND_DISABLE_ALL;
5988         REG_WR(sc, BCE_MISC_COMMAND, val);
5989 }
5990
5991
5992 /****************************************************************************/
5993 /* Unfreezes the controller after a freeze operation.  This may not always  */\r
5994 /* work and the controller will require a reset!                            */
5995 /*                                                                          */
5996 /* Returns:                                                                 */
5997 /*   Nothing.                                                               */
5998 /****************************************************************************/
5999 static void
6000 bce_unfreeze_controller(struct bce_softc *sc)
6001 {
6002         uint32_t val;
6003
6004         val = REG_RD(sc, BCE_MISC_COMMAND);
6005         val |= BCE_MISC_COMMAND_ENABLE_ALL;
6006         REG_WR(sc, BCE_MISC_COMMAND, val);
6007 }
6008
6009
6010 /****************************************************************************/
6011 /* Prints out information about an mbuf.                                    */
6012 /*                                                                          */
6013 /* Returns:                                                                 */
6014 /*   Nothing.                                                               */
6015 /****************************************************************************/
6016 static void
6017 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6018 {
6019         struct ifnet *ifp = &sc->arpcom.ac_if;
6020         uint32_t val_hi, val_lo;
6021         struct mbuf *mp = m;
6022
6023         if (m == NULL) {
6024                 /* Index out of range. */
6025                 if_printf(ifp, "mbuf: null pointer\n");
6026                 return;
6027         }
6028
6029         while (mp) {
6030                 val_hi = BCE_ADDR_HI(mp);
6031                 val_lo = BCE_ADDR_LO(mp);
6032                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6033                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
6034
6035                 if (mp->m_flags & M_EXT)
6036                         kprintf("M_EXT ");
6037                 if (mp->m_flags & M_PKTHDR)
6038                         kprintf("M_PKTHDR ");
6039                 if (mp->m_flags & M_EOR)
6040                         kprintf("M_EOR ");
6041 #ifdef M_RDONLY
6042                 if (mp->m_flags & M_RDONLY)
6043                         kprintf("M_RDONLY ");
6044 #endif
6045
6046                 val_hi = BCE_ADDR_HI(mp->m_data);
6047                 val_lo = BCE_ADDR_LO(mp->m_data);
6048                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6049
6050                 if (mp->m_flags & M_PKTHDR) {
6051                         if_printf(ifp, "- m_pkthdr: flags = ( ");
6052                         if (mp->m_flags & M_BCAST)
6053                                 kprintf("M_BCAST ");
6054                         if (mp->m_flags & M_MCAST)
6055                                 kprintf("M_MCAST ");
6056                         if (mp->m_flags & M_FRAG)
6057                                 kprintf("M_FRAG ");
6058                         if (mp->m_flags & M_FIRSTFRAG)
6059                                 kprintf("M_FIRSTFRAG ");
6060                         if (mp->m_flags & M_LASTFRAG)
6061                                 kprintf("M_LASTFRAG ");
6062 #ifdef M_VLANTAG
6063                         if (mp->m_flags & M_VLANTAG)
6064                                 kprintf("M_VLANTAG ");
6065 #endif
6066 #ifdef M_PROMISC
6067                         if (mp->m_flags & M_PROMISC)
6068                                 kprintf("M_PROMISC ");
6069 #endif
6070                         kprintf(") csum_flags = ( ");
6071                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
6072                                 kprintf("CSUM_IP ");
6073                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6074                                 kprintf("CSUM_TCP ");
6075                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6076                                 kprintf("CSUM_UDP ");
6077                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6078                                 kprintf("CSUM_IP_FRAGS ");
6079                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6080                                 kprintf("CSUM_FRAGMENT ");
6081 #ifdef CSUM_TSO
6082                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6083                                 kprintf("CSUM_TSO ");
6084 #endif
6085                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6086                                 kprintf("CSUM_IP_CHECKED ");
6087                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6088                                 kprintf("CSUM_IP_VALID ");
6089                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6090                                 kprintf("CSUM_DATA_VALID ");
6091                         kprintf(")\n");
6092                 }
6093
6094                 if (mp->m_flags & M_EXT) {
6095                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6096                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6097                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6098                                   "ext_size = %d\n",
6099                                   val_hi, val_lo, mp->m_ext.ext_size);
6100                 }
6101                 mp = mp->m_next;
6102         }
6103 }
6104
6105
6106 /****************************************************************************/
6107 /* Prints out the mbufs in the TX mbuf chain.                               */
6108 /*                                                                          */
6109 /* Returns:                                                                 */
6110 /*   Nothing.                                                               */
6111 /****************************************************************************/
6112 static void
6113 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6114 {
6115         struct ifnet *ifp = &sc->arpcom.ac_if;
6116         int i;
6117
6118         if_printf(ifp,
6119         "----------------------------"
6120         "  tx mbuf data  "
6121         "----------------------------\n");
6122
6123         for (i = 0; i < count; i++) {
6124                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6125                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6126                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6127         }
6128
6129         if_printf(ifp,
6130         "----------------------------"
6131         "----------------"
6132         "----------------------------\n");
6133 }
6134
6135
6136 /****************************************************************************/
6137 /* Prints out the mbufs in the RX mbuf chain.                               */
6138 /*                                                                          */
6139 /* Returns:                                                                 */
6140 /*   Nothing.                                                               */
6141 /****************************************************************************/
6142 static void
6143 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6144 {
6145         struct ifnet *ifp = &sc->arpcom.ac_if;
6146         int i;
6147
6148         if_printf(ifp,
6149         "----------------------------"
6150         "  rx mbuf data  "
6151         "----------------------------\n");
6152
6153         for (i = 0; i < count; i++) {
6154                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6155                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6156                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6157         }
6158
6159         if_printf(ifp,
6160         "----------------------------"
6161         "----------------"
6162         "----------------------------\n");
6163 }
6164
6165
6166 /****************************************************************************/
6167 /* Prints out a tx_bd structure.                                            */
6168 /*                                                                          */
6169 /* Returns:                                                                 */
6170 /*   Nothing.                                                               */
6171 /****************************************************************************/
6172 static void
6173 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6174 {
6175         struct ifnet *ifp = &sc->arpcom.ac_if;
6176
6177         if (idx > MAX_TX_BD) {
6178                 /* Index out of range. */
6179                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6180         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6181                 /* TX Chain page pointer. */
6182                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6183                           "chain page pointer\n",
6184                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6185         } else {
6186                 /* Normal tx_bd entry. */
6187                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6188                           "nbytes = 0x%08X, "
6189                           "vlan tag= 0x%04X, flags = 0x%04X (",
6190                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6191                           txbd->tx_bd_mss_nbytes,
6192                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6193
6194                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6195                         kprintf(" CONN_FAULT");
6196
6197                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6198                         kprintf(" TCP_UDP_CKSUM");
6199
6200                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6201                         kprintf(" IP_CKSUM");
6202
6203                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6204                         kprintf("  VLAN");
6205
6206                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6207                         kprintf(" COAL_NOW");
6208
6209                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6210                         kprintf(" DONT_GEN_CRC");
6211
6212                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6213                         kprintf(" START");
6214
6215                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6216                         kprintf(" END");
6217
6218                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6219                         kprintf(" LSO");
6220
6221                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6222                         kprintf(" OPTION_WORD");
6223
6224                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6225                         kprintf(" FLAGS");
6226
6227                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6228                         kprintf(" SNAP");
6229
6230                 kprintf(" )\n");
6231         }
6232 }
6233
6234
6235 /****************************************************************************/
6236 /* Prints out a rx_bd structure.                                            */
6237 /*                                                                          */
6238 /* Returns:                                                                 */
6239 /*   Nothing.                                                               */
6240 /****************************************************************************/
6241 static void
6242 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6243 {
6244         struct ifnet *ifp = &sc->arpcom.ac_if;
6245
6246         if (idx > MAX_RX_BD) {
6247                 /* Index out of range. */
6248                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6249         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6250                 /* TX Chain page pointer. */
6251                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6252                           "chain page pointer\n",
6253                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6254         } else {
6255                 /* Normal tx_bd entry. */
6256                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6257                           "nbytes = 0x%08X, flags = 0x%08X\n",
6258                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6259                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6260         }
6261 }
6262
6263
6264 /****************************************************************************/
6265 /* Prints out a l2_fhdr structure.                                          */
6266 /*                                                                          */
6267 /* Returns:                                                                 */
6268 /*   Nothing.                                                               */
6269 /****************************************************************************/
6270 static void
6271 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6272 {
6273         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6274                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6275                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6276                   idx, l2fhdr->l2_fhdr_status,
6277                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6278                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6279 }
6280
6281
6282 /****************************************************************************/
6283 /* Prints out the tx chain.                                                 */
6284 /*                                                                          */
6285 /* Returns:                                                                 */
6286 /*   Nothing.                                                               */
6287 /****************************************************************************/
6288 static void
6289 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6290 {
6291         struct ifnet *ifp = &sc->arpcom.ac_if;
6292         int i;
6293
6294         /* First some info about the tx_bd chain structure. */
6295         if_printf(ifp,
6296         "----------------------------"
6297         "  tx_bd  chain  "
6298         "----------------------------\n");
6299
6300         if_printf(ifp, "page size      = 0x%08X, "
6301                   "tx chain pages        = 0x%08X\n",
6302                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6303
6304         if_printf(ifp, "tx_bd per page = 0x%08X, "
6305                   "usable tx_bd per page = 0x%08X\n",
6306                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6307                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6308
6309         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6310
6311         if_printf(ifp,
6312         "----------------------------"
6313         "  tx_bd data    "
6314         "----------------------------\n");
6315
6316         /* Now print out the tx_bd's themselves. */
6317         for (i = 0; i < count; i++) {
6318                 struct tx_bd *txbd;
6319
6320                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6321                 bce_dump_txbd(sc, tx_prod, txbd);
6322                 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6323         }
6324
6325         if_printf(ifp,
6326         "----------------------------"
6327         "----------------"
6328         "----------------------------\n");
6329 }
6330
6331
6332 /****************************************************************************/
6333 /* Prints out the rx chain.                                                 */
6334 /*                                                                          */
6335 /* Returns:                                                                 */
6336 /*   Nothing.                                                               */
6337 /****************************************************************************/
6338 static void
6339 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6340 {
6341         struct ifnet *ifp = &sc->arpcom.ac_if;
6342         int i;
6343
6344         /* First some info about the tx_bd chain structure. */
6345         if_printf(ifp,
6346         "----------------------------"
6347         "  rx_bd  chain  "
6348         "----------------------------\n");
6349
6350         if_printf(ifp, "page size      = 0x%08X, "
6351                   "rx chain pages        = 0x%08X\n",
6352                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6353
6354         if_printf(ifp, "rx_bd per page = 0x%08X, "
6355                   "usable rx_bd per page = 0x%08X\n",
6356                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6357                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6358
6359         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6360
6361         if_printf(ifp,
6362         "----------------------------"
6363         "   rx_bd data   "
6364         "----------------------------\n");
6365
6366         /* Now print out the rx_bd's themselves. */
6367         for (i = 0; i < count; i++) {
6368                 struct rx_bd *rxbd;
6369
6370                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6371                 bce_dump_rxbd(sc, rx_prod, rxbd);
6372                 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6373         }
6374
6375         if_printf(ifp,
6376         "----------------------------"
6377         "----------------"
6378         "----------------------------\n");
6379 }
6380
6381
6382 /****************************************************************************/
6383 /* Prints out the status block from host memory.                            */
6384 /*                                                                          */
6385 /* Returns:                                                                 */
6386 /*   Nothing.                                                               */
6387 /****************************************************************************/
6388 static void
6389 bce_dump_status_block(struct bce_softc *sc)
6390 {
6391         struct status_block *sblk = sc->status_block;
6392         struct ifnet *ifp = &sc->arpcom.ac_if;
6393
6394         if_printf(ifp,
6395         "----------------------------"
6396         "  Status Block  "
6397         "----------------------------\n");
6398
6399         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6400
6401         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6402                   sblk->status_attn_bits_ack);
6403
6404         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6405             sblk->status_rx_quick_consumer_index0,
6406             (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6407
6408         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6409             sblk->status_tx_quick_consumer_index0,
6410             (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6411
6412         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6413
6414         /* Theses indices are not used for normal L2 drivers. */
6415         if (sblk->status_rx_quick_consumer_index1) {
6416                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6417                 sblk->status_rx_quick_consumer_index1,
6418                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6419         }
6420
6421         if (sblk->status_tx_quick_consumer_index1) {
6422                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6423                 sblk->status_tx_quick_consumer_index1,
6424                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6425         }
6426
6427         if (sblk->status_rx_quick_consumer_index2) {
6428                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6429                 sblk->status_rx_quick_consumer_index2,
6430                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6431         }
6432
6433         if (sblk->status_tx_quick_consumer_index2) {
6434                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6435                 sblk->status_tx_quick_consumer_index2,
6436                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6437         }
6438
6439         if (sblk->status_rx_quick_consumer_index3) {
6440                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6441                 sblk->status_rx_quick_consumer_index3,
6442                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6443         }
6444
6445         if (sblk->status_tx_quick_consumer_index3) {
6446                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6447                 sblk->status_tx_quick_consumer_index3,
6448                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6449         }
6450
6451         if (sblk->status_rx_quick_consumer_index4 ||
6452             sblk->status_rx_quick_consumer_index5) {
6453                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
6454                           sblk->status_rx_quick_consumer_index4,
6455                           sblk->status_rx_quick_consumer_index5);
6456         }
6457
6458         if (sblk->status_rx_quick_consumer_index6 ||
6459             sblk->status_rx_quick_consumer_index7) {
6460                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
6461                           sblk->status_rx_quick_consumer_index6,
6462                           sblk->status_rx_quick_consumer_index7);
6463         }
6464
6465         if (sblk->status_rx_quick_consumer_index8 ||
6466             sblk->status_rx_quick_consumer_index9) {
6467                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
6468                           sblk->status_rx_quick_consumer_index8,
6469                           sblk->status_rx_quick_consumer_index9);
6470         }
6471
6472         if (sblk->status_rx_quick_consumer_index10 ||
6473             sblk->status_rx_quick_consumer_index11) {
6474                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
6475                           sblk->status_rx_quick_consumer_index10,
6476                           sblk->status_rx_quick_consumer_index11);
6477         }
6478
6479         if (sblk->status_rx_quick_consumer_index12 ||
6480             sblk->status_rx_quick_consumer_index13) {
6481                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
6482                           sblk->status_rx_quick_consumer_index12,
6483                           sblk->status_rx_quick_consumer_index13);
6484         }
6485
6486         if (sblk->status_rx_quick_consumer_index14 ||
6487             sblk->status_rx_quick_consumer_index15) {
6488                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
6489                           sblk->status_rx_quick_consumer_index14,
6490                           sblk->status_rx_quick_consumer_index15);
6491         }
6492
6493         if (sblk->status_completion_producer_index ||
6494             sblk->status_cmd_consumer_index) {
6495                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
6496                           sblk->status_completion_producer_index,
6497                           sblk->status_cmd_consumer_index);
6498         }
6499
6500         if_printf(ifp,
6501         "----------------------------"
6502         "----------------"
6503         "----------------------------\n");
6504 }
6505
6506
6507 /****************************************************************************/
6508 /* Prints out the statistics block.                                         */
6509 /*                                                                          */
6510 /* Returns:                                                                 */
6511 /*   Nothing.                                                               */
6512 /****************************************************************************/
6513 static void
6514 bce_dump_stats_block(struct bce_softc *sc)
6515 {
6516         struct statistics_block *sblk = sc->stats_block;
6517         struct ifnet *ifp = &sc->arpcom.ac_if;
6518
6519         if_printf(ifp,
6520         "---------------"
6521         " Stats Block  (All Stats Not Shown Are 0) "
6522         "---------------\n");
6523
6524         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6525                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6526                           sblk->stat_IfHCInOctets_hi,
6527                           sblk->stat_IfHCInOctets_lo);
6528         }
6529
6530         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6531                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6532                           sblk->stat_IfHCInBadOctets_hi,
6533                           sblk->stat_IfHCInBadOctets_lo);
6534         }
6535
6536         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6537                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6538                           sblk->stat_IfHCOutOctets_hi,
6539                           sblk->stat_IfHCOutOctets_lo);
6540         }
6541
6542         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6543                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6544                           sblk->stat_IfHCOutBadOctets_hi,
6545                           sblk->stat_IfHCOutBadOctets_lo);
6546         }
6547
6548         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
6549                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
6550                           sblk->stat_IfHCInUcastPkts_hi,
6551                           sblk->stat_IfHCInUcastPkts_lo);
6552         }
6553
6554         if (sblk->stat_IfHCInBroadcastPkts_hi ||
6555             sblk->stat_IfHCInBroadcastPkts_lo) {
6556                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
6557                           sblk->stat_IfHCInBroadcastPkts_hi,
6558                           sblk->stat_IfHCInBroadcastPkts_lo);
6559         }
6560
6561         if (sblk->stat_IfHCInMulticastPkts_hi ||
6562             sblk->stat_IfHCInMulticastPkts_lo) {
6563                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
6564                           sblk->stat_IfHCInMulticastPkts_hi,
6565                           sblk->stat_IfHCInMulticastPkts_lo);
6566         }
6567
6568         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
6569                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
6570                           sblk->stat_IfHCOutUcastPkts_hi,
6571                           sblk->stat_IfHCOutUcastPkts_lo);
6572         }
6573
6574         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
6575             sblk->stat_IfHCOutBroadcastPkts_lo) {
6576                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
6577                           sblk->stat_IfHCOutBroadcastPkts_hi,
6578                           sblk->stat_IfHCOutBroadcastPkts_lo);
6579         }
6580
6581         if (sblk->stat_IfHCOutMulticastPkts_hi ||
6582             sblk->stat_IfHCOutMulticastPkts_lo) {
6583                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
6584                           sblk->stat_IfHCOutMulticastPkts_hi,
6585                           sblk->stat_IfHCOutMulticastPkts_lo);
6586         }
6587
6588         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
6589                 if_printf(ifp, "         0x%08X : "
6590                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
6591                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
6592         }
6593
6594         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
6595                 if_printf(ifp, "         0x%08X : "
6596                           "Dot3StatsCarrierSenseErrors\n",
6597                           sblk->stat_Dot3StatsCarrierSenseErrors);
6598         }
6599
6600         if (sblk->stat_Dot3StatsFCSErrors) {
6601                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
6602                           sblk->stat_Dot3StatsFCSErrors);
6603         }
6604
6605         if (sblk->stat_Dot3StatsAlignmentErrors) {
6606                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
6607                           sblk->stat_Dot3StatsAlignmentErrors);
6608         }
6609
6610         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
6611                 if_printf(ifp, "         0x%08X : "
6612                           "Dot3StatsSingleCollisionFrames\n",
6613                           sblk->stat_Dot3StatsSingleCollisionFrames);
6614         }
6615
6616         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
6617                 if_printf(ifp, "         0x%08X : "
6618                           "Dot3StatsMultipleCollisionFrames\n",
6619                           sblk->stat_Dot3StatsMultipleCollisionFrames);
6620         }
6621
6622         if (sblk->stat_Dot3StatsDeferredTransmissions) {
6623                 if_printf(ifp, "         0x%08X : "
6624                           "Dot3StatsDeferredTransmissions\n",
6625                           sblk->stat_Dot3StatsDeferredTransmissions);
6626         }
6627
6628         if (sblk->stat_Dot3StatsExcessiveCollisions) {
6629                 if_printf(ifp, "         0x%08X : "
6630                           "Dot3StatsExcessiveCollisions\n",
6631                           sblk->stat_Dot3StatsExcessiveCollisions);
6632         }
6633
6634         if (sblk->stat_Dot3StatsLateCollisions) {
6635                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
6636                           sblk->stat_Dot3StatsLateCollisions);
6637         }
6638
6639         if (sblk->stat_EtherStatsCollisions) {
6640                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
6641                           sblk->stat_EtherStatsCollisions);
6642         }
6643
6644         if (sblk->stat_EtherStatsFragments)  {
6645                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
6646                           sblk->stat_EtherStatsFragments);
6647         }
6648
6649         if (sblk->stat_EtherStatsJabbers) {
6650                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
6651                           sblk->stat_EtherStatsJabbers);
6652         }
6653
6654         if (sblk->stat_EtherStatsUndersizePkts) {
6655                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
6656                           sblk->stat_EtherStatsUndersizePkts);
6657         }
6658
6659         if (sblk->stat_EtherStatsOverrsizePkts) {
6660                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
6661                           sblk->stat_EtherStatsOverrsizePkts);
6662         }
6663
6664         if (sblk->stat_EtherStatsPktsRx64Octets) {
6665                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
6666                           sblk->stat_EtherStatsPktsRx64Octets);
6667         }
6668
6669         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
6670                 if_printf(ifp, "         0x%08X : "
6671                           "EtherStatsPktsRx65Octetsto127Octets\n",
6672                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
6673         }
6674
6675         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
6676                 if_printf(ifp, "         0x%08X : "
6677                           "EtherStatsPktsRx128Octetsto255Octets\n",
6678                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
6679         }
6680
6681         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
6682                 if_printf(ifp, "         0x%08X : "
6683                           "EtherStatsPktsRx256Octetsto511Octets\n",
6684                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
6685         }
6686
6687         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
6688                 if_printf(ifp, "         0x%08X : "
6689                           "EtherStatsPktsRx512Octetsto1023Octets\n",
6690                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
6691         }
6692
6693         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
6694                 if_printf(ifp, "         0x%08X : "
6695                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
6696                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
6697         }
6698
6699         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
6700                 if_printf(ifp, "         0x%08X : "
6701                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
6702                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
6703         }
6704
6705         if (sblk->stat_EtherStatsPktsTx64Octets) {
6706                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
6707                           sblk->stat_EtherStatsPktsTx64Octets);
6708         }
6709
6710         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
6711                 if_printf(ifp, "         0x%08X : "
6712                           "EtherStatsPktsTx65Octetsto127Octets\n",
6713                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
6714         }
6715
6716         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
6717                 if_printf(ifp, "         0x%08X : "
6718                           "EtherStatsPktsTx128Octetsto255Octets\n",
6719                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
6720         }
6721
6722         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
6723                 if_printf(ifp, "         0x%08X : "
6724                           "EtherStatsPktsTx256Octetsto511Octets\n",
6725                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
6726         }
6727
6728         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
6729                 if_printf(ifp, "         0x%08X : "
6730                           "EtherStatsPktsTx512Octetsto1023Octets\n",
6731                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
6732         }
6733
6734         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
6735                 if_printf(ifp, "         0x%08X : "
6736                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
6737                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
6738         }
6739
6740         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
6741                 if_printf(ifp, "         0x%08X : "
6742                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
6743                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
6744         }
6745
6746         if (sblk->stat_XonPauseFramesReceived) {
6747                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
6748                           sblk->stat_XonPauseFramesReceived);
6749         }
6750
6751         if (sblk->stat_XoffPauseFramesReceived) {
6752                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
6753                           sblk->stat_XoffPauseFramesReceived);
6754         }
6755
6756         if (sblk->stat_OutXonSent) {
6757                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
6758                           sblk->stat_OutXonSent);
6759         }
6760
6761         if (sblk->stat_OutXoffSent) {
6762                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
6763                           sblk->stat_OutXoffSent);
6764         }
6765
6766         if (sblk->stat_FlowControlDone) {
6767                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
6768                           sblk->stat_FlowControlDone);
6769         }
6770
6771         if (sblk->stat_MacControlFramesReceived) {
6772                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
6773                           sblk->stat_MacControlFramesReceived);
6774         }
6775
6776         if (sblk->stat_XoffStateEntered) {
6777                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
6778                           sblk->stat_XoffStateEntered);
6779         }
6780
6781         if (sblk->stat_IfInFramesL2FilterDiscards) {
6782                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
6783         }
6784
6785         if (sblk->stat_IfInRuleCheckerDiscards) {
6786                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
6787                           sblk->stat_IfInRuleCheckerDiscards);
6788         }
6789
6790         if (sblk->stat_IfInFTQDiscards) {
6791                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
6792                           sblk->stat_IfInFTQDiscards);
6793         }
6794
6795         if (sblk->stat_IfInMBUFDiscards) {
6796                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
6797                           sblk->stat_IfInMBUFDiscards);
6798         }
6799
6800         if (sblk->stat_IfInRuleCheckerP4Hit) {
6801                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
6802                           sblk->stat_IfInRuleCheckerP4Hit);
6803         }
6804
6805         if (sblk->stat_CatchupInRuleCheckerDiscards) {
6806                 if_printf(ifp, "         0x%08X : "
6807                           "CatchupInRuleCheckerDiscards\n",
6808                           sblk->stat_CatchupInRuleCheckerDiscards);
6809         }
6810
6811         if (sblk->stat_CatchupInFTQDiscards) {
6812                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
6813                           sblk->stat_CatchupInFTQDiscards);
6814         }
6815
6816         if (sblk->stat_CatchupInMBUFDiscards) {
6817                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
6818                           sblk->stat_CatchupInMBUFDiscards);
6819         }
6820
6821         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
6822                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
6823                           sblk->stat_CatchupInRuleCheckerP4Hit);
6824         }
6825
6826         if_printf(ifp,
6827         "----------------------------"
6828         "----------------"
6829         "----------------------------\n");
6830 }
6831
6832
6833 /****************************************************************************/
6834 /* Prints out a summary of the driver state.                                */
6835 /*                                                                          */
6836 /* Returns:                                                                 */
6837 /*   Nothing.                                                               */
6838 /****************************************************************************/
6839 static void
6840 bce_dump_driver_state(struct bce_softc *sc)
6841 {
6842         struct ifnet *ifp = &sc->arpcom.ac_if;
6843         uint32_t val_hi, val_lo;
6844
6845         if_printf(ifp,
6846         "-----------------------------"
6847         " Driver State "
6848         "-----------------------------\n");
6849
6850         val_hi = BCE_ADDR_HI(sc);
6851         val_lo = BCE_ADDR_LO(sc);
6852         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
6853                   "virtual address\n", val_hi, val_lo);
6854
6855         val_hi = BCE_ADDR_HI(sc->status_block);
6856         val_lo = BCE_ADDR_LO(sc->status_block);
6857         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
6858                   "virtual address\n", val_hi, val_lo);
6859
6860         val_hi = BCE_ADDR_HI(sc->stats_block);
6861         val_lo = BCE_ADDR_LO(sc->stats_block);
6862         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
6863                   "virtual address\n", val_hi, val_lo);
6864
6865         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
6866         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
6867         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
6868                   "virtual adddress\n", val_hi, val_lo);
6869
6870         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
6871         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
6872         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
6873                   "virtual address\n", val_hi, val_lo);
6874
6875         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
6876         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
6877         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
6878                   "virtual address\n", val_hi, val_lo);
6879
6880         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
6881         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
6882         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
6883                   "virtual address\n", val_hi, val_lo);
6884
6885         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
6886                   "h/w intrs\n", sc->interrupts_generated);
6887
6888         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
6889                   "rx interrupts handled\n", sc->rx_interrupts);
6890
6891         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
6892                   "tx interrupts handled\n", sc->tx_interrupts);
6893
6894         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
6895                   "status block index\n", sc->last_status_idx);
6896
6897         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
6898                   "tx producer index\n",
6899                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
6900
6901         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
6902                   "tx consumer index\n",
6903                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
6904
6905         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
6906                   "tx producer bseq index\n", sc->tx_prod_bseq);
6907
6908         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
6909                   "rx producer index\n",
6910                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
6911
6912         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
6913                   "rx consumer index\n",
6914                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
6915
6916         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
6917                   "rx producer bseq index\n", sc->rx_prod_bseq);
6918
6919         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
6920                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6921
6922         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
6923                   "free rx_bd's\n", sc->free_rx_bd);
6924
6925         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
6926                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
6927
6928         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
6929                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
6930
6931         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
6932                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6933
6934         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
6935                   sc->used_tx_bd);
6936
6937         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
6938                   sc->tx_hi_watermark, sc->max_tx_bd);
6939
6940         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
6941                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
6942
6943         if_printf(ifp,
6944         "----------------------------"
6945         "----------------"
6946         "----------------------------\n");
6947 }
6948
6949
6950 /****************************************************************************/
6951 /* Prints out the hardware state through a summary of important registers,  */\r
6952 /* followed by a complete register dump.                                    */
6953 /*                                                                          */
6954 /* Returns:                                                                 */
6955 /*   Nothing.                                                               */
6956 /****************************************************************************/
6957 static void
6958 bce_dump_hw_state(struct bce_softc *sc)
6959 {
6960         struct ifnet *ifp = &sc->arpcom.ac_if;
6961         uint32_t val1;
6962         int i;
6963
6964         if_printf(ifp,
6965         "----------------------------"
6966         " Hardware State "
6967         "----------------------------\n");
6968
6969         if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_fw_ver);
6970
6971         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
6972         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
6973                   val1, BCE_MISC_ENABLE_STATUS_BITS);
6974
6975         val1 = REG_RD(sc, BCE_DMA_STATUS);
6976         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
6977
6978         val1 = REG_RD(sc, BCE_CTX_STATUS);
6979         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
6980
6981         val1 = REG_RD(sc, BCE_EMAC_STATUS);
6982         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
6983                   val1, BCE_EMAC_STATUS);
6984
6985         val1 = REG_RD(sc, BCE_RPM_STATUS);
6986         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
6987
6988         val1 = REG_RD(sc, BCE_TBDR_STATUS);
6989         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
6990                   val1, BCE_TBDR_STATUS);
6991
6992         val1 = REG_RD(sc, BCE_TDMA_STATUS);
6993         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
6994                   val1, BCE_TDMA_STATUS);
6995
6996         val1 = REG_RD(sc, BCE_HC_STATUS);
6997         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
6998
6999         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7000         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7001                   val1, BCE_TXP_CPU_STATE);
7002
7003         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7004         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7005                   val1, BCE_TPAT_CPU_STATE);
7006
7007         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7008         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7009                   val1, BCE_RXP_CPU_STATE);
7010
7011         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7012         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7013                   val1, BCE_COM_CPU_STATE);
7014
7015         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7016         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7017                   val1, BCE_MCP_CPU_STATE);
7018
7019         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7020         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7021                   val1, BCE_CP_CPU_STATE);
7022
7023         if_printf(ifp,
7024         "----------------------------"
7025         "----------------"
7026         "----------------------------\n");
7027
7028         if_printf(ifp,
7029         "----------------------------"
7030         " Register  Dump "
7031         "----------------------------\n");
7032
7033         for (i = 0x400; i < 0x8000; i += 0x10) {
7034                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7035                           REG_RD(sc, i),
7036                           REG_RD(sc, i + 0x4),
7037                           REG_RD(sc, i + 0x8),
7038                           REG_RD(sc, i + 0xc));
7039         }
7040
7041         if_printf(ifp,
7042         "----------------------------"
7043         "----------------"
7044         "----------------------------\n");
7045 }
7046
7047
7048 /****************************************************************************/
7049 /* Prints out the TXP state.                                                */\r
7050 /*                                                                          */
7051 /* Returns:                                                                 */
7052 /*   Nothing.                                                               */
7053 /****************************************************************************/
7054 static void
7055 bce_dump_txp_state(struct bce_softc *sc)
7056 {
7057         struct ifnet *ifp = &sc->arpcom.ac_if;
7058         uint32_t val1;
7059         int i;
7060
7061         if_printf(ifp,
7062         "----------------------------"
7063         "   TXP  State   "
7064         "----------------------------\n");
7065
7066         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7067         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7068                   val1, BCE_TXP_CPU_MODE);
7069
7070         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7071         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7072                   val1, BCE_TXP_CPU_STATE);
7073
7074         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7075         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7076                   val1, BCE_TXP_CPU_EVENT_MASK);
7077
7078         if_printf(ifp,
7079         "----------------------------"
7080         " Register  Dump "
7081         "----------------------------\n");
7082
7083         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7084                 /* Skip the big blank spaces */
7085                 if (i < 0x454000 && i > 0x5ffff) {
7086                         if_printf(ifp, "0x%04X: "
7087                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7088                                   REG_RD_IND(sc, i),
7089                                   REG_RD_IND(sc, i + 0x4),
7090                                   REG_RD_IND(sc, i + 0x8),
7091                                   REG_RD_IND(sc, i + 0xc));
7092                 }
7093         }
7094
7095         if_printf(ifp,
7096         "----------------------------"
7097         "----------------"
7098         "----------------------------\n");
7099 }
7100
7101
7102 /****************************************************************************/
7103 /* Prints out the RXP state.                                                */\r
7104 /*                                                                          */
7105 /* Returns:                                                                 */
7106 /*   Nothing.                                                               */
7107 /****************************************************************************/
7108 static void
7109 bce_dump_rxp_state(struct bce_softc *sc)
7110 {
7111         struct ifnet *ifp = &sc->arpcom.ac_if;
7112         uint32_t val1;
7113         int i;
7114
7115         if_printf(ifp,
7116         "----------------------------"
7117         "   RXP  State   "
7118         "----------------------------\n");
7119
7120         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7121         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7122                   val1, BCE_RXP_CPU_MODE);
7123
7124         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7125         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7126                   val1, BCE_RXP_CPU_STATE);
7127
7128         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7129         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7130                   val1, BCE_RXP_CPU_EVENT_MASK);
7131
7132         if_printf(ifp,
7133         "----------------------------"
7134         " Register  Dump "
7135         "----------------------------\n");
7136
7137         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7138                 /* Skip the big blank sapces */
7139                 if (i < 0xc5400 && i > 0xdffff) {
7140                         if_printf(ifp, "0x%04X: "
7141                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7142                                   REG_RD_IND(sc, i),
7143                                   REG_RD_IND(sc, i + 0x4),
7144                                   REG_RD_IND(sc, i + 0x8),
7145                                   REG_RD_IND(sc, i + 0xc));
7146                 }
7147         }
7148
7149         if_printf(ifp,
7150         "----------------------------"
7151         "----------------"
7152         "----------------------------\n");
7153 }
7154
7155
7156 /****************************************************************************/
7157 /* Prints out the TPAT state.                                               */\r
7158 /*                                                                          */
7159 /* Returns:                                                                 */
7160 /*   Nothing.                                                               */
7161 /****************************************************************************/
7162 static void
7163 bce_dump_tpat_state(struct bce_softc *sc)
7164 {
7165         struct ifnet *ifp = &sc->arpcom.ac_if;
7166         uint32_t val1;
7167         int i;
7168
7169         if_printf(ifp,
7170         "----------------------------"
7171         "   TPAT State   "
7172         "----------------------------\n");
7173
7174         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7175         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7176                   val1, BCE_TPAT_CPU_MODE);
7177
7178         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7179         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7180                   val1, BCE_TPAT_CPU_STATE);
7181
7182         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7183         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7184                   val1, BCE_TPAT_CPU_EVENT_MASK);
7185
7186         if_printf(ifp,
7187         "----------------------------"
7188         " Register  Dump "
7189         "----------------------------\n");
7190
7191         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7192                 /* Skip the big blank spaces */
7193                 if (i < 0x854000 && i > 0x9ffff) {
7194                         if_printf(ifp, "0x%04X: "
7195                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7196                                   REG_RD_IND(sc, i),
7197                                   REG_RD_IND(sc, i + 0x4),
7198                                   REG_RD_IND(sc, i + 0x8),
7199                                   REG_RD_IND(sc, i + 0xc));
7200                 }
7201         }
7202
7203         if_printf(ifp,
7204         "----------------------------"
7205         "----------------"
7206         "----------------------------\n");
7207 }
7208
7209
7210 /****************************************************************************/
7211 /* Prints out the driver state and then enters the debugger.                */
7212 /*                                                                          */
7213 /* Returns:                                                                 */
7214 /*   Nothing.                                                               */
7215 /****************************************************************************/
7216 static void
7217 bce_breakpoint(struct bce_softc *sc)
7218 {
7219 #if 0
7220         bce_freeze_controller(sc);
7221 #endif
7222
7223         bce_dump_driver_state(sc);
7224         bce_dump_status_block(sc);
7225         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7226         bce_dump_hw_state(sc);
7227         bce_dump_txp_state(sc);
7228
7229 #if 0
7230         bce_unfreeze_controller(sc);
7231 #endif
7232
7233         /* Call the debugger. */
7234         breakpoint();
7235 }
7236
7237 #endif  /* BCE_DEBUG */
7238
7239 static int
7240 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7241 {
7242         struct bce_softc *sc = arg1;
7243
7244         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7245                         &sc->bce_tx_quick_cons_trip_int,
7246                         BCE_COALMASK_TX_BDS_INT);
7247 }
7248
7249 static int
7250 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7251 {
7252         struct bce_softc *sc = arg1;
7253
7254         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7255                         &sc->bce_tx_quick_cons_trip,
7256                         BCE_COALMASK_TX_BDS);
7257 }
7258
7259 static int
7260 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7261 {
7262         struct bce_softc *sc = arg1;
7263
7264         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7265                         &sc->bce_tx_ticks_int,
7266                         BCE_COALMASK_TX_TICKS_INT);
7267 }
7268
7269 static int
7270 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7271 {
7272         struct bce_softc *sc = arg1;
7273
7274         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7275                         &sc->bce_tx_ticks,
7276                         BCE_COALMASK_TX_TICKS);
7277 }
7278
7279 static int
7280 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7281 {
7282         struct bce_softc *sc = arg1;
7283
7284         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7285                         &sc->bce_rx_quick_cons_trip_int,
7286                         BCE_COALMASK_RX_BDS_INT);
7287 }
7288
7289 static int
7290 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7291 {
7292         struct bce_softc *sc = arg1;
7293
7294         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7295                         &sc->bce_rx_quick_cons_trip,
7296                         BCE_COALMASK_RX_BDS);
7297 }
7298
7299 static int
7300 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7301 {
7302         struct bce_softc *sc = arg1;
7303
7304         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7305                         &sc->bce_rx_ticks_int,
7306                         BCE_COALMASK_RX_TICKS_INT);
7307 }
7308
7309 static int
7310 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7311 {
7312         struct bce_softc *sc = arg1;
7313
7314         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7315                         &sc->bce_rx_ticks,
7316                         BCE_COALMASK_RX_TICKS);
7317 }
7318
7319 static int
7320 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7321                        uint32_t coalchg_mask)
7322 {
7323         struct bce_softc *sc = arg1;
7324         struct ifnet *ifp = &sc->arpcom.ac_if;
7325         int error = 0, v;
7326
7327         lwkt_serialize_enter(ifp->if_serializer);
7328
7329         v = *coal;
7330         error = sysctl_handle_int(oidp, &v, 0, req);
7331         if (!error && req->newptr != NULL) {
7332                 if (v < 0) {
7333                         error = EINVAL;
7334                 } else {
7335                         *coal = v;
7336                         sc->bce_coalchg_mask |= coalchg_mask;
7337                 }
7338         }
7339
7340         lwkt_serialize_exit(ifp->if_serializer);
7341         return error;
7342 }
7343
7344 static void
7345 bce_coal_change(struct bce_softc *sc)
7346 {
7347         struct ifnet *ifp = &sc->arpcom.ac_if;
7348
7349         ASSERT_SERIALIZED(ifp->if_serializer);
7350
7351         if ((ifp->if_flags & IFF_RUNNING) == 0) {
7352                 sc->bce_coalchg_mask = 0;
7353                 return;
7354         }
7355
7356         if (sc->bce_coalchg_mask &
7357             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7358                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7359                        (sc->bce_tx_quick_cons_trip_int << 16) |
7360                        sc->bce_tx_quick_cons_trip);
7361                 if (bootverbose) {
7362                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7363                                   sc->bce_tx_quick_cons_trip,
7364                                   sc->bce_tx_quick_cons_trip_int);
7365                 }
7366         }
7367
7368         if (sc->bce_coalchg_mask &
7369             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7370                 REG_WR(sc, BCE_HC_TX_TICKS,
7371                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7372                 if (bootverbose) {
7373                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7374                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7375                 }
7376         }
7377
7378         if (sc->bce_coalchg_mask &
7379             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7380                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7381                        (sc->bce_rx_quick_cons_trip_int << 16) |
7382                        sc->bce_rx_quick_cons_trip);
7383                 if (bootverbose) {
7384                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7385                                   sc->bce_rx_quick_cons_trip,
7386                                   sc->bce_rx_quick_cons_trip_int);
7387                 }
7388         }
7389
7390         if (sc->bce_coalchg_mask &
7391             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7392                 REG_WR(sc, BCE_HC_RX_TICKS,
7393                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7394                 if (bootverbose) {
7395                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7396                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7397                 }
7398         }
7399
7400         sc->bce_coalchg_mask = 0;
7401 }