sys/i386/icu/icu_vector.s

   1 /*
   2  *      from: vector.s, 386BSD 0.1 unknown origin
   3  * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $
   4  * $DragonFly: src/sys/i386/icu/Attic/icu_vector.s,v 1.22 2005/11/03 05:24:53 dillon Exp $
   5  */
   6
   7 #include "use_npx.h"
   8 #include "opt_auto_eoi.h"
   9
  10 #include <machine/asmacros.h>
  11 #include <machine/ipl.h>
  12 #include <machine/lock.h>
  13 #include <machine/psl.h>
  14 #include <machine/trap.h>
  15 #include <machine/smptests.h>           /** various SMP options */
  16
  17 #include <i386/icu/icu.h>
  18 #include <bus/isa/i386/isa.h>
  19
  20 #include "assym.s"
  21
  22 #ifndef APIC_IO
  23
  24 #define ICU_IMR_OFFSET          1       /* IO_ICU{1,2} + 1 */
  25
  26 #define ICU_EOI                 0x20    /* XXX - define elsewhere */
  27
  28 #define IRQ_LBIT(irq_num)       (1 << (irq_num))
  29 #define IRQ_BIT(irq_num)        (1 << ((irq_num) % 8))
  30 #define IRQ_BYTE(irq_num)       ((irq_num) >> 3)
  31
  32 #ifdef AUTO_EOI_1
  33 #define ENABLE_ICU1             /* use auto-EOI to reduce i/o */
  34 #define OUTB_ICU1
  35 #else
  36 #define ENABLE_ICU1                                                     \
  37         movb    $ICU_EOI,%al ;  /* as soon as possible send EOI ... */  \
  38         OUTB_ICU1 ;             /* ... to clear in service bit */       \
  39
  40 #define OUTB_ICU1                                                       \
  41         outb    %al,$IO_ICU1 ;                                          \
  42
  43 #endif
  44
  45 #ifdef AUTO_EOI_2
  46 /*
  47  * The data sheet says no auto-EOI on slave, but it sometimes works.
  48  */
  49 #define ENABLE_ICU1_AND_2       ENABLE_ICU1
  50 #else
  51 #define ENABLE_ICU1_AND_2                                               \
  52         movb    $ICU_EOI,%al ;  /* as above */                          \
  53         outb    %al,$IO_ICU2 ;  /* but do second icu first ... */       \
  54         OUTB_ICU1 ;     /* ... then first icu (if !AUTO_EOI_1) */       \
  55
  56 #endif
  57
  58 /*
  59  * Macro helpers
  60  */
  61 #define PUSH_FRAME                                                      \
  62         pushl   $0 ;            /* dummy error code */                  \
  63         pushl   $0 ;            /* dummy trap type */                   \
  64         pushal ;                /* 8 registers */                       \
  65         pushl   %ds ;                                                   \
  66         pushl   %es ;                                                   \
  67         pushl   %fs ;                                                   \
  68         mov     $KDSEL,%ax ;                                            \
  69         mov     %ax,%ds ;                                               \
  70         mov     %ax,%es ;                                               \
  71         mov     $KPSEL,%ax ;                                            \
  72         mov     %ax,%fs ;                                               \
  73
  74 #define PUSH_DUMMY                                                      \
  75         pushfl ;                /* phys int frame / flags */            \
  76         pushl %cs ;             /* phys int frame / cs */               \
  77         pushl   12(%esp) ;      /* original caller eip */               \
  78         pushl   $0 ;            /* dummy error code */                  \
  79         pushl   $0 ;            /* dummy trap type */                   \
  80         subl    $12*4,%esp ;    /* pushal + 3 seg regs (dummy) + CPL */ \
  81
  82 /*
  83  * Warning: POP_FRAME can only be used if there is no chance of a
  84  * segment register being changed (e.g. by procfs), which is why syscalls
  85  * have to use doreti.
  86  */
  87 #define POP_FRAME                                                       \
  88         popl    %fs ;                                                   \
  89         popl    %es ;                                                   \
  90         popl    %ds ;                                                   \
  91         popal ;                                                         \
  92         addl    $2*4,%esp ;     /* dummy trap & error codes */          \
  93
  94 #define POP_DUMMY                                                       \
  95         addl    $17*4,%esp ;                                            \
  96
  97 #define MASK_IRQ(icu, irq_num)                                          \
  98         movb    icu_imen + IRQ_BYTE(irq_num),%al ;                      \
  99         orb     $IRQ_BIT(irq_num),%al ;                                 \
 100         movb    %al,icu_imen + IRQ_BYTE(irq_num) ;                      \
 101         outb    %al,$icu+ICU_IMR_OFFSET ;                               \
 102
 103 #define UNMASK_IRQ(icu, irq_num)                                        \
 104         cmpl    $0,%eax ;                                               \
 105         jnz     8f ;                                                    \
 106         movb    icu_imen + IRQ_BYTE(irq_num),%al ;                      \
 107         andb    $~IRQ_BIT(irq_num),%al ;                                \
 108         movb    %al,icu_imen + IRQ_BYTE(irq_num) ;                      \
 109         outb    %al,$icu+ICU_IMR_OFFSET ;                               \
 110 8: ;                                                                    \
 111
 112 /*
 113  * Fast interrupt call handlers run in the following sequence:
 114  *
 115  *      - Push the trap frame required by doreti.
 116  *      - Mask the interrupt and reenable its source.
 117  *      - If we cannot take the interrupt set its fpending bit and
 118  *        doreti.
 119  *      - If we can take the interrupt clear its fpending bit,
 120  *        call the handler, then unmask the interrupt and doreti.
 121  *
 122  *      YYY can cache gd base pointer instead of using hidden %fs
 123  *      prefixes.
 124  */
 125
 126 #define FAST_INTR(irq_num, vec_name, icu, enable_icus, maybe_extra_ipending) \
 127         .text ;                                                         \
 128         SUPERALIGN_TEXT ;                                               \
 129 IDTVEC(vec_name) ;                                                      \
 130         PUSH_FRAME ;                                                    \
 131         FAKE_MCOUNT(13*4(%esp)) ;                                       \
 132         maybe_extra_ipending ;                                          \
 133         MASK_IRQ(icu, irq_num) ;                                        \
 134         enable_icus ;                                                   \
 135         movl    PCPU(curthread),%ebx ;                                  \
 136         pushl   $0 ;                    /* DUMMY CPL FOR DORETI */      \
 137         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 138         jl      2f ;                                                    \
 139 1: ;                                                                    \
 140         /* set pending bit and return, leave interrupt masked */        \
 141         orl     $IRQ_LBIT(irq_num),PCPU(fpending) ;                     \
 142         orl     $RQF_INTPEND, PCPU(reqflags) ;                          \
 143         jmp     5f ;                                                    \
 144 2: ;                                                                    \
 145         /* clear pending bit, run handler */                            \
 146         andl    $~IRQ_LBIT(irq_num),PCPU(fpending) ;                    \
 147         pushl   $irq_num ;                                              \
 148         call    ithread_fast_handler ;  /* returns 0 to unmask int */   \
 149         addl    $4,%esp ;                                               \
 150         UNMASK_IRQ(icu, irq_num) ;                                      \
 151 5: ;                                                                    \
 152         MEXITCOUNT ;                                                    \
 153         jmp     doreti ;                                                \
 154
 155 /*
 156  * Slow interrupt call handlers run in the following sequence:
 157  *
 158  *      - Push the trap frame required by doreti.
 159  *      - Mask the interrupt and reenable its source.
 160  *      - If we cannot take the interrupt set its ipending bit and
 161  *        doreti.  In addition to checking for a critical section
 162  *        and cpl mask we also check to see if the thread is still
 163  *        running.
 164  *      - If we can take the interrupt clear its ipending bit
 165  *        and schedule its thread.  Leave interrupts masked and doreti.
 166  *
 167  *      sched_ithd() is called with interrupts enabled and outside of a
 168  *      critical section (so it can preempt us).
 169  *
 170  *      YYY sched_ithd may preempt us synchronously (fix interrupt stacking)
 171  *
 172  *      Note that intr_nesting_level is not bumped during sched_ithd because
 173  *      blocking allocations are allowed in the preemption case.
 174  *
 175  *      YYY can cache gd base pointer instead of using hidden %fs
 176  *      prefixes.
 177  */
 178
 179 #define INTR(irq_num, vec_name, icu, enable_icus, reg, maybe_extra_ipending) \
 180         .text ;                                                         \
 181         SUPERALIGN_TEXT ;                                               \
 182 IDTVEC(vec_name) ;                                                      \
 183         PUSH_FRAME ;                                                    \
 184         FAKE_MCOUNT(13*4(%esp)) ;                                       \
 185         maybe_extra_ipending ;                                          \
 186         MASK_IRQ(icu, irq_num) ;                                        \
 187         enable_icus ;                                                   \
 188         movl    PCPU(curthread),%ebx ;                                  \
 189         pushl   $0 ;                    /* DUMMY CPL FOR DORETI */      \
 190         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 191         jl      2f ;                                                    \
 192 1: ;                                                                    \
 193         /* set the pending bit and return, leave interrupt masked */    \
 194         orl     $IRQ_LBIT(irq_num), PCPU(ipending) ;                    \
 195         orl     $RQF_INTPEND, PCPU(reqflags) ;                          \
 196         jmp     5f ;                                                    \
 197 2: ;                                                                    \
 198         /* set running bit, clear pending bit, run handler */           \
 199         andl    $~IRQ_LBIT(irq_num), PCPU(ipending) ;                   \
 200         sti ;                                                           \
 201         pushl   $irq_num ;                                              \
 202         call    sched_ithd ;                                            \
 203         addl    $4,%esp ;                                               \
 204 5: ;                                                                    \
 205         MEXITCOUNT ;                                                    \
 206         jmp     doreti ;                                                \
 207
 208 /*
 209  * Unmask a slow interrupt.  This function is used by interrupt threads
 210  * after they have descheduled themselves to reenable interrupts and
 211  * possibly cause a reschedule to occur.
 212  */
 213
 214 #define INTR_UNMASK(irq_num, vec_name, icu)                             \
 215         .text ;                                                         \
 216         SUPERALIGN_TEXT ;                                               \
 217 IDTVEC(vec_name) ;                                                      \
 218         pushl %ebp ;     /* frame for ddb backtrace */                  \
 219         movl    %esp, %ebp ;                                            \
 220         subl    %eax, %eax ;                                            \
 221         UNMASK_IRQ(icu, irq_num) ;                                      \
 222         popl %ebp ;                                                     \
 223         ret ;                                                           \
 224
 225 MCOUNT_LABEL(bintr)
 226         FAST_INTR(0,icu_fastintr0, IO_ICU1, ENABLE_ICU1,)
 227         FAST_INTR(1,icu_fastintr1, IO_ICU1, ENABLE_ICU1,)
 228         FAST_INTR(2,icu_fastintr2, IO_ICU1, ENABLE_ICU1,)
 229         FAST_INTR(3,icu_fastintr3, IO_ICU1, ENABLE_ICU1,)
 230         FAST_INTR(4,icu_fastintr4, IO_ICU1, ENABLE_ICU1,)
 231         FAST_INTR(5,icu_fastintr5, IO_ICU1, ENABLE_ICU1,)
 232         FAST_INTR(6,icu_fastintr6, IO_ICU1, ENABLE_ICU1,)
 233         FAST_INTR(7,icu_fastintr7, IO_ICU1, ENABLE_ICU1,)
 234         FAST_INTR(8,icu_fastintr8, IO_ICU2, ENABLE_ICU1_AND_2,)
 235         FAST_INTR(9,icu_fastintr9, IO_ICU2, ENABLE_ICU1_AND_2,)
 236         FAST_INTR(10,icu_fastintr10, IO_ICU2, ENABLE_ICU1_AND_2,)
 237         FAST_INTR(11,icu_fastintr11, IO_ICU2, ENABLE_ICU1_AND_2,)
 238         FAST_INTR(12,icu_fastintr12, IO_ICU2, ENABLE_ICU1_AND_2,)
 239         FAST_INTR(13,icu_fastintr13, IO_ICU2, ENABLE_ICU1_AND_2,)
 240         FAST_INTR(14,icu_fastintr14, IO_ICU2, ENABLE_ICU1_AND_2,)
 241         FAST_INTR(15,icu_fastintr15, IO_ICU2, ENABLE_ICU1_AND_2,)
 242
 243         INTR(0,icu_slowintr0, IO_ICU1, ENABLE_ICU1, al,)
 244         INTR(1,icu_slowintr1, IO_ICU1, ENABLE_ICU1, al,)
 245         INTR(2,icu_slowintr2, IO_ICU1, ENABLE_ICU1, al,)
 246         INTR(3,icu_slowintr3, IO_ICU1, ENABLE_ICU1, al,)
 247         INTR(4,icu_slowintr4, IO_ICU1, ENABLE_ICU1, al,)
 248         INTR(5,icu_slowintr5, IO_ICU1, ENABLE_ICU1, al,)
 249         INTR(6,icu_slowintr6, IO_ICU1, ENABLE_ICU1, al,)
 250         INTR(7,icu_slowintr7, IO_ICU1, ENABLE_ICU1, al,)
 251         INTR(8,icu_slowintr8, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
 252         INTR(9,icu_slowintr9, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
 253         INTR(10,icu_slowintr10, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
 254         INTR(11,icu_slowintr11, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
 255         INTR(12,icu_slowintr12, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
 256         INTR(13,icu_slowintr13, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
 257         INTR(14,icu_slowintr14, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
 258         INTR(15,icu_slowintr15, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
 259
 260 MCOUNT_LABEL(eintr)
 261
 262         .data
 263
 264         .text
 265
 266 #endif