2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/machintr.h>
46 #include <sys/interrupt.h>
49 #include <machine/segments.h>
50 #include <machine/md_var.h>
51 #include <machine/intr_machdep.h>
52 #include <machine/globaldata.h>
53 #include <machine/smp.h>
55 #include <sys/thread2.h>
57 #include <machine_base/apic/ioapic_abi.h>
58 #include <machine_base/isa/elcr_var.h>
64 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
65 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
66 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
67 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
68 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
69 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
70 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
71 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
73 static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
74 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
75 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
76 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
77 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
78 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
79 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
80 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
81 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
84 static struct icu_irqmap {
85 int im_type; /* ICU_IMT_ */
86 enum intr_trigger im_trig;
87 } icu_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
89 #define ICU_IMT_UNUSED 0 /* KEEP THIS */
90 #define ICU_IMT_RESERVED 1
91 #define ICU_IMT_LINE 2
93 extern void ICU_INTREN(int);
94 extern void ICU_INTRDIS(int);
96 static int icu_vectorctl(int, int, int);
97 static int icu_setvar(int, const void *);
98 static int icu_getvar(int, void *);
99 static void icu_finalize(void);
100 static void icu_cleanup(void);
101 static void icu_setdefault(void);
102 static void icu_stabilize(void);
103 static void icu_initmap(void);
105 struct machintr_abi MachIntrABI_ICU = {
107 .intrdis = ICU_INTRDIS,
108 .intren = ICU_INTREN,
109 .vectorctl = icu_vectorctl,
110 .setvar = icu_setvar,
111 .getvar = icu_getvar,
112 .finalize = icu_finalize,
113 .cleanup = icu_cleanup,
114 .setdefault = icu_setdefault,
115 .stabilize = icu_stabilize,
116 .initmap = icu_initmap
119 static int icu_imcr_present;
122 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
125 icu_setvar(int varid, const void *buf)
130 case MACHINTR_VAR_IMCR_PRESENT:
131 icu_imcr_present = *(const int *)buf;
142 icu_getvar(int varid, void *buf)
147 case MACHINTR_VAR_IMCR_PRESENT:
148 *(int *)buf = icu_imcr_present;
159 * Called before interrupts are physically enabled
166 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
167 machintr_intrdis(intr);
168 machintr_intren(ICU_IRQ_SLAVE);
172 * Called after interrupts physically enabled but before the
173 * critical section is released.
178 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
182 * Called after stablize and cleanup; critical section is not
183 * held and interrupts are not physically disabled.
186 * Further delayed after BSP's LAPIC is initialized
191 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
194 if (apic_io_enable) {
196 * MachIntrABI switching will happen in
197 * MachIntrABI_IOAPIC.finalize()
199 MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
201 MachIntrABI_IOAPIC.finalize();
206 * If an IMCR is present, programming bit 0 disconnects the 8259
207 * from the BSP. The 8259 may still be connected to LINT0 on the
210 * If we are running SMP the LAPIC is active, try to use virtual
211 * wire mode so we can use other interrupt sources within the LAPIC
212 * in addition to the 8259.
214 if (icu_imcr_present) {
233 icu_vectorctl(int op, int intr, int flags)
238 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
246 case MACHINTR_VECTOR_SETUP:
247 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
248 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
249 machintr_intren(intr);
252 case MACHINTR_VECTOR_TEARDOWN:
253 machintr_intrdis(intr);
254 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
255 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
271 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
272 if (intr == ICU_IRQ_SLAVE)
274 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
275 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
284 for (i = 0; i < ICU_HWI_VECTORS; ++i)
285 icu_irqmaps[i].im_type = ICU_IMT_LINE;
286 icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;
289 for (i = 0; i < ICU_HWI_VECTORS; ++i)
290 icu_irqmaps[i].im_trig = elcr_read_trigger(i);
292 for (i = 0; i < ICU_HWI_VECTORS; ++i) {
299 icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
303 icu_irqmaps[i].im_trig = INTR_TRIGGER_LEVEL;