2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/md_var.h>
35 #include <machine/pmap.h>
36 #include <machine_base/apic/mpapic.h>
37 #include <machine/segments.h>
38 #include <sys/thread2.h>
40 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
43 extern pt_entry_t *SMPpt;
45 /* EISA Edge/Level trigger control registers */
46 #define ELCR0 0x4d0 /* eisa irq 0-7 */
47 #define ELCR1 0x4d1 /* eisa irq 8-15 */
49 static void lapic_timer_calibrate(void);
50 static void lapic_timer_set_divisor(int);
51 static void lapic_timer_fixup_handler(void *);
52 static void lapic_timer_restart_handler(void *);
54 void lapic_timer_process(void);
55 void lapic_timer_process_frame(struct intrframe *);
57 static int lapic_timer_enable = 1;
58 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
60 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
61 static void lapic_timer_intr_enable(struct cputimer_intr *);
62 static void lapic_timer_intr_restart(struct cputimer_intr *);
63 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
65 static struct cputimer_intr lapic_cputimer_intr = {
67 .reload = lapic_timer_intr_reload,
68 .enable = lapic_timer_intr_enable,
69 .config = cputimer_intr_default_config,
70 .restart = lapic_timer_intr_restart,
71 .pmfixup = lapic_timer_intr_pmfixup,
72 .initclock = cputimer_intr_default_initclock,
73 .next = SLIST_ENTRY_INITIALIZER,
75 .type = CPUTIMER_INTR_LAPIC,
76 .prio = CPUTIMER_INTR_PRIO_LAPIC,
77 .caps = CPUTIMER_INTR_CAP_NONE
81 * pointers to pmapped apic hardware.
84 volatile ioapic_t **ioapic;
86 static int lapic_timer_divisor_idx = -1;
87 static const uint32_t lapic_timer_divisors[] = {
88 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
89 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
91 #define APIC_TIMER_NDIVISORS \
92 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
96 * Enable APIC, configure interrupts.
99 apic_initialize(boolean_t bsp)
105 * setup LVT1 as ExtINT on the BSP. This is theoretically an
106 * aggregate interrupt input from the 8259. The INTA cycle
107 * will be routed to the external controller (the 8259) which
108 * is expected to supply the vector.
110 * Must be setup edge triggered, active high.
112 * Disable LVT1 on the APs. It doesn't matter what delivery
113 * mode we use because we leave it masked.
115 temp = lapic.lvt_lint0;
116 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
117 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
118 if (mycpu->gd_cpuid == 0)
119 temp |= APIC_LVT_DM_EXTINT;
121 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
122 lapic.lvt_lint0 = temp;
125 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
127 temp = lapic.lvt_lint1;
128 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
129 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
130 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
131 lapic.lvt_lint1 = temp;
134 * Mask the apic error interrupt, apic performance counter
137 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
138 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
140 /* Set apic timer vector and mask the apic timer interrupt. */
141 timer = lapic.lvt_timer;
142 timer &= ~APIC_LVTT_VECTOR;
143 timer |= XTIMER_OFFSET;
144 timer |= APIC_LVTT_MASKED;
145 lapic.lvt_timer = timer;
148 * Set the Task Priority Register as needed. At the moment allow
149 * interrupts on all cpus (the APs will remain CLId until they are
150 * ready to deal). We could disable all but IPIs by setting
151 * temp |= TPR_IPI_ONLY for cpu != 0.
154 temp &= ~APIC_TPR_PRIO; /* clear priority field */
157 * If we are NOT running the IO APICs, the LAPIC will only be used
158 * for IPIs. Set the TPR to prevent any unintentional interrupts.
160 temp |= TPR_IPI_ONLY;
166 * enable the local APIC
169 temp |= APIC_SVR_ENABLE; /* enable the APIC */
170 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
173 * Set the spurious interrupt vector. The low 4 bits of the vector
176 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
177 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
178 temp &= ~APIC_SVR_VECTOR;
179 temp |= XSPURIOUSINT_OFFSET;
184 * Pump out a few EOIs to clean out interrupts that got through
185 * before we were able to set the TPR.
192 lapic_timer_calibrate();
193 if (lapic_timer_enable) {
194 cputimer_intr_register(&lapic_cputimer_intr);
195 cputimer_intr_select(&lapic_cputimer_intr, 0);
198 lapic_timer_set_divisor(lapic_timer_divisor_idx);
202 apic_dump("apic_initialize()");
207 lapic_timer_set_divisor(int divisor_idx)
209 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
210 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
214 lapic_timer_oneshot(u_int count)
218 value = lapic.lvt_timer;
219 value &= ~APIC_LVTT_PERIODIC;
220 lapic.lvt_timer = value;
221 lapic.icr_timer = count;
225 lapic_timer_oneshot_quick(u_int count)
227 lapic.icr_timer = count;
231 lapic_timer_calibrate(void)
235 /* Try to calibrate the local APIC timer. */
236 for (lapic_timer_divisor_idx = 0;
237 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
238 lapic_timer_divisor_idx++) {
239 lapic_timer_set_divisor(lapic_timer_divisor_idx);
240 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
242 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
243 if (value != APIC_TIMER_MAX_COUNT)
246 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
247 panic("lapic: no proper timer divisor?!\n");
248 lapic_cputimer_intr.freq = value / 2;
250 kprintf("lapic: divisor index %d, frequency %u Hz\n",
251 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
255 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
259 gd->gd_timer_running = 0;
261 count = sys_cputimer->count();
262 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
263 systimer_intr(&count, 0, frame);
267 lapic_timer_process(void)
269 lapic_timer_process_oncpu(mycpu, NULL);
273 lapic_timer_process_frame(struct intrframe *frame)
275 lapic_timer_process_oncpu(mycpu, frame);
279 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
281 struct globaldata *gd = mycpu;
283 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
287 if (gd->gd_timer_running) {
288 if (reload < lapic.ccr_timer)
289 lapic_timer_oneshot_quick(reload);
291 gd->gd_timer_running = 1;
292 lapic_timer_oneshot_quick(reload);
297 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
301 timer = lapic.lvt_timer;
302 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
303 lapic.lvt_timer = timer;
305 lapic_timer_fixup_handler(NULL);
309 lapic_timer_fixup_handler(void *arg)
316 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
318 * Detect the presence of C1E capability mostly on latest
319 * dual-cores (or future) k8 family. This feature renders
320 * the local APIC timer dead, so we disable it by reading
321 * the Interrupt Pending Message register and clearing both
322 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
325 * "BIOS and Kernel Developer's Guide for AMD NPT
326 * Family 0Fh Processors"
327 * #32559 revision 3.00
329 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
330 (cpu_id & 0x0fff0000) >= 0x00040000) {
333 msr = rdmsr(0xc0010055);
334 if (msr & 0x18000000) {
335 struct globaldata *gd = mycpu;
337 kprintf("cpu%d: AMD C1E detected\n",
339 wrmsr(0xc0010055, msr & ~0x18000000ULL);
342 * We are kinda stalled;
345 gd->gd_timer_running = 1;
346 lapic_timer_oneshot_quick(2);
356 lapic_timer_restart_handler(void *dummy __unused)
360 lapic_timer_fixup_handler(&started);
362 struct globaldata *gd = mycpu;
364 gd->gd_timer_running = 1;
365 lapic_timer_oneshot_quick(2);
370 * This function is called only by ACPI-CA code currently:
371 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
372 * module controls PM. So once ACPI-CA is attached, we try
373 * to apply the fixup to prevent LAPIC timer from hanging.
376 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
378 lwkt_send_ipiq_mask(smp_active_mask,
379 lapic_timer_fixup_handler, NULL);
383 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
385 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
390 * dump contents of local APIC registers
395 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
396 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
397 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
407 #define IOAPIC_ISA_INTS 16
408 #define REDIRCNT_IOAPIC(A) \
409 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
411 static int trigger (int apic, int pin, u_int32_t * flags);
412 static void polarity (int apic, int pin, u_int32_t * flags, int level);
414 #define DEFAULT_FLAGS \
420 #define DEFAULT_ISA_FLAGS \
429 io_apic_set_id(int apic, int id)
433 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
434 if (((ux & APIC_ID_MASK) >> 24) != id) {
435 kprintf("Changing APIC ID for IO APIC #%d"
436 " from %d to %d on chip\n",
437 apic, ((ux & APIC_ID_MASK) >> 24), id);
438 ux &= ~APIC_ID_MASK; /* clear the ID field */
440 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
441 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
442 if (((ux & APIC_ID_MASK) >> 24) != id)
443 panic("can't control IO APIC #%d ID, reg: 0x%08x",
450 io_apic_get_id(int apic)
452 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
461 io_apic_setup_intpin(int apic, int pin)
463 int bus, bustype, irq;
464 u_char select; /* the select register is 8 bits */
465 u_int32_t flags; /* the window register is 32 bits */
466 u_int32_t target; /* the window register is 32 bits */
467 u_int32_t vector; /* the window register is 32 bits */
472 select = pin * 2 + IOAPIC_REDTBL0; /* register */
475 * Always clear an IO APIC pin before [re]programming it. This is
476 * particularly important if the pin is set up for a level interrupt
477 * as the IOART_REM_IRR bit might be set. When we reprogram the
478 * vector any EOI from pending ints on this pin could be lost and
479 * IRR might never get reset.
481 * To fix this problem, clear the vector and make sure it is
482 * programmed as an edge interrupt. This should theoretically
483 * clear IRR so we can later, safely program it as a level
488 flags = io_apic_read(apic, select) & IOART_RESV;
489 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
490 flags |= IOART_DESTPHY | IOART_DELFIXED;
492 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
493 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
497 io_apic_write(apic, select, flags | vector);
498 io_apic_write(apic, select + 1, target);
503 * We only deal with vectored interrupts here. ? documentation is
504 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
507 * This test also catches unconfigured pins.
509 if (apic_int_type(apic, pin) != 0)
513 * Leave the pin unprogrammed if it does not correspond to
516 irq = apic_irq(apic, pin);
520 /* determine the bus type for this pin */
521 bus = apic_src_bus_id(apic, pin);
524 bustype = apic_bus_type(bus);
526 if ((bustype == ISA) &&
527 (pin < IOAPIC_ISA_INTS) &&
529 (apic_polarity(apic, pin) == 0x1) &&
530 (apic_trigger(apic, pin) == 0x3)) {
532 * A broken BIOS might describe some ISA
533 * interrupts as active-high level-triggered.
534 * Use default ISA flags for those interrupts.
536 flags = DEFAULT_ISA_FLAGS;
539 * Program polarity and trigger mode according to
542 flags = DEFAULT_FLAGS;
543 level = trigger(apic, pin, &flags);
545 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
546 polarity(apic, pin, &flags, level);
550 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
551 kgetenv_int(envpath, &cpuid);
553 /* ncpus may not be available yet */
558 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
559 apic, pin, irq, cpuid);
563 * Program the appropriate registers. This routing may be
564 * overridden when an interrupt handler for a device is
565 * actually added (see register_int(), which calls through
566 * the MACHINTR ABI to set up an interrupt handler/vector).
568 * The order in which we must program the two registers for
569 * safety is unclear! XXX
573 vector = IDT_OFFSET + irq; /* IDT vec */
574 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
575 /* Deliver all interrupts to CPU0 (BSP) */
576 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
578 flags |= io_apic_read(apic, select) & IOART_RESV;
579 io_apic_write(apic, select, flags | vector);
580 io_apic_write(apic, select + 1, target);
586 io_apic_setup(int apic)
591 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
592 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
594 for (pin = 0; pin < maxpin; ++pin) {
595 io_apic_setup_intpin(apic, pin);
598 if (apic_int_type(apic, pin) >= 0) {
599 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
600 " cannot program!\n", apic, pin);
605 /* return GOOD status */
608 #undef DEFAULT_ISA_FLAGS
612 #define DEFAULT_EXTINT_FLAGS \
621 * XXX this function is only used by 8254 setup
622 * Setup the source of External INTerrupts.
625 ext_int_setup(int apic, int intr)
627 u_char select; /* the select register is 8 bits */
628 u_int32_t flags; /* the window register is 32 bits */
629 u_int32_t target; /* the window register is 32 bits */
630 u_int32_t vector; /* the window register is 32 bits */
634 if (apic_int_type(apic, intr) != 3)
638 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
639 kgetenv_int(envpath, &cpuid);
641 /* ncpus may not be available yet */
645 /* Deliver interrupts to CPU0 (BSP) */
646 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
648 select = IOAPIC_REDTBL0 + (2 * intr);
649 vector = IDT_OFFSET + intr;
650 flags = DEFAULT_EXTINT_FLAGS;
652 io_apic_write(apic, select, flags | vector);
653 io_apic_write(apic, select + 1, target);
657 #undef DEFAULT_EXTINT_FLAGS
661 * Set the trigger level for an IO APIC pin.
664 trigger(int apic, int pin, u_int32_t * flags)
669 static int intcontrol = -1;
671 switch (apic_trigger(apic, pin)) {
677 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
681 *flags |= IOART_TRGRLVL;
689 if ((id = apic_src_bus_id(apic, pin)) == -1)
692 switch (apic_bus_type(id)) {
694 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
698 eirq = apic_src_bus_irq(apic, pin);
700 if (eirq < 0 || eirq > 15) {
701 kprintf("EISA IRQ %d?!?!\n", eirq);
705 if (intcontrol == -1) {
706 intcontrol = inb(ELCR1) << 8;
707 intcontrol |= inb(ELCR0);
708 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
711 /* Use ELCR settings to determine level or edge mode */
712 level = (intcontrol >> eirq) & 1;
715 * Note that on older Neptune chipset based systems, any
716 * pci interrupts often show up here and in the ELCR as well
717 * as level sensitive interrupts attributed to the EISA bus.
721 *flags |= IOART_TRGRLVL;
723 *flags &= ~IOART_TRGRLVL;
728 *flags |= IOART_TRGRLVL;
737 panic("bad APIC IO INT flags");
742 * Set the polarity value for an IO APIC pin.
745 polarity(int apic, int pin, u_int32_t * flags, int level)
749 switch (apic_polarity(apic, pin)) {
755 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
759 *flags |= IOART_INTALO;
767 if ((id = apic_src_bus_id(apic, pin)) == -1)
770 switch (apic_bus_type(id)) {
772 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
776 /* polarity converter always gives active high */
777 *flags &= ~IOART_INTALO;
781 *flags |= IOART_INTALO;
790 panic("bad APIC IO INT flags");
795 * Print contents of unmasked IRQs.
802 kprintf("SMP: enabled INTs: ");
803 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
804 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
812 * Inter Processor Interrupt functions.
818 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
820 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
821 * vector is any valid SYSTEM INT vector
822 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
824 * A backlog of requests can create a deadlock between cpus. To avoid this
825 * we have to be able to accept IPIs at the same time we are trying to send
826 * them. The critical section prevents us from attempting to send additional
827 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
828 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
829 * to occur but fortunately it does not happen too often.
832 apic_ipi(int dest_type, int vector, int delivery_mode)
837 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
838 unsigned int eflags = read_eflags();
840 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
843 write_eflags(eflags);
846 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
847 delivery_mode | vector;
848 lapic.icr_lo = icr_lo;
854 single_apic_ipi(int cpu, int vector, int delivery_mode)
860 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
861 unsigned int eflags = read_eflags();
863 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
866 write_eflags(eflags);
868 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
869 icr_hi |= (CPU_TO_ID(cpu) << 24);
870 lapic.icr_hi = icr_hi;
873 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
874 | APIC_DEST_DESTFLD | delivery_mode | vector;
877 lapic.icr_lo = icr_lo;
884 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
886 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
887 * to the target, and the scheduler does not 'poll' for IPI messages.
890 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
896 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
900 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
901 icr_hi |= (CPU_TO_ID(cpu) << 24);
902 lapic.icr_hi = icr_hi;
905 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
906 | APIC_DEST_DESTFLD | delivery_mode | vector;
909 lapic.icr_lo = icr_lo;
917 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
919 * target is a bitmask of destination cpus. Vector is any
920 * valid system INT vector. Delivery mode may be either
921 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
924 selected_apic_ipi(u_int target, int vector, int delivery_mode)
928 int n = bsfl(target);
930 single_apic_ipi(n, vector, delivery_mode);
936 * Timer code, in development...
937 * - suggested by rgrimes@gndrsh.aac.dev.com
941 * Load a 'downcount time' in uSeconds.
944 set_apic_timer(int us)
949 * When we reach here, lapic timer's frequency
950 * must have been calculated as well as the
951 * divisor (lapic.dcr_timer is setup during the
952 * divisor calculation).
954 KKASSERT(lapic_cputimer_intr.freq != 0 &&
955 lapic_timer_divisor_idx >= 0);
957 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
958 lapic_timer_oneshot(count);
963 * Read remaining time in timer.
966 read_apic_timer(void)
969 /** XXX FIXME: we need to return the actual remaining time,
970 * for now we just return the remaining count.
973 return lapic.ccr_timer;
979 * Spin-style delay, set delay time in uS, spin till it drains.
984 set_apic_timer(count);
985 while (read_apic_timer())
990 lapic_map(vm_offset_t lapic_addr)
992 /* Local apic is mapped on last page */
993 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
994 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
996 kprintf("lapic: at %p\n", (void *)lapic_addr);
999 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1000 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1005 struct lapic_enumerator *e;
1008 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1009 error = e->lapic_probe(e);
1014 panic("can't config lapic\n");
1016 e->lapic_enumerate(e);
1020 lapic_enumerator_register(struct lapic_enumerator *ne)
1022 struct lapic_enumerator *e;
1024 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1025 if (e->lapic_prio < ne->lapic_prio) {
1026 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1030 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);