1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of storing fp registers
996 in SFmode, DFmode and XFmode */
997 2, /* cost of moving MMX register */
998 {6, 6}, /* cost of loading MMX registers
999 in SImode and DImode */
1000 {4, 4}, /* cost of storing MMX registers
1001 in SImode and DImode */
1002 2, /* cost of moving SSE register */
1003 {6, 6, 6}, /* cost of loading SSE registers
1004 in SImode, DImode and TImode */
1005 {4, 4, 4}, /* cost of storing SSE registers
1006 in SImode, DImode and TImode */
1007 2, /* MMX or SSE register to integer */
1008 32, /* size of l1 cache. */
1009 2048, /* size of l2 cache. */
1010 128, /* size of prefetch block */
1011 8, /* number of parallel prefetches */
1012 3, /* Branch cost */
1013 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1014 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1015 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1016 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1017 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1018 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1019 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1020 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 {{libcall, {{8, loop}, {15, unrolled_loop},
1023 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1024 {libcall, {{24, loop}, {32, unrolled_loop},
1025 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1026 1, /* scalar_stmt_cost. */
1027 1, /* scalar load_cost. */
1028 1, /* scalar_store_cost. */
1029 1, /* vec_stmt_cost. */
1030 1, /* vec_to_scalar_cost. */
1031 1, /* scalar_to_vec_cost. */
1032 1, /* vec_align_load_cost. */
1033 2, /* vec_unalign_load_cost. */
1034 1, /* vec_store_cost. */
1035 3, /* cond_taken_branch_cost. */
1036 1, /* cond_not_taken_branch_cost. */
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1041 struct processor_costs generic64_cost = {
1042 COSTS_N_INSNS (1), /* cost of an add instruction */
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1047 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1048 COSTS_N_INSNS (1), /* variable shift costs */
1049 COSTS_N_INSNS (1), /* constant shift costs */
1050 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1051 COSTS_N_INSNS (4), /* HI */
1052 COSTS_N_INSNS (3), /* SI */
1053 COSTS_N_INSNS (4), /* DI */
1054 COSTS_N_INSNS (2)}, /* other */
1055 0, /* cost of multiply per each bit set */
1056 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1057 COSTS_N_INSNS (26), /* HI */
1058 COSTS_N_INSNS (42), /* SI */
1059 COSTS_N_INSNS (74), /* DI */
1060 COSTS_N_INSNS (74)}, /* other */
1061 COSTS_N_INSNS (1), /* cost of movsx */
1062 COSTS_N_INSNS (1), /* cost of movzx */
1063 8, /* "large" insn */
1064 17, /* MOVE_RATIO */
1065 4, /* cost for loading QImode using movzbl */
1066 {4, 4, 4}, /* cost of loading integer registers
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1069 {4, 4, 4}, /* cost of storing integer registers */
1070 4, /* cost of reg,reg fld/fst */
1071 {12, 12, 12}, /* cost of loading fp registers
1072 in SFmode, DFmode and XFmode */
1073 {6, 6, 8}, /* cost of storing fp registers
1074 in SFmode, DFmode and XFmode */
1075 2, /* cost of moving MMX register */
1076 {8, 8}, /* cost of loading MMX registers
1077 in SImode and DImode */
1078 {8, 8}, /* cost of storing MMX registers
1079 in SImode and DImode */
1080 2, /* cost of moving SSE register */
1081 {8, 8, 8}, /* cost of loading SSE registers
1082 in SImode, DImode and TImode */
1083 {8, 8, 8}, /* cost of storing SSE registers
1084 in SImode, DImode and TImode */
1085 5, /* MMX or SSE register to integer */
1086 32, /* size of l1 cache. */
1087 512, /* size of l2 cache. */
1088 64, /* size of prefetch block */
1089 6, /* number of parallel prefetches */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1092 3, /* Branch cost */
1093 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1094 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1095 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1096 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1097 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1098 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 {DUMMY_STRINGOP_ALGS,
1102 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1103 1, /* scalar_stmt_cost. */
1104 1, /* scalar load_cost. */
1105 1, /* scalar_store_cost. */
1106 1, /* vec_stmt_cost. */
1107 1, /* vec_to_scalar_cost. */
1108 1, /* scalar_to_vec_cost. */
1109 1, /* vec_align_load_cost. */
1110 2, /* vec_unalign_load_cost. */
1111 1, /* vec_store_cost. */
1112 3, /* cond_taken_branch_cost. */
1113 1, /* cond_not_taken_branch_cost. */
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1118 struct processor_costs generic32_cost = {
1119 COSTS_N_INSNS (1), /* cost of an add instruction */
1120 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1121 COSTS_N_INSNS (1), /* variable shift costs */
1122 COSTS_N_INSNS (1), /* constant shift costs */
1123 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1124 COSTS_N_INSNS (4), /* HI */
1125 COSTS_N_INSNS (3), /* SI */
1126 COSTS_N_INSNS (4), /* DI */
1127 COSTS_N_INSNS (2)}, /* other */
1128 0, /* cost of multiply per each bit set */
1129 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1130 COSTS_N_INSNS (26), /* HI */
1131 COSTS_N_INSNS (42), /* SI */
1132 COSTS_N_INSNS (74), /* DI */
1133 COSTS_N_INSNS (74)}, /* other */
1134 COSTS_N_INSNS (1), /* cost of movsx */
1135 COSTS_N_INSNS (1), /* cost of movzx */
1136 8, /* "large" insn */
1137 17, /* MOVE_RATIO */
1138 4, /* cost for loading QImode using movzbl */
1139 {4, 4, 4}, /* cost of loading integer registers
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1142 {4, 4, 4}, /* cost of storing integer registers */
1143 4, /* cost of reg,reg fld/fst */
1144 {12, 12, 12}, /* cost of loading fp registers
1145 in SFmode, DFmode and XFmode */
1146 {6, 6, 8}, /* cost of storing fp registers
1147 in SFmode, DFmode and XFmode */
1148 2, /* cost of moving MMX register */
1149 {8, 8}, /* cost of loading MMX registers
1150 in SImode and DImode */
1151 {8, 8}, /* cost of storing MMX registers
1152 in SImode and DImode */
1153 2, /* cost of moving SSE register */
1154 {8, 8, 8}, /* cost of loading SSE registers
1155 in SImode, DImode and TImode */
1156 {8, 8, 8}, /* cost of storing SSE registers
1157 in SImode, DImode and TImode */
1158 5, /* MMX or SSE register to integer */
1159 32, /* size of l1 cache. */
1160 256, /* size of l2 cache. */
1161 64, /* size of prefetch block */
1162 6, /* number of parallel prefetches */
1163 3, /* Branch cost */
1164 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1165 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1166 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1167 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1168 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1169 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1173 DUMMY_STRINGOP_ALGS},
1174 1, /* scalar_stmt_cost. */
1175 1, /* scalar load_cost. */
1176 1, /* scalar_store_cost. */
1177 1, /* vec_stmt_cost. */
1178 1, /* vec_to_scalar_cost. */
1179 1, /* scalar_to_vec_cost. */
1180 1, /* vec_align_load_cost. */
1181 2, /* vec_unalign_load_cost. */
1182 1, /* vec_store_cost. */
1183 3, /* cond_taken_branch_cost. */
1184 1, /* cond_not_taken_branch_cost. */
1187 const struct processor_costs *ix86_cost = &pentium_cost;
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1215 unsigned char ix86_tune_features[X86_TUNE_LAST];
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1219 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1224 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1226 /* X86_TUNE_PUSH_MEMORY */
1227 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1228 | m_NOCONA | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1234 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1249 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1250 | m_NOCONA | m_CORE2 | m_GENERIC,
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1254 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1255 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1268 m_CORE2 | m_GENERIC,
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1271 m_386 | m_486 | m_K6_GEODE,
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1274 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_MOV0 */
1279 /* X86_TUNE_USE_CLTD */
1280 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1295 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1296 | m_GENERIC /* | m_PENT4 ? */,
1298 /* X86_TUNE_FAST_PREFIX */
1299 ~(m_PENT | m_486 | m_386),
1301 /* X86_TUNE_SINGLE_STRINGOP */
1302 m_386 | m_PENT4 | m_NOCONA,
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1322 /* X86_TUNE_ADD_ESP_8 */
1323 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1324 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_4 */
1327 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1329 /* X86_TUNE_SUB_ESP_8 */
1330 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1331 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1335 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1336 | m_GENERIC | m_GEODE),
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1350 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1365 m_PPRO | m_PENT4 | m_NOCONA,
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1368 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1374 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1383 ~(m_AMD_MULTIPLE | m_GENERIC),
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1390 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_SCHEDULE */
1393 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_BT */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_USE_INCDEC */
1399 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1401 /* X86_TUNE_PAD_RETURNS */
1402 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1405 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1419 m_K8 | m_GENERIC64 | m_AMDFAM10,
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 m_K8 | m_GENERIC64 | m_AMDFAM10,
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1440 m_AMDFAM10 | m_GENERIC,
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1452 /* Feature tests against the various architecture variations. */
1453 unsigned char ix86_arch_features[X86_ARCH_LAST];
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1457 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1459 ~(m_386 | m_486 | m_PENT | m_K6),
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1474 static const unsigned int x86_accumulate_outgoing_args
1475 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1477 static const unsigned int x86_arch_always_fancy_math_387
1478 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1479 | m_NOCONA | m_CORE2 | m_GENERIC;
1481 static enum stringop_alg stringop_alg = no_stringop;
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1489 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1490 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1491 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1496 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1498 /* ax, dx, cx, bx */
1499 AREG, DREG, CREG, BREG,
1500 /* si, di, bp, sp */
1501 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1503 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1504 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1507 /* flags, fpsr, fpcr, frame */
1508 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1510 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1513 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1516 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1517 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1518 /* SSE REX registers */
1519 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1523 /* The "default" register map used in 32bit mode. */
1525 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1527 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1528 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1529 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1530 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1531 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1532 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1533 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1536 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Define parameter passing and return registers. */
1623 static int const x86_64_int_parameter_registers[6] =
1625 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1628 static int const x86_64_ms_abi_int_parameter_registers[4] =
1630 CX_REG, DX_REG, R8_REG, R9_REG
1633 static int const x86_64_int_return_registers[4] =
1635 AX_REG, DX_REG, DI_REG, SI_REG
1638 /* Define the structure for the machine field in struct function. */
1640 struct stack_local_entry GTY(())
1642 unsigned short mode;
1645 struct stack_local_entry *next;
1648 /* Structure describing stack frame layout.
1649 Stack grows downward:
1655 saved frame pointer if frame_pointer_needed
1656 <- HARD_FRAME_POINTER
1665 [va_arg registers] (
1666 > to_allocate <- FRAME_POINTER
1678 HOST_WIDE_INT frame;
1680 int outgoing_arguments_size;
1683 HOST_WIDE_INT to_allocate;
1684 /* The offsets relative to ARG_POINTER. */
1685 HOST_WIDE_INT frame_pointer_offset;
1686 HOST_WIDE_INT hard_frame_pointer_offset;
1687 HOST_WIDE_INT stack_pointer_offset;
1689 /* When save_regs_using_mov is set, emit prologue using
1690 move instead of push instructions. */
1691 bool save_regs_using_mov;
1694 /* Code model option. */
1695 enum cmodel ix86_cmodel;
1697 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1699 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1701 /* Which unit we are generating floating point math for. */
1702 enum fpmath_unit ix86_fpmath;
1704 /* Which cpu are we scheduling for. */
1705 enum attr_cpu ix86_schedule;
1707 /* Which cpu are we optimizing for. */
1708 enum processor_type ix86_tune;
1710 /* Which instruction set architecture to use. */
1711 enum processor_type ix86_arch;
1713 /* true if sse prefetch instruction is not NOOP. */
1714 int x86_prefetch_sse;
1716 /* ix86_regparm_string as a number */
1717 static int ix86_regparm;
1719 /* -mstackrealign option */
1720 extern int ix86_force_align_arg_pointer;
1721 static const char ix86_force_align_arg_pointer_string[]
1722 = "force_align_arg_pointer";
1724 static rtx (*ix86_gen_leave) (void);
1725 static rtx (*ix86_gen_pop1) (rtx);
1726 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1727 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1728 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1729 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1730 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1731 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1733 /* Preferred alignment for stack boundary in bits. */
1734 unsigned int ix86_preferred_stack_boundary;
1736 /* Alignment for incoming stack boundary in bits specified at
1738 static unsigned int ix86_user_incoming_stack_boundary;
1740 /* Default alignment for incoming stack boundary in bits. */
1741 static unsigned int ix86_default_incoming_stack_boundary;
1743 /* Alignment for incoming stack boundary in bits. */
1744 unsigned int ix86_incoming_stack_boundary;
1746 /* Values 1-5: see jump.c */
1747 int ix86_branch_cost;
1749 /* Calling abi specific va_list type nodes. */
1750 static GTY(()) tree sysv_va_list_type_node;
1751 static GTY(()) tree ms_va_list_type_node;
1753 /* Variables which are this size or smaller are put in the data/bss
1754 or ldata/lbss sections. */
1756 int ix86_section_threshold = 65536;
1758 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1759 char internal_label_prefix[16];
1760 int internal_label_prefix_len;
1762 /* Fence to use after loop using movnt. */
1765 /* Register class used for passing given 64bit part of the argument.
1766 These represent classes as documented by the PS ABI, with the exception
1767 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1768 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1770 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1771 whenever possible (upper half does contain padding). */
1772 enum x86_64_reg_class
1775 X86_64_INTEGER_CLASS,
1776 X86_64_INTEGERSI_CLASS,
1783 X86_64_COMPLEX_X87_CLASS,
1787 #define MAX_CLASSES 4
1789 /* Table of constants used by fldpi, fldln2, etc.... */
1790 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1791 static bool ext_80387_constants_init = 0;
1794 static struct machine_function * ix86_init_machine_status (void);
1795 static rtx ix86_function_value (const_tree, const_tree, bool);
1796 static int ix86_function_regparm (const_tree, const_tree);
1797 static void ix86_compute_frame_layout (struct ix86_frame *);
1798 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1800 static void ix86_add_new_builtins (int);
1802 enum ix86_function_specific_strings
1804 IX86_FUNCTION_SPECIFIC_ARCH,
1805 IX86_FUNCTION_SPECIFIC_TUNE,
1806 IX86_FUNCTION_SPECIFIC_FPMATH,
1807 IX86_FUNCTION_SPECIFIC_MAX
1810 static char *ix86_target_string (int, int, const char *, const char *,
1811 const char *, bool);
1812 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1813 static void ix86_function_specific_save (struct cl_target_option *);
1814 static void ix86_function_specific_restore (struct cl_target_option *);
1815 static void ix86_function_specific_print (FILE *, int,
1816 struct cl_target_option *);
1817 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1818 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1819 static bool ix86_can_inline_p (tree, tree);
1820 static void ix86_set_current_function (tree);
1823 /* The svr4 ABI for the i386 says that records and unions are returned
1825 #ifndef DEFAULT_PCC_STRUCT_RETURN
1826 #define DEFAULT_PCC_STRUCT_RETURN 1
1829 /* Whether -mtune= or -march= were specified */
1830 static int ix86_tune_defaulted;
1831 static int ix86_arch_specified;
1833 /* Bit flags that specify the ISA we are compiling for. */
1834 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1836 /* A mask of ix86_isa_flags that includes bit X if X
1837 was set or cleared on the command line. */
1838 static int ix86_isa_flags_explicit;
1840 /* Define a set of ISAs which are available when a given ISA is
1841 enabled. MMX and SSE ISAs are handled separately. */
1843 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1844 #define OPTION_MASK_ISA_3DNOW_SET \
1845 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1847 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1848 #define OPTION_MASK_ISA_SSE2_SET \
1849 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1850 #define OPTION_MASK_ISA_SSE3_SET \
1851 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1852 #define OPTION_MASK_ISA_SSSE3_SET \
1853 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1854 #define OPTION_MASK_ISA_SSE4_1_SET \
1855 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1856 #define OPTION_MASK_ISA_SSE4_2_SET \
1857 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1858 #define OPTION_MASK_ISA_AVX_SET \
1859 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1860 #define OPTION_MASK_ISA_FMA_SET \
1861 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1863 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1865 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1867 #define OPTION_MASK_ISA_SSE4A_SET \
1868 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1869 #define OPTION_MASK_ISA_SSE5_SET \
1870 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1872 /* AES and PCLMUL need SSE2 because they use xmm registers */
1873 #define OPTION_MASK_ISA_AES_SET \
1874 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1875 #define OPTION_MASK_ISA_PCLMUL_SET \
1876 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1878 #define OPTION_MASK_ISA_ABM_SET \
1879 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1880 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1881 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1882 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1884 /* Define a set of ISAs which aren't available when a given ISA is
1885 disabled. MMX and SSE ISAs are handled separately. */
1887 #define OPTION_MASK_ISA_MMX_UNSET \
1888 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1889 #define OPTION_MASK_ISA_3DNOW_UNSET \
1890 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1891 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1893 #define OPTION_MASK_ISA_SSE_UNSET \
1894 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1895 #define OPTION_MASK_ISA_SSE2_UNSET \
1896 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1897 #define OPTION_MASK_ISA_SSE3_UNSET \
1898 (OPTION_MASK_ISA_SSE3 \
1899 | OPTION_MASK_ISA_SSSE3_UNSET \
1900 | OPTION_MASK_ISA_SSE4A_UNSET )
1901 #define OPTION_MASK_ISA_SSSE3_UNSET \
1902 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1903 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1904 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1905 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1906 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1907 #define OPTION_MASK_ISA_AVX_UNSET \
1908 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1909 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1911 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1913 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1915 #define OPTION_MASK_ISA_SSE4A_UNSET \
1916 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1917 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1918 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1919 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1920 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1921 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1922 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1923 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1925 /* Vectorization library interface and handlers. */
1926 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1927 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1928 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1930 /* Processor target table, indexed by processor number */
1933 const struct processor_costs *cost; /* Processor costs */
1934 const int align_loop; /* Default alignments. */
1935 const int align_loop_max_skip;
1936 const int align_jump;
1937 const int align_jump_max_skip;
1938 const int align_func;
1941 static const struct ptt processor_target_table[PROCESSOR_max] =
1943 {&i386_cost, 4, 3, 4, 3, 4},
1944 {&i486_cost, 16, 15, 16, 15, 16},
1945 {&pentium_cost, 16, 7, 16, 7, 16},
1946 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1947 {&geode_cost, 0, 0, 0, 0, 0},
1948 {&k6_cost, 32, 7, 32, 7, 32},
1949 {&athlon_cost, 16, 7, 16, 7, 16},
1950 {&pentium4_cost, 0, 0, 0, 0, 0},
1951 {&k8_cost, 16, 7, 16, 7, 16},
1952 {&nocona_cost, 0, 0, 0, 0, 0},
1953 {&core2_cost, 16, 10, 16, 10, 16},
1954 {&generic32_cost, 16, 7, 16, 7, 16},
1955 {&generic64_cost, 16, 10, 16, 10, 16},
1956 {&amdfam10_cost, 32, 24, 32, 7, 32}
1959 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1984 /* Implement TARGET_HANDLE_OPTION. */
1987 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1994 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1995 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1999 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2000 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2007 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2008 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2012 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2013 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2023 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2024 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2028 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2029 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2036 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2037 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2041 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2042 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2049 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2050 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2054 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2055 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2062 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2063 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2067 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2068 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2075 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2076 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2080 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2081 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2088 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2089 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2093 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2094 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2101 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2102 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2106 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2107 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2114 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2115 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2119 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2120 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2125 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2126 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2130 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2131 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2137 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2138 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2142 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2150 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2151 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2155 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2163 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2164 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2168 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2176 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2177 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2181 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2189 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2190 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2194 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2202 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2203 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2207 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2215 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2216 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2220 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2221 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2228 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2229 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2233 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2234 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2243 /* Return a string the documents the current -m options. The caller is
2244 responsible for freeing the string. */
2247 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2248 const char *fpmath, bool add_nl_p)
2250 struct ix86_target_opts
2252 const char *option; /* option string */
2253 int mask; /* isa mask options */
2256 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2257 preceding options while match those first. */
2258 static struct ix86_target_opts isa_opts[] =
2260 { "-m64", OPTION_MASK_ISA_64BIT },
2261 { "-msse5", OPTION_MASK_ISA_SSE5 },
2262 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2263 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2264 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2265 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2266 { "-msse3", OPTION_MASK_ISA_SSE3 },
2267 { "-msse2", OPTION_MASK_ISA_SSE2 },
2268 { "-msse", OPTION_MASK_ISA_SSE },
2269 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2270 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2271 { "-mmmx", OPTION_MASK_ISA_MMX },
2272 { "-mabm", OPTION_MASK_ISA_ABM },
2273 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2274 { "-maes", OPTION_MASK_ISA_AES },
2275 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2279 static struct ix86_target_opts flag_opts[] =
2281 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2282 { "-m80387", MASK_80387 },
2283 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2284 { "-malign-double", MASK_ALIGN_DOUBLE },
2285 { "-mcld", MASK_CLD },
2286 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2287 { "-mieee-fp", MASK_IEEE_FP },
2288 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2289 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2290 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2291 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2292 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2293 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2294 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2295 { "-mno-red-zone", MASK_NO_RED_ZONE },
2296 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2297 { "-mrecip", MASK_RECIP },
2298 { "-mrtd", MASK_RTD },
2299 { "-msseregparm", MASK_SSEREGPARM },
2300 { "-mstack-arg-probe", MASK_STACK_PROBE },
2301 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2304 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2307 char target_other[40];
2316 memset (opts, '\0', sizeof (opts));
2318 /* Add -march= option. */
2321 opts[num][0] = "-march=";
2322 opts[num++][1] = arch;
2325 /* Add -mtune= option. */
2328 opts[num][0] = "-mtune=";
2329 opts[num++][1] = tune;
2332 /* Pick out the options in isa options. */
2333 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2335 if ((isa & isa_opts[i].mask) != 0)
2337 opts[num++][0] = isa_opts[i].option;
2338 isa &= ~ isa_opts[i].mask;
2342 if (isa && add_nl_p)
2344 opts[num++][0] = isa_other;
2345 sprintf (isa_other, "(other isa: 0x%x)", isa);
2348 /* Add flag options. */
2349 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2351 if ((flags & flag_opts[i].mask) != 0)
2353 opts[num++][0] = flag_opts[i].option;
2354 flags &= ~ flag_opts[i].mask;
2358 if (flags && add_nl_p)
2360 opts[num++][0] = target_other;
2361 sprintf (target_other, "(other flags: 0x%x)", flags);
2364 /* Add -fpmath= option. */
2367 opts[num][0] = "-mfpmath=";
2368 opts[num++][1] = fpmath;
2375 gcc_assert (num < ARRAY_SIZE (opts));
2377 /* Size the string. */
2379 sep_len = (add_nl_p) ? 3 : 1;
2380 for (i = 0; i < num; i++)
2383 for (j = 0; j < 2; j++)
2385 len += strlen (opts[i][j]);
2388 /* Build the string. */
2389 ret = ptr = (char *) xmalloc (len);
2392 for (i = 0; i < num; i++)
2396 for (j = 0; j < 2; j++)
2397 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2404 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2412 for (j = 0; j < 2; j++)
2415 memcpy (ptr, opts[i][j], len2[j]);
2417 line_len += len2[j];
2422 gcc_assert (ret + len >= ptr);
2427 /* Function that is callable from the debugger to print the current
2430 ix86_debug_options (void)
2432 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2433 ix86_arch_string, ix86_tune_string,
2434 ix86_fpmath_string, true);
2438 fprintf (stderr, "%s\n\n", opts);
2442 fprintf (stderr, "<no options>\n\n");
2447 /* Sometimes certain combinations of command options do not make
2448 sense on a particular target machine. You can define a macro
2449 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2450 defined, is executed once just after all the command options have
2453 Don't use this macro to turn on various extra optimizations for
2454 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2457 override_options (bool main_args_p)
2460 unsigned int ix86_arch_mask, ix86_tune_mask;
2465 /* Comes from final.c -- no real reason to change it. */
2466 #define MAX_CODE_ALIGN 16
2474 PTA_PREFETCH_SSE = 1 << 4,
2476 PTA_3DNOW_A = 1 << 6,
2480 PTA_POPCNT = 1 << 10,
2482 PTA_SSE4A = 1 << 12,
2483 PTA_NO_SAHF = 1 << 13,
2484 PTA_SSE4_1 = 1 << 14,
2485 PTA_SSE4_2 = 1 << 15,
2488 PTA_PCLMUL = 1 << 18,
2495 const char *const name; /* processor name or nickname. */
2496 const enum processor_type processor;
2497 const enum attr_cpu schedule;
2498 const unsigned /*enum pta_flags*/ flags;
2500 const processor_alias_table[] =
2502 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2503 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2504 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2505 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2506 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2507 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2508 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2509 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2510 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2511 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2512 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2513 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2514 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2516 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2518 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2519 PTA_MMX | PTA_SSE | PTA_SSE2},
2520 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2521 PTA_MMX |PTA_SSE | PTA_SSE2},
2522 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2523 PTA_MMX | PTA_SSE | PTA_SSE2},
2524 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2525 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2526 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2527 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2528 | PTA_CX16 | PTA_NO_SAHF},
2529 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2530 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2531 | PTA_SSSE3 | PTA_CX16},
2532 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2533 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2534 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2535 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2536 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2537 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2538 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2539 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2540 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2541 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2542 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2543 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2544 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2545 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2546 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2547 {"x86-64", PROCESSOR_K8, CPU_K8,
2548 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2549 {"k8", PROCESSOR_K8, CPU_K8,
2550 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2551 | PTA_SSE2 | PTA_NO_SAHF},
2552 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2553 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2554 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2555 {"opteron", PROCESSOR_K8, CPU_K8,
2556 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2557 | PTA_SSE2 | PTA_NO_SAHF},
2558 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2559 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2560 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2561 {"athlon64", PROCESSOR_K8, CPU_K8,
2562 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2563 | PTA_SSE2 | PTA_NO_SAHF},
2564 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2565 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2566 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2567 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2568 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2569 | PTA_SSE2 | PTA_NO_SAHF},
2570 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2571 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2572 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2573 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2574 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2575 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2576 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2577 0 /* flags are only used for -march switch. */ },
2578 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2579 PTA_64BIT /* flags are only used for -march switch. */ },
2582 int const pta_size = ARRAY_SIZE (processor_alias_table);
2584 /* Set up prefix/suffix so the error messages refer to either the command
2585 line argument, or the attribute(target). */
2594 prefix = "option(\"";
2599 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2600 SUBTARGET_OVERRIDE_OPTIONS;
2603 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2604 SUBSUBTARGET_OVERRIDE_OPTIONS;
2607 /* -fPIC is the default for x86_64. */
2608 if (TARGET_MACHO && TARGET_64BIT)
2611 /* Set the default values for switches whose default depends on TARGET_64BIT
2612 in case they weren't overwritten by command line options. */
2615 /* Mach-O doesn't support omitting the frame pointer for now. */
2616 if (flag_omit_frame_pointer == 2)
2617 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2618 if (flag_asynchronous_unwind_tables == 2)
2619 flag_asynchronous_unwind_tables = 1;
2620 if (flag_pcc_struct_return == 2)
2621 flag_pcc_struct_return = 0;
2625 if (flag_omit_frame_pointer == 2)
2626 flag_omit_frame_pointer = 0;
2627 if (flag_asynchronous_unwind_tables == 2)
2628 flag_asynchronous_unwind_tables = 0;
2629 if (flag_pcc_struct_return == 2)
2630 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2633 /* Need to check -mtune=generic first. */
2634 if (ix86_tune_string)
2636 if (!strcmp (ix86_tune_string, "generic")
2637 || !strcmp (ix86_tune_string, "i686")
2638 /* As special support for cross compilers we read -mtune=native
2639 as -mtune=generic. With native compilers we won't see the
2640 -mtune=native, as it was changed by the driver. */
2641 || !strcmp (ix86_tune_string, "native"))
2644 ix86_tune_string = "generic64";
2646 ix86_tune_string = "generic32";
2648 /* If this call is for setting the option attribute, allow the
2649 generic32/generic64 that was previously set. */
2650 else if (!main_args_p
2651 && (!strcmp (ix86_tune_string, "generic32")
2652 || !strcmp (ix86_tune_string, "generic64")))
2654 else if (!strncmp (ix86_tune_string, "generic", 7))
2655 error ("bad value (%s) for %stune=%s %s",
2656 ix86_tune_string, prefix, suffix, sw);
2660 if (ix86_arch_string)
2661 ix86_tune_string = ix86_arch_string;
2662 if (!ix86_tune_string)
2664 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2665 ix86_tune_defaulted = 1;
2668 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2669 need to use a sensible tune option. */
2670 if (!strcmp (ix86_tune_string, "generic")
2671 || !strcmp (ix86_tune_string, "x86-64")
2672 || !strcmp (ix86_tune_string, "i686"))
2675 ix86_tune_string = "generic64";
2677 ix86_tune_string = "generic32";
2680 if (ix86_stringop_string)
2682 if (!strcmp (ix86_stringop_string, "rep_byte"))
2683 stringop_alg = rep_prefix_1_byte;
2684 else if (!strcmp (ix86_stringop_string, "libcall"))
2685 stringop_alg = libcall;
2686 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2687 stringop_alg = rep_prefix_4_byte;
2688 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2690 /* rep; movq isn't available in 32-bit code. */
2691 stringop_alg = rep_prefix_8_byte;
2692 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2693 stringop_alg = loop_1_byte;
2694 else if (!strcmp (ix86_stringop_string, "loop"))
2695 stringop_alg = loop;
2696 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2697 stringop_alg = unrolled_loop;
2699 error ("bad value (%s) for %sstringop-strategy=%s %s",
2700 ix86_stringop_string, prefix, suffix, sw);
2702 if (!strcmp (ix86_tune_string, "x86-64"))
2703 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2704 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2705 prefix, suffix, prefix, suffix, prefix, suffix);
2707 if (!ix86_arch_string)
2708 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i486";
2710 ix86_arch_specified = 1;
2712 if (!strcmp (ix86_arch_string, "generic"))
2713 error ("generic CPU can be used only for %stune=%s %s",
2714 prefix, suffix, sw);
2715 if (!strncmp (ix86_arch_string, "generic", 7))
2716 error ("bad value (%s) for %sarch=%s %s",
2717 ix86_arch_string, prefix, suffix, sw);
2719 if (ix86_cmodel_string != 0)
2721 if (!strcmp (ix86_cmodel_string, "small"))
2722 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2723 else if (!strcmp (ix86_cmodel_string, "medium"))
2724 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2725 else if (!strcmp (ix86_cmodel_string, "large"))
2726 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2728 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2729 else if (!strcmp (ix86_cmodel_string, "32"))
2730 ix86_cmodel = CM_32;
2731 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2732 ix86_cmodel = CM_KERNEL;
2734 error ("bad value (%s) for %scmodel=%s %s",
2735 ix86_cmodel_string, prefix, suffix, sw);
2739 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2740 use of rip-relative addressing. This eliminates fixups that
2741 would otherwise be needed if this object is to be placed in a
2742 DLL, and is essentially just as efficient as direct addressing. */
2743 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2744 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2745 else if (TARGET_64BIT)
2746 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2748 ix86_cmodel = CM_32;
2750 if (ix86_asm_string != 0)
2753 && !strcmp (ix86_asm_string, "intel"))
2754 ix86_asm_dialect = ASM_INTEL;
2755 else if (!strcmp (ix86_asm_string, "att"))
2756 ix86_asm_dialect = ASM_ATT;
2758 error ("bad value (%s) for %sasm=%s %s",
2759 ix86_asm_string, prefix, suffix, sw);
2761 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2762 error ("code model %qs not supported in the %s bit mode",
2763 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2764 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2765 sorry ("%i-bit mode not compiled in",
2766 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2768 for (i = 0; i < pta_size; i++)
2769 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2771 ix86_schedule = processor_alias_table[i].schedule;
2772 ix86_arch = processor_alias_table[i].processor;
2773 /* Default cpu tuning to the architecture. */
2774 ix86_tune = ix86_arch;
2776 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2777 error ("CPU you selected does not support x86-64 "
2780 if (processor_alias_table[i].flags & PTA_MMX
2781 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2782 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2783 if (processor_alias_table[i].flags & PTA_3DNOW
2784 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2785 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2786 if (processor_alias_table[i].flags & PTA_3DNOW_A
2787 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2788 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2789 if (processor_alias_table[i].flags & PTA_SSE
2790 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2791 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2792 if (processor_alias_table[i].flags & PTA_SSE2
2793 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2794 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2795 if (processor_alias_table[i].flags & PTA_SSE3
2796 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2797 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2798 if (processor_alias_table[i].flags & PTA_SSSE3
2799 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2800 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2801 if (processor_alias_table[i].flags & PTA_SSE4_1
2802 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2803 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2804 if (processor_alias_table[i].flags & PTA_SSE4_2
2805 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2806 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2807 if (processor_alias_table[i].flags & PTA_AVX
2808 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2809 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2810 if (processor_alias_table[i].flags & PTA_FMA
2811 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2812 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2813 if (processor_alias_table[i].flags & PTA_SSE4A
2814 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2815 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2816 if (processor_alias_table[i].flags & PTA_SSE5
2817 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2818 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2819 if (processor_alias_table[i].flags & PTA_ABM
2820 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2821 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2822 if (processor_alias_table[i].flags & PTA_CX16
2823 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2824 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2825 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2826 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2827 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2828 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2829 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2830 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2831 if (processor_alias_table[i].flags & PTA_AES
2832 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2833 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2834 if (processor_alias_table[i].flags & PTA_PCLMUL
2835 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2836 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2837 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2838 x86_prefetch_sse = true;
2844 error ("bad value (%s) for %sarch=%s %s",
2845 ix86_arch_string, prefix, suffix, sw);
2847 ix86_arch_mask = 1u << ix86_arch;
2848 for (i = 0; i < X86_ARCH_LAST; ++i)
2849 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2851 for (i = 0; i < pta_size; i++)
2852 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2854 ix86_schedule = processor_alias_table[i].schedule;
2855 ix86_tune = processor_alias_table[i].processor;
2856 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2858 if (ix86_tune_defaulted)
2860 ix86_tune_string = "x86-64";
2861 for (i = 0; i < pta_size; i++)
2862 if (! strcmp (ix86_tune_string,
2863 processor_alias_table[i].name))
2865 ix86_schedule = processor_alias_table[i].schedule;
2866 ix86_tune = processor_alias_table[i].processor;
2869 error ("CPU you selected does not support x86-64 "
2872 /* Intel CPUs have always interpreted SSE prefetch instructions as
2873 NOPs; so, we can enable SSE prefetch instructions even when
2874 -mtune (rather than -march) points us to a processor that has them.
2875 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2876 higher processors. */
2878 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2879 x86_prefetch_sse = true;
2883 error ("bad value (%s) for %stune=%s %s",
2884 ix86_tune_string, prefix, suffix, sw);
2886 ix86_tune_mask = 1u << ix86_tune;
2887 for (i = 0; i < X86_TUNE_LAST; ++i)
2888 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2891 ix86_cost = &ix86_size_cost;
2893 ix86_cost = processor_target_table[ix86_tune].cost;
2895 /* Arrange to set up i386_stack_locals for all functions. */
2896 init_machine_status = ix86_init_machine_status;
2898 /* Validate -mregparm= value. */
2899 if (ix86_regparm_string)
2902 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2903 i = atoi (ix86_regparm_string);
2904 if (i < 0 || i > REGPARM_MAX)
2905 error ("%sregparm=%d%s is not between 0 and %d",
2906 prefix, i, suffix, REGPARM_MAX);
2911 ix86_regparm = REGPARM_MAX;
2913 /* If the user has provided any of the -malign-* options,
2914 warn and use that value only if -falign-* is not set.
2915 Remove this code in GCC 3.2 or later. */
2916 if (ix86_align_loops_string)
2918 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
2919 prefix, suffix, suffix);
2920 if (align_loops == 0)
2922 i = atoi (ix86_align_loops_string);
2923 if (i < 0 || i > MAX_CODE_ALIGN)
2924 error ("%salign-loops=%d%s is not between 0 and %d",
2925 prefix, i, suffix, MAX_CODE_ALIGN);
2927 align_loops = 1 << i;
2931 if (ix86_align_jumps_string)
2933 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
2934 prefix, suffix, suffix);
2935 if (align_jumps == 0)
2937 i = atoi (ix86_align_jumps_string);
2938 if (i < 0 || i > MAX_CODE_ALIGN)
2939 error ("%salign-loops=%d%s is not between 0 and %d",
2940 prefix, i, suffix, MAX_CODE_ALIGN);
2942 align_jumps = 1 << i;
2946 if (ix86_align_funcs_string)
2948 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
2949 prefix, suffix, suffix);
2950 if (align_functions == 0)
2952 i = atoi (ix86_align_funcs_string);
2953 if (i < 0 || i > MAX_CODE_ALIGN)
2954 error ("%salign-loops=%d%s is not between 0 and %d",
2955 prefix, i, suffix, MAX_CODE_ALIGN);
2957 align_functions = 1 << i;
2961 /* Default align_* from the processor table. */
2962 if (align_loops == 0)
2964 align_loops = processor_target_table[ix86_tune].align_loop;
2965 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2967 if (align_jumps == 0)
2969 align_jumps = processor_target_table[ix86_tune].align_jump;
2970 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2972 if (align_functions == 0)
2974 align_functions = processor_target_table[ix86_tune].align_func;
2977 /* Validate -mbranch-cost= value, or provide default. */
2978 ix86_branch_cost = ix86_cost->branch_cost;
2979 if (ix86_branch_cost_string)
2981 i = atoi (ix86_branch_cost_string);
2983 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2985 ix86_branch_cost = i;
2987 if (ix86_section_threshold_string)
2989 i = atoi (ix86_section_threshold_string);
2991 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2993 ix86_section_threshold = i;
2996 if (ix86_tls_dialect_string)
2998 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2999 ix86_tls_dialect = TLS_DIALECT_GNU;
3000 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3001 ix86_tls_dialect = TLS_DIALECT_GNU2;
3003 error ("bad value (%s) for %stls-dialect=%s %s",
3004 ix86_tls_dialect_string, prefix, suffix, sw);
3007 if (ix87_precision_string)
3009 i = atoi (ix87_precision_string);
3010 if (i != 32 && i != 64 && i != 80)
3011 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3016 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3018 /* Enable by default the SSE and MMX builtins. Do allow the user to
3019 explicitly disable any of these. In particular, disabling SSE and
3020 MMX for kernel code is extremely useful. */
3021 if (!ix86_arch_specified)
3023 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3024 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3027 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3031 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3033 if (!ix86_arch_specified)
3035 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3037 /* i386 ABI does not specify red zone. It still makes sense to use it
3038 when programmer takes care to stack from being destroyed. */
3039 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3040 target_flags |= MASK_NO_RED_ZONE;
3043 /* Keep nonleaf frame pointers. */
3044 if (flag_omit_frame_pointer)
3045 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3046 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3047 flag_omit_frame_pointer = 1;
3049 /* If we're doing fast math, we don't care about comparison order
3050 wrt NaNs. This lets us use a shorter comparison sequence. */
3051 if (flag_finite_math_only)
3052 target_flags &= ~MASK_IEEE_FP;
3054 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3055 since the insns won't need emulation. */
3056 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3057 target_flags &= ~MASK_NO_FANCY_MATH_387;
3059 /* Likewise, if the target doesn't have a 387, or we've specified
3060 software floating point, don't use 387 inline intrinsics. */
3062 target_flags |= MASK_NO_FANCY_MATH_387;
3064 /* Turn on MMX builtins for -msse. */
3067 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3068 x86_prefetch_sse = true;
3071 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3072 if (TARGET_SSE4_2 || TARGET_ABM)
3073 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3075 /* Validate -mpreferred-stack-boundary= value or default it to
3076 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3077 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3078 if (ix86_preferred_stack_boundary_string)
3080 i = atoi (ix86_preferred_stack_boundary_string);
3081 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3082 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3083 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3085 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3088 /* Set the default value for -mstackrealign. */
3089 if (ix86_force_align_arg_pointer == -1)
3090 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3092 /* Validate -mincoming-stack-boundary= value or default it to
3093 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3094 if (ix86_force_align_arg_pointer)
3095 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3097 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3098 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3099 if (ix86_incoming_stack_boundary_string)
3101 i = atoi (ix86_incoming_stack_boundary_string);
3102 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3103 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3104 i, TARGET_64BIT ? 4 : 2);
3107 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3108 ix86_incoming_stack_boundary
3109 = ix86_user_incoming_stack_boundary;
3113 /* Accept -msseregparm only if at least SSE support is enabled. */
3114 if (TARGET_SSEREGPARM
3116 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3118 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3119 if (ix86_fpmath_string != 0)
3121 if (! strcmp (ix86_fpmath_string, "387"))
3122 ix86_fpmath = FPMATH_387;
3123 else if (! strcmp (ix86_fpmath_string, "sse"))
3127 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3128 ix86_fpmath = FPMATH_387;
3131 ix86_fpmath = FPMATH_SSE;
3133 else if (! strcmp (ix86_fpmath_string, "387,sse")
3134 || ! strcmp (ix86_fpmath_string, "387+sse")
3135 || ! strcmp (ix86_fpmath_string, "sse,387")
3136 || ! strcmp (ix86_fpmath_string, "sse+387")
3137 || ! strcmp (ix86_fpmath_string, "both"))
3141 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3142 ix86_fpmath = FPMATH_387;
3144 else if (!TARGET_80387)
3146 warning (0, "387 instruction set disabled, using SSE arithmetics");
3147 ix86_fpmath = FPMATH_SSE;
3150 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3153 error ("bad value (%s) for %sfpmath=%s %s",
3154 ix86_fpmath_string, prefix, suffix, sw);
3157 /* If the i387 is disabled, then do not return values in it. */
3159 target_flags &= ~MASK_FLOAT_RETURNS;
3161 /* Use external vectorized library in vectorizing intrinsics. */
3162 if (ix86_veclibabi_string)
3164 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3165 ix86_veclib_handler = ix86_veclibabi_svml;
3166 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3167 ix86_veclib_handler = ix86_veclibabi_acml;
3169 error ("unknown vectorization library ABI type (%s) for "
3170 "%sveclibabi=%s %s", ix86_veclibabi_string,
3171 prefix, suffix, sw);
3174 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3175 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3177 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3179 /* ??? Unwind info is not correct around the CFG unless either a frame
3180 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3181 unwind info generation to be aware of the CFG and propagating states
3183 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3184 || flag_exceptions || flag_non_call_exceptions)
3185 && flag_omit_frame_pointer
3186 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3188 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3189 warning (0, "unwind tables currently require either a frame pointer "
3190 "or %saccumulate-outgoing-args%s for correctness",
3192 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3195 /* If stack probes are required, the space used for large function
3196 arguments on the stack must also be probed, so enable
3197 -maccumulate-outgoing-args so this happens in the prologue. */
3198 if (TARGET_STACK_PROBE
3199 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3201 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3202 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3203 "for correctness", prefix, suffix);
3204 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3207 /* For sane SSE instruction set generation we need fcomi instruction.
3208 It is safe to enable all CMOVE instructions. */
3212 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3215 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3216 p = strchr (internal_label_prefix, 'X');
3217 internal_label_prefix_len = p - internal_label_prefix;
3221 /* When scheduling description is not available, disable scheduler pass
3222 so it won't slow down the compilation and make x87 code slower. */
3223 if (!TARGET_SCHEDULE)
3224 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3226 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3227 set_param_value ("simultaneous-prefetches",
3228 ix86_cost->simultaneous_prefetches);
3229 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3230 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3231 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3232 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3233 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3234 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3236 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3237 can be optimized to ap = __builtin_next_arg (0). */
3239 targetm.expand_builtin_va_start = NULL;
3243 ix86_gen_leave = gen_leave_rex64;
3244 ix86_gen_pop1 = gen_popdi1;
3245 ix86_gen_add3 = gen_adddi3;
3246 ix86_gen_sub3 = gen_subdi3;
3247 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3248 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3249 ix86_gen_monitor = gen_sse3_monitor64;
3250 ix86_gen_andsp = gen_anddi3;
3254 ix86_gen_leave = gen_leave;
3255 ix86_gen_pop1 = gen_popsi1;
3256 ix86_gen_add3 = gen_addsi3;
3257 ix86_gen_sub3 = gen_subsi3;
3258 ix86_gen_sub3_carry = gen_subsi3_carry;
3259 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3260 ix86_gen_monitor = gen_sse3_monitor;
3261 ix86_gen_andsp = gen_andsi3;
3265 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3267 target_flags |= MASK_CLD & ~target_flags_explicit;
3270 /* Save the initial options in case the user does function specific options */
3272 target_option_default_node = target_option_current_node
3273 = build_target_option_node ();
3276 /* Update register usage after having seen the compiler flags. */
3279 ix86_conditional_register_usage (void)
3284 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3286 if (fixed_regs[i] > 1)
3287 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3288 if (call_used_regs[i] > 1)
3289 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3292 /* The PIC register, if it exists, is fixed. */
3293 j = PIC_OFFSET_TABLE_REGNUM;
3294 if (j != INVALID_REGNUM)
3295 fixed_regs[j] = call_used_regs[j] = 1;
3297 /* The MS_ABI changes the set of call-used registers. */
3298 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3300 call_used_regs[SI_REG] = 0;
3301 call_used_regs[DI_REG] = 0;
3302 call_used_regs[XMM6_REG] = 0;
3303 call_used_regs[XMM7_REG] = 0;
3304 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3305 call_used_regs[i] = 0;
3308 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3309 other call-clobbered regs for 64-bit. */
3312 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3314 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3315 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3316 && call_used_regs[i])
3317 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3320 /* If MMX is disabled, squash the registers. */
3322 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3323 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3324 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3326 /* If SSE is disabled, squash the registers. */
3328 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3329 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3330 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3332 /* If the FPU is disabled, squash the registers. */
3333 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3334 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3335 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3336 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3338 /* If 32-bit, squash the 64-bit registers. */
3341 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3343 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3349 /* Save the current options */
3352 ix86_function_specific_save (struct cl_target_option *ptr)
3354 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3355 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3356 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3357 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3358 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3360 ptr->arch = ix86_arch;
3361 ptr->schedule = ix86_schedule;
3362 ptr->tune = ix86_tune;
3363 ptr->fpmath = ix86_fpmath;
3364 ptr->branch_cost = ix86_branch_cost;
3365 ptr->tune_defaulted = ix86_tune_defaulted;
3366 ptr->arch_specified = ix86_arch_specified;
3367 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3368 ptr->target_flags_explicit = target_flags_explicit;
3371 /* Restore the current options */
3374 ix86_function_specific_restore (struct cl_target_option *ptr)
3376 enum processor_type old_tune = ix86_tune;
3377 enum processor_type old_arch = ix86_arch;
3378 unsigned int ix86_arch_mask, ix86_tune_mask;
3381 ix86_arch = ptr->arch;
3382 ix86_schedule = ptr->schedule;
3383 ix86_tune = ptr->tune;
3384 ix86_fpmath = ptr->fpmath;
3385 ix86_branch_cost = ptr->branch_cost;
3386 ix86_tune_defaulted = ptr->tune_defaulted;
3387 ix86_arch_specified = ptr->arch_specified;
3388 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3389 target_flags_explicit = ptr->target_flags_explicit;
3391 /* Recreate the arch feature tests if the arch changed */
3392 if (old_arch != ix86_arch)
3394 ix86_arch_mask = 1u << ix86_arch;
3395 for (i = 0; i < X86_ARCH_LAST; ++i)
3396 ix86_arch_features[i]
3397 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3400 /* Recreate the tune optimization tests */
3401 if (old_tune != ix86_tune)
3403 ix86_tune_mask = 1u << ix86_tune;
3404 for (i = 0; i < X86_TUNE_LAST; ++i)
3405 ix86_tune_features[i]
3406 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3410 /* Print the current options */
3413 ix86_function_specific_print (FILE *file, int indent,
3414 struct cl_target_option *ptr)
3417 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3418 NULL, NULL, NULL, false);
3420 fprintf (file, "%*sarch = %d (%s)\n",
3423 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3424 ? cpu_names[ptr->arch]
3427 fprintf (file, "%*stune = %d (%s)\n",
3430 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3431 ? cpu_names[ptr->tune]
3434 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3435 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3436 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3437 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3441 fprintf (file, "%*s%s\n", indent, "", target_string);
3442 free (target_string);
3447 /* Inner function to process the attribute((target(...))), take an argument and
3448 set the current options from the argument. If we have a list, recursively go
3452 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3457 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3458 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3459 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3460 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3475 enum ix86_opt_type type;
3480 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3481 IX86_ATTR_ISA ("abm", OPT_mabm),
3482 IX86_ATTR_ISA ("aes", OPT_maes),
3483 IX86_ATTR_ISA ("avx", OPT_mavx),
3484 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3485 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3486 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3487 IX86_ATTR_ISA ("sse", OPT_msse),
3488 IX86_ATTR_ISA ("sse2", OPT_msse2),
3489 IX86_ATTR_ISA ("sse3", OPT_msse3),
3490 IX86_ATTR_ISA ("sse4", OPT_msse4),
3491 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3492 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3493 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3494 IX86_ATTR_ISA ("sse5", OPT_msse5),
3495 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3497 /* string options */
3498 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3499 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3500 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3503 IX86_ATTR_YES ("cld",
3507 IX86_ATTR_NO ("fancy-math-387",
3508 OPT_mfancy_math_387,
3509 MASK_NO_FANCY_MATH_387),
3511 IX86_ATTR_NO ("fused-madd",
3513 MASK_NO_FUSED_MADD),
3515 IX86_ATTR_YES ("ieee-fp",
3519 IX86_ATTR_YES ("inline-all-stringops",
3520 OPT_minline_all_stringops,
3521 MASK_INLINE_ALL_STRINGOPS),
3523 IX86_ATTR_YES ("inline-stringops-dynamically",
3524 OPT_minline_stringops_dynamically,
3525 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3527 IX86_ATTR_NO ("align-stringops",
3528 OPT_mno_align_stringops,
3529 MASK_NO_ALIGN_STRINGOPS),
3531 IX86_ATTR_YES ("recip",
3537 /* If this is a list, recurse to get the options. */
3538 if (TREE_CODE (args) == TREE_LIST)
3542 for (; args; args = TREE_CHAIN (args))
3543 if (TREE_VALUE (args)
3544 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3550 else if (TREE_CODE (args) != STRING_CST)
3553 /* Handle multiple arguments separated by commas. */
3554 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3556 while (next_optstr && *next_optstr != '\0')
3558 char *p = next_optstr;
3560 char *comma = strchr (next_optstr, ',');
3561 const char *opt_string;
3562 size_t len, opt_len;
3567 enum ix86_opt_type type = ix86_opt_unknown;
3573 len = comma - next_optstr;
3574 next_optstr = comma + 1;
3582 /* Recognize no-xxx. */
3583 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3592 /* Find the option. */
3595 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3597 type = attrs[i].type;
3598 opt_len = attrs[i].len;
3599 if (ch == attrs[i].string[0]
3600 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3601 && memcmp (p, attrs[i].string, opt_len) == 0)
3604 mask = attrs[i].mask;
3605 opt_string = attrs[i].string;
3610 /* Process the option. */
3613 error ("attribute(target(\"%s\")) is unknown", orig_p);
3617 else if (type == ix86_opt_isa)
3618 ix86_handle_option (opt, p, opt_set_p);
3620 else if (type == ix86_opt_yes || type == ix86_opt_no)
3622 if (type == ix86_opt_no)
3623 opt_set_p = !opt_set_p;
3626 target_flags |= mask;
3628 target_flags &= ~mask;
3631 else if (type == ix86_opt_str)
3635 error ("option(\"%s\") was already specified", opt_string);
3639 p_strings[opt] = xstrdup (p + opt_len);
3649 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3652 ix86_valid_target_attribute_tree (tree args)
3654 const char *orig_arch_string = ix86_arch_string;
3655 const char *orig_tune_string = ix86_tune_string;
3656 const char *orig_fpmath_string = ix86_fpmath_string;
3657 int orig_tune_defaulted = ix86_tune_defaulted;
3658 int orig_arch_specified = ix86_arch_specified;
3659 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3662 struct cl_target_option *def
3663 = TREE_TARGET_OPTION (target_option_default_node);
3665 /* Process each of the options on the chain. */
3666 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3669 /* If the changed options are different from the default, rerun override_options,
3670 and then save the options away. The string options are are attribute options,
3671 and will be undone when we copy the save structure. */
3672 if (ix86_isa_flags != def->ix86_isa_flags
3673 || target_flags != def->target_flags
3674 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3675 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3676 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3678 /* If we are using the default tune= or arch=, undo the string assigned,
3679 and use the default. */
3680 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3681 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3682 else if (!orig_arch_specified)
3683 ix86_arch_string = NULL;
3685 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3686 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3687 else if (orig_tune_defaulted)
3688 ix86_tune_string = NULL;
3690 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3691 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3692 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3693 else if (!TARGET_64BIT && TARGET_SSE)
3694 ix86_fpmath_string = "sse,387";
3696 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3697 override_options (false);
3699 /* Add any builtin functions with the new isa if any. */
3700 ix86_add_new_builtins (ix86_isa_flags);
3702 /* Save the current options unless we are validating options for
3704 t = build_target_option_node ();
3706 ix86_arch_string = orig_arch_string;
3707 ix86_tune_string = orig_tune_string;
3708 ix86_fpmath_string = orig_fpmath_string;
3710 /* Free up memory allocated to hold the strings */
3711 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3712 if (option_strings[i])
3713 free (option_strings[i]);
3719 /* Hook to validate attribute((target("string"))). */
3722 ix86_valid_target_attribute_p (tree fndecl,
3723 tree ARG_UNUSED (name),
3725 int ARG_UNUSED (flags))
3727 struct cl_target_option cur_target;
3729 tree old_optimize = build_optimization_node ();
3730 tree new_target, new_optimize;
3731 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3733 /* If the function changed the optimization levels as well as setting target
3734 options, start with the optimizations specified. */
3735 if (func_optimize && func_optimize != old_optimize)
3736 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3738 /* The target attributes may also change some optimization flags, so update
3739 the optimization options if necessary. */
3740 cl_target_option_save (&cur_target);
3741 new_target = ix86_valid_target_attribute_tree (args);
3742 new_optimize = build_optimization_node ();
3749 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3751 if (old_optimize != new_optimize)
3752 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3755 cl_target_option_restore (&cur_target);
3757 if (old_optimize != new_optimize)
3758 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3764 /* Hook to determine if one function can safely inline another. */
3767 ix86_can_inline_p (tree caller, tree callee)
3770 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3771 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3773 /* If callee has no option attributes, then it is ok to inline. */
3777 /* If caller has no option attributes, but callee does then it is not ok to
3779 else if (!caller_tree)
3784 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3785 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3787 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3788 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3790 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3791 != callee_opts->ix86_isa_flags)
3794 /* See if we have the same non-isa options. */
3795 else if (caller_opts->target_flags != callee_opts->target_flags)
3798 /* See if arch, tune, etc. are the same. */
3799 else if (caller_opts->arch != callee_opts->arch)
3802 else if (caller_opts->tune != callee_opts->tune)
3805 else if (caller_opts->fpmath != callee_opts->fpmath)
3808 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3819 /* Remember the last target of ix86_set_current_function. */
3820 static GTY(()) tree ix86_previous_fndecl;
3822 /* Establish appropriate back-end context for processing the function
3823 FNDECL. The argument might be NULL to indicate processing at top
3824 level, outside of any function scope. */
3826 ix86_set_current_function (tree fndecl)
3828 /* Only change the context if the function changes. This hook is called
3829 several times in the course of compiling a function, and we don't want to
3830 slow things down too much or call target_reinit when it isn't safe. */
3831 if (fndecl && fndecl != ix86_previous_fndecl)
3833 tree old_tree = (ix86_previous_fndecl
3834 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3837 tree new_tree = (fndecl
3838 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3841 ix86_previous_fndecl = fndecl;
3842 if (old_tree == new_tree)
3847 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3853 struct cl_target_option *def
3854 = TREE_TARGET_OPTION (target_option_current_node);
3856 cl_target_option_restore (def);
3863 /* Return true if this goes in large data/bss. */
3866 ix86_in_large_data_p (tree exp)
3868 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3871 /* Functions are never large data. */
3872 if (TREE_CODE (exp) == FUNCTION_DECL)
3875 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3877 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3878 if (strcmp (section, ".ldata") == 0
3879 || strcmp (section, ".lbss") == 0)
3885 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3887 /* If this is an incomplete type with size 0, then we can't put it
3888 in data because it might be too big when completed. */
3889 if (!size || size > ix86_section_threshold)
3896 /* Switch to the appropriate section for output of DECL.
3897 DECL is either a `VAR_DECL' node or a constant of some sort.
3898 RELOC indicates whether forming the initial value of DECL requires
3899 link-time relocations. */
3901 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3905 x86_64_elf_select_section (tree decl, int reloc,
3906 unsigned HOST_WIDE_INT align)
3908 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3909 && ix86_in_large_data_p (decl))
3911 const char *sname = NULL;
3912 unsigned int flags = SECTION_WRITE;
3913 switch (categorize_decl_for_section (decl, reloc))
3918 case SECCAT_DATA_REL:
3919 sname = ".ldata.rel";
3921 case SECCAT_DATA_REL_LOCAL:
3922 sname = ".ldata.rel.local";
3924 case SECCAT_DATA_REL_RO:
3925 sname = ".ldata.rel.ro";
3927 case SECCAT_DATA_REL_RO_LOCAL:
3928 sname = ".ldata.rel.ro.local";
3932 flags |= SECTION_BSS;
3935 case SECCAT_RODATA_MERGE_STR:
3936 case SECCAT_RODATA_MERGE_STR_INIT:
3937 case SECCAT_RODATA_MERGE_CONST:
3941 case SECCAT_SRODATA:
3948 /* We don't split these for medium model. Place them into
3949 default sections and hope for best. */
3951 case SECCAT_EMUTLS_VAR:
3952 case SECCAT_EMUTLS_TMPL:
3957 /* We might get called with string constants, but get_named_section
3958 doesn't like them as they are not DECLs. Also, we need to set
3959 flags in that case. */
3961 return get_section (sname, flags, NULL);
3962 return get_named_section (decl, sname, reloc);
3965 return default_elf_select_section (decl, reloc, align);
3968 /* Build up a unique section name, expressed as a
3969 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3970 RELOC indicates whether the initial value of EXP requires
3971 link-time relocations. */
3973 static void ATTRIBUTE_UNUSED
3974 x86_64_elf_unique_section (tree decl, int reloc)
3976 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3977 && ix86_in_large_data_p (decl))
3979 const char *prefix = NULL;
3980 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3981 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3983 switch (categorize_decl_for_section (decl, reloc))
3986 case SECCAT_DATA_REL:
3987 case SECCAT_DATA_REL_LOCAL:
3988 case SECCAT_DATA_REL_RO:
3989 case SECCAT_DATA_REL_RO_LOCAL:
3990 prefix = one_only ? ".ld" : ".ldata";
3993 prefix = one_only ? ".lb" : ".lbss";
3996 case SECCAT_RODATA_MERGE_STR:
3997 case SECCAT_RODATA_MERGE_STR_INIT:
3998 case SECCAT_RODATA_MERGE_CONST:
3999 prefix = one_only ? ".lr" : ".lrodata";
4001 case SECCAT_SRODATA:
4008 /* We don't split these for medium model. Place them into
4009 default sections and hope for best. */
4011 case SECCAT_EMUTLS_VAR:
4012 prefix = targetm.emutls.var_section;
4014 case SECCAT_EMUTLS_TMPL:
4015 prefix = targetm.emutls.tmpl_section;
4020 const char *name, *linkonce;
4023 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4024 name = targetm.strip_name_encoding (name);
4026 /* If we're using one_only, then there needs to be a .gnu.linkonce
4027 prefix to the section name. */
4028 linkonce = one_only ? ".gnu.linkonce" : "";
4030 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4032 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4036 default_unique_section (decl, reloc);
4039 #ifdef COMMON_ASM_OP
4040 /* This says how to output assembler code to declare an
4041 uninitialized external linkage data object.
4043 For medium model x86-64 we need to use .largecomm opcode for
4046 x86_elf_aligned_common (FILE *file,
4047 const char *name, unsigned HOST_WIDE_INT size,
4050 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4051 && size > (unsigned int)ix86_section_threshold)
4052 fprintf (file, ".largecomm\t");
4054 fprintf (file, "%s", COMMON_ASM_OP);
4055 assemble_name (file, name);
4056 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
4057 size, align / BITS_PER_UNIT);
4061 /* Utility function for targets to use in implementing
4062 ASM_OUTPUT_ALIGNED_BSS. */
4065 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4066 const char *name, unsigned HOST_WIDE_INT size,
4069 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4070 && size > (unsigned int)ix86_section_threshold)
4071 switch_to_section (get_named_section (decl, ".lbss", 0));
4073 switch_to_section (bss_section);
4074 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4075 #ifdef ASM_DECLARE_OBJECT_NAME
4076 last_assemble_variable_decl = decl;
4077 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4079 /* Standard thing is just output label for the object. */
4080 ASM_OUTPUT_LABEL (file, name);
4081 #endif /* ASM_DECLARE_OBJECT_NAME */
4082 ASM_OUTPUT_SKIP (file, size ? size : 1);
4086 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4088 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4089 make the problem with not enough registers even worse. */
4090 #ifdef INSN_SCHEDULING
4092 flag_schedule_insns = 0;
4096 /* The Darwin libraries never set errno, so we might as well
4097 avoid calling them when that's the only reason we would. */
4098 flag_errno_math = 0;
4100 /* The default values of these switches depend on the TARGET_64BIT
4101 that is not known at this moment. Mark these values with 2 and
4102 let user the to override these. In case there is no command line option
4103 specifying them, we will set the defaults in override_options. */
4105 flag_omit_frame_pointer = 2;
4106 flag_pcc_struct_return = 2;
4107 flag_asynchronous_unwind_tables = 2;
4108 flag_vect_cost_model = 1;
4109 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4110 SUBTARGET_OPTIMIZATION_OPTIONS;
4114 /* Decide whether we can make a sibling call to a function. DECL is the
4115 declaration of the function being targeted by the call and EXP is the
4116 CALL_EXPR representing the call. */
4119 ix86_function_ok_for_sibcall (tree decl, tree exp)
4121 tree type, decl_or_type;
4124 /* If we are generating position-independent code, we cannot sibcall
4125 optimize any indirect call, or a direct call to a global function,
4126 as the PLT requires %ebx be live. */
4127 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4130 /* If we need to align the outgoing stack, then sibcalling would
4131 unalign the stack, which may break the called function. */
4132 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4137 decl_or_type = decl;
4138 type = TREE_TYPE (decl);
4142 /* We're looking at the CALL_EXPR, we need the type of the function. */
4143 type = CALL_EXPR_FN (exp); /* pointer expression */
4144 type = TREE_TYPE (type); /* pointer type */
4145 type = TREE_TYPE (type); /* function type */
4146 decl_or_type = type;
4149 /* Check that the return value locations are the same. Like
4150 if we are returning floats on the 80387 register stack, we cannot
4151 make a sibcall from a function that doesn't return a float to a
4152 function that does or, conversely, from a function that does return
4153 a float to a function that doesn't; the necessary stack adjustment
4154 would not be executed. This is also the place we notice
4155 differences in the return value ABI. Note that it is ok for one
4156 of the functions to have void return type as long as the return
4157 value of the other is passed in a register. */
4158 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4159 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4161 if (STACK_REG_P (a) || STACK_REG_P (b))
4163 if (!rtx_equal_p (a, b))
4166 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4168 else if (!rtx_equal_p (a, b))
4173 /* The SYSV ABI has more call-clobbered registers;
4174 disallow sibcalls from MS to SYSV. */
4175 if (cfun->machine->call_abi == MS_ABI
4176 && ix86_function_type_abi (type) == SYSV_ABI)
4181 /* If this call is indirect, we'll need to be able to use a
4182 call-clobbered register for the address of the target function.
4183 Make sure that all such registers are not used for passing
4184 parameters. Note that DLLIMPORT functions are indirect. */
4186 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4188 if (ix86_function_regparm (type, NULL) >= 3)
4190 /* ??? Need to count the actual number of registers to be used,
4191 not the possible number of registers. Fix later. */
4197 /* Otherwise okay. That also includes certain types of indirect calls. */
4201 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4202 calling convention attributes;
4203 arguments as in struct attribute_spec.handler. */
4206 ix86_handle_cconv_attribute (tree *node, tree name,
4208 int flags ATTRIBUTE_UNUSED,
4211 if (TREE_CODE (*node) != FUNCTION_TYPE
4212 && TREE_CODE (*node) != METHOD_TYPE
4213 && TREE_CODE (*node) != FIELD_DECL
4214 && TREE_CODE (*node) != TYPE_DECL)
4216 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4217 IDENTIFIER_POINTER (name));
4218 *no_add_attrs = true;
4222 /* Can combine regparm with all attributes but fastcall. */
4223 if (is_attribute_p ("regparm", name))
4227 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4229 error ("fastcall and regparm attributes are not compatible");
4232 cst = TREE_VALUE (args);
4233 if (TREE_CODE (cst) != INTEGER_CST)
4235 warning (OPT_Wattributes,
4236 "%qs attribute requires an integer constant argument",
4237 IDENTIFIER_POINTER (name));
4238 *no_add_attrs = true;
4240 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4242 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4243 IDENTIFIER_POINTER (name), REGPARM_MAX);
4244 *no_add_attrs = true;
4252 /* Do not warn when emulating the MS ABI. */
4253 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4254 warning (OPT_Wattributes, "%qs attribute ignored",
4255 IDENTIFIER_POINTER (name));
4256 *no_add_attrs = true;
4260 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4261 if (is_attribute_p ("fastcall", name))
4263 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4265 error ("fastcall and cdecl attributes are not compatible");
4267 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4269 error ("fastcall and stdcall attributes are not compatible");
4271 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4273 error ("fastcall and regparm attributes are not compatible");
4277 /* Can combine stdcall with fastcall (redundant), regparm and
4279 else if (is_attribute_p ("stdcall", name))
4281 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4283 error ("stdcall and cdecl attributes are not compatible");
4285 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4287 error ("stdcall and fastcall attributes are not compatible");
4291 /* Can combine cdecl with regparm and sseregparm. */
4292 else if (is_attribute_p ("cdecl", name))
4294 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4296 error ("stdcall and cdecl attributes are not compatible");
4298 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4300 error ("fastcall and cdecl attributes are not compatible");
4304 /* Can combine sseregparm with all attributes. */
4309 /* Return 0 if the attributes for two types are incompatible, 1 if they
4310 are compatible, and 2 if they are nearly compatible (which causes a
4311 warning to be generated). */
4314 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4316 /* Check for mismatch of non-default calling convention. */
4317 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4319 if (TREE_CODE (type1) != FUNCTION_TYPE
4320 && TREE_CODE (type1) != METHOD_TYPE)
4323 /* Check for mismatched fastcall/regparm types. */
4324 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4325 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4326 || (ix86_function_regparm (type1, NULL)
4327 != ix86_function_regparm (type2, NULL)))
4330 /* Check for mismatched sseregparm types. */
4331 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4332 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4335 /* Check for mismatched return types (cdecl vs stdcall). */
4336 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4337 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4343 /* Return the regparm value for a function with the indicated TYPE and DECL.
4344 DECL may be NULL when calling function indirectly
4345 or considering a libcall. */
4348 ix86_function_regparm (const_tree type, const_tree decl)
4353 static bool error_issued;
4356 return (ix86_function_type_abi (type) == SYSV_ABI
4357 ? X86_64_REGPARM_MAX : X64_REGPARM_MAX);
4359 regparm = ix86_regparm;
4360 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4364 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4366 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4368 /* We can't use regparm(3) for nested functions because
4369 these pass static chain pointer in %ecx register. */
4370 if (!error_issued && regparm == 3
4371 && decl_function_context (decl)
4372 && !DECL_NO_STATIC_CHAIN (decl))
4374 error ("nested functions are limited to 2 register parameters");
4375 error_issued = true;
4383 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4386 /* Use register calling convention for local functions when possible. */
4388 && TREE_CODE (decl) == FUNCTION_DECL
4392 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4393 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4396 int local_regparm, globals = 0, regno;
4399 /* Make sure no regparm register is taken by a
4400 fixed register variable. */
4401 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4402 if (fixed_regs[local_regparm])
4405 /* We can't use regparm(3) for nested functions as these use
4406 static chain pointer in third argument. */
4407 if (local_regparm == 3
4408 && decl_function_context (decl)
4409 && !DECL_NO_STATIC_CHAIN (decl))
4412 /* If the function realigns its stackpointer, the prologue will
4413 clobber %ecx. If we've already generated code for the callee,
4414 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4415 scanning the attributes for the self-realigning property. */
4416 f = DECL_STRUCT_FUNCTION (decl);
4417 /* Since current internal arg pointer won't conflict with
4418 parameter passing regs, so no need to change stack
4419 realignment and adjust regparm number.
4421 Each fixed register usage increases register pressure,
4422 so less registers should be used for argument passing.
4423 This functionality can be overriden by an explicit
4425 for (regno = 0; regno <= DI_REG; regno++)
4426 if (fixed_regs[regno])
4430 = globals < local_regparm ? local_regparm - globals : 0;
4432 if (local_regparm > regparm)
4433 regparm = local_regparm;
4440 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4441 DFmode (2) arguments in SSE registers for a function with the
4442 indicated TYPE and DECL. DECL may be NULL when calling function
4443 indirectly or considering a libcall. Otherwise return 0. */
4446 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4448 gcc_assert (!TARGET_64BIT);
4450 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4451 by the sseregparm attribute. */
4452 if (TARGET_SSEREGPARM
4453 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4460 error ("Calling %qD with attribute sseregparm without "
4461 "SSE/SSE2 enabled", decl);
4463 error ("Calling %qT with attribute sseregparm without "
4464 "SSE/SSE2 enabled", type);
4472 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4473 (and DFmode for SSE2) arguments in SSE registers. */
4474 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4476 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4477 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4479 return TARGET_SSE2 ? 2 : 1;
4485 /* Return true if EAX is live at the start of the function. Used by
4486 ix86_expand_prologue to determine if we need special help before
4487 calling allocate_stack_worker. */
4490 ix86_eax_live_at_start_p (void)
4492 /* Cheat. Don't bother working forward from ix86_function_regparm
4493 to the function type to whether an actual argument is located in
4494 eax. Instead just look at cfg info, which is still close enough
4495 to correct at this point. This gives false positives for broken
4496 functions that might use uninitialized data that happens to be
4497 allocated in eax, but who cares? */
4498 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4501 /* Value is the number of bytes of arguments automatically
4502 popped when returning from a subroutine call.
4503 FUNDECL is the declaration node of the function (as a tree),
4504 FUNTYPE is the data type of the function (as a tree),
4505 or for a library call it is an identifier node for the subroutine name.
4506 SIZE is the number of bytes of arguments passed on the stack.
4508 On the 80386, the RTD insn may be used to pop them if the number
4509 of args is fixed, but if the number is variable then the caller
4510 must pop them all. RTD can't be used for library calls now
4511 because the library is compiled with the Unix compiler.
4512 Use of RTD is a selectable option, since it is incompatible with
4513 standard Unix calling sequences. If the option is not selected,
4514 the caller must always pop the args.
4516 The attribute stdcall is equivalent to RTD on a per module basis. */
4519 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4523 /* None of the 64-bit ABIs pop arguments. */
4527 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4529 /* Cdecl functions override -mrtd, and never pop the stack. */
4530 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4532 /* Stdcall and fastcall functions will pop the stack if not
4534 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4535 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4538 if (rtd && ! stdarg_p (funtype))
4542 /* Lose any fake structure return argument if it is passed on the stack. */
4543 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4544 && !KEEP_AGGREGATE_RETURN_POINTER)
4546 int nregs = ix86_function_regparm (funtype, fundecl);
4548 return GET_MODE_SIZE (Pmode);
4554 /* Argument support functions. */
4556 /* Return true when register may be used to pass function parameters. */
4558 ix86_function_arg_regno_p (int regno)
4561 const int *parm_regs;
4566 return (regno < REGPARM_MAX
4567 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4569 return (regno < REGPARM_MAX
4570 || (TARGET_MMX && MMX_REGNO_P (regno)
4571 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4572 || (TARGET_SSE && SSE_REGNO_P (regno)
4573 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4578 if (SSE_REGNO_P (regno) && TARGET_SSE)
4583 if (TARGET_SSE && SSE_REGNO_P (regno)
4584 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4588 /* TODO: The function should depend on current function ABI but
4589 builtins.c would need updating then. Therefore we use the
4592 /* RAX is used as hidden argument to va_arg functions. */
4593 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4596 if (DEFAULT_ABI == MS_ABI)
4597 parm_regs = x86_64_ms_abi_int_parameter_registers;
4599 parm_regs = x86_64_int_parameter_registers;
4600 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4601 : X86_64_REGPARM_MAX); i++)
4602 if (regno == parm_regs[i])
4607 /* Return if we do not know how to pass TYPE solely in registers. */
4610 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4612 if (must_pass_in_stack_var_size_or_pad (mode, type))
4615 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4616 The layout_type routine is crafty and tries to trick us into passing
4617 currently unsupported vector types on the stack by using TImode. */
4618 return (!TARGET_64BIT && mode == TImode
4619 && type && TREE_CODE (type) != VECTOR_TYPE);
4622 /* It returns the size, in bytes, of the area reserved for arguments passed
4623 in registers for the function represented by fndecl dependent to the used
4626 ix86_reg_parm_stack_space (const_tree fndecl)
4628 int call_abi = SYSV_ABI;
4629 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4630 call_abi = ix86_function_abi (fndecl);
4632 call_abi = ix86_function_type_abi (fndecl);
4633 if (call_abi == MS_ABI)
4638 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4641 ix86_function_type_abi (const_tree fntype)
4643 if (TARGET_64BIT && fntype != NULL)
4646 if (DEFAULT_ABI == SYSV_ABI)
4647 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4649 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4657 ix86_function_abi (const_tree fndecl)
4661 return ix86_function_type_abi (TREE_TYPE (fndecl));
4664 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4667 ix86_cfun_abi (void)
4669 if (! cfun || ! TARGET_64BIT)
4671 return cfun->machine->call_abi;
4675 extern void init_regs (void);
4677 /* Implementation of call abi switching target hook. Specific to FNDECL
4678 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4679 for more details. */
4681 ix86_call_abi_override (const_tree fndecl)
4683 if (fndecl == NULL_TREE)
4684 cfun->machine->call_abi = DEFAULT_ABI;
4686 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4689 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4690 re-initialization of init_regs each time we switch function context since
4691 this is needed only during RTL expansion. */
4693 ix86_maybe_switch_abi (void)
4696 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4700 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4701 for a call to a function whose data type is FNTYPE.
4702 For a library call, FNTYPE is 0. */
4705 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4706 tree fntype, /* tree ptr for function decl */
4707 rtx libname, /* SYMBOL_REF of library name or 0 */
4710 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4711 memset (cum, 0, sizeof (*cum));
4714 cum->call_abi = ix86_function_abi (fndecl);
4716 cum->call_abi = ix86_function_type_abi (fntype);
4717 /* Set up the number of registers to use for passing arguments. */
4719 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4720 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4721 "or subtarget optimization implying it");
4722 cum->nregs = ix86_regparm;
4725 if (cum->call_abi != DEFAULT_ABI)
4726 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4731 cum->sse_nregs = SSE_REGPARM_MAX;
4734 if (cum->call_abi != DEFAULT_ABI)
4735 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4736 : X64_SSE_REGPARM_MAX;
4740 cum->mmx_nregs = MMX_REGPARM_MAX;
4741 cum->warn_avx = true;
4742 cum->warn_sse = true;
4743 cum->warn_mmx = true;
4745 /* Because type might mismatch in between caller and callee, we need to
4746 use actual type of function for local calls.
4747 FIXME: cgraph_analyze can be told to actually record if function uses
4748 va_start so for local functions maybe_vaarg can be made aggressive
4750 FIXME: once typesytem is fixed, we won't need this code anymore. */
4752 fntype = TREE_TYPE (fndecl);
4753 cum->maybe_vaarg = (fntype
4754 ? (!prototype_p (fntype) || stdarg_p (fntype))
4759 /* If there are variable arguments, then we won't pass anything
4760 in registers in 32-bit mode. */
4761 if (stdarg_p (fntype))
4772 /* Use ecx and edx registers if function has fastcall attribute,
4773 else look for regparm information. */
4776 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4782 cum->nregs = ix86_function_regparm (fntype, fndecl);
4785 /* Set up the number of SSE registers used for passing SFmode
4786 and DFmode arguments. Warn for mismatching ABI. */
4787 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4791 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4792 But in the case of vector types, it is some vector mode.
4794 When we have only some of our vector isa extensions enabled, then there
4795 are some modes for which vector_mode_supported_p is false. For these
4796 modes, the generic vector support in gcc will choose some non-vector mode
4797 in order to implement the type. By computing the natural mode, we'll
4798 select the proper ABI location for the operand and not depend on whatever
4799 the middle-end decides to do with these vector types.
4801 The midde-end can't deal with the vector types > 16 bytes. In this
4802 case, we return the original mode and warn ABI change if CUM isn't
4805 static enum machine_mode
4806 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4808 enum machine_mode mode = TYPE_MODE (type);
4810 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4812 HOST_WIDE_INT size = int_size_in_bytes (type);
4813 if ((size == 8 || size == 16 || size == 32)
4814 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4815 && TYPE_VECTOR_SUBPARTS (type) > 1)
4817 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4819 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4820 mode = MIN_MODE_VECTOR_FLOAT;
4822 mode = MIN_MODE_VECTOR_INT;
4824 /* Get the mode which has this inner mode and number of units. */
4825 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4826 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4827 && GET_MODE_INNER (mode) == innermode)
4829 if (size == 32 && !TARGET_AVX)
4831 static bool warnedavx;
4838 warning (0, "AVX vector argument without AVX "
4839 "enabled changes the ABI");
4841 return TYPE_MODE (type);
4854 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4855 this may not agree with the mode that the type system has chosen for the
4856 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4857 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4860 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4865 if (orig_mode != BLKmode)
4866 tmp = gen_rtx_REG (orig_mode, regno);
4869 tmp = gen_rtx_REG (mode, regno);
4870 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4871 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4877 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4878 of this code is to classify each 8bytes of incoming argument by the register
4879 class and assign registers accordingly. */
4881 /* Return the union class of CLASS1 and CLASS2.
4882 See the x86-64 PS ABI for details. */
4884 static enum x86_64_reg_class
4885 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4887 /* Rule #1: If both classes are equal, this is the resulting class. */
4888 if (class1 == class2)
4891 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4893 if (class1 == X86_64_NO_CLASS)
4895 if (class2 == X86_64_NO_CLASS)
4898 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4899 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4900 return X86_64_MEMORY_CLASS;
4902 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4903 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4904 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4905 return X86_64_INTEGERSI_CLASS;
4906 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4907 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4908 return X86_64_INTEGER_CLASS;
4910 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4912 if (class1 == X86_64_X87_CLASS
4913 || class1 == X86_64_X87UP_CLASS
4914 || class1 == X86_64_COMPLEX_X87_CLASS
4915 || class2 == X86_64_X87_CLASS
4916 || class2 == X86_64_X87UP_CLASS
4917 || class2 == X86_64_COMPLEX_X87_CLASS)
4918 return X86_64_MEMORY_CLASS;
4920 /* Rule #6: Otherwise class SSE is used. */
4921 return X86_64_SSE_CLASS;
4924 /* Classify the argument of type TYPE and mode MODE.
4925 CLASSES will be filled by the register class used to pass each word
4926 of the operand. The number of words is returned. In case the parameter
4927 should be passed in memory, 0 is returned. As a special case for zero
4928 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4930 BIT_OFFSET is used internally for handling records and specifies offset
4931 of the offset in bits modulo 256 to avoid overflow cases.
4933 See the x86-64 PS ABI for details.
4937 classify_argument (enum machine_mode mode, const_tree type,
4938 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4940 HOST_WIDE_INT bytes =
4941 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4942 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4944 /* Variable sized entities are always passed/returned in memory. */
4948 if (mode != VOIDmode
4949 && targetm.calls.must_pass_in_stack (mode, type))
4952 if (type && AGGREGATE_TYPE_P (type))
4956 enum x86_64_reg_class subclasses[MAX_CLASSES];
4958 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
4962 for (i = 0; i < words; i++)
4963 classes[i] = X86_64_NO_CLASS;
4965 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4966 signalize memory class, so handle it as special case. */
4969 classes[0] = X86_64_NO_CLASS;
4973 /* Classify each field of record and merge classes. */
4974 switch (TREE_CODE (type))
4977 /* And now merge the fields of structure. */
4978 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4980 if (TREE_CODE (field) == FIELD_DECL)
4984 if (TREE_TYPE (field) == error_mark_node)
4987 /* Bitfields are always classified as integer. Handle them
4988 early, since later code would consider them to be
4989 misaligned integers. */
4990 if (DECL_BIT_FIELD (field))
4992 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4993 i < ((int_bit_position (field) + (bit_offset % 64))
4994 + tree_low_cst (DECL_SIZE (field), 0)
4997 merge_classes (X86_64_INTEGER_CLASS,
5002 type = TREE_TYPE (field);
5004 /* Flexible array member is ignored. */
5005 if (TYPE_MODE (type) == BLKmode
5006 && TREE_CODE (type) == ARRAY_TYPE
5007 && TYPE_SIZE (type) == NULL_TREE
5008 && TYPE_DOMAIN (type) != NULL_TREE
5009 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5014 if (!warned && warn_psabi)
5017 inform (input_location,
5018 "The ABI of passing struct with"
5019 " a flexible array member has"
5020 " changed in GCC 4.4");
5024 num = classify_argument (TYPE_MODE (type), type,
5026 (int_bit_position (field)
5027 + bit_offset) % 256);
5030 for (i = 0; i < num; i++)
5033 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5035 merge_classes (subclasses[i], classes[i + pos]);
5043 /* Arrays are handled as small records. */
5046 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5047 TREE_TYPE (type), subclasses, bit_offset);
5051 /* The partial classes are now full classes. */
5052 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5053 subclasses[0] = X86_64_SSE_CLASS;
5054 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5055 && !((bit_offset % 64) == 0 && bytes == 4))
5056 subclasses[0] = X86_64_INTEGER_CLASS;
5058 for (i = 0; i < words; i++)
5059 classes[i] = subclasses[i % num];
5064 case QUAL_UNION_TYPE:
5065 /* Unions are similar to RECORD_TYPE but offset is always 0.
5067 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5069 if (TREE_CODE (field) == FIELD_DECL)
5073 if (TREE_TYPE (field) == error_mark_node)
5076 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5077 TREE_TYPE (field), subclasses,
5081 for (i = 0; i < num; i++)
5082 classes[i] = merge_classes (subclasses[i], classes[i]);
5093 /* When size > 16 bytes, if the first one isn't
5094 X86_64_SSE_CLASS or any other ones aren't
5095 X86_64_SSEUP_CLASS, everything should be passed in
5097 if (classes[0] != X86_64_SSE_CLASS)
5100 for (i = 1; i < words; i++)
5101 if (classes[i] != X86_64_SSEUP_CLASS)
5105 /* Final merger cleanup. */
5106 for (i = 0; i < words; i++)
5108 /* If one class is MEMORY, everything should be passed in
5110 if (classes[i] == X86_64_MEMORY_CLASS)
5113 /* The X86_64_SSEUP_CLASS should be always preceded by
5114 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5115 if (classes[i] == X86_64_SSEUP_CLASS
5116 && classes[i - 1] != X86_64_SSE_CLASS
5117 && classes[i - 1] != X86_64_SSEUP_CLASS)
5119 /* The first one should never be X86_64_SSEUP_CLASS. */
5120 gcc_assert (i != 0);
5121 classes[i] = X86_64_SSE_CLASS;
5124 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5125 everything should be passed in memory. */
5126 if (classes[i] == X86_64_X87UP_CLASS
5127 && (classes[i - 1] != X86_64_X87_CLASS))
5131 /* The first one should never be X86_64_X87UP_CLASS. */
5132 gcc_assert (i != 0);
5133 if (!warned && warn_psabi)
5136 inform (input_location,
5137 "The ABI of passing union with long double"
5138 " has changed in GCC 4.4");
5146 /* Compute alignment needed. We align all types to natural boundaries with
5147 exception of XFmode that is aligned to 64bits. */
5148 if (mode != VOIDmode && mode != BLKmode)
5150 int mode_alignment = GET_MODE_BITSIZE (mode);
5153 mode_alignment = 128;
5154 else if (mode == XCmode)
5155 mode_alignment = 256;
5156 if (COMPLEX_MODE_P (mode))
5157 mode_alignment /= 2;
5158 /* Misaligned fields are always returned in memory. */
5159 if (bit_offset % mode_alignment)
5163 /* for V1xx modes, just use the base mode */
5164 if (VECTOR_MODE_P (mode) && mode != V1DImode
5165 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5166 mode = GET_MODE_INNER (mode);
5168 /* Classification of atomic types. */
5173 classes[0] = X86_64_SSE_CLASS;
5176 classes[0] = X86_64_SSE_CLASS;
5177 classes[1] = X86_64_SSEUP_CLASS;
5187 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5191 classes[0] = X86_64_INTEGERSI_CLASS;
5194 else if (size <= 64)
5196 classes[0] = X86_64_INTEGER_CLASS;
5199 else if (size <= 64+32)
5201 classes[0] = X86_64_INTEGER_CLASS;
5202 classes[1] = X86_64_INTEGERSI_CLASS;
5205 else if (size <= 64+64)
5207 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5215 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5219 /* OImode shouldn't be used directly. */
5224 if (!(bit_offset % 64))
5225 classes[0] = X86_64_SSESF_CLASS;
5227 classes[0] = X86_64_SSE_CLASS;
5230 classes[0] = X86_64_SSEDF_CLASS;
5233 classes[0] = X86_64_X87_CLASS;
5234 classes[1] = X86_64_X87UP_CLASS;
5237 classes[0] = X86_64_SSE_CLASS;
5238 classes[1] = X86_64_SSEUP_CLASS;
5241 classes[0] = X86_64_SSE_CLASS;
5242 if (!(bit_offset % 64))
5248 if (!warned && warn_psabi)
5251 inform (input_location,
5252 "The ABI of passing structure with complex float"
5253 " member has changed in GCC 4.4");
5255 classes[1] = X86_64_SSESF_CLASS;
5259 classes[0] = X86_64_SSEDF_CLASS;
5260 classes[1] = X86_64_SSEDF_CLASS;
5263 classes[0] = X86_64_COMPLEX_X87_CLASS;
5266 /* This modes is larger than 16 bytes. */
5274 classes[0] = X86_64_SSE_CLASS;
5275 classes[1] = X86_64_SSEUP_CLASS;
5276 classes[2] = X86_64_SSEUP_CLASS;
5277 classes[3] = X86_64_SSEUP_CLASS;
5285 classes[0] = X86_64_SSE_CLASS;
5286 classes[1] = X86_64_SSEUP_CLASS;
5293 classes[0] = X86_64_SSE_CLASS;
5299 gcc_assert (VECTOR_MODE_P (mode));
5304 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5306 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5307 classes[0] = X86_64_INTEGERSI_CLASS;
5309 classes[0] = X86_64_INTEGER_CLASS;
5310 classes[1] = X86_64_INTEGER_CLASS;
5311 return 1 + (bytes > 8);
5315 /* Examine the argument and return set number of register required in each
5316 class. Return 0 iff parameter should be passed in memory. */
5318 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5319 int *int_nregs, int *sse_nregs)
5321 enum x86_64_reg_class regclass[MAX_CLASSES];
5322 int n = classify_argument (mode, type, regclass, 0);
5328 for (n--; n >= 0; n--)
5329 switch (regclass[n])
5331 case X86_64_INTEGER_CLASS:
5332 case X86_64_INTEGERSI_CLASS:
5335 case X86_64_SSE_CLASS:
5336 case X86_64_SSESF_CLASS:
5337 case X86_64_SSEDF_CLASS:
5340 case X86_64_NO_CLASS:
5341 case X86_64_SSEUP_CLASS:
5343 case X86_64_X87_CLASS:
5344 case X86_64_X87UP_CLASS:
5348 case X86_64_COMPLEX_X87_CLASS:
5349 return in_return ? 2 : 0;
5350 case X86_64_MEMORY_CLASS:
5356 /* Construct container for the argument used by GCC interface. See
5357 FUNCTION_ARG for the detailed description. */
5360 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5361 const_tree type, int in_return, int nintregs, int nsseregs,
5362 const int *intreg, int sse_regno)
5364 /* The following variables hold the static issued_error state. */
5365 static bool issued_sse_arg_error;
5366 static bool issued_sse_ret_error;
5367 static bool issued_x87_ret_error;
5369 enum machine_mode tmpmode;
5371 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5372 enum x86_64_reg_class regclass[MAX_CLASSES];
5376 int needed_sseregs, needed_intregs;
5377 rtx exp[MAX_CLASSES];
5380 n = classify_argument (mode, type, regclass, 0);
5383 if (!examine_argument (mode, type, in_return, &needed_intregs,
5386 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5389 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5390 some less clueful developer tries to use floating-point anyway. */
5391 if (needed_sseregs && !TARGET_SSE)
5395 if (!issued_sse_ret_error)
5397 error ("SSE register return with SSE disabled");
5398 issued_sse_ret_error = true;
5401 else if (!issued_sse_arg_error)
5403 error ("SSE register argument with SSE disabled");
5404 issued_sse_arg_error = true;
5409 /* Likewise, error if the ABI requires us to return values in the
5410 x87 registers and the user specified -mno-80387. */
5411 if (!TARGET_80387 && in_return)
5412 for (i = 0; i < n; i++)
5413 if (regclass[i] == X86_64_X87_CLASS
5414 || regclass[i] == X86_64_X87UP_CLASS
5415 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5417 if (!issued_x87_ret_error)
5419 error ("x87 register return with x87 disabled");
5420 issued_x87_ret_error = true;
5425 /* First construct simple cases. Avoid SCmode, since we want to use
5426 single register to pass this type. */
5427 if (n == 1 && mode != SCmode)
5428 switch (regclass[0])
5430 case X86_64_INTEGER_CLASS:
5431 case X86_64_INTEGERSI_CLASS:
5432 return gen_rtx_REG (mode, intreg[0]);
5433 case X86_64_SSE_CLASS:
5434 case X86_64_SSESF_CLASS:
5435 case X86_64_SSEDF_CLASS:
5436 if (mode != BLKmode)
5437 return gen_reg_or_parallel (mode, orig_mode,
5438 SSE_REGNO (sse_regno));
5440 case X86_64_X87_CLASS:
5441 case X86_64_COMPLEX_X87_CLASS:
5442 return gen_rtx_REG (mode, FIRST_STACK_REG);
5443 case X86_64_NO_CLASS:
5444 /* Zero sized array, struct or class. */
5449 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5450 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5451 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5453 && regclass[0] == X86_64_SSE_CLASS
5454 && regclass[1] == X86_64_SSEUP_CLASS
5455 && regclass[2] == X86_64_SSEUP_CLASS
5456 && regclass[3] == X86_64_SSEUP_CLASS
5458 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5461 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5462 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5463 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5464 && regclass[1] == X86_64_INTEGER_CLASS
5465 && (mode == CDImode || mode == TImode || mode == TFmode)
5466 && intreg[0] + 1 == intreg[1])
5467 return gen_rtx_REG (mode, intreg[0]);
5469 /* Otherwise figure out the entries of the PARALLEL. */
5470 for (i = 0; i < n; i++)
5474 switch (regclass[i])
5476 case X86_64_NO_CLASS:
5478 case X86_64_INTEGER_CLASS:
5479 case X86_64_INTEGERSI_CLASS:
5480 /* Merge TImodes on aligned occasions here too. */
5481 if (i * 8 + 8 > bytes)
5482 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5483 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5487 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5488 if (tmpmode == BLKmode)
5490 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5491 gen_rtx_REG (tmpmode, *intreg),
5495 case X86_64_SSESF_CLASS:
5496 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5497 gen_rtx_REG (SFmode,
5498 SSE_REGNO (sse_regno)),
5502 case X86_64_SSEDF_CLASS:
5503 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5504 gen_rtx_REG (DFmode,
5505 SSE_REGNO (sse_regno)),
5509 case X86_64_SSE_CLASS:
5517 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5527 && regclass[1] == X86_64_SSEUP_CLASS
5528 && regclass[2] == X86_64_SSEUP_CLASS
5529 && regclass[3] == X86_64_SSEUP_CLASS);
5536 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5537 gen_rtx_REG (tmpmode,
5538 SSE_REGNO (sse_regno)),
5547 /* Empty aligned struct, union or class. */
5551 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5552 for (i = 0; i < nexps; i++)
5553 XVECEXP (ret, 0, i) = exp [i];
5557 /* Update the data in CUM to advance over an argument of mode MODE
5558 and data type TYPE. (TYPE is null for libcalls where that information
5559 may not be available.) */
5562 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5563 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5579 cum->words += words;
5580 cum->nregs -= words;
5581 cum->regno += words;
5583 if (cum->nregs <= 0)
5591 /* OImode shouldn't be used directly. */
5595 if (cum->float_in_sse < 2)
5598 if (cum->float_in_sse < 1)
5615 if (!type || !AGGREGATE_TYPE_P (type))
5617 cum->sse_words += words;
5618 cum->sse_nregs -= 1;
5619 cum->sse_regno += 1;
5620 if (cum->sse_nregs <= 0)
5633 if (!type || !AGGREGATE_TYPE_P (type))
5635 cum->mmx_words += words;
5636 cum->mmx_nregs -= 1;
5637 cum->mmx_regno += 1;
5638 if (cum->mmx_nregs <= 0)
5649 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5650 tree type, HOST_WIDE_INT words, int named)
5652 int int_nregs, sse_nregs;
5654 /* Unnamed 256bit vector mode parameters are passed on stack. */
5655 if (!named && VALID_AVX256_REG_MODE (mode))
5658 if (examine_argument (mode, type, 0, &int_nregs, &sse_nregs)
5659 && sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5661 cum->nregs -= int_nregs;
5662 cum->sse_nregs -= sse_nregs;
5663 cum->regno += int_nregs;
5664 cum->sse_regno += sse_nregs;
5668 int align = ix86_function_arg_boundary (mode, type) / BITS_PER_WORD;
5669 cum->words = (cum->words + align - 1) & ~(align - 1);
5670 cum->words += words;
5675 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5676 HOST_WIDE_INT words)
5678 /* Otherwise, this should be passed indirect. */
5679 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5681 cum->words += words;
5690 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5691 tree type, int named)
5693 HOST_WIDE_INT bytes, words;
5695 if (mode == BLKmode)
5696 bytes = int_size_in_bytes (type);
5698 bytes = GET_MODE_SIZE (mode);
5699 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5702 mode = type_natural_mode (type, NULL);
5704 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5705 function_arg_advance_ms_64 (cum, bytes, words);
5706 else if (TARGET_64BIT)
5707 function_arg_advance_64 (cum, mode, type, words, named);
5709 function_arg_advance_32 (cum, mode, type, bytes, words);
5712 /* Define where to put the arguments to a function.
5713 Value is zero to push the argument on the stack,
5714 or a hard register in which to store the argument.
5716 MODE is the argument's machine mode.
5717 TYPE is the data type of the argument (as a tree).
5718 This is null for libcalls where that information may
5720 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5721 the preceding args and about the function being called.
5722 NAMED is nonzero if this argument is a named parameter
5723 (otherwise it is an extra parameter matching an ellipsis). */
5726 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5727 enum machine_mode orig_mode, tree type,
5728 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5730 static bool warnedsse, warnedmmx;
5732 /* Avoid the AL settings for the Unix64 ABI. */
5733 if (mode == VOIDmode)
5749 if (words <= cum->nregs)
5751 int regno = cum->regno;
5753 /* Fastcall allocates the first two DWORD (SImode) or
5754 smaller arguments to ECX and EDX if it isn't an
5760 || (type && AGGREGATE_TYPE_P (type)))
5763 /* ECX not EAX is the first allocated register. */
5764 if (regno == AX_REG)
5767 return gen_rtx_REG (mode, regno);
5772 if (cum->float_in_sse < 2)
5775 if (cum->float_in_sse < 1)
5779 /* In 32bit, we pass TImode in xmm registers. */
5786 if (!type || !AGGREGATE_TYPE_P (type))
5788 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5791 warning (0, "SSE vector argument without SSE enabled "
5795 return gen_reg_or_parallel (mode, orig_mode,
5796 cum->sse_regno + FIRST_SSE_REG);
5801 /* OImode shouldn't be used directly. */
5810 if (!type || !AGGREGATE_TYPE_P (type))
5813 return gen_reg_or_parallel (mode, orig_mode,
5814 cum->sse_regno + FIRST_SSE_REG);
5823 if (!type || !AGGREGATE_TYPE_P (type))
5825 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5828 warning (0, "MMX vector argument without MMX enabled "
5832 return gen_reg_or_parallel (mode, orig_mode,
5833 cum->mmx_regno + FIRST_MMX_REG);
5842 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5843 enum machine_mode orig_mode, tree type, int named)
5845 /* Handle a hidden AL argument containing number of registers
5846 for varargs x86-64 functions. */
5847 if (mode == VOIDmode)
5848 return GEN_INT (cum->maybe_vaarg
5849 ? (cum->sse_nregs < 0
5850 ? (cum->call_abi == DEFAULT_ABI
5852 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5853 : X64_SSE_REGPARM_MAX))
5868 /* Unnamed 256bit vector mode parameters are passed on stack. */
5874 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5876 &x86_64_int_parameter_registers [cum->regno],
5881 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5882 enum machine_mode orig_mode, int named,
5883 HOST_WIDE_INT bytes)
5887 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5888 We use value of -2 to specify that current function call is MSABI. */
5889 if (mode == VOIDmode)
5890 return GEN_INT (-2);
5892 /* If we've run out of registers, it goes on the stack. */
5893 if (cum->nregs == 0)
5896 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5898 /* Only floating point modes are passed in anything but integer regs. */
5899 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5902 regno = cum->regno + FIRST_SSE_REG;
5907 /* Unnamed floating parameters are passed in both the
5908 SSE and integer registers. */
5909 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5910 t2 = gen_rtx_REG (mode, regno);
5911 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5912 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5913 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5916 /* Handle aggregated types passed in register. */
5917 if (orig_mode == BLKmode)
5919 if (bytes > 0 && bytes <= 8)
5920 mode = (bytes > 4 ? DImode : SImode);
5921 if (mode == BLKmode)
5925 return gen_reg_or_parallel (mode, orig_mode, regno);
5929 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5930 tree type, int named)
5932 enum machine_mode mode = omode;
5933 HOST_WIDE_INT bytes, words;
5935 if (mode == BLKmode)
5936 bytes = int_size_in_bytes (type);
5938 bytes = GET_MODE_SIZE (mode);
5939 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5941 /* To simplify the code below, represent vector types with a vector mode
5942 even if MMX/SSE are not active. */
5943 if (type && TREE_CODE (type) == VECTOR_TYPE)
5944 mode = type_natural_mode (type, cum);
5946 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5947 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5948 else if (TARGET_64BIT)
5949 return function_arg_64 (cum, mode, omode, type, named);
5951 return function_arg_32 (cum, mode, omode, type, bytes, words);
5954 /* A C expression that indicates when an argument must be passed by
5955 reference. If nonzero for an argument, a copy of that argument is
5956 made in memory and a pointer to the argument is passed instead of
5957 the argument itself. The pointer is passed in whatever way is
5958 appropriate for passing a pointer to that type. */
5961 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5962 enum machine_mode mode ATTRIBUTE_UNUSED,
5963 const_tree type, bool named ATTRIBUTE_UNUSED)
5965 /* See Windows x64 Software Convention. */
5966 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5968 int msize = (int) GET_MODE_SIZE (mode);
5971 /* Arrays are passed by reference. */
5972 if (TREE_CODE (type) == ARRAY_TYPE)
5975 if (AGGREGATE_TYPE_P (type))
5977 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5978 are passed by reference. */
5979 msize = int_size_in_bytes (type);
5983 /* __m128 is passed by reference. */
5985 case 1: case 2: case 4: case 8:
5991 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5997 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6000 contains_aligned_value_p (const_tree type)
6002 enum machine_mode mode = TYPE_MODE (type);
6003 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6007 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6009 if (TYPE_ALIGN (type) < 128)
6012 if (AGGREGATE_TYPE_P (type))
6014 /* Walk the aggregates recursively. */
6015 switch (TREE_CODE (type))
6019 case QUAL_UNION_TYPE:
6023 /* Walk all the structure fields. */
6024 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6026 if (TREE_CODE (field) == FIELD_DECL
6027 && contains_aligned_value_p (TREE_TYPE (field)))
6034 /* Just for use if some languages passes arrays by value. */
6035 if (contains_aligned_value_p (TREE_TYPE (type)))
6046 /* Gives the alignment boundary, in bits, of an argument with the
6047 specified mode and type. */
6050 ix86_function_arg_boundary (enum machine_mode mode, const_tree type)
6055 /* Since canonical type is used for call, we convert it to
6056 canonical type if needed. */
6057 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6058 type = TYPE_CANONICAL (type);
6059 align = TYPE_ALIGN (type);
6062 align = GET_MODE_ALIGNMENT (mode);
6063 if (align < PARM_BOUNDARY)
6064 align = PARM_BOUNDARY;
6065 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6066 natural boundaries. */
6067 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6069 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6070 make an exception for SSE modes since these require 128bit
6073 The handling here differs from field_alignment. ICC aligns MMX
6074 arguments to 4 byte boundaries, while structure fields are aligned
6075 to 8 byte boundaries. */
6078 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6079 align = PARM_BOUNDARY;
6083 if (!contains_aligned_value_p (type))
6084 align = PARM_BOUNDARY;
6087 if (align > BIGGEST_ALIGNMENT)
6088 align = BIGGEST_ALIGNMENT;
6092 /* Return true if N is a possible register number of function value. */
6095 ix86_function_value_regno_p (int regno)
6102 case FIRST_FLOAT_REG:
6103 /* TODO: The function should depend on current function ABI but
6104 builtins.c would need updating then. Therefore we use the
6106 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
6108 return TARGET_FLOAT_RETURNS_IN_80387;
6114 if (TARGET_MACHO || TARGET_64BIT)
6122 /* Define how to find the value returned by a function.
6123 VALTYPE is the data type of the value (as a tree).
6124 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6125 otherwise, FUNC is 0. */
6128 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6129 const_tree fntype, const_tree fn)
6133 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6134 we normally prevent this case when mmx is not available. However
6135 some ABIs may require the result to be returned like DImode. */
6136 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6137 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6139 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6140 we prevent this case when sse is not available. However some ABIs
6141 may require the result to be returned like integer TImode. */
6142 else if (mode == TImode
6143 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6144 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6146 /* 32-byte vector modes in %ymm0. */
6147 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6148 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6150 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6151 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6152 regno = FIRST_FLOAT_REG;
6154 /* Most things go in %eax. */
6157 /* Override FP return register with %xmm0 for local functions when
6158 SSE math is enabled or for functions with sseregparm attribute. */
6159 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6161 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6162 if ((sse_level >= 1 && mode == SFmode)
6163 || (sse_level == 2 && mode == DFmode))
6164 regno = FIRST_SSE_REG;
6167 /* OImode shouldn't be used directly. */
6168 gcc_assert (mode != OImode);
6170 return gen_rtx_REG (orig_mode, regno);
6174 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6179 /* Handle libcalls, which don't provide a type node. */
6180 if (valtype == NULL)
6192 return gen_rtx_REG (mode, FIRST_SSE_REG);
6195 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6199 return gen_rtx_REG (mode, AX_REG);
6203 ret = construct_container (mode, orig_mode, valtype, 1,
6204 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6205 x86_64_int_return_registers, 0);
6207 /* For zero sized structures, construct_container returns NULL, but we
6208 need to keep rest of compiler happy by returning meaningful value. */
6210 ret = gen_rtx_REG (orig_mode, AX_REG);
6216 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6218 unsigned int regno = AX_REG;
6222 switch (GET_MODE_SIZE (mode))
6225 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6226 && !COMPLEX_MODE_P (mode))
6227 regno = FIRST_SSE_REG;
6231 if (mode == SFmode || mode == DFmode)
6232 regno = FIRST_SSE_REG;
6238 return gen_rtx_REG (orig_mode, regno);
6242 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6243 enum machine_mode orig_mode, enum machine_mode mode)
6245 const_tree fn, fntype;
6248 if (fntype_or_decl && DECL_P (fntype_or_decl))
6249 fn = fntype_or_decl;
6250 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6252 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6253 return function_value_ms_64 (orig_mode, mode);
6254 else if (TARGET_64BIT)
6255 return function_value_64 (orig_mode, mode, valtype);
6257 return function_value_32 (orig_mode, mode, fntype, fn);
6261 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6262 bool outgoing ATTRIBUTE_UNUSED)
6264 enum machine_mode mode, orig_mode;
6266 orig_mode = TYPE_MODE (valtype);
6267 mode = type_natural_mode (valtype, NULL);
6268 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6272 ix86_libcall_value (enum machine_mode mode)
6274 return ix86_function_value_1 (NULL, NULL, mode, mode);
6277 /* Return true iff type is returned in memory. */
6279 static int ATTRIBUTE_UNUSED
6280 return_in_memory_32 (const_tree type, enum machine_mode mode)
6284 if (mode == BLKmode)
6287 size = int_size_in_bytes (type);
6289 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6292 if (VECTOR_MODE_P (mode) || mode == TImode)
6294 /* User-created vectors small enough to fit in EAX. */
6298 /* MMX/3dNow values are returned in MM0,
6299 except when it doesn't exits. */
6301 return (TARGET_MMX ? 0 : 1);
6303 /* SSE values are returned in XMM0, except when it doesn't exist. */
6305 return (TARGET_SSE ? 0 : 1);
6307 /* AVX values are returned in YMM0, except when it doesn't exist. */
6309 return TARGET_AVX ? 0 : 1;
6318 /* OImode shouldn't be used directly. */
6319 gcc_assert (mode != OImode);
6324 static int ATTRIBUTE_UNUSED
6325 return_in_memory_64 (const_tree type, enum machine_mode mode)
6327 int needed_intregs, needed_sseregs;
6328 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6331 static int ATTRIBUTE_UNUSED
6332 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6334 HOST_WIDE_INT size = int_size_in_bytes (type);
6336 /* __m128 is returned in xmm0. */
6337 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6338 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6341 /* Otherwise, the size must be exactly in [1248]. */
6342 return (size != 1 && size != 2 && size != 4 && size != 8);
6346 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6348 #ifdef SUBTARGET_RETURN_IN_MEMORY
6349 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6351 const enum machine_mode mode = type_natural_mode (type, NULL);
6355 if (ix86_function_type_abi (fntype) == MS_ABI)
6356 return return_in_memory_ms_64 (type, mode);
6358 return return_in_memory_64 (type, mode);
6361 return return_in_memory_32 (type, mode);
6365 /* Return false iff TYPE is returned in memory. This version is used
6366 on Solaris 2. It is similar to the generic ix86_return_in_memory,
6367 but differs notably in that when MMX is available, 8-byte vectors
6368 are returned in memory, rather than in MMX registers. */
6371 ix86_solaris_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6374 enum machine_mode mode = type_natural_mode (type, NULL);
6377 return return_in_memory_64 (type, mode);
6379 if (mode == BLKmode)
6382 size = int_size_in_bytes (type);
6384 if (VECTOR_MODE_P (mode))
6386 /* Return in memory only if MMX registers *are* available. This
6387 seems backwards, but it is consistent with the existing
6394 else if (mode == TImode)
6396 else if (mode == XFmode)
6402 /* When returning SSE vector types, we have a choice of either
6403 (1) being abi incompatible with a -march switch, or
6404 (2) generating an error.
6405 Given no good solution, I think the safest thing is one warning.
6406 The user won't be able to use -Werror, but....
6408 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6409 called in response to actually generating a caller or callee that
6410 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6411 via aggregate_value_p for general type probing from tree-ssa. */
6414 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6416 static bool warnedsse, warnedmmx;
6418 if (!TARGET_64BIT && type)
6420 /* Look at the return type of the function, not the function type. */
6421 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6423 if (!TARGET_SSE && !warnedsse)
6426 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6429 warning (0, "SSE vector return without SSE enabled "
6434 if (!TARGET_MMX && !warnedmmx)
6436 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6439 warning (0, "MMX vector return without MMX enabled "
6449 /* Create the va_list data type. */
6451 /* Returns the calling convention specific va_list date type.
6452 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6455 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6457 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6459 /* For i386 we use plain pointer to argument area. */
6460 if (!TARGET_64BIT || abi == MS_ABI)
6461 return build_pointer_type (char_type_node);
6463 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6464 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6466 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6467 unsigned_type_node);
6468 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6469 unsigned_type_node);
6470 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6472 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6475 va_list_gpr_counter_field = f_gpr;
6476 va_list_fpr_counter_field = f_fpr;
6478 DECL_FIELD_CONTEXT (f_gpr) = record;
6479 DECL_FIELD_CONTEXT (f_fpr) = record;
6480 DECL_FIELD_CONTEXT (f_ovf) = record;
6481 DECL_FIELD_CONTEXT (f_sav) = record;
6483 TREE_CHAIN (record) = type_decl;
6484 TYPE_NAME (record) = type_decl;
6485 TYPE_FIELDS (record) = f_gpr;
6486 TREE_CHAIN (f_gpr) = f_fpr;
6487 TREE_CHAIN (f_fpr) = f_ovf;
6488 TREE_CHAIN (f_ovf) = f_sav;
6490 layout_type (record);
6492 /* The correct type is an array type of one element. */
6493 return build_array_type (record, build_index_type (size_zero_node));
6496 /* Setup the builtin va_list data type and for 64-bit the additional
6497 calling convention specific va_list data types. */
6500 ix86_build_builtin_va_list (void)
6502 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6504 /* Initialize abi specific va_list builtin types. */
6508 if (DEFAULT_ABI == MS_ABI)
6510 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6511 if (TREE_CODE (t) != RECORD_TYPE)
6512 t = build_variant_type_copy (t);
6513 sysv_va_list_type_node = t;
6518 if (TREE_CODE (t) != RECORD_TYPE)
6519 t = build_variant_type_copy (t);
6520 sysv_va_list_type_node = t;
6522 if (DEFAULT_ABI != MS_ABI)
6524 t = ix86_build_builtin_va_list_abi (MS_ABI);
6525 if (TREE_CODE (t) != RECORD_TYPE)
6526 t = build_variant_type_copy (t);
6527 ms_va_list_type_node = t;
6532 if (TREE_CODE (t) != RECORD_TYPE)
6533 t = build_variant_type_copy (t);
6534 ms_va_list_type_node = t;
6541 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6544 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6553 int regparm = ix86_regparm;
6555 if (cum->call_abi != DEFAULT_ABI)
6556 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6558 /* GPR size of varargs save area. */
6559 if (cfun->va_list_gpr_size)
6560 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6562 ix86_varargs_gpr_size = 0;
6564 /* FPR size of varargs save area. We don't need it if we don't pass
6565 anything in SSE registers. */
6566 if (cum->sse_nregs && cfun->va_list_fpr_size)
6567 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6569 ix86_varargs_fpr_size = 0;
6571 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6574 save_area = frame_pointer_rtx;
6575 set = get_varargs_alias_set ();
6577 for (i = cum->regno;
6579 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6582 mem = gen_rtx_MEM (Pmode,
6583 plus_constant (save_area, i * UNITS_PER_WORD));
6584 MEM_NOTRAP_P (mem) = 1;
6585 set_mem_alias_set (mem, set);
6586 emit_move_insn (mem, gen_rtx_REG (Pmode,
6587 x86_64_int_parameter_registers[i]));
6590 if (ix86_varargs_fpr_size)
6592 /* Stack must be aligned to 16byte for FP register save area. */
6593 if (crtl->stack_alignment_needed < 128)
6594 crtl->stack_alignment_needed = 128;
6596 /* Now emit code to save SSE registers. The AX parameter contains number
6597 of SSE parameter registers used to call this function. We use
6598 sse_prologue_save insn template that produces computed jump across
6599 SSE saves. We need some preparation work to get this working. */
6601 label = gen_label_rtx ();
6602 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6604 /* Compute address to jump to :
6605 label - eax*4 + nnamed_sse_arguments*4 Or
6606 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6607 tmp_reg = gen_reg_rtx (Pmode);
6608 nsse_reg = gen_reg_rtx (Pmode);
6609 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6610 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6611 gen_rtx_MULT (Pmode, nsse_reg,
6614 /* vmovaps is one byte longer than movaps. */
6616 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6617 gen_rtx_PLUS (Pmode, tmp_reg,
6623 gen_rtx_CONST (DImode,
6624 gen_rtx_PLUS (DImode,
6626 GEN_INT (cum->sse_regno
6627 * (TARGET_AVX ? 5 : 4)))));
6629 emit_move_insn (nsse_reg, label_ref);
6630 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6632 /* Compute address of memory block we save into. We always use pointer
6633 pointing 127 bytes after first byte to store - this is needed to keep
6634 instruction size limited by 4 bytes (5 bytes for AVX) with one
6635 byte displacement. */
6636 tmp_reg = gen_reg_rtx (Pmode);
6637 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6638 plus_constant (save_area,
6639 ix86_varargs_gpr_size + 127)));
6640 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6641 MEM_NOTRAP_P (mem) = 1;
6642 set_mem_alias_set (mem, set);
6643 set_mem_align (mem, BITS_PER_WORD);
6645 /* And finally do the dirty job! */
6646 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6647 GEN_INT (cum->sse_regno), label));
6652 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6654 alias_set_type set = get_varargs_alias_set ();
6657 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6661 mem = gen_rtx_MEM (Pmode,
6662 plus_constant (virtual_incoming_args_rtx,
6663 i * UNITS_PER_WORD));
6664 MEM_NOTRAP_P (mem) = 1;
6665 set_mem_alias_set (mem, set);
6667 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6668 emit_move_insn (mem, reg);
6673 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6674 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6677 CUMULATIVE_ARGS next_cum;
6680 /* This argument doesn't appear to be used anymore. Which is good,
6681 because the old code here didn't suppress rtl generation. */
6682 gcc_assert (!no_rtl);
6687 fntype = TREE_TYPE (current_function_decl);
6689 /* For varargs, we do not want to skip the dummy va_dcl argument.
6690 For stdargs, we do want to skip the last named argument. */
6692 if (stdarg_p (fntype))
6693 function_arg_advance (&next_cum, mode, type, 1);
6695 if (cum->call_abi == MS_ABI)
6696 setup_incoming_varargs_ms_64 (&next_cum);
6698 setup_incoming_varargs_64 (&next_cum);
6701 /* Checks if TYPE is of kind va_list char *. */
6704 is_va_list_char_pointer (tree type)
6708 /* For 32-bit it is always true. */
6711 canonic = ix86_canonical_va_list_type (type);
6712 return (canonic == ms_va_list_type_node
6713 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6716 /* Implement va_start. */
6719 ix86_va_start (tree valist, rtx nextarg)
6721 HOST_WIDE_INT words, n_gpr, n_fpr;
6722 tree f_gpr, f_fpr, f_ovf, f_sav;
6723 tree gpr, fpr, ovf, sav, t;
6726 /* Only 64bit target needs something special. */
6727 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6729 std_expand_builtin_va_start (valist, nextarg);
6733 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6734 f_fpr = TREE_CHAIN (f_gpr);
6735 f_ovf = TREE_CHAIN (f_fpr);
6736 f_sav = TREE_CHAIN (f_ovf);
6738 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6739 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6740 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6741 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6742 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6744 /* Count number of gp and fp argument registers used. */
6745 words = crtl->args.info.words;
6746 n_gpr = crtl->args.info.regno;
6747 n_fpr = crtl->args.info.sse_regno;
6749 if (cfun->va_list_gpr_size)
6751 type = TREE_TYPE (gpr);
6752 t = build2 (MODIFY_EXPR, type,
6753 gpr, build_int_cst (type, n_gpr * 8));
6754 TREE_SIDE_EFFECTS (t) = 1;
6755 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6758 if (TARGET_SSE && cfun->va_list_fpr_size)
6760 type = TREE_TYPE (fpr);
6761 t = build2 (MODIFY_EXPR, type, fpr,
6762 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6763 TREE_SIDE_EFFECTS (t) = 1;
6764 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6767 /* Find the overflow area. */
6768 type = TREE_TYPE (ovf);
6769 t = make_tree (type, crtl->args.internal_arg_pointer);
6771 t = build2 (POINTER_PLUS_EXPR, type, t,
6772 size_int (words * UNITS_PER_WORD));
6773 t = build2 (MODIFY_EXPR, type, ovf, t);
6774 TREE_SIDE_EFFECTS (t) = 1;
6775 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6777 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6779 /* Find the register save area.
6780 Prologue of the function save it right above stack frame. */
6781 type = TREE_TYPE (sav);
6782 t = make_tree (type, frame_pointer_rtx);
6783 if (!ix86_varargs_gpr_size)
6784 t = build2 (POINTER_PLUS_EXPR, type, t,
6785 size_int (-8 * X86_64_REGPARM_MAX));
6786 t = build2 (MODIFY_EXPR, type, sav, t);
6787 TREE_SIDE_EFFECTS (t) = 1;
6788 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6792 /* Implement va_arg. */
6795 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6798 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6799 tree f_gpr, f_fpr, f_ovf, f_sav;
6800 tree gpr, fpr, ovf, sav, t;
6802 tree lab_false, lab_over = NULL_TREE;
6807 enum machine_mode nat_mode;
6810 /* Only 64bit target needs something special. */
6811 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6812 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6814 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6815 f_fpr = TREE_CHAIN (f_gpr);
6816 f_ovf = TREE_CHAIN (f_fpr);
6817 f_sav = TREE_CHAIN (f_ovf);
6819 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6820 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6821 valist = build_va_arg_indirect_ref (valist);
6822 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6823 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6824 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6826 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6828 type = build_pointer_type (type);
6829 size = int_size_in_bytes (type);
6830 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6832 nat_mode = type_natural_mode (type, NULL);
6841 /* Unnamed 256bit vector mode parameters are passed on stack. */
6842 if (ix86_cfun_abi () == SYSV_ABI)
6849 container = construct_container (nat_mode, TYPE_MODE (type),
6850 type, 0, X86_64_REGPARM_MAX,
6851 X86_64_SSE_REGPARM_MAX, intreg,
6856 /* Pull the value out of the saved registers. */
6858 addr = create_tmp_var (ptr_type_node, "addr");
6859 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6863 int needed_intregs, needed_sseregs;
6865 tree int_addr, sse_addr;
6867 lab_false = create_artificial_label ();
6868 lab_over = create_artificial_label ();
6870 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6872 need_temp = (!REG_P (container)
6873 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6874 || TYPE_ALIGN (type) > 128));
6876 /* In case we are passing structure, verify that it is consecutive block
6877 on the register save area. If not we need to do moves. */
6878 if (!need_temp && !REG_P (container))
6880 /* Verify that all registers are strictly consecutive */
6881 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6885 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6887 rtx slot = XVECEXP (container, 0, i);
6888 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6889 || INTVAL (XEXP (slot, 1)) != i * 16)
6897 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6899 rtx slot = XVECEXP (container, 0, i);
6900 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6901 || INTVAL (XEXP (slot, 1)) != i * 8)
6913 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6914 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6915 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6916 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6919 /* First ensure that we fit completely in registers. */
6922 t = build_int_cst (TREE_TYPE (gpr),
6923 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6924 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6925 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6926 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6927 gimplify_and_add (t, pre_p);
6931 t = build_int_cst (TREE_TYPE (fpr),
6932 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6933 + X86_64_REGPARM_MAX * 8);
6934 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6935 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6936 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6937 gimplify_and_add (t, pre_p);
6940 /* Compute index to start of area used for integer regs. */
6943 /* int_addr = gpr + sav; */
6944 t = fold_convert (sizetype, gpr);
6945 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6946 gimplify_assign (int_addr, t, pre_p);
6950 /* sse_addr = fpr + sav; */
6951 t = fold_convert (sizetype, fpr);
6952 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6953 gimplify_assign (sse_addr, t, pre_p);
6957 int i, prev_size = 0;
6958 tree temp = create_tmp_var (type, "va_arg_tmp");
6961 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6962 gimplify_assign (addr, t, pre_p);
6964 for (i = 0; i < XVECLEN (container, 0); i++)
6966 rtx slot = XVECEXP (container, 0, i);
6967 rtx reg = XEXP (slot, 0);
6968 enum machine_mode mode = GET_MODE (reg);
6974 tree dest_addr, dest;
6975 int cur_size = GET_MODE_SIZE (mode);
6977 gcc_assert (prev_size <= INTVAL (XEXP (slot, 1)));
6978 prev_size = INTVAL (XEXP (slot, 1));
6979 if (prev_size + cur_size > size)
6981 cur_size = size - prev_size;
6982 mode = mode_for_size (cur_size * BITS_PER_UNIT, MODE_INT, 1);
6983 if (mode == BLKmode)
6986 piece_type = lang_hooks.types.type_for_mode (mode, 1);
6987 if (mode == GET_MODE (reg))
6988 addr_type = build_pointer_type (piece_type);
6990 addr_type = build_pointer_type_for_mode (piece_type, ptr_mode,
6992 daddr_type = build_pointer_type_for_mode (piece_type, ptr_mode,
6995 if (SSE_REGNO_P (REGNO (reg)))
6997 src_addr = sse_addr;
6998 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7002 src_addr = int_addr;
7003 src_offset = REGNO (reg) * 8;
7005 src_addr = fold_convert (addr_type, src_addr);
7006 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7007 size_int (src_offset));
7009 dest_addr = fold_convert (daddr_type, addr);
7010 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7011 size_int (prev_size));
7012 if (cur_size == GET_MODE_SIZE (mode))
7014 src = build_va_arg_indirect_ref (src_addr);
7015 dest = build_va_arg_indirect_ref (dest_addr);
7017 gimplify_assign (dest, src, pre_p);
7022 = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
7023 3, dest_addr, src_addr,
7024 size_int (cur_size));
7025 gimplify_and_add (copy, pre_p);
7027 prev_size += cur_size;
7033 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7034 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7035 gimplify_assign (gpr, t, pre_p);
7040 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7041 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7042 gimplify_assign (fpr, t, pre_p);
7045 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7047 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7050 /* ... otherwise out of the overflow area. */
7052 /* When we align parameter on stack for caller, if the parameter
7053 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7054 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7055 here with caller. */
7056 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7057 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7058 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7060 /* Care for on-stack alignment if needed. */
7061 if (arg_boundary <= 64
7062 || integer_zerop (TYPE_SIZE (type)))
7066 HOST_WIDE_INT align = arg_boundary / 8;
7067 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7068 size_int (align - 1));
7069 t = fold_convert (sizetype, t);
7070 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7072 t = fold_convert (TREE_TYPE (ovf), t);
7074 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7075 gimplify_assign (addr, t, pre_p);
7077 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7078 size_int (rsize * UNITS_PER_WORD));
7079 gimplify_assign (unshare_expr (ovf), t, pre_p);
7082 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7084 ptrtype = build_pointer_type (type);
7085 addr = fold_convert (ptrtype, addr);
7088 addr = build_va_arg_indirect_ref (addr);
7089 return build_va_arg_indirect_ref (addr);
7092 /* Return nonzero if OPNUM's MEM should be matched
7093 in movabs* patterns. */
7096 ix86_check_movabs (rtx insn, int opnum)
7100 set = PATTERN (insn);
7101 if (GET_CODE (set) == PARALLEL)
7102 set = XVECEXP (set, 0, 0);
7103 gcc_assert (GET_CODE (set) == SET);
7104 mem = XEXP (set, opnum);
7105 while (GET_CODE (mem) == SUBREG)
7106 mem = SUBREG_REG (mem);
7107 gcc_assert (MEM_P (mem));
7108 return (volatile_ok || !MEM_VOLATILE_P (mem));
7111 /* Initialize the table of extra 80387 mathematical constants. */
7114 init_ext_80387_constants (void)
7116 static const char * cst[5] =
7118 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7119 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7120 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7121 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7122 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7126 for (i = 0; i < 5; i++)
7128 real_from_string (&ext_80387_constants_table[i], cst[i]);
7129 /* Ensure each constant is rounded to XFmode precision. */
7130 real_convert (&ext_80387_constants_table[i],
7131 XFmode, &ext_80387_constants_table[i]);
7134 ext_80387_constants_init = 1;
7137 /* Return true if the constant is something that can be loaded with
7138 a special instruction. */
7141 standard_80387_constant_p (rtx x)
7143 enum machine_mode mode = GET_MODE (x);
7147 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7150 if (x == CONST0_RTX (mode))
7152 if (x == CONST1_RTX (mode))
7155 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7157 /* For XFmode constants, try to find a special 80387 instruction when
7158 optimizing for size or on those CPUs that benefit from them. */
7160 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7164 if (! ext_80387_constants_init)
7165 init_ext_80387_constants ();
7167 for (i = 0; i < 5; i++)
7168 if (real_identical (&r, &ext_80387_constants_table[i]))
7172 /* Load of the constant -0.0 or -1.0 will be split as
7173 fldz;fchs or fld1;fchs sequence. */
7174 if (real_isnegzero (&r))
7176 if (real_identical (&r, &dconstm1))
7182 /* Return the opcode of the special instruction to be used to load
7186 standard_80387_constant_opcode (rtx x)
7188 switch (standard_80387_constant_p (x))
7212 /* Return the CONST_DOUBLE representing the 80387 constant that is
7213 loaded by the specified special instruction. The argument IDX
7214 matches the return value from standard_80387_constant_p. */
7217 standard_80387_constant_rtx (int idx)
7221 if (! ext_80387_constants_init)
7222 init_ext_80387_constants ();
7238 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7242 /* Return 1 if mode is a valid mode for sse. */
7244 standard_sse_mode_p (enum machine_mode mode)
7261 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7262 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7263 modes and AVX is enabled. */
7266 standard_sse_constant_p (rtx x)
7268 enum machine_mode mode = GET_MODE (x);
7270 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7272 if (vector_all_ones_operand (x, mode))
7274 if (standard_sse_mode_p (mode))
7275 return TARGET_SSE2 ? 2 : -2;
7276 else if (VALID_AVX256_REG_MODE (mode))
7277 return TARGET_AVX ? 3 : -3;
7283 /* Return the opcode of the special instruction to be used to load
7287 standard_sse_constant_opcode (rtx insn, rtx x)
7289 switch (standard_sse_constant_p (x))
7292 switch (get_attr_mode (insn))
7295 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7297 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7299 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7301 return "vxorps\t%x0, %x0, %x0";
7303 return "vxorpd\t%x0, %x0, %x0";
7305 return "vpxor\t%x0, %x0, %x0";
7311 switch (get_attr_mode (insn))
7316 return "vpcmpeqd\t%0, %0, %0";
7322 return "pcmpeqd\t%0, %0";
7327 /* Returns 1 if OP contains a symbol reference */
7330 symbolic_reference_mentioned_p (rtx op)
7335 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7338 fmt = GET_RTX_FORMAT (GET_CODE (op));
7339 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7345 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7346 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7350 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7357 /* Return 1 if it is appropriate to emit `ret' instructions in the
7358 body of a function. Do this only if the epilogue is simple, needing a
7359 couple of insns. Prior to reloading, we can't tell how many registers
7360 must be saved, so return 0 then. Return 0 if there is no frame
7361 marker to de-allocate. */
7364 ix86_can_use_return_insn_p (void)
7366 struct ix86_frame frame;
7368 if (! reload_completed || frame_pointer_needed)
7371 /* Don't allow more than 32 pop, since that's all we can do
7372 with one instruction. */
7373 if (crtl->args.pops_args
7374 && crtl->args.size >= 32768)
7377 ix86_compute_frame_layout (&frame);
7378 return frame.to_allocate == 0 && frame.padding0 == 0
7379 && (frame.nregs + frame.nsseregs) == 0;
7382 /* Value should be nonzero if functions must have frame pointers.
7383 Zero means the frame pointer need not be set up (and parms may
7384 be accessed via the stack pointer) in functions that seem suitable. */
7387 ix86_frame_pointer_required (void)
7389 /* If we accessed previous frames, then the generated code expects
7390 to be able to access the saved ebp value in our frame. */
7391 if (cfun->machine->accesses_prev_frame)
7394 /* Several x86 os'es need a frame pointer for other reasons,
7395 usually pertaining to setjmp. */
7396 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7399 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7400 the frame pointer by default. Turn it back on now if we've not
7401 got a leaf function. */
7402 if (TARGET_OMIT_LEAF_FRAME_POINTER
7403 && (!current_function_is_leaf
7404 || ix86_current_function_calls_tls_descriptor))
7413 /* Record that the current function accesses previous call frames. */
7416 ix86_setup_frame_addresses (void)
7418 cfun->machine->accesses_prev_frame = 1;
7421 #ifndef USE_HIDDEN_LINKONCE
7422 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7423 # define USE_HIDDEN_LINKONCE 1
7425 # define USE_HIDDEN_LINKONCE 0
7429 static int pic_labels_used;
7431 /* Fills in the label name that should be used for a pc thunk for
7432 the given register. */
7435 get_pc_thunk_name (char name[32], unsigned int regno)
7437 gcc_assert (!TARGET_64BIT);
7439 if (USE_HIDDEN_LINKONCE)
7440 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7442 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7446 /* This function generates code for -fpic that loads %ebx with
7447 the return address of the caller and then returns. */
7450 ix86_file_end (void)
7455 for (regno = 0; regno < 8; ++regno)
7459 if (! ((pic_labels_used >> regno) & 1))
7462 get_pc_thunk_name (name, regno);
7467 switch_to_section (darwin_sections[text_coal_section]);
7468 fputs ("\t.weak_definition\t", asm_out_file);
7469 assemble_name (asm_out_file, name);
7470 fputs ("\n\t.private_extern\t", asm_out_file);
7471 assemble_name (asm_out_file, name);
7472 fputs ("\n", asm_out_file);
7473 ASM_OUTPUT_LABEL (asm_out_file, name);
7477 if (USE_HIDDEN_LINKONCE)
7481 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7483 TREE_PUBLIC (decl) = 1;
7484 TREE_STATIC (decl) = 1;
7485 DECL_ONE_ONLY (decl) = 1;
7487 (*targetm.asm_out.unique_section) (decl, 0);
7488 switch_to_section (get_named_section (decl, NULL, 0));
7490 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7491 fputs ("\t.hidden\t", asm_out_file);
7492 assemble_name (asm_out_file, name);
7493 fputc ('\n', asm_out_file);
7494 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7498 switch_to_section (text_section);
7499 ASM_OUTPUT_LABEL (asm_out_file, name);
7502 xops[0] = gen_rtx_REG (Pmode, regno);
7503 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7504 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7505 output_asm_insn ("ret", xops);
7508 if (NEED_INDICATE_EXEC_STACK)
7509 file_end_indicate_exec_stack ();
7512 /* Emit code for the SET_GOT patterns. */
7515 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7521 if (TARGET_VXWORKS_RTP && flag_pic)
7523 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7524 xops[2] = gen_rtx_MEM (Pmode,
7525 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7526 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7528 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7529 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7530 an unadorned address. */
7531 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7532 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7533 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7537 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7539 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7541 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7544 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7546 output_asm_insn ("call\t%a2", xops);
7549 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7550 is what will be referenced by the Mach-O PIC subsystem. */
7552 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7555 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7556 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7559 output_asm_insn ("pop%z0\t%0", xops);
7564 get_pc_thunk_name (name, REGNO (dest));
7565 pic_labels_used |= 1 << REGNO (dest);
7567 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7568 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7569 output_asm_insn ("call\t%X2", xops);
7570 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7571 is what will be referenced by the Mach-O PIC subsystem. */
7574 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7576 targetm.asm_out.internal_label (asm_out_file, "L",
7577 CODE_LABEL_NUMBER (label));
7584 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7585 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7587 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7592 /* Generate an "push" pattern for input ARG. */
7597 return gen_rtx_SET (VOIDmode,
7599 gen_rtx_PRE_DEC (Pmode,
7600 stack_pointer_rtx)),
7604 /* Return >= 0 if there is an unused call-clobbered register available
7605 for the entire function. */
7608 ix86_select_alt_pic_regnum (void)
7610 if (current_function_is_leaf && !crtl->profile
7611 && !ix86_current_function_calls_tls_descriptor)
7614 /* Can't use the same register for both PIC and DRAP. */
7616 drap = REGNO (crtl->drap_reg);
7619 for (i = 2; i >= 0; --i)
7620 if (i != drap && !df_regs_ever_live_p (i))
7624 return INVALID_REGNUM;
7627 /* Return 1 if we need to save REGNO. */
7629 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7631 if (pic_offset_table_rtx
7632 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7633 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7635 || crtl->calls_eh_return
7636 || crtl->uses_const_pool))
7638 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7643 if (crtl->calls_eh_return && maybe_eh_return)
7648 unsigned test = EH_RETURN_DATA_REGNO (i);
7649 if (test == INVALID_REGNUM)
7657 && regno == REGNO (crtl->drap_reg))
7660 return (df_regs_ever_live_p (regno)
7661 && !call_used_regs[regno]
7662 && !fixed_regs[regno]
7663 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7666 /* Return number of saved general prupose registers. */
7669 ix86_nsaved_regs (void)
7674 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7675 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7680 /* Return number of saved SSE registrers. */
7683 ix86_nsaved_sseregs (void)
7688 if (ix86_cfun_abi () != MS_ABI)
7690 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7691 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7696 /* Given FROM and TO register numbers, say whether this elimination is
7697 allowed. If stack alignment is needed, we can only replace argument
7698 pointer with hard frame pointer, or replace frame pointer with stack
7699 pointer. Otherwise, frame pointer elimination is automatically
7700 handled and all other eliminations are valid. */
7703 ix86_can_eliminate (int from, int to)
7705 if (stack_realign_fp)
7706 return ((from == ARG_POINTER_REGNUM
7707 && to == HARD_FRAME_POINTER_REGNUM)
7708 || (from == FRAME_POINTER_REGNUM
7709 && to == STACK_POINTER_REGNUM));
7711 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7714 /* Return the offset between two registers, one to be eliminated, and the other
7715 its replacement, at the start of a routine. */
7718 ix86_initial_elimination_offset (int from, int to)
7720 struct ix86_frame frame;
7721 ix86_compute_frame_layout (&frame);
7723 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7724 return frame.hard_frame_pointer_offset;
7725 else if (from == FRAME_POINTER_REGNUM
7726 && to == HARD_FRAME_POINTER_REGNUM)
7727 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7730 gcc_assert (to == STACK_POINTER_REGNUM);
7732 if (from == ARG_POINTER_REGNUM)
7733 return frame.stack_pointer_offset;
7735 gcc_assert (from == FRAME_POINTER_REGNUM);
7736 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7740 /* In a dynamically-aligned function, we can't know the offset from
7741 stack pointer to frame pointer, so we must ensure that setjmp
7742 eliminates fp against the hard fp (%ebp) rather than trying to
7743 index from %esp up to the top of the frame across a gap that is
7744 of unknown (at compile-time) size. */
7746 ix86_builtin_setjmp_frame_value (void)
7748 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7751 /* Fill structure ix86_frame about frame of currently computed function. */
7754 ix86_compute_frame_layout (struct ix86_frame *frame)
7756 HOST_WIDE_INT total_size;
7757 unsigned int stack_alignment_needed;
7758 HOST_WIDE_INT offset;
7759 unsigned int preferred_alignment;
7760 HOST_WIDE_INT size = get_frame_size ();
7762 frame->nregs = ix86_nsaved_regs ();
7763 frame->nsseregs = ix86_nsaved_sseregs ();
7766 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7767 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7769 /* MS ABI seem to require stack alignment to be always 16 except for function
7771 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7773 preferred_alignment = 16;
7774 stack_alignment_needed = 16;
7775 crtl->preferred_stack_boundary = 128;
7776 crtl->stack_alignment_needed = 128;
7779 gcc_assert (!size || stack_alignment_needed);
7780 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7781 gcc_assert (preferred_alignment <= stack_alignment_needed);
7783 /* During reload iteration the amount of registers saved can change.
7784 Recompute the value as needed. Do not recompute when amount of registers
7785 didn't change as reload does multiple calls to the function and does not
7786 expect the decision to change within single iteration. */
7787 if (!optimize_function_for_size_p (cfun)
7788 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7790 int count = frame->nregs;
7792 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7793 /* The fast prologue uses move instead of push to save registers. This
7794 is significantly longer, but also executes faster as modern hardware
7795 can execute the moves in parallel, but can't do that for push/pop.
7797 Be careful about choosing what prologue to emit: When function takes
7798 many instructions to execute we may use slow version as well as in
7799 case function is known to be outside hot spot (this is known with
7800 feedback only). Weight the size of function by number of registers
7801 to save as it is cheap to use one or two push instructions but very
7802 slow to use many of them. */
7804 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7805 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7806 || (flag_branch_probabilities
7807 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7808 cfun->machine->use_fast_prologue_epilogue = false;
7810 cfun->machine->use_fast_prologue_epilogue
7811 = !expensive_function_p (count);
7813 if (TARGET_PROLOGUE_USING_MOVE
7814 && cfun->machine->use_fast_prologue_epilogue)
7815 frame->save_regs_using_mov = true;
7817 frame->save_regs_using_mov = false;
7820 /* Skip return address and saved base pointer. */
7821 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7823 frame->hard_frame_pointer_offset = offset;
7825 /* Set offset to aligned because the realigned frame starts from
7827 if (stack_realign_fp)
7828 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7830 /* Register save area */
7831 offset += frame->nregs * UNITS_PER_WORD;
7833 /* Align SSE reg save area. */
7834 if (frame->nsseregs)
7835 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7837 frame->padding0 = 0;
7839 /* SSE register save area. */
7840 offset += frame->padding0 + frame->nsseregs * 16;
7843 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7844 offset += frame->va_arg_size;
7846 /* Align start of frame for local function. */
7847 frame->padding1 = ((offset + stack_alignment_needed - 1)
7848 & -stack_alignment_needed) - offset;
7850 offset += frame->padding1;
7852 /* Frame pointer points here. */
7853 frame->frame_pointer_offset = offset;
7857 /* Add outgoing arguments area. Can be skipped if we eliminated
7858 all the function calls as dead code.
7859 Skipping is however impossible when function calls alloca. Alloca
7860 expander assumes that last crtl->outgoing_args_size
7861 of stack frame are unused. */
7862 if (ACCUMULATE_OUTGOING_ARGS
7863 && (!current_function_is_leaf || cfun->calls_alloca
7864 || ix86_current_function_calls_tls_descriptor))
7866 offset += crtl->outgoing_args_size;
7867 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7870 frame->outgoing_arguments_size = 0;
7872 /* Align stack boundary. Only needed if we're calling another function
7874 if (!current_function_is_leaf || cfun->calls_alloca
7875 || ix86_current_function_calls_tls_descriptor)
7876 frame->padding2 = ((offset + preferred_alignment - 1)
7877 & -preferred_alignment) - offset;
7879 frame->padding2 = 0;
7881 offset += frame->padding2;
7883 /* We've reached end of stack frame. */
7884 frame->stack_pointer_offset = offset;
7886 /* Size prologue needs to allocate. */
7887 frame->to_allocate =
7888 (size + frame->padding1 + frame->padding2
7889 + frame->outgoing_arguments_size + frame->va_arg_size);
7891 if ((!frame->to_allocate && frame->nregs <= 1)
7892 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7893 frame->save_regs_using_mov = false;
7895 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
7896 && current_function_sp_is_unchanging
7897 && current_function_is_leaf
7898 && !ix86_current_function_calls_tls_descriptor)
7900 frame->red_zone_size = frame->to_allocate;
7901 if (frame->save_regs_using_mov)
7902 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7903 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7904 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7907 frame->red_zone_size = 0;
7908 frame->to_allocate -= frame->red_zone_size;
7909 frame->stack_pointer_offset -= frame->red_zone_size;
7911 fprintf (stderr, "\n");
7912 fprintf (stderr, "size: %ld\n", (long)size);
7913 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7914 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7915 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7916 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7917 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7918 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7919 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7920 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7921 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7922 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7923 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7924 (long)frame->hard_frame_pointer_offset);
7925 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7926 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7927 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7928 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7932 /* Emit code to save registers in the prologue. */
7935 ix86_emit_save_regs (void)
7940 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7941 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7943 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7944 RTX_FRAME_RELATED_P (insn) = 1;
7948 /* Emit code to save registers using MOV insns. First register
7949 is restored from POINTER + OFFSET. */
7951 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7956 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7957 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7959 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7961 gen_rtx_REG (Pmode, regno));
7962 RTX_FRAME_RELATED_P (insn) = 1;
7963 offset += UNITS_PER_WORD;
7967 /* Emit code to save registers using MOV insns. First register
7968 is restored from POINTER + OFFSET. */
7970 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7976 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7977 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7979 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7980 set_mem_align (mem, 128);
7981 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7982 RTX_FRAME_RELATED_P (insn) = 1;
7987 /* Expand prologue or epilogue stack adjustment.
7988 The pattern exist to put a dependency on all ebp-based memory accesses.
7989 STYLE should be negative if instructions should be marked as frame related,
7990 zero if %r11 register is live and cannot be freely used and positive
7994 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7999 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8000 else if (x86_64_immediate_operand (offset, DImode))
8001 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8005 /* r11 is used by indirect sibcall return as well, set before the
8006 epilogue and used after the epilogue. ATM indirect sibcall
8007 shouldn't be used together with huge frame sizes in one
8008 function because of the frame_size check in sibcall.c. */
8010 r11 = gen_rtx_REG (DImode, R11_REG);
8011 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8013 RTX_FRAME_RELATED_P (insn) = 1;
8014 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8018 RTX_FRAME_RELATED_P (insn) = 1;
8021 /* Find an available register to be used as dynamic realign argument
8022 pointer regsiter. Such a register will be written in prologue and
8023 used in begin of body, so it must not be
8024 1. parameter passing register.
8026 We reuse static-chain register if it is available. Otherwise, we
8027 use DI for i386 and R13 for x86-64. We chose R13 since it has
8030 Return: the regno of chosen register. */
8033 find_drap_reg (void)
8035 tree decl = cfun->decl;
8039 /* Use R13 for nested function or function need static chain.
8040 Since function with tail call may use any caller-saved
8041 registers in epilogue, DRAP must not use caller-saved
8042 register in such case. */
8043 if ((decl_function_context (decl)
8044 && !DECL_NO_STATIC_CHAIN (decl))
8045 || crtl->tail_call_emit)
8052 /* Use DI for nested function or function need static chain.
8053 Since function with tail call may use any caller-saved
8054 registers in epilogue, DRAP must not use caller-saved
8055 register in such case. */
8056 if ((decl_function_context (decl)
8057 && !DECL_NO_STATIC_CHAIN (decl))
8058 || crtl->tail_call_emit)
8061 /* Reuse static chain register if it isn't used for parameter
8063 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8064 && !lookup_attribute ("fastcall",
8065 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8072 /* Update incoming stack boundary and estimated stack alignment. */
8075 ix86_update_stack_boundary (void)
8077 /* Prefer the one specified at command line. */
8078 ix86_incoming_stack_boundary
8079 = (ix86_user_incoming_stack_boundary
8080 ? ix86_user_incoming_stack_boundary
8081 : ix86_default_incoming_stack_boundary);
8083 /* Incoming stack alignment can be changed on individual functions
8084 via force_align_arg_pointer attribute. We use the smallest
8085 incoming stack boundary. */
8086 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8087 && lookup_attribute (ix86_force_align_arg_pointer_string,
8088 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8089 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8091 /* The incoming stack frame has to be aligned at least at
8092 parm_stack_boundary. */
8093 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8094 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8096 /* Stack at entrance of main is aligned by runtime. We use the
8097 smallest incoming stack boundary. */
8098 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8099 && DECL_NAME (current_function_decl)
8100 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8101 && DECL_FILE_SCOPE_P (current_function_decl))
8102 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8104 /* x86_64 vararg needs 16byte stack alignment for register save
8108 && crtl->stack_alignment_estimated < 128)
8109 crtl->stack_alignment_estimated = 128;
8112 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8113 needed or an rtx for DRAP otherwise. */
8116 ix86_get_drap_rtx (void)
8118 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8119 crtl->need_drap = true;
8121 if (stack_realign_drap)
8123 /* Assign DRAP to vDRAP and returns vDRAP */
8124 unsigned int regno = find_drap_reg ();
8129 arg_ptr = gen_rtx_REG (Pmode, regno);
8130 crtl->drap_reg = arg_ptr;
8133 drap_vreg = copy_to_reg (arg_ptr);
8137 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8138 RTX_FRAME_RELATED_P (insn) = 1;
8145 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8148 ix86_internal_arg_pointer (void)
8150 return virtual_incoming_args_rtx;
8153 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8154 This is called from dwarf2out.c to emit call frame instructions
8155 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8157 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
8159 rtx unspec = SET_SRC (pattern);
8160 gcc_assert (GET_CODE (unspec) == UNSPEC);
8164 case UNSPEC_REG_SAVE:
8165 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
8166 SET_DEST (pattern));
8168 case UNSPEC_DEF_CFA:
8169 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
8170 INTVAL (XVECEXP (unspec, 0, 0)));
8177 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8178 to be generated in correct form. */
8180 ix86_finalize_stack_realign_flags (void)
8182 /* Check if stack realign is really needed after reload, and
8183 stores result in cfun */
8184 unsigned int incoming_stack_boundary
8185 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8186 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8187 unsigned int stack_realign = (incoming_stack_boundary
8188 < (current_function_is_leaf
8189 ? crtl->max_used_stack_slot_alignment
8190 : crtl->stack_alignment_needed));
8192 if (crtl->stack_realign_finalized)
8194 /* After stack_realign_needed is finalized, we can't no longer
8196 gcc_assert (crtl->stack_realign_needed == stack_realign);
8200 crtl->stack_realign_needed = stack_realign;
8201 crtl->stack_realign_finalized = true;
8205 /* Expand the prologue into a bunch of separate insns. */
8208 ix86_expand_prologue (void)
8212 struct ix86_frame frame;
8213 HOST_WIDE_INT allocate;
8215 ix86_finalize_stack_realign_flags ();
8217 /* DRAP should not coexist with stack_realign_fp */
8218 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8220 ix86_compute_frame_layout (&frame);
8222 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8223 of DRAP is needed and stack realignment is really needed after reload */
8224 if (crtl->drap_reg && crtl->stack_realign_needed)
8227 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8228 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8229 ? 0 : UNITS_PER_WORD);
8231 gcc_assert (stack_realign_drap);
8233 /* Grab the argument pointer. */
8234 x = plus_constant (stack_pointer_rtx,
8235 (UNITS_PER_WORD + param_ptr_offset));
8238 /* Only need to push parameter pointer reg if it is caller
8240 if (!call_used_regs[REGNO (crtl->drap_reg)])
8242 /* Push arg pointer reg */
8243 insn = emit_insn (gen_push (y));
8244 RTX_FRAME_RELATED_P (insn) = 1;
8247 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8248 RTX_FRAME_RELATED_P (insn) = 1;
8250 /* Align the stack. */
8251 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8253 GEN_INT (-align_bytes)));
8254 RTX_FRAME_RELATED_P (insn) = 1;
8256 /* Replicate the return address on the stack so that return
8257 address can be reached via (argp - 1) slot. This is needed
8258 to implement macro RETURN_ADDR_RTX and intrinsic function
8259 expand_builtin_return_addr etc. */
8261 x = gen_frame_mem (Pmode,
8262 plus_constant (x, -UNITS_PER_WORD));
8263 insn = emit_insn (gen_push (x));
8264 RTX_FRAME_RELATED_P (insn) = 1;
8267 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8268 slower on all targets. Also sdb doesn't like it. */
8270 if (frame_pointer_needed)
8272 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8273 RTX_FRAME_RELATED_P (insn) = 1;
8275 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8276 RTX_FRAME_RELATED_P (insn) = 1;
8279 if (stack_realign_fp)
8281 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8282 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8284 /* Align the stack. */
8285 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8287 GEN_INT (-align_bytes)));
8288 RTX_FRAME_RELATED_P (insn) = 1;
8291 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8293 if (!frame.save_regs_using_mov)
8294 ix86_emit_save_regs ();
8296 allocate += frame.nregs * UNITS_PER_WORD;
8298 /* When using red zone we may start register saving before allocating
8299 the stack frame saving one cycle of the prologue. However I will
8300 avoid doing this if I am going to have to probe the stack since
8301 at least on x86_64 the stack probe can turn into a call that clobbers
8302 a red zone location */
8303 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8304 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8305 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8306 && !crtl->stack_realign_needed)
8307 ? hard_frame_pointer_rtx
8308 : stack_pointer_rtx,
8309 -frame.nregs * UNITS_PER_WORD);
8313 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8314 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8315 GEN_INT (-allocate), -1);
8318 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8322 if (cfun->machine->call_abi == MS_ABI)
8325 eax_live = ix86_eax_live_at_start_p ();
8329 emit_insn (gen_push (eax));
8330 allocate -= UNITS_PER_WORD;
8333 emit_move_insn (eax, GEN_INT (allocate));
8336 insn = gen_allocate_stack_worker_64 (eax, eax);
8338 insn = gen_allocate_stack_worker_32 (eax, eax);
8339 insn = emit_insn (insn);
8340 RTX_FRAME_RELATED_P (insn) = 1;
8341 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8342 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8343 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8344 t, REG_NOTES (insn));
8348 if (frame_pointer_needed)
8349 t = plus_constant (hard_frame_pointer_rtx,
8352 - frame.nregs * UNITS_PER_WORD);
8354 t = plus_constant (stack_pointer_rtx, allocate);
8355 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8359 if (frame.save_regs_using_mov
8360 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8361 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8363 if (!frame_pointer_needed
8364 || !(frame.to_allocate + frame.padding0)
8365 || crtl->stack_realign_needed)
8366 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8368 + frame.nsseregs * 16 + frame.padding0);
8370 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8371 -frame.nregs * UNITS_PER_WORD);
8373 if (!frame_pointer_needed
8374 || !(frame.to_allocate + frame.padding0)
8375 || crtl->stack_realign_needed)
8376 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8379 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8380 - frame.nregs * UNITS_PER_WORD
8381 - frame.nsseregs * 16
8384 pic_reg_used = false;
8385 if (pic_offset_table_rtx
8386 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8389 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8391 if (alt_pic_reg_used != INVALID_REGNUM)
8392 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8394 pic_reg_used = true;
8401 if (ix86_cmodel == CM_LARGE_PIC)
8403 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8404 rtx label = gen_label_rtx ();
8406 LABEL_PRESERVE_P (label) = 1;
8407 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8408 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8409 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8410 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8411 pic_offset_table_rtx, tmp_reg));
8414 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8417 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8420 /* In the pic_reg_used case, make sure that the got load isn't deleted
8421 when mcount needs it. Blockage to avoid call movement across mcount
8422 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8424 if (crtl->profile && pic_reg_used)
8425 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8427 if (crtl->drap_reg && !crtl->stack_realign_needed)
8429 /* vDRAP is setup but after reload it turns out stack realign
8430 isn't necessary, here we will emit prologue to setup DRAP
8431 without stack realign adjustment */
8432 int drap_bp_offset = UNITS_PER_WORD * 2;
8433 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8434 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8437 /* Prevent instructions from being scheduled into register save push
8438 sequence when access to the redzone area is done through frame pointer.
8439 The offset betweeh the frame pointer and the stack pointer is calculated
8440 relative to the value of the stack pointer at the end of the function
8441 prologue, and moving instructions that access redzone area via frame
8442 pointer inside push sequence violates this assumption. */
8443 if (frame_pointer_needed && frame.red_zone_size)
8444 emit_insn (gen_memory_blockage ());
8446 /* Emit cld instruction if stringops are used in the function. */
8447 if (TARGET_CLD && ix86_current_function_needs_cld)
8448 emit_insn (gen_cld ());
8451 /* Emit code to restore saved registers using MOV insns. First register
8452 is restored from POINTER + OFFSET. */
8454 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8455 int maybe_eh_return)
8458 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8460 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8461 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8463 /* Ensure that adjust_address won't be forced to produce pointer
8464 out of range allowed by x86-64 instruction set. */
8465 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8469 r11 = gen_rtx_REG (DImode, R11_REG);
8470 emit_move_insn (r11, GEN_INT (offset));
8471 emit_insn (gen_adddi3 (r11, r11, pointer));
8472 base_address = gen_rtx_MEM (Pmode, r11);
8475 emit_move_insn (gen_rtx_REG (Pmode, regno),
8476 adjust_address (base_address, Pmode, offset));
8477 offset += UNITS_PER_WORD;
8481 /* Emit code to restore saved registers using MOV insns. First register
8482 is restored from POINTER + OFFSET. */
8484 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8485 int maybe_eh_return)
8488 rtx base_address = gen_rtx_MEM (TImode, pointer);
8491 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8492 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8494 /* Ensure that adjust_address won't be forced to produce pointer
8495 out of range allowed by x86-64 instruction set. */
8496 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8500 r11 = gen_rtx_REG (DImode, R11_REG);
8501 emit_move_insn (r11, GEN_INT (offset));
8502 emit_insn (gen_adddi3 (r11, r11, pointer));
8503 base_address = gen_rtx_MEM (TImode, r11);
8506 mem = adjust_address (base_address, TImode, offset);
8507 set_mem_align (mem, 128);
8508 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8513 /* Restore function stack, frame, and registers. */
8516 ix86_expand_epilogue (int style)
8520 struct ix86_frame frame;
8521 HOST_WIDE_INT offset;
8523 ix86_finalize_stack_realign_flags ();
8525 /* When stack is realigned, SP must be valid. */
8526 sp_valid = (!frame_pointer_needed
8527 || current_function_sp_is_unchanging
8528 || stack_realign_fp);
8530 ix86_compute_frame_layout (&frame);
8532 /* See the comment about red zone and frame
8533 pointer usage in ix86_expand_prologue. */
8534 if (frame_pointer_needed && frame.red_zone_size)
8535 emit_insn (gen_memory_blockage ());
8537 /* Calculate start of saved registers relative to ebp. Special care
8538 must be taken for the normal return case of a function using
8539 eh_return: the eax and edx registers are marked as saved, but not
8540 restored along this path. */
8541 offset = frame.nregs;
8542 if (crtl->calls_eh_return && style != 2)
8544 offset *= -UNITS_PER_WORD;
8545 offset -= frame.nsseregs * 16 + frame.padding0;
8547 /* If we're only restoring one register and sp is not valid then
8548 using a move instruction to restore the register since it's
8549 less work than reloading sp and popping the register.
8551 The default code result in stack adjustment using add/lea instruction,
8552 while this code results in LEAVE instruction (or discrete equivalent),
8553 so it is profitable in some other cases as well. Especially when there
8554 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8555 and there is exactly one register to pop. This heuristic may need some
8556 tuning in future. */
8557 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8558 || (TARGET_EPILOGUE_USING_MOVE
8559 && cfun->machine->use_fast_prologue_epilogue
8560 && ((frame.nregs + frame.nsseregs) > 1
8561 || (frame.to_allocate + frame.padding0) != 0))
8562 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8563 && (frame.to_allocate + frame.padding0) != 0)
8564 || (frame_pointer_needed && TARGET_USE_LEAVE
8565 && cfun->machine->use_fast_prologue_epilogue
8566 && (frame.nregs + frame.nsseregs) == 1)
8567 || crtl->calls_eh_return)
8569 /* Restore registers. We can use ebp or esp to address the memory
8570 locations. If both are available, default to ebp, since offsets
8571 are known to be small. Only exception is esp pointing directly
8572 to the end of block of saved registers, where we may simplify
8575 If we are realigning stack with bp and sp, regs restore can't
8576 be addressed by bp. sp must be used instead. */
8578 if (!frame_pointer_needed
8579 || (sp_valid && !(frame.to_allocate + frame.padding0))
8580 || stack_realign_fp)
8582 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8583 frame.to_allocate, style == 2);
8584 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8586 + frame.nsseregs * 16
8587 + frame.padding0, style == 2);
8591 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8592 offset, style == 2);
8593 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8595 + frame.nsseregs * 16
8596 + frame.padding0, style == 2);
8599 /* eh_return epilogues need %ecx added to the stack pointer. */
8602 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8604 /* Stack align doesn't work with eh_return. */
8605 gcc_assert (!crtl->stack_realign_needed);
8607 if (frame_pointer_needed)
8609 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8610 tmp = plus_constant (tmp, UNITS_PER_WORD);
8611 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8613 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8614 emit_move_insn (hard_frame_pointer_rtx, tmp);
8616 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8621 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8622 tmp = plus_constant (tmp, (frame.to_allocate
8623 + frame.nregs * UNITS_PER_WORD
8624 + frame.nsseregs * 16
8626 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8629 else if (!frame_pointer_needed)
8630 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8631 GEN_INT (frame.to_allocate
8632 + frame.nregs * UNITS_PER_WORD
8633 + frame.nsseregs * 16
8636 /* If not an i386, mov & pop is faster than "leave". */
8637 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8638 || !cfun->machine->use_fast_prologue_epilogue)
8639 emit_insn ((*ix86_gen_leave) ());
8642 pro_epilogue_adjust_stack (stack_pointer_rtx,
8643 hard_frame_pointer_rtx,
8646 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8651 /* First step is to deallocate the stack frame so that we can
8654 If we realign stack with frame pointer, then stack pointer
8655 won't be able to recover via lea $offset(%bp), %sp, because
8656 there is a padding area between bp and sp for realign.
8657 "add $to_allocate, %sp" must be used instead. */
8660 gcc_assert (frame_pointer_needed);
8661 gcc_assert (!stack_realign_fp);
8662 pro_epilogue_adjust_stack (stack_pointer_rtx,
8663 hard_frame_pointer_rtx,
8664 GEN_INT (offset), style);
8665 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8667 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8668 GEN_INT (frame.nsseregs * 16 +
8669 frame.padding0), style);
8671 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
8673 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8676 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8677 GEN_INT (frame.to_allocate
8678 + frame.nsseregs * 16
8679 + frame.padding0), style);
8682 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8683 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8684 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8685 if (frame_pointer_needed)
8687 /* Leave results in shorter dependency chains on CPUs that are
8688 able to grok it fast. */
8689 if (TARGET_USE_LEAVE)
8690 emit_insn ((*ix86_gen_leave) ());
8693 /* For stack realigned really happens, recover stack
8694 pointer to hard frame pointer is a must, if not using
8696 if (stack_realign_fp)
8697 pro_epilogue_adjust_stack (stack_pointer_rtx,
8698 hard_frame_pointer_rtx,
8700 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8705 if (crtl->drap_reg && crtl->stack_realign_needed)
8707 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8708 ? 0 : UNITS_PER_WORD);
8709 gcc_assert (stack_realign_drap);
8710 emit_insn (gen_rtx_SET
8711 (VOIDmode, stack_pointer_rtx,
8712 gen_rtx_PLUS (Pmode,
8714 GEN_INT (-(UNITS_PER_WORD
8715 + param_ptr_offset)))));
8716 if (!call_used_regs[REGNO (crtl->drap_reg)])
8717 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8721 /* Sibcall epilogues don't want a return instruction. */
8725 if (crtl->args.pops_args && crtl->args.size)
8727 rtx popc = GEN_INT (crtl->args.pops_args);
8729 /* i386 can only pop 64K bytes. If asked to pop more, pop
8730 return address, do explicit add, and jump indirectly to the
8733 if (crtl->args.pops_args >= 65536)
8735 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8737 /* There is no "pascal" calling convention in any 64bit ABI. */
8738 gcc_assert (!TARGET_64BIT);
8740 emit_insn (gen_popsi1 (ecx));
8741 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8742 emit_jump_insn (gen_return_indirect_internal (ecx));
8745 emit_jump_insn (gen_return_pop_internal (popc));
8748 emit_jump_insn (gen_return_internal ());
8751 /* Reset from the function's potential modifications. */
8754 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8755 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8757 if (pic_offset_table_rtx)
8758 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8760 /* Mach-O doesn't support labels at the end of objects, so if
8761 it looks like we might want one, insert a NOP. */
8763 rtx insn = get_last_insn ();
8766 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8767 insn = PREV_INSN (insn);
8771 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8772 fputs ("\tnop\n", file);
8778 /* Extract the parts of an RTL expression that is a valid memory address
8779 for an instruction. Return 0 if the structure of the address is
8780 grossly off. Return -1 if the address contains ASHIFT, so it is not
8781 strictly valid, but still used for computing length of lea instruction. */
8784 ix86_decompose_address (rtx addr, struct ix86_address *out)
8786 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8787 rtx base_reg, index_reg;
8788 HOST_WIDE_INT scale = 1;
8789 rtx scale_rtx = NULL_RTX;
8791 enum ix86_address_seg seg = SEG_DEFAULT;
8793 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8795 else if (GET_CODE (addr) == PLUS)
8805 addends[n++] = XEXP (op, 1);
8808 while (GET_CODE (op) == PLUS);
8813 for (i = n; i >= 0; --i)
8816 switch (GET_CODE (op))
8821 index = XEXP (op, 0);
8822 scale_rtx = XEXP (op, 1);
8826 if (XINT (op, 1) == UNSPEC_TP
8827 && TARGET_TLS_DIRECT_SEG_REFS
8828 && seg == SEG_DEFAULT)
8829 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8858 else if (GET_CODE (addr) == MULT)
8860 index = XEXP (addr, 0); /* index*scale */
8861 scale_rtx = XEXP (addr, 1);
8863 else if (GET_CODE (addr) == ASHIFT)
8867 /* We're called for lea too, which implements ashift on occasion. */
8868 index = XEXP (addr, 0);
8869 tmp = XEXP (addr, 1);
8870 if (!CONST_INT_P (tmp))
8872 scale = INTVAL (tmp);
8873 if ((unsigned HOST_WIDE_INT) scale > 3)
8879 disp = addr; /* displacement */
8881 /* Extract the integral value of scale. */
8884 if (!CONST_INT_P (scale_rtx))
8886 scale = INTVAL (scale_rtx);
8889 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8890 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8892 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8893 if (base_reg && index_reg && scale == 1
8894 && (index_reg == arg_pointer_rtx
8895 || index_reg == frame_pointer_rtx
8896 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8899 tmp = base, base = index, index = tmp;
8900 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8903 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8904 if ((base_reg == hard_frame_pointer_rtx
8905 || base_reg == frame_pointer_rtx
8906 || base_reg == arg_pointer_rtx) && !disp)
8909 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8910 Avoid this by transforming to [%esi+0].
8911 Reload calls address legitimization without cfun defined, so we need
8912 to test cfun for being non-NULL. */
8913 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8914 && base_reg && !index_reg && !disp
8915 && REG_P (base_reg) && REGNO (base_reg) == SI_REG)
8918 /* Special case: encode reg+reg instead of reg*2. */
8919 if (!base && index && scale && scale == 2)
8920 base = index, base_reg = index_reg, scale = 1;
8922 /* Special case: scaling cannot be encoded without base or displacement. */
8923 if (!base && !disp && index && scale != 1)
8935 /* Return cost of the memory address x.
8936 For i386, it is better to use a complex address than let gcc copy
8937 the address into a reg and make a new pseudo. But not if the address
8938 requires to two regs - that would mean more pseudos with longer
8941 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8943 struct ix86_address parts;
8945 int ok = ix86_decompose_address (x, &parts);
8949 if (parts.base && GET_CODE (parts.base) == SUBREG)
8950 parts.base = SUBREG_REG (parts.base);
8951 if (parts.index && GET_CODE (parts.index) == SUBREG)
8952 parts.index = SUBREG_REG (parts.index);
8954 /* Attempt to minimize number of registers in the address. */
8956 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8958 && (!REG_P (parts.index)
8959 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8963 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8965 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8966 && parts.base != parts.index)
8969 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8970 since it's predecode logic can't detect the length of instructions
8971 and it degenerates to vector decoded. Increase cost of such
8972 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8973 to split such addresses or even refuse such addresses at all.
8975 Following addressing modes are affected:
8980 The first and last case may be avoidable by explicitly coding the zero in
8981 memory address, but I don't have AMD-K6 machine handy to check this
8985 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8986 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8987 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8993 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8994 this is used for to form addresses to local data when -fPIC is in
8998 darwin_local_data_pic (rtx disp)
9000 return (GET_CODE (disp) == UNSPEC
9001 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9004 /* Determine if a given RTX is a valid constant. We already know this
9005 satisfies CONSTANT_P. */
9008 legitimate_constant_p (rtx x)
9010 switch (GET_CODE (x))
9015 if (GET_CODE (x) == PLUS)
9017 if (!CONST_INT_P (XEXP (x, 1)))
9022 if (TARGET_MACHO && darwin_local_data_pic (x))
9025 /* Only some unspecs are valid as "constants". */
9026 if (GET_CODE (x) == UNSPEC)
9027 switch (XINT (x, 1))
9032 return TARGET_64BIT;
9035 x = XVECEXP (x, 0, 0);
9036 return (GET_CODE (x) == SYMBOL_REF
9037 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9039 x = XVECEXP (x, 0, 0);
9040 return (GET_CODE (x) == SYMBOL_REF
9041 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9046 /* We must have drilled down to a symbol. */
9047 if (GET_CODE (x) == LABEL_REF)
9049 if (GET_CODE (x) != SYMBOL_REF)
9054 /* TLS symbols are never valid. */
9055 if (SYMBOL_REF_TLS_MODEL (x))
9058 /* DLLIMPORT symbols are never valid. */
9059 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9060 && SYMBOL_REF_DLLIMPORT_P (x))
9065 if (GET_MODE (x) == TImode
9066 && x != CONST0_RTX (TImode)
9072 if (x == CONST0_RTX (GET_MODE (x)))
9080 /* Otherwise we handle everything else in the move patterns. */
9084 /* Determine if it's legal to put X into the constant pool. This
9085 is not possible for the address of thread-local symbols, which
9086 is checked above. */
9089 ix86_cannot_force_const_mem (rtx x)
9091 /* We can always put integral constants and vectors in memory. */
9092 switch (GET_CODE (x))
9102 return !legitimate_constant_p (x);
9105 /* Determine if a given RTX is a valid constant address. */
9108 constant_address_p (rtx x)
9110 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
9113 /* Nonzero if the constant value X is a legitimate general operand
9114 when generating PIC code. It is given that flag_pic is on and
9115 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9118 legitimate_pic_operand_p (rtx x)
9122 switch (GET_CODE (x))
9125 inner = XEXP (x, 0);
9126 if (GET_CODE (inner) == PLUS
9127 && CONST_INT_P (XEXP (inner, 1)))
9128 inner = XEXP (inner, 0);
9130 /* Only some unspecs are valid as "constants". */
9131 if (GET_CODE (inner) == UNSPEC)
9132 switch (XINT (inner, 1))
9137 return TARGET_64BIT;
9139 x = XVECEXP (inner, 0, 0);
9140 return (GET_CODE (x) == SYMBOL_REF
9141 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9142 case UNSPEC_MACHOPIC_OFFSET:
9143 return legitimate_pic_address_disp_p (x);
9151 return legitimate_pic_address_disp_p (x);
9158 /* Determine if a given CONST RTX is a valid memory displacement
9162 legitimate_pic_address_disp_p (rtx disp)
9166 /* In 64bit mode we can allow direct addresses of symbols and labels
9167 when they are not dynamic symbols. */
9170 rtx op0 = disp, op1;
9172 switch (GET_CODE (disp))
9178 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9180 op0 = XEXP (XEXP (disp, 0), 0);
9181 op1 = XEXP (XEXP (disp, 0), 1);
9182 if (!CONST_INT_P (op1)
9183 || INTVAL (op1) >= 16*1024*1024
9184 || INTVAL (op1) < -16*1024*1024)
9186 if (GET_CODE (op0) == LABEL_REF)
9188 if (GET_CODE (op0) != SYMBOL_REF)
9193 /* TLS references should always be enclosed in UNSPEC. */
9194 if (SYMBOL_REF_TLS_MODEL (op0))
9196 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9197 && ix86_cmodel != CM_LARGE_PIC)
9205 if (GET_CODE (disp) != CONST)
9207 disp = XEXP (disp, 0);
9211 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9212 of GOT tables. We should not need these anyway. */
9213 if (GET_CODE (disp) != UNSPEC
9214 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9215 && XINT (disp, 1) != UNSPEC_GOTOFF
9216 && XINT (disp, 1) != UNSPEC_PLTOFF))
9219 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9220 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9226 if (GET_CODE (disp) == PLUS)
9228 if (!CONST_INT_P (XEXP (disp, 1)))
9230 disp = XEXP (disp, 0);
9234 if (TARGET_MACHO && darwin_local_data_pic (disp))
9237 if (GET_CODE (disp) != UNSPEC)
9240 switch (XINT (disp, 1))
9245 /* We need to check for both symbols and labels because VxWorks loads
9246 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9248 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9249 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9251 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9252 While ABI specify also 32bit relocation but we don't produce it in
9253 small PIC model at all. */
9254 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9255 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9257 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9259 case UNSPEC_GOTTPOFF:
9260 case UNSPEC_GOTNTPOFF:
9261 case UNSPEC_INDNTPOFF:
9264 disp = XVECEXP (disp, 0, 0);
9265 return (GET_CODE (disp) == SYMBOL_REF
9266 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9268 disp = XVECEXP (disp, 0, 0);
9269 return (GET_CODE (disp) == SYMBOL_REF
9270 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9272 disp = XVECEXP (disp, 0, 0);
9273 return (GET_CODE (disp) == SYMBOL_REF
9274 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9280 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
9281 memory address for an instruction. The MODE argument is the machine mode
9282 for the MEM expression that wants to use this address.
9284 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9285 convert common non-canonical forms to canonical form so that they will
9289 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9290 rtx addr, int strict)
9292 struct ix86_address parts;
9293 rtx base, index, disp;
9294 HOST_WIDE_INT scale;
9295 const char *reason = NULL;
9296 rtx reason_rtx = NULL_RTX;
9298 if (ix86_decompose_address (addr, &parts) <= 0)
9300 reason = "decomposition failed";
9305 index = parts.index;
9307 scale = parts.scale;
9309 /* Validate base register.
9311 Don't allow SUBREG's that span more than a word here. It can lead to spill
9312 failures when the base is one word out of a two word structure, which is
9313 represented internally as a DImode int. */
9322 else if (GET_CODE (base) == SUBREG
9323 && REG_P (SUBREG_REG (base))
9324 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9326 reg = SUBREG_REG (base);
9329 reason = "base is not a register";
9333 if (GET_MODE (base) != Pmode)
9335 reason = "base is not in Pmode";
9339 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9340 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9342 reason = "base is not valid";
9347 /* Validate index register.
9349 Don't allow SUBREG's that span more than a word here -- same as above. */
9358 else if (GET_CODE (index) == SUBREG
9359 && REG_P (SUBREG_REG (index))
9360 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9362 reg = SUBREG_REG (index);
9365 reason = "index is not a register";
9369 if (GET_MODE (index) != Pmode)
9371 reason = "index is not in Pmode";
9375 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9376 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9378 reason = "index is not valid";
9383 /* Validate scale factor. */
9386 reason_rtx = GEN_INT (scale);
9389 reason = "scale without index";
9393 if (scale != 2 && scale != 4 && scale != 8)
9395 reason = "scale is not a valid multiplier";
9400 /* Validate displacement. */
9405 if (GET_CODE (disp) == CONST
9406 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9407 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9408 switch (XINT (XEXP (disp, 0), 1))
9410 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9411 used. While ABI specify also 32bit relocations, we don't produce
9412 them at all and use IP relative instead. */
9415 gcc_assert (flag_pic);
9417 goto is_legitimate_pic;
9418 reason = "64bit address unspec";
9421 case UNSPEC_GOTPCREL:
9422 gcc_assert (flag_pic);
9423 goto is_legitimate_pic;
9425 case UNSPEC_GOTTPOFF:
9426 case UNSPEC_GOTNTPOFF:
9427 case UNSPEC_INDNTPOFF:
9433 reason = "invalid address unspec";
9437 else if (SYMBOLIC_CONST (disp)
9441 && MACHOPIC_INDIRECT
9442 && !machopic_operand_p (disp)
9448 if (TARGET_64BIT && (index || base))
9450 /* foo@dtpoff(%rX) is ok. */
9451 if (GET_CODE (disp) != CONST
9452 || GET_CODE (XEXP (disp, 0)) != PLUS
9453 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9454 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9455 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9456 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9458 reason = "non-constant pic memory reference";
9462 else if (! legitimate_pic_address_disp_p (disp))
9464 reason = "displacement is an invalid pic construct";
9468 /* This code used to verify that a symbolic pic displacement
9469 includes the pic_offset_table_rtx register.
9471 While this is good idea, unfortunately these constructs may
9472 be created by "adds using lea" optimization for incorrect
9481 This code is nonsensical, but results in addressing
9482 GOT table with pic_offset_table_rtx base. We can't
9483 just refuse it easily, since it gets matched by
9484 "addsi3" pattern, that later gets split to lea in the
9485 case output register differs from input. While this
9486 can be handled by separate addsi pattern for this case
9487 that never results in lea, this seems to be easier and
9488 correct fix for crash to disable this test. */
9490 else if (GET_CODE (disp) != LABEL_REF
9491 && !CONST_INT_P (disp)
9492 && (GET_CODE (disp) != CONST
9493 || !legitimate_constant_p (disp))
9494 && (GET_CODE (disp) != SYMBOL_REF
9495 || !legitimate_constant_p (disp)))
9497 reason = "displacement is not constant";
9500 else if (TARGET_64BIT
9501 && !x86_64_immediate_operand (disp, VOIDmode))
9503 reason = "displacement is out of range";
9508 /* Everything looks valid. */
9515 /* Return a unique alias set for the GOT. */
9517 static alias_set_type
9518 ix86_GOT_alias_set (void)
9520 static alias_set_type set = -1;
9522 set = new_alias_set ();
9526 /* Return a legitimate reference for ORIG (an address) using the
9527 register REG. If REG is 0, a new pseudo is generated.
9529 There are two types of references that must be handled:
9531 1. Global data references must load the address from the GOT, via
9532 the PIC reg. An insn is emitted to do this load, and the reg is
9535 2. Static data references, constant pool addresses, and code labels
9536 compute the address as an offset from the GOT, whose base is in
9537 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9538 differentiate them from global data objects. The returned
9539 address is the PIC reg + an unspec constant.
9541 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9542 reg also appears in the address. */
9545 legitimize_pic_address (rtx orig, rtx reg)
9552 if (TARGET_MACHO && !TARGET_64BIT)
9555 reg = gen_reg_rtx (Pmode);
9556 /* Use the generic Mach-O PIC machinery. */
9557 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9561 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9563 else if (TARGET_64BIT
9564 && ix86_cmodel != CM_SMALL_PIC
9565 && gotoff_operand (addr, Pmode))
9568 /* This symbol may be referenced via a displacement from the PIC
9569 base address (@GOTOFF). */
9571 if (reload_in_progress)
9572 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9573 if (GET_CODE (addr) == CONST)
9574 addr = XEXP (addr, 0);
9575 if (GET_CODE (addr) == PLUS)
9577 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9579 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9582 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9583 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9585 tmpreg = gen_reg_rtx (Pmode);
9588 emit_move_insn (tmpreg, new_rtx);
9592 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9593 tmpreg, 1, OPTAB_DIRECT);
9596 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9598 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9600 /* This symbol may be referenced via a displacement from the PIC
9601 base address (@GOTOFF). */
9603 if (reload_in_progress)
9604 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9605 if (GET_CODE (addr) == CONST)
9606 addr = XEXP (addr, 0);
9607 if (GET_CODE (addr) == PLUS)
9609 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9611 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9614 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9615 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9616 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9620 emit_move_insn (reg, new_rtx);
9624 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9625 /* We can't use @GOTOFF for text labels on VxWorks;
9626 see gotoff_operand. */
9627 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9629 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9631 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9632 return legitimize_dllimport_symbol (addr, true);
9633 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9634 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9635 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9637 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9638 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9642 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9644 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9645 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9646 new_rtx = gen_const_mem (Pmode, new_rtx);
9647 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9650 reg = gen_reg_rtx (Pmode);
9651 /* Use directly gen_movsi, otherwise the address is loaded
9652 into register for CSE. We don't want to CSE this addresses,
9653 instead we CSE addresses from the GOT table, so skip this. */
9654 emit_insn (gen_movsi (reg, new_rtx));
9659 /* This symbol must be referenced via a load from the
9660 Global Offset Table (@GOT). */
9662 if (reload_in_progress)
9663 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9664 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9665 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9667 new_rtx = force_reg (Pmode, new_rtx);
9668 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9669 new_rtx = gen_const_mem (Pmode, new_rtx);
9670 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9673 reg = gen_reg_rtx (Pmode);
9674 emit_move_insn (reg, new_rtx);
9680 if (CONST_INT_P (addr)
9681 && !x86_64_immediate_operand (addr, VOIDmode))
9685 emit_move_insn (reg, addr);
9689 new_rtx = force_reg (Pmode, addr);
9691 else if (GET_CODE (addr) == CONST)
9693 addr = XEXP (addr, 0);
9695 /* We must match stuff we generate before. Assume the only
9696 unspecs that can get here are ours. Not that we could do
9697 anything with them anyway.... */
9698 if (GET_CODE (addr) == UNSPEC
9699 || (GET_CODE (addr) == PLUS
9700 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9702 gcc_assert (GET_CODE (addr) == PLUS);
9704 if (GET_CODE (addr) == PLUS)
9706 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9708 /* Check first to see if this is a constant offset from a @GOTOFF
9709 symbol reference. */
9710 if (gotoff_operand (op0, Pmode)
9711 && CONST_INT_P (op1))
9715 if (reload_in_progress)
9716 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9717 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9719 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9720 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9721 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9725 emit_move_insn (reg, new_rtx);
9731 if (INTVAL (op1) < -16*1024*1024
9732 || INTVAL (op1) >= 16*1024*1024)
9734 if (!x86_64_immediate_operand (op1, Pmode))
9735 op1 = force_reg (Pmode, op1);
9736 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9742 base = legitimize_pic_address (XEXP (addr, 0), reg);
9743 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9744 base == reg ? NULL_RTX : reg);
9746 if (CONST_INT_P (new_rtx))
9747 new_rtx = plus_constant (base, INTVAL (new_rtx));
9750 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9752 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9753 new_rtx = XEXP (new_rtx, 1);
9755 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9763 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9766 get_thread_pointer (int to_reg)
9770 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9774 reg = gen_reg_rtx (Pmode);
9775 insn = gen_rtx_SET (VOIDmode, reg, tp);
9776 insn = emit_insn (insn);
9781 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9782 false if we expect this to be used for a memory address and true if
9783 we expect to load the address into a register. */
9786 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9788 rtx dest, base, off, pic, tp;
9793 case TLS_MODEL_GLOBAL_DYNAMIC:
9794 dest = gen_reg_rtx (Pmode);
9795 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9797 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9799 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9802 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9803 insns = get_insns ();
9806 RTL_CONST_CALL_P (insns) = 1;
9807 emit_libcall_block (insns, dest, rax, x);
9809 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9810 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9812 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9814 if (TARGET_GNU2_TLS)
9816 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9818 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9822 case TLS_MODEL_LOCAL_DYNAMIC:
9823 base = gen_reg_rtx (Pmode);
9824 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9826 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9828 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9831 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9832 insns = get_insns ();
9835 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9836 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9837 RTL_CONST_CALL_P (insns) = 1;
9838 emit_libcall_block (insns, base, rax, note);
9840 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9841 emit_insn (gen_tls_local_dynamic_base_64 (base));
9843 emit_insn (gen_tls_local_dynamic_base_32 (base));
9845 if (TARGET_GNU2_TLS)
9847 rtx x = ix86_tls_module_base ();
9849 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9850 gen_rtx_MINUS (Pmode, x, tp));
9853 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9854 off = gen_rtx_CONST (Pmode, off);
9856 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9858 if (TARGET_GNU2_TLS)
9860 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9862 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9867 case TLS_MODEL_INITIAL_EXEC:
9872 /* The Sun linker took the AMD64 TLS spec literally
9873 and can only handle %rax as destination of the
9874 initial executable code sequence. */
9876 dest = gen_reg_rtx (Pmode);
9877 emit_insn (gen_tls_initial_exec_64_sun (dest, x));
9882 type = UNSPEC_GOTNTPOFF;
9886 if (reload_in_progress)
9887 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9888 pic = pic_offset_table_rtx;
9889 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9891 else if (!TARGET_ANY_GNU_TLS)
9893 pic = gen_reg_rtx (Pmode);
9894 emit_insn (gen_set_got (pic));
9895 type = UNSPEC_GOTTPOFF;
9900 type = UNSPEC_INDNTPOFF;
9903 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9904 off = gen_rtx_CONST (Pmode, off);
9906 off = gen_rtx_PLUS (Pmode, pic, off);
9907 off = gen_const_mem (Pmode, off);
9908 set_mem_alias_set (off, ix86_GOT_alias_set ());
9910 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9912 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9913 off = force_reg (Pmode, off);
9914 return gen_rtx_PLUS (Pmode, base, off);
9918 base = get_thread_pointer (true);
9919 dest = gen_reg_rtx (Pmode);
9920 emit_insn (gen_subsi3 (dest, base, off));
9924 case TLS_MODEL_LOCAL_EXEC:
9925 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9926 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9927 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9928 off = gen_rtx_CONST (Pmode, off);
9930 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9932 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9933 return gen_rtx_PLUS (Pmode, base, off);
9937 base = get_thread_pointer (true);
9938 dest = gen_reg_rtx (Pmode);
9939 emit_insn (gen_subsi3 (dest, base, off));
9950 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9953 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9954 htab_t dllimport_map;
9957 get_dllimport_decl (tree decl)
9959 struct tree_map *h, in;
9963 size_t namelen, prefixlen;
9969 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9971 in.hash = htab_hash_pointer (decl);
9972 in.base.from = decl;
9973 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9974 h = (struct tree_map *) *loc;
9978 *loc = h = GGC_NEW (struct tree_map);
9980 h->base.from = decl;
9981 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9982 DECL_ARTIFICIAL (to) = 1;
9983 DECL_IGNORED_P (to) = 1;
9984 DECL_EXTERNAL (to) = 1;
9985 TREE_READONLY (to) = 1;
9987 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9988 name = targetm.strip_name_encoding (name);
9989 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9990 ? "*__imp_" : "*__imp__";
9991 namelen = strlen (name);
9992 prefixlen = strlen (prefix);
9993 imp_name = (char *) alloca (namelen + prefixlen + 1);
9994 memcpy (imp_name, prefix, prefixlen);
9995 memcpy (imp_name + prefixlen, name, namelen + 1);
9997 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9998 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9999 SET_SYMBOL_REF_DECL (rtl, to);
10000 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10002 rtl = gen_const_mem (Pmode, rtl);
10003 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10005 SET_DECL_RTL (to, rtl);
10006 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10011 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10012 true if we require the result be a register. */
10015 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10020 gcc_assert (SYMBOL_REF_DECL (symbol));
10021 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10023 x = DECL_RTL (imp_decl);
10025 x = force_reg (Pmode, x);
10029 /* Try machine-dependent ways of modifying an illegitimate address
10030 to be legitimate. If we find one, return the new, valid address.
10031 This macro is used in only one place: `memory_address' in explow.c.
10033 OLDX is the address as it was before break_out_memory_refs was called.
10034 In some cases it is useful to look at this to decide what needs to be done.
10036 MODE and WIN are passed so that this macro can use
10037 GO_IF_LEGITIMATE_ADDRESS.
10039 It is always safe for this macro to do nothing. It exists to recognize
10040 opportunities to optimize the output.
10042 For the 80386, we handle X+REG by loading X into a register R and
10043 using R+REG. R will go in a general reg and indexing will be used.
10044 However, if REG is a broken-out memory address or multiplication,
10045 nothing needs to be done because REG can certainly go in a general reg.
10047 When -fpic is used, special handling is needed for symbolic references.
10048 See comments by legitimize_pic_address in i386.c for details. */
10051 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
10056 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10058 return legitimize_tls_address (x, (enum tls_model) log, false);
10059 if (GET_CODE (x) == CONST
10060 && GET_CODE (XEXP (x, 0)) == PLUS
10061 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10062 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10064 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10065 (enum tls_model) log, false);
10066 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10069 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10071 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10072 return legitimize_dllimport_symbol (x, true);
10073 if (GET_CODE (x) == CONST
10074 && GET_CODE (XEXP (x, 0)) == PLUS
10075 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10076 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10078 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10079 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10083 if (flag_pic && SYMBOLIC_CONST (x))
10084 return legitimize_pic_address (x, 0);
10086 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10087 if (GET_CODE (x) == ASHIFT
10088 && CONST_INT_P (XEXP (x, 1))
10089 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10092 log = INTVAL (XEXP (x, 1));
10093 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10094 GEN_INT (1 << log));
10097 if (GET_CODE (x) == PLUS)
10099 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10101 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10102 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10103 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10106 log = INTVAL (XEXP (XEXP (x, 0), 1));
10107 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10108 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10109 GEN_INT (1 << log));
10112 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10113 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10114 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10117 log = INTVAL (XEXP (XEXP (x, 1), 1));
10118 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10119 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10120 GEN_INT (1 << log));
10123 /* Put multiply first if it isn't already. */
10124 if (GET_CODE (XEXP (x, 1)) == MULT)
10126 rtx tmp = XEXP (x, 0);
10127 XEXP (x, 0) = XEXP (x, 1);
10132 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10133 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10134 created by virtual register instantiation, register elimination, and
10135 similar optimizations. */
10136 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10139 x = gen_rtx_PLUS (Pmode,
10140 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10141 XEXP (XEXP (x, 1), 0)),
10142 XEXP (XEXP (x, 1), 1));
10146 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10147 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10148 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10149 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10150 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10151 && CONSTANT_P (XEXP (x, 1)))
10154 rtx other = NULL_RTX;
10156 if (CONST_INT_P (XEXP (x, 1)))
10158 constant = XEXP (x, 1);
10159 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10161 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10163 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10164 other = XEXP (x, 1);
10172 x = gen_rtx_PLUS (Pmode,
10173 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10174 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10175 plus_constant (other, INTVAL (constant)));
10179 if (changed && legitimate_address_p (mode, x, FALSE))
10182 if (GET_CODE (XEXP (x, 0)) == MULT)
10185 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10188 if (GET_CODE (XEXP (x, 1)) == MULT)
10191 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10195 && REG_P (XEXP (x, 1))
10196 && REG_P (XEXP (x, 0)))
10199 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10202 x = legitimize_pic_address (x, 0);
10205 if (changed && legitimate_address_p (mode, x, FALSE))
10208 if (REG_P (XEXP (x, 0)))
10210 rtx temp = gen_reg_rtx (Pmode);
10211 rtx val = force_operand (XEXP (x, 1), temp);
10213 emit_move_insn (temp, val);
10215 XEXP (x, 1) = temp;
10219 else if (REG_P (XEXP (x, 1)))
10221 rtx temp = gen_reg_rtx (Pmode);
10222 rtx val = force_operand (XEXP (x, 0), temp);
10224 emit_move_insn (temp, val);
10226 XEXP (x, 0) = temp;
10234 /* Print an integer constant expression in assembler syntax. Addition
10235 and subtraction are the only arithmetic that may appear in these
10236 expressions. FILE is the stdio stream to write to, X is the rtx, and
10237 CODE is the operand print code from the output string. */
10240 output_pic_addr_const (FILE *file, rtx x, int code)
10244 switch (GET_CODE (x))
10247 gcc_assert (flag_pic);
10252 if (! TARGET_MACHO || TARGET_64BIT)
10253 output_addr_const (file, x);
10256 const char *name = XSTR (x, 0);
10258 /* Mark the decl as referenced so that cgraph will
10259 output the function. */
10260 if (SYMBOL_REF_DECL (x))
10261 mark_decl_referenced (SYMBOL_REF_DECL (x));
10264 if (MACHOPIC_INDIRECT
10265 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10266 name = machopic_indirection_name (x, /*stub_p=*/true);
10268 assemble_name (file, name);
10270 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10271 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10272 fputs ("@PLT", file);
10279 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10280 assemble_name (asm_out_file, buf);
10284 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10288 /* This used to output parentheses around the expression,
10289 but that does not work on the 386 (either ATT or BSD assembler). */
10290 output_pic_addr_const (file, XEXP (x, 0), code);
10294 if (GET_MODE (x) == VOIDmode)
10296 /* We can use %d if the number is <32 bits and positive. */
10297 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10298 fprintf (file, "0x%lx%08lx",
10299 (unsigned long) CONST_DOUBLE_HIGH (x),
10300 (unsigned long) CONST_DOUBLE_LOW (x));
10302 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10305 /* We can't handle floating point constants;
10306 PRINT_OPERAND must handle them. */
10307 output_operand_lossage ("floating constant misused");
10311 /* Some assemblers need integer constants to appear first. */
10312 if (CONST_INT_P (XEXP (x, 0)))
10314 output_pic_addr_const (file, XEXP (x, 0), code);
10316 output_pic_addr_const (file, XEXP (x, 1), code);
10320 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10321 output_pic_addr_const (file, XEXP (x, 1), code);
10323 output_pic_addr_const (file, XEXP (x, 0), code);
10329 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10330 output_pic_addr_const (file, XEXP (x, 0), code);
10332 output_pic_addr_const (file, XEXP (x, 1), code);
10334 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10338 gcc_assert (XVECLEN (x, 0) == 1);
10339 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10340 switch (XINT (x, 1))
10343 fputs ("@GOT", file);
10345 case UNSPEC_GOTOFF:
10346 fputs ("@GOTOFF", file);
10348 case UNSPEC_PLTOFF:
10349 fputs ("@PLTOFF", file);
10351 case UNSPEC_GOTPCREL:
10352 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10353 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10355 case UNSPEC_GOTTPOFF:
10356 /* FIXME: This might be @TPOFF in Sun ld too. */
10357 fputs ("@GOTTPOFF", file);
10360 fputs ("@TPOFF", file);
10362 case UNSPEC_NTPOFF:
10364 fputs ("@TPOFF", file);
10366 fputs ("@NTPOFF", file);
10368 case UNSPEC_DTPOFF:
10369 fputs ("@DTPOFF", file);
10371 case UNSPEC_GOTNTPOFF:
10373 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10374 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10376 fputs ("@GOTNTPOFF", file);
10378 case UNSPEC_INDNTPOFF:
10379 fputs ("@INDNTPOFF", file);
10382 case UNSPEC_MACHOPIC_OFFSET:
10384 machopic_output_function_base_name (file);
10388 output_operand_lossage ("invalid UNSPEC as operand");
10394 output_operand_lossage ("invalid expression as operand");
10398 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10399 We need to emit DTP-relative relocations. */
10401 static void ATTRIBUTE_UNUSED
10402 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10404 fputs (ASM_LONG, file);
10405 output_addr_const (file, x);
10406 fputs ("@DTPOFF", file);
10412 fputs (", 0", file);
10415 gcc_unreachable ();
10419 /* Return true if X is a representation of the PIC register. This copes
10420 with calls from ix86_find_base_term, where the register might have
10421 been replaced by a cselib value. */
10424 ix86_pic_register_p (rtx x)
10426 if (GET_CODE (x) == VALUE && CSELIB_VAL_PTR (x))
10427 return (pic_offset_table_rtx
10428 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10430 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10433 /* In the name of slightly smaller debug output, and to cater to
10434 general assembler lossage, recognize PIC+GOTOFF and turn it back
10435 into a direct symbol reference.
10437 On Darwin, this is necessary to avoid a crash, because Darwin
10438 has a different PIC label for each routine but the DWARF debugging
10439 information is not associated with any particular routine, so it's
10440 necessary to remove references to the PIC label from RTL stored by
10441 the DWARF output code. */
10444 ix86_delegitimize_address (rtx orig_x)
10447 /* reg_addend is NULL or a multiple of some register. */
10448 rtx reg_addend = NULL_RTX;
10449 /* const_addend is NULL or a const_int. */
10450 rtx const_addend = NULL_RTX;
10451 /* This is the result, or NULL. */
10452 rtx result = NULL_RTX;
10459 if (GET_CODE (x) != CONST
10460 || GET_CODE (XEXP (x, 0)) != UNSPEC
10461 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10462 || !MEM_P (orig_x))
10464 return XVECEXP (XEXP (x, 0), 0, 0);
10467 if (GET_CODE (x) != PLUS
10468 || GET_CODE (XEXP (x, 1)) != CONST)
10471 if (ix86_pic_register_p (XEXP (x, 0)))
10472 /* %ebx + GOT/GOTOFF */
10474 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10476 /* %ebx + %reg * scale + GOT/GOTOFF */
10477 reg_addend = XEXP (x, 0);
10478 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10479 reg_addend = XEXP (reg_addend, 1);
10480 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10481 reg_addend = XEXP (reg_addend, 0);
10484 if (!REG_P (reg_addend)
10485 && GET_CODE (reg_addend) != MULT
10486 && GET_CODE (reg_addend) != ASHIFT)
10492 x = XEXP (XEXP (x, 1), 0);
10493 if (GET_CODE (x) == PLUS
10494 && CONST_INT_P (XEXP (x, 1)))
10496 const_addend = XEXP (x, 1);
10500 if (GET_CODE (x) == UNSPEC
10501 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10502 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10503 result = XVECEXP (x, 0, 0);
10505 if (TARGET_MACHO && darwin_local_data_pic (x)
10506 && !MEM_P (orig_x))
10507 result = XVECEXP (x, 0, 0);
10513 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10515 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10519 /* If X is a machine specific address (i.e. a symbol or label being
10520 referenced as a displacement from the GOT implemented using an
10521 UNSPEC), then return the base term. Otherwise return X. */
10524 ix86_find_base_term (rtx x)
10530 if (GET_CODE (x) != CONST)
10532 term = XEXP (x, 0);
10533 if (GET_CODE (term) == PLUS
10534 && (CONST_INT_P (XEXP (term, 1))
10535 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10536 term = XEXP (term, 0);
10537 if (GET_CODE (term) != UNSPEC
10538 || XINT (term, 1) != UNSPEC_GOTPCREL)
10541 return XVECEXP (term, 0, 0);
10544 return ix86_delegitimize_address (x);
10548 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10549 int fp, FILE *file)
10551 const char *suffix;
10553 if (mode == CCFPmode || mode == CCFPUmode)
10555 enum rtx_code second_code, bypass_code;
10556 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10557 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10558 code = ix86_fp_compare_code_to_integer (code);
10562 code = reverse_condition (code);
10613 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10617 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10618 Those same assemblers have the same but opposite lossage on cmov. */
10619 if (mode == CCmode)
10620 suffix = fp ? "nbe" : "a";
10621 else if (mode == CCCmode)
10624 gcc_unreachable ();
10640 gcc_unreachable ();
10644 gcc_assert (mode == CCmode || mode == CCCmode);
10661 gcc_unreachable ();
10665 /* ??? As above. */
10666 gcc_assert (mode == CCmode || mode == CCCmode);
10667 suffix = fp ? "nb" : "ae";
10670 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10674 /* ??? As above. */
10675 if (mode == CCmode)
10677 else if (mode == CCCmode)
10678 suffix = fp ? "nb" : "ae";
10680 gcc_unreachable ();
10683 suffix = fp ? "u" : "p";
10686 suffix = fp ? "nu" : "np";
10689 gcc_unreachable ();
10691 fputs (suffix, file);
10694 /* Print the name of register X to FILE based on its machine mode and number.
10695 If CODE is 'w', pretend the mode is HImode.
10696 If CODE is 'b', pretend the mode is QImode.
10697 If CODE is 'k', pretend the mode is SImode.
10698 If CODE is 'q', pretend the mode is DImode.
10699 If CODE is 'x', pretend the mode is V4SFmode.
10700 If CODE is 't', pretend the mode is V8SFmode.
10701 If CODE is 'h', pretend the reg is the 'high' byte register.
10702 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10703 If CODE is 'd', duplicate the operand for AVX instruction.
10707 print_reg (rtx x, int code, FILE *file)
10710 bool duplicated = code == 'd' && TARGET_AVX;
10712 gcc_assert (x == pc_rtx
10713 || (REGNO (x) != ARG_POINTER_REGNUM
10714 && REGNO (x) != FRAME_POINTER_REGNUM
10715 && REGNO (x) != FLAGS_REG
10716 && REGNO (x) != FPSR_REG
10717 && REGNO (x) != FPCR_REG));
10719 if (ASSEMBLER_DIALECT == ASM_ATT)
10724 gcc_assert (TARGET_64BIT);
10725 fputs ("rip", file);
10729 if (code == 'w' || MMX_REG_P (x))
10731 else if (code == 'b')
10733 else if (code == 'k')
10735 else if (code == 'q')
10737 else if (code == 'y')
10739 else if (code == 'h')
10741 else if (code == 'x')
10743 else if (code == 't')
10746 code = GET_MODE_SIZE (GET_MODE (x));
10748 /* Irritatingly, AMD extended registers use different naming convention
10749 from the normal registers. */
10750 if (REX_INT_REG_P (x))
10752 gcc_assert (TARGET_64BIT);
10756 error ("extended registers have no high halves");
10759 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10762 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10765 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10768 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10771 error ("unsupported operand size for extended register");
10781 if (STACK_TOP_P (x))
10790 if (! ANY_FP_REG_P (x))
10791 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10796 reg = hi_reg_name[REGNO (x)];
10799 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10801 reg = qi_reg_name[REGNO (x)];
10804 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10806 reg = qi_high_reg_name[REGNO (x)];
10811 gcc_assert (!duplicated);
10813 fputs (hi_reg_name[REGNO (x)] + 1, file);
10818 gcc_unreachable ();
10824 if (ASSEMBLER_DIALECT == ASM_ATT)
10825 fprintf (file, ", %%%s", reg);
10827 fprintf (file, ", %s", reg);
10831 /* Locate some local-dynamic symbol still in use by this function
10832 so that we can print its name in some tls_local_dynamic_base
10836 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10840 if (GET_CODE (x) == SYMBOL_REF
10841 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10843 cfun->machine->some_ld_name = XSTR (x, 0);
10850 static const char *
10851 get_some_local_dynamic_name (void)
10855 if (cfun->machine->some_ld_name)
10856 return cfun->machine->some_ld_name;
10858 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10860 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10861 return cfun->machine->some_ld_name;
10863 gcc_unreachable ();
10866 /* Meaning of CODE:
10867 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10868 C -- print opcode suffix for set/cmov insn.
10869 c -- like C, but print reversed condition
10870 F,f -- likewise, but for floating-point.
10871 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10873 R -- print the prefix for register names.
10874 z -- print the opcode suffix for the size of the current operand.
10875 * -- print a star (in certain assembler syntax)
10876 A -- print an absolute memory reference.
10877 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10878 s -- print a shift double count, followed by the assemblers argument
10880 b -- print the QImode name of the register for the indicated operand.
10881 %b0 would print %al if operands[0] is reg 0.
10882 w -- likewise, print the HImode name of the register.
10883 k -- likewise, print the SImode name of the register.
10884 q -- likewise, print the DImode name of the register.
10885 x -- likewise, print the V4SFmode name of the register.
10886 t -- likewise, print the V8SFmode name of the register.
10887 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10888 y -- print "st(0)" instead of "st" as a register.
10889 d -- print duplicated register operand for AVX instruction.
10890 D -- print condition for SSE cmp instruction.
10891 P -- if PIC, print an @PLT suffix.
10892 X -- don't print any sort of PIC '@' suffix for a symbol.
10893 & -- print some in-use local-dynamic symbol name.
10894 H -- print a memory address offset by 8; used for sse high-parts
10895 Y -- print condition for SSE5 com* instruction.
10896 + -- print a branch hint as 'cs' or 'ds' prefix
10897 ; -- print a semicolon (after prefixes due to bug in older gas).
10901 print_operand (FILE *file, rtx x, int code)
10908 if (ASSEMBLER_DIALECT == ASM_ATT)
10913 assemble_name (file, get_some_local_dynamic_name ());
10917 switch (ASSEMBLER_DIALECT)
10924 /* Intel syntax. For absolute addresses, registers should not
10925 be surrounded by braces. */
10929 PRINT_OPERAND (file, x, 0);
10936 gcc_unreachable ();
10939 PRINT_OPERAND (file, x, 0);
10944 if (ASSEMBLER_DIALECT == ASM_ATT)
10949 if (ASSEMBLER_DIALECT == ASM_ATT)
10954 if (ASSEMBLER_DIALECT == ASM_ATT)
10959 if (ASSEMBLER_DIALECT == ASM_ATT)
10964 if (ASSEMBLER_DIALECT == ASM_ATT)
10969 if (ASSEMBLER_DIALECT == ASM_ATT)
10974 /* 387 opcodes don't get size suffixes if the operands are
10976 if (STACK_REG_P (x))
10979 /* Likewise if using Intel opcodes. */
10980 if (ASSEMBLER_DIALECT == ASM_INTEL)
10983 /* This is the size of op from size of operand. */
10984 switch (GET_MODE_SIZE (GET_MODE (x)))
10993 #ifdef HAVE_GAS_FILDS_FISTS
11003 if (GET_MODE (x) == SFmode)
11018 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11022 #ifdef GAS_MNEMONICS
11037 gcc_unreachable ();
11054 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11056 PRINT_OPERAND (file, x, 0);
11057 fputs (", ", file);
11062 /* Little bit of braindamage here. The SSE compare instructions
11063 does use completely different names for the comparisons that the
11064 fp conditional moves. */
11067 switch (GET_CODE (x))
11070 fputs ("eq", file);
11073 fputs ("eq_us", file);
11076 fputs ("lt", file);
11079 fputs ("nge", file);
11082 fputs ("le", file);
11085 fputs ("ngt", file);
11088 fputs ("unord", file);
11091 fputs ("neq", file);
11094 fputs ("neq_oq", file);
11097 fputs ("ge", file);
11100 fputs ("nlt", file);
11103 fputs ("gt", file);
11106 fputs ("nle", file);
11109 fputs ("ord", file);
11112 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11118 switch (GET_CODE (x))
11122 fputs ("eq", file);
11126 fputs ("lt", file);
11130 fputs ("le", file);
11133 fputs ("unord", file);
11137 fputs ("neq", file);
11141 fputs ("nlt", file);
11145 fputs ("nle", file);
11148 fputs ("ord", file);
11151 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11157 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11158 if (ASSEMBLER_DIALECT == ASM_ATT)
11160 switch (GET_MODE (x))
11162 case HImode: putc ('w', file); break;
11164 case SFmode: putc ('l', file); break;
11166 case DFmode: putc ('q', file); break;
11167 default: gcc_unreachable ();
11174 if (!COMPARISON_P (x))
11176 output_operand_lossage ("operand is neither a constant nor a "
11177 "condition code, invalid operand code "
11181 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11184 if (!COMPARISON_P (x))
11186 output_operand_lossage ("operand is neither a constant nor a "
11187 "condition code, invalid operand code "
11191 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11192 if (ASSEMBLER_DIALECT == ASM_ATT)
11195 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11198 /* Like above, but reverse condition */
11200 /* Check to see if argument to %c is really a constant
11201 and not a condition code which needs to be reversed. */
11202 if (!COMPARISON_P (x))
11204 output_operand_lossage ("operand is neither a constant nor a "
11205 "condition code, invalid operand "
11209 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11212 if (!COMPARISON_P (x))
11214 output_operand_lossage ("operand is neither a constant nor a "
11215 "condition code, invalid operand "
11219 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11220 if (ASSEMBLER_DIALECT == ASM_ATT)
11223 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11227 /* It doesn't actually matter what mode we use here, as we're
11228 only going to use this for printing. */
11229 x = adjust_address_nv (x, DImode, 8);
11237 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11240 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11243 int pred_val = INTVAL (XEXP (x, 0));
11245 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11246 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11248 int taken = pred_val > REG_BR_PROB_BASE / 2;
11249 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11251 /* Emit hints only in the case default branch prediction
11252 heuristics would fail. */
11253 if (taken != cputaken)
11255 /* We use 3e (DS) prefix for taken branches and
11256 2e (CS) prefix for not taken branches. */
11258 fputs ("ds ; ", file);
11260 fputs ("cs ; ", file);
11268 switch (GET_CODE (x))
11271 fputs ("neq", file);
11274 fputs ("eq", file);
11278 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11282 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11286 fputs ("le", file);
11290 fputs ("lt", file);
11293 fputs ("unord", file);
11296 fputs ("ord", file);
11299 fputs ("ueq", file);
11302 fputs ("nlt", file);
11305 fputs ("nle", file);
11308 fputs ("ule", file);
11311 fputs ("ult", file);
11314 fputs ("une", file);
11317 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11323 #if TARGET_MACHO || !HAVE_AS_IX86_REP_LOCK_PREFIX
11329 output_operand_lossage ("invalid operand code '%c'", code);
11334 print_reg (x, code, file);
11336 else if (MEM_P (x))
11338 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11339 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11340 && GET_MODE (x) != BLKmode)
11343 switch (GET_MODE_SIZE (GET_MODE (x)))
11345 case 1: size = "BYTE"; break;
11346 case 2: size = "WORD"; break;
11347 case 4: size = "DWORD"; break;
11348 case 8: size = "QWORD"; break;
11349 case 12: size = "TBYTE"; break;
11351 if (GET_MODE (x) == XFmode)
11356 case 32: size = "YMMWORD"; break;
11358 gcc_unreachable ();
11361 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11364 else if (code == 'w')
11366 else if (code == 'k')
11369 fputs (size, file);
11370 fputs (" PTR ", file);
11374 /* Avoid (%rip) for call operands. */
11375 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11376 && !CONST_INT_P (x))
11377 output_addr_const (file, x);
11378 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11379 output_operand_lossage ("invalid constraints for operand");
11381 output_address (x);
11384 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11389 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11390 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11392 if (ASSEMBLER_DIALECT == ASM_ATT)
11394 fprintf (file, "0x%08lx", (long unsigned int) l);
11397 /* These float cases don't actually occur as immediate operands. */
11398 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11402 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11403 fprintf (file, "%s", dstr);
11406 else if (GET_CODE (x) == CONST_DOUBLE
11407 && GET_MODE (x) == XFmode)
11411 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11412 fprintf (file, "%s", dstr);
11417 /* We have patterns that allow zero sets of memory, for instance.
11418 In 64-bit mode, we should probably support all 8-byte vectors,
11419 since we can in fact encode that into an immediate. */
11420 if (GET_CODE (x) == CONST_VECTOR)
11422 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11428 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11430 if (ASSEMBLER_DIALECT == ASM_ATT)
11433 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11434 || GET_CODE (x) == LABEL_REF)
11436 if (ASSEMBLER_DIALECT == ASM_ATT)
11439 fputs ("OFFSET FLAT:", file);
11442 if (CONST_INT_P (x))
11443 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11445 output_pic_addr_const (file, x, code);
11447 output_addr_const (file, x);
11451 /* Print a memory operand whose address is ADDR. */
11454 print_operand_address (FILE *file, rtx addr)
11456 struct ix86_address parts;
11457 rtx base, index, disp;
11459 int ok = ix86_decompose_address (addr, &parts);
11464 index = parts.index;
11466 scale = parts.scale;
11474 if (ASSEMBLER_DIALECT == ASM_ATT)
11476 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11479 gcc_unreachable ();
11482 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11483 if (TARGET_64BIT && !base && !index)
11487 if (GET_CODE (disp) == CONST
11488 && GET_CODE (XEXP (disp, 0)) == PLUS
11489 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11490 symbol = XEXP (XEXP (disp, 0), 0);
11492 if (GET_CODE (symbol) == LABEL_REF
11493 || (GET_CODE (symbol) == SYMBOL_REF
11494 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11497 if (!base && !index)
11499 /* Displacement only requires special attention. */
11501 if (CONST_INT_P (disp))
11503 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11504 fputs ("ds:", file);
11505 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11508 output_pic_addr_const (file, disp, 0);
11510 output_addr_const (file, disp);
11514 if (ASSEMBLER_DIALECT == ASM_ATT)
11519 output_pic_addr_const (file, disp, 0);
11520 else if (GET_CODE (disp) == LABEL_REF)
11521 output_asm_label (disp);
11523 output_addr_const (file, disp);
11528 print_reg (base, 0, file);
11532 print_reg (index, 0, file);
11534 fprintf (file, ",%d", scale);
11540 rtx offset = NULL_RTX;
11544 /* Pull out the offset of a symbol; print any symbol itself. */
11545 if (GET_CODE (disp) == CONST
11546 && GET_CODE (XEXP (disp, 0)) == PLUS
11547 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11549 offset = XEXP (XEXP (disp, 0), 1);
11550 disp = gen_rtx_CONST (VOIDmode,
11551 XEXP (XEXP (disp, 0), 0));
11555 output_pic_addr_const (file, disp, 0);
11556 else if (GET_CODE (disp) == LABEL_REF)
11557 output_asm_label (disp);
11558 else if (CONST_INT_P (disp))
11561 output_addr_const (file, disp);
11567 print_reg (base, 0, file);
11570 if (INTVAL (offset) >= 0)
11572 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11576 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11583 print_reg (index, 0, file);
11585 fprintf (file, "*%d", scale);
11593 output_addr_const_extra (FILE *file, rtx x)
11597 if (GET_CODE (x) != UNSPEC)
11600 op = XVECEXP (x, 0, 0);
11601 switch (XINT (x, 1))
11603 case UNSPEC_GOTTPOFF:
11604 output_addr_const (file, op);
11605 /* FIXME: This might be @TPOFF in Sun ld. */
11606 fputs ("@GOTTPOFF", file);
11609 output_addr_const (file, op);
11610 fputs ("@TPOFF", file);
11612 case UNSPEC_NTPOFF:
11613 output_addr_const (file, op);
11615 fputs ("@TPOFF", file);
11617 fputs ("@NTPOFF", file);
11619 case UNSPEC_DTPOFF:
11620 output_addr_const (file, op);
11621 fputs ("@DTPOFF", file);
11623 case UNSPEC_GOTNTPOFF:
11624 output_addr_const (file, op);
11626 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11627 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11629 fputs ("@GOTNTPOFF", file);
11631 case UNSPEC_INDNTPOFF:
11632 output_addr_const (file, op);
11633 fputs ("@INDNTPOFF", file);
11636 case UNSPEC_MACHOPIC_OFFSET:
11637 output_addr_const (file, op);
11639 machopic_output_function_base_name (file);
11650 /* Split one or more DImode RTL references into pairs of SImode
11651 references. The RTL can be REG, offsettable MEM, integer constant, or
11652 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11653 split and "num" is its length. lo_half and hi_half are output arrays
11654 that parallel "operands". */
11657 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11661 rtx op = operands[num];
11663 /* simplify_subreg refuse to split volatile memory addresses,
11664 but we still have to handle it. */
11667 lo_half[num] = adjust_address (op, SImode, 0);
11668 hi_half[num] = adjust_address (op, SImode, 4);
11672 lo_half[num] = simplify_gen_subreg (SImode, op,
11673 GET_MODE (op) == VOIDmode
11674 ? DImode : GET_MODE (op), 0);
11675 hi_half[num] = simplify_gen_subreg (SImode, op,
11676 GET_MODE (op) == VOIDmode
11677 ? DImode : GET_MODE (op), 4);
11681 /* Split one or more TImode RTL references into pairs of DImode
11682 references. The RTL can be REG, offsettable MEM, integer constant, or
11683 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11684 split and "num" is its length. lo_half and hi_half are output arrays
11685 that parallel "operands". */
11688 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11692 rtx op = operands[num];
11694 /* simplify_subreg refuse to split volatile memory addresses, but we
11695 still have to handle it. */
11698 lo_half[num] = adjust_address (op, DImode, 0);
11699 hi_half[num] = adjust_address (op, DImode, 8);
11703 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11704 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11709 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11710 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11711 is the expression of the binary operation. The output may either be
11712 emitted here, or returned to the caller, like all output_* functions.
11714 There is no guarantee that the operands are the same mode, as they
11715 might be within FLOAT or FLOAT_EXTEND expressions. */
11717 #ifndef SYSV386_COMPAT
11718 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11719 wants to fix the assemblers because that causes incompatibility
11720 with gcc. No-one wants to fix gcc because that causes
11721 incompatibility with assemblers... You can use the option of
11722 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11723 #define SYSV386_COMPAT 1
11727 output_387_binary_op (rtx insn, rtx *operands)
11729 static char buf[40];
11732 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11734 #ifdef ENABLE_CHECKING
11735 /* Even if we do not want to check the inputs, this documents input
11736 constraints. Which helps in understanding the following code. */
11737 if (STACK_REG_P (operands[0])
11738 && ((REG_P (operands[1])
11739 && REGNO (operands[0]) == REGNO (operands[1])
11740 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11741 || (REG_P (operands[2])
11742 && REGNO (operands[0]) == REGNO (operands[2])
11743 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11744 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11747 gcc_assert (is_sse);
11750 switch (GET_CODE (operands[3]))
11753 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11754 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11762 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11763 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11771 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11772 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11780 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11781 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11789 gcc_unreachable ();
11796 strcpy (buf, ssep);
11797 if (GET_MODE (operands[0]) == SFmode)
11798 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11800 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11804 strcpy (buf, ssep + 1);
11805 if (GET_MODE (operands[0]) == SFmode)
11806 strcat (buf, "ss\t{%2, %0|%0, %2}");
11808 strcat (buf, "sd\t{%2, %0|%0, %2}");
11814 switch (GET_CODE (operands[3]))
11818 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11820 rtx temp = operands[2];
11821 operands[2] = operands[1];
11822 operands[1] = temp;
11825 /* know operands[0] == operands[1]. */
11827 if (MEM_P (operands[2]))
11833 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11835 if (STACK_TOP_P (operands[0]))
11836 /* How is it that we are storing to a dead operand[2]?
11837 Well, presumably operands[1] is dead too. We can't
11838 store the result to st(0) as st(0) gets popped on this
11839 instruction. Instead store to operands[2] (which I
11840 think has to be st(1)). st(1) will be popped later.
11841 gcc <= 2.8.1 didn't have this check and generated
11842 assembly code that the Unixware assembler rejected. */
11843 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11845 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11849 if (STACK_TOP_P (operands[0]))
11850 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11852 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11857 if (MEM_P (operands[1]))
11863 if (MEM_P (operands[2]))
11869 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11872 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11873 derived assemblers, confusingly reverse the direction of
11874 the operation for fsub{r} and fdiv{r} when the
11875 destination register is not st(0). The Intel assembler
11876 doesn't have this brain damage. Read !SYSV386_COMPAT to
11877 figure out what the hardware really does. */
11878 if (STACK_TOP_P (operands[0]))
11879 p = "{p\t%0, %2|rp\t%2, %0}";
11881 p = "{rp\t%2, %0|p\t%0, %2}";
11883 if (STACK_TOP_P (operands[0]))
11884 /* As above for fmul/fadd, we can't store to st(0). */
11885 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11887 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11892 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11895 if (STACK_TOP_P (operands[0]))
11896 p = "{rp\t%0, %1|p\t%1, %0}";
11898 p = "{p\t%1, %0|rp\t%0, %1}";
11900 if (STACK_TOP_P (operands[0]))
11901 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11903 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11908 if (STACK_TOP_P (operands[0]))
11910 if (STACK_TOP_P (operands[1]))
11911 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11913 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11916 else if (STACK_TOP_P (operands[1]))
11919 p = "{\t%1, %0|r\t%0, %1}";
11921 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11927 p = "{r\t%2, %0|\t%0, %2}";
11929 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11935 gcc_unreachable ();
11942 /* Return needed mode for entity in optimize_mode_switching pass. */
11945 ix86_mode_needed (int entity, rtx insn)
11947 enum attr_i387_cw mode;
11949 /* The mode UNINITIALIZED is used to store control word after a
11950 function call or ASM pattern. The mode ANY specify that function
11951 has no requirements on the control word and make no changes in the
11952 bits we are interested in. */
11955 || (NONJUMP_INSN_P (insn)
11956 && (asm_noperands (PATTERN (insn)) >= 0
11957 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11958 return I387_CW_UNINITIALIZED;
11960 if (recog_memoized (insn) < 0)
11961 return I387_CW_ANY;
11963 mode = get_attr_i387_cw (insn);
11968 if (mode == I387_CW_TRUNC)
11973 if (mode == I387_CW_FLOOR)
11978 if (mode == I387_CW_CEIL)
11983 if (mode == I387_CW_MASK_PM)
11988 gcc_unreachable ();
11991 return I387_CW_ANY;
11994 /* Output code to initialize control word copies used by trunc?f?i and
11995 rounding patterns. CURRENT_MODE is set to current control word,
11996 while NEW_MODE is set to new control word. */
11999 emit_i387_cw_initialization (int mode)
12001 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12004 enum ix86_stack_slot slot;
12006 rtx reg = gen_reg_rtx (HImode);
12008 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12009 emit_move_insn (reg, copy_rtx (stored_mode));
12011 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12012 || optimize_function_for_size_p (cfun))
12016 case I387_CW_TRUNC:
12017 /* round toward zero (truncate) */
12018 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12019 slot = SLOT_CW_TRUNC;
12022 case I387_CW_FLOOR:
12023 /* round down toward -oo */
12024 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12025 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12026 slot = SLOT_CW_FLOOR;
12030 /* round up toward +oo */
12031 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12032 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12033 slot = SLOT_CW_CEIL;
12036 case I387_CW_MASK_PM:
12037 /* mask precision exception for nearbyint() */
12038 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12039 slot = SLOT_CW_MASK_PM;
12043 gcc_unreachable ();
12050 case I387_CW_TRUNC:
12051 /* round toward zero (truncate) */
12052 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12053 slot = SLOT_CW_TRUNC;
12056 case I387_CW_FLOOR:
12057 /* round down toward -oo */
12058 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12059 slot = SLOT_CW_FLOOR;
12063 /* round up toward +oo */
12064 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12065 slot = SLOT_CW_CEIL;
12068 case I387_CW_MASK_PM:
12069 /* mask precision exception for nearbyint() */
12070 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12071 slot = SLOT_CW_MASK_PM;
12075 gcc_unreachable ();
12079 gcc_assert (slot < MAX_386_STACK_LOCALS);
12081 new_mode = assign_386_stack_local (HImode, slot);
12082 emit_move_insn (new_mode, reg);
12085 /* Output code for INSN to convert a float to a signed int. OPERANDS
12086 are the insn operands. The output may be [HSD]Imode and the input
12087 operand may be [SDX]Fmode. */
12090 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12092 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12093 int dimode_p = GET_MODE (operands[0]) == DImode;
12094 int round_mode = get_attr_i387_cw (insn);
12096 /* Jump through a hoop or two for DImode, since the hardware has no
12097 non-popping instruction. We used to do this a different way, but
12098 that was somewhat fragile and broke with post-reload splitters. */
12099 if ((dimode_p || fisttp) && !stack_top_dies)
12100 output_asm_insn ("fld\t%y1", operands);
12102 gcc_assert (STACK_TOP_P (operands[1]));
12103 gcc_assert (MEM_P (operands[0]));
12104 gcc_assert (GET_MODE (operands[1]) != TFmode);
12107 output_asm_insn ("fisttp%z0\t%0", operands);
12110 if (round_mode != I387_CW_ANY)
12111 output_asm_insn ("fldcw\t%3", operands);
12112 if (stack_top_dies || dimode_p)
12113 output_asm_insn ("fistp%z0\t%0", operands);
12115 output_asm_insn ("fist%z0\t%0", operands);
12116 if (round_mode != I387_CW_ANY)
12117 output_asm_insn ("fldcw\t%2", operands);
12123 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12124 have the values zero or one, indicates the ffreep insn's operand
12125 from the OPERANDS array. */
12127 static const char *
12128 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12130 if (TARGET_USE_FFREEP)
12131 #ifdef HAVE_AS_IX86_FFREEP
12132 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12135 static char retval[32];
12136 int regno = REGNO (operands[opno]);
12138 gcc_assert (FP_REGNO_P (regno));
12140 regno -= FIRST_STACK_REG;
12142 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12147 return opno ? "fstp\t%y1" : "fstp\t%y0";
12151 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12152 should be used. UNORDERED_P is true when fucom should be used. */
12155 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12157 int stack_top_dies;
12158 rtx cmp_op0, cmp_op1;
12159 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12163 cmp_op0 = operands[0];
12164 cmp_op1 = operands[1];
12168 cmp_op0 = operands[1];
12169 cmp_op1 = operands[2];
12174 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12175 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12176 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12177 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12179 if (GET_MODE (operands[0]) == SFmode)
12181 return &ucomiss[TARGET_AVX ? 0 : 1];
12183 return &comiss[TARGET_AVX ? 0 : 1];
12186 return &ucomisd[TARGET_AVX ? 0 : 1];
12188 return &comisd[TARGET_AVX ? 0 : 1];
12191 gcc_assert (STACK_TOP_P (cmp_op0));
12193 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12195 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12197 if (stack_top_dies)
12199 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12200 return output_387_ffreep (operands, 1);
12203 return "ftst\n\tfnstsw\t%0";
12206 if (STACK_REG_P (cmp_op1)
12208 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12209 && REGNO (cmp_op1) != FIRST_STACK_REG)
12211 /* If both the top of the 387 stack dies, and the other operand
12212 is also a stack register that dies, then this must be a
12213 `fcompp' float compare */
12217 /* There is no double popping fcomi variant. Fortunately,
12218 eflags is immune from the fstp's cc clobbering. */
12220 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12222 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12223 return output_387_ffreep (operands, 0);
12228 return "fucompp\n\tfnstsw\t%0";
12230 return "fcompp\n\tfnstsw\t%0";
12235 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12237 static const char * const alt[16] =
12239 "fcom%z2\t%y2\n\tfnstsw\t%0",
12240 "fcomp%z2\t%y2\n\tfnstsw\t%0",
12241 "fucom%z2\t%y2\n\tfnstsw\t%0",
12242 "fucomp%z2\t%y2\n\tfnstsw\t%0",
12244 "ficom%z2\t%y2\n\tfnstsw\t%0",
12245 "ficomp%z2\t%y2\n\tfnstsw\t%0",
12249 "fcomi\t{%y1, %0|%0, %y1}",
12250 "fcomip\t{%y1, %0|%0, %y1}",
12251 "fucomi\t{%y1, %0|%0, %y1}",
12252 "fucomip\t{%y1, %0|%0, %y1}",
12263 mask = eflags_p << 3;
12264 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12265 mask |= unordered_p << 1;
12266 mask |= stack_top_dies;
12268 gcc_assert (mask < 16);
12277 ix86_output_addr_vec_elt (FILE *file, int value)
12279 const char *directive = ASM_LONG;
12283 directive = ASM_QUAD;
12285 gcc_assert (!TARGET_64BIT);
12288 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12292 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12294 const char *directive = ASM_LONG;
12297 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12298 directive = ASM_QUAD;
12300 gcc_assert (!TARGET_64BIT);
12302 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12303 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12304 fprintf (file, "%s%s%d-%s%d\n",
12305 directive, LPREFIX, value, LPREFIX, rel);
12306 else if (HAVE_AS_GOTOFF_IN_DATA)
12307 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12309 else if (TARGET_MACHO)
12311 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12312 machopic_output_function_base_name (file);
12313 fprintf(file, "\n");
12317 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12318 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12321 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12325 ix86_expand_clear (rtx dest)
12329 /* We play register width games, which are only valid after reload. */
12330 gcc_assert (reload_completed);
12332 /* Avoid HImode and its attendant prefix byte. */
12333 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12334 dest = gen_rtx_REG (SImode, REGNO (dest));
12335 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12337 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12338 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12340 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12341 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12347 /* X is an unchanging MEM. If it is a constant pool reference, return
12348 the constant pool rtx, else NULL. */
12351 maybe_get_pool_constant (rtx x)
12353 x = ix86_delegitimize_address (XEXP (x, 0));
12355 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12356 return get_pool_constant (x);
12362 ix86_expand_move (enum machine_mode mode, rtx operands[])
12365 enum tls_model model;
12370 if (GET_CODE (op1) == SYMBOL_REF)
12372 model = SYMBOL_REF_TLS_MODEL (op1);
12375 op1 = legitimize_tls_address (op1, model, true);
12376 op1 = force_operand (op1, op0);
12380 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12381 && SYMBOL_REF_DLLIMPORT_P (op1))
12382 op1 = legitimize_dllimport_symbol (op1, false);
12384 else if (GET_CODE (op1) == CONST
12385 && GET_CODE (XEXP (op1, 0)) == PLUS
12386 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12388 rtx addend = XEXP (XEXP (op1, 0), 1);
12389 rtx symbol = XEXP (XEXP (op1, 0), 0);
12392 model = SYMBOL_REF_TLS_MODEL (symbol);
12394 tmp = legitimize_tls_address (symbol, model, true);
12395 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12396 && SYMBOL_REF_DLLIMPORT_P (symbol))
12397 tmp = legitimize_dllimport_symbol (symbol, true);
12401 tmp = force_operand (tmp, NULL);
12402 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12403 op0, 1, OPTAB_DIRECT);
12409 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12411 if (TARGET_MACHO && !TARGET_64BIT)
12416 rtx temp = ((reload_in_progress
12417 || ((op0 && REG_P (op0))
12419 ? op0 : gen_reg_rtx (Pmode));
12420 op1 = machopic_indirect_data_reference (op1, temp);
12421 op1 = machopic_legitimize_pic_address (op1, mode,
12422 temp == op1 ? 0 : temp);
12424 else if (MACHOPIC_INDIRECT)
12425 op1 = machopic_indirect_data_reference (op1, 0);
12433 op1 = force_reg (Pmode, op1);
12434 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12436 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12437 op1 = legitimize_pic_address (op1, reg);
12446 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12447 || !push_operand (op0, mode))
12449 op1 = force_reg (mode, op1);
12451 if (push_operand (op0, mode)
12452 && ! general_no_elim_operand (op1, mode))
12453 op1 = copy_to_mode_reg (mode, op1);
12455 /* Force large constants in 64bit compilation into register
12456 to get them CSEed. */
12457 if (can_create_pseudo_p ()
12458 && (mode == DImode) && TARGET_64BIT
12459 && immediate_operand (op1, mode)
12460 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12461 && !register_operand (op0, mode)
12463 op1 = copy_to_mode_reg (mode, op1);
12465 if (can_create_pseudo_p ()
12466 && FLOAT_MODE_P (mode)
12467 && GET_CODE (op1) == CONST_DOUBLE)
12469 /* If we are loading a floating point constant to a register,
12470 force the value to memory now, since we'll get better code
12471 out the back end. */
12473 op1 = validize_mem (force_const_mem (mode, op1));
12474 if (!register_operand (op0, mode))
12476 rtx temp = gen_reg_rtx (mode);
12477 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12478 emit_move_insn (op0, temp);
12484 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12488 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12490 rtx op0 = operands[0], op1 = operands[1];
12491 unsigned int align = GET_MODE_ALIGNMENT (mode);
12493 /* Force constants other than zero into memory. We do not know how
12494 the instructions used to build constants modify the upper 64 bits
12495 of the register, once we have that information we may be able
12496 to handle some of them more efficiently. */
12497 if (can_create_pseudo_p ()
12498 && register_operand (op0, mode)
12499 && (CONSTANT_P (op1)
12500 || (GET_CODE (op1) == SUBREG
12501 && CONSTANT_P (SUBREG_REG (op1))))
12502 && standard_sse_constant_p (op1) <= 0)
12503 op1 = validize_mem (force_const_mem (mode, op1));
12505 /* We need to check memory alignment for SSE mode since attribute
12506 can make operands unaligned. */
12507 if (can_create_pseudo_p ()
12508 && SSE_REG_MODE_P (mode)
12509 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12510 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12514 /* ix86_expand_vector_move_misalign() does not like constants ... */
12515 if (CONSTANT_P (op1)
12516 || (GET_CODE (op1) == SUBREG
12517 && CONSTANT_P (SUBREG_REG (op1))))
12518 op1 = validize_mem (force_const_mem (mode, op1));
12520 /* ... nor both arguments in memory. */
12521 if (!register_operand (op0, mode)
12522 && !register_operand (op1, mode))
12523 op1 = force_reg (mode, op1);
12525 tmp[0] = op0; tmp[1] = op1;
12526 ix86_expand_vector_move_misalign (mode, tmp);
12530 /* Make operand1 a register if it isn't already. */
12531 if (can_create_pseudo_p ()
12532 && !register_operand (op0, mode)
12533 && !register_operand (op1, mode))
12535 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12539 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12542 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12543 straight to ix86_expand_vector_move. */
12544 /* Code generation for scalar reg-reg moves of single and double precision data:
12545 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12549 if (x86_sse_partial_reg_dependency == true)
12554 Code generation for scalar loads of double precision data:
12555 if (x86_sse_split_regs == true)
12556 movlpd mem, reg (gas syntax)
12560 Code generation for unaligned packed loads of single precision data
12561 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12562 if (x86_sse_unaligned_move_optimal)
12565 if (x86_sse_partial_reg_dependency == true)
12577 Code generation for unaligned packed loads of double precision data
12578 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12579 if (x86_sse_unaligned_move_optimal)
12582 if (x86_sse_split_regs == true)
12595 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12604 switch (GET_MODE_CLASS (mode))
12606 case MODE_VECTOR_INT:
12608 switch (GET_MODE_SIZE (mode))
12611 op0 = gen_lowpart (V16QImode, op0);
12612 op1 = gen_lowpart (V16QImode, op1);
12613 emit_insn (gen_avx_movdqu (op0, op1));
12616 op0 = gen_lowpart (V32QImode, op0);
12617 op1 = gen_lowpart (V32QImode, op1);
12618 emit_insn (gen_avx_movdqu256 (op0, op1));
12621 gcc_unreachable ();
12624 case MODE_VECTOR_FLOAT:
12625 op0 = gen_lowpart (mode, op0);
12626 op1 = gen_lowpart (mode, op1);
12631 emit_insn (gen_avx_movups (op0, op1));
12634 emit_insn (gen_avx_movups256 (op0, op1));
12637 emit_insn (gen_avx_movupd (op0, op1));
12640 emit_insn (gen_avx_movupd256 (op0, op1));
12643 gcc_unreachable ();
12648 gcc_unreachable ();
12656 /* If we're optimizing for size, movups is the smallest. */
12657 if (optimize_insn_for_size_p ())
12659 op0 = gen_lowpart (V4SFmode, op0);
12660 op1 = gen_lowpart (V4SFmode, op1);
12661 emit_insn (gen_sse_movups (op0, op1));
12665 /* ??? If we have typed data, then it would appear that using
12666 movdqu is the only way to get unaligned data loaded with
12668 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12670 op0 = gen_lowpart (V16QImode, op0);
12671 op1 = gen_lowpart (V16QImode, op1);
12672 emit_insn (gen_sse2_movdqu (op0, op1));
12676 if (TARGET_SSE2 && mode == V2DFmode)
12680 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12682 op0 = gen_lowpart (V2DFmode, op0);
12683 op1 = gen_lowpart (V2DFmode, op1);
12684 emit_insn (gen_sse2_movupd (op0, op1));
12688 /* When SSE registers are split into halves, we can avoid
12689 writing to the top half twice. */
12690 if (TARGET_SSE_SPLIT_REGS)
12692 emit_clobber (op0);
12697 /* ??? Not sure about the best option for the Intel chips.
12698 The following would seem to satisfy; the register is
12699 entirely cleared, breaking the dependency chain. We
12700 then store to the upper half, with a dependency depth
12701 of one. A rumor has it that Intel recommends two movsd
12702 followed by an unpacklpd, but this is unconfirmed. And
12703 given that the dependency depth of the unpacklpd would
12704 still be one, I'm not sure why this would be better. */
12705 zero = CONST0_RTX (V2DFmode);
12708 m = adjust_address (op1, DFmode, 0);
12709 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12710 m = adjust_address (op1, DFmode, 8);
12711 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12715 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12717 op0 = gen_lowpart (V4SFmode, op0);
12718 op1 = gen_lowpart (V4SFmode, op1);
12719 emit_insn (gen_sse_movups (op0, op1));
12723 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12724 emit_move_insn (op0, CONST0_RTX (mode));
12726 emit_clobber (op0);
12728 if (mode != V4SFmode)
12729 op0 = gen_lowpart (V4SFmode, op0);
12730 m = adjust_address (op1, V2SFmode, 0);
12731 emit_insn (gen_sse_loadlps (op0, op0, m));
12732 m = adjust_address (op1, V2SFmode, 8);
12733 emit_insn (gen_sse_loadhps (op0, op0, m));
12736 else if (MEM_P (op0))
12738 /* If we're optimizing for size, movups is the smallest. */
12739 if (optimize_insn_for_size_p ())
12741 op0 = gen_lowpart (V4SFmode, op0);
12742 op1 = gen_lowpart (V4SFmode, op1);
12743 emit_insn (gen_sse_movups (op0, op1));
12747 /* ??? Similar to above, only less clear because of quote
12748 typeless stores unquote. */
12749 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12750 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12752 op0 = gen_lowpart (V16QImode, op0);
12753 op1 = gen_lowpart (V16QImode, op1);
12754 emit_insn (gen_sse2_movdqu (op0, op1));
12758 if (TARGET_SSE2 && mode == V2DFmode)
12760 m = adjust_address (op0, DFmode, 0);
12761 emit_insn (gen_sse2_storelpd (m, op1));
12762 m = adjust_address (op0, DFmode, 8);
12763 emit_insn (gen_sse2_storehpd (m, op1));
12767 if (mode != V4SFmode)
12768 op1 = gen_lowpart (V4SFmode, op1);
12769 m = adjust_address (op0, V2SFmode, 0);
12770 emit_insn (gen_sse_storelps (m, op1));
12771 m = adjust_address (op0, V2SFmode, 8);
12772 emit_insn (gen_sse_storehps (m, op1));
12776 gcc_unreachable ();
12779 /* Expand a push in MODE. This is some mode for which we do not support
12780 proper push instructions, at least from the registers that we expect
12781 the value to live in. */
12784 ix86_expand_push (enum machine_mode mode, rtx x)
12788 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12789 GEN_INT (-GET_MODE_SIZE (mode)),
12790 stack_pointer_rtx, 1, OPTAB_DIRECT);
12791 if (tmp != stack_pointer_rtx)
12792 emit_move_insn (stack_pointer_rtx, tmp);
12794 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12796 /* When we push an operand onto stack, it has to be aligned at least
12797 at the function argument boundary. However since we don't have
12798 the argument type, we can't determine the actual argument
12800 emit_move_insn (tmp, x);
12803 /* Helper function of ix86_fixup_binary_operands to canonicalize
12804 operand order. Returns true if the operands should be swapped. */
12807 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12810 rtx dst = operands[0];
12811 rtx src1 = operands[1];
12812 rtx src2 = operands[2];
12814 /* If the operation is not commutative, we can't do anything. */
12815 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12818 /* Highest priority is that src1 should match dst. */
12819 if (rtx_equal_p (dst, src1))
12821 if (rtx_equal_p (dst, src2))
12824 /* Next highest priority is that immediate constants come second. */
12825 if (immediate_operand (src2, mode))
12827 if (immediate_operand (src1, mode))
12830 /* Lowest priority is that memory references should come second. */
12840 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12841 destination to use for the operation. If different from the true
12842 destination in operands[0], a copy operation will be required. */
12845 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12848 rtx dst = operands[0];
12849 rtx src1 = operands[1];
12850 rtx src2 = operands[2];
12852 /* Canonicalize operand order. */
12853 if (ix86_swap_binary_operands_p (code, mode, operands))
12857 /* It is invalid to swap operands of different modes. */
12858 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12865 /* Both source operands cannot be in memory. */
12866 if (MEM_P (src1) && MEM_P (src2))
12868 /* Optimization: Only read from memory once. */
12869 if (rtx_equal_p (src1, src2))
12871 src2 = force_reg (mode, src2);
12875 src2 = force_reg (mode, src2);
12878 /* If the destination is memory, and we do not have matching source
12879 operands, do things in registers. */
12880 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12881 dst = gen_reg_rtx (mode);
12883 /* Source 1 cannot be a constant. */
12884 if (CONSTANT_P (src1))
12885 src1 = force_reg (mode, src1);
12887 /* Source 1 cannot be a non-matching memory. */
12888 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12889 src1 = force_reg (mode, src1);
12891 operands[1] = src1;
12892 operands[2] = src2;
12896 /* Similarly, but assume that the destination has already been
12897 set up properly. */
12900 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12901 enum machine_mode mode, rtx operands[])
12903 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12904 gcc_assert (dst == operands[0]);
12907 /* Attempt to expand a binary operator. Make the expansion closer to the
12908 actual machine, then just general_operand, which will allow 3 separate
12909 memory references (one output, two input) in a single insn. */
12912 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12915 rtx src1, src2, dst, op, clob;
12917 dst = ix86_fixup_binary_operands (code, mode, operands);
12918 src1 = operands[1];
12919 src2 = operands[2];
12921 /* Emit the instruction. */
12923 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12924 if (reload_in_progress)
12926 /* Reload doesn't know about the flags register, and doesn't know that
12927 it doesn't want to clobber it. We can only do this with PLUS. */
12928 gcc_assert (code == PLUS);
12933 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12934 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12937 /* Fix up the destination if needed. */
12938 if (dst != operands[0])
12939 emit_move_insn (operands[0], dst);
12942 /* Return TRUE or FALSE depending on whether the binary operator meets the
12943 appropriate constraints. */
12946 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12949 rtx dst = operands[0];
12950 rtx src1 = operands[1];
12951 rtx src2 = operands[2];
12953 /* Both source operands cannot be in memory. */
12954 if (MEM_P (src1) && MEM_P (src2))
12957 /* Canonicalize operand order for commutative operators. */
12958 if (ix86_swap_binary_operands_p (code, mode, operands))
12965 /* If the destination is memory, we must have a matching source operand. */
12966 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12969 /* Source 1 cannot be a constant. */
12970 if (CONSTANT_P (src1))
12973 /* Source 1 cannot be a non-matching memory. */
12974 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12980 /* Attempt to expand a unary operator. Make the expansion closer to the
12981 actual machine, then just general_operand, which will allow 2 separate
12982 memory references (one output, one input) in a single insn. */
12985 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12988 int matching_memory;
12989 rtx src, dst, op, clob;
12994 /* If the destination is memory, and we do not have matching source
12995 operands, do things in registers. */
12996 matching_memory = 0;
12999 if (rtx_equal_p (dst, src))
13000 matching_memory = 1;
13002 dst = gen_reg_rtx (mode);
13005 /* When source operand is memory, destination must match. */
13006 if (MEM_P (src) && !matching_memory)
13007 src = force_reg (mode, src);
13009 /* Emit the instruction. */
13011 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13012 if (reload_in_progress || code == NOT)
13014 /* Reload doesn't know about the flags register, and doesn't know that
13015 it doesn't want to clobber it. */
13016 gcc_assert (code == NOT);
13021 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13022 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13025 /* Fix up the destination if needed. */
13026 if (dst != operands[0])
13027 emit_move_insn (operands[0], dst);
13030 /* Return TRUE or FALSE depending on whether the unary operator meets the
13031 appropriate constraints. */
13034 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13035 enum machine_mode mode ATTRIBUTE_UNUSED,
13036 rtx operands[2] ATTRIBUTE_UNUSED)
13038 /* If one of operands is memory, source and destination must match. */
13039 if ((MEM_P (operands[0])
13040 || MEM_P (operands[1]))
13041 && ! rtx_equal_p (operands[0], operands[1]))
13046 /* Post-reload splitter for converting an SF or DFmode value in an
13047 SSE register into an unsigned SImode. */
13050 ix86_split_convert_uns_si_sse (rtx operands[])
13052 enum machine_mode vecmode;
13053 rtx value, large, zero_or_two31, input, two31, x;
13055 large = operands[1];
13056 zero_or_two31 = operands[2];
13057 input = operands[3];
13058 two31 = operands[4];
13059 vecmode = GET_MODE (large);
13060 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13062 /* Load up the value into the low element. We must ensure that the other
13063 elements are valid floats -- zero is the easiest such value. */
13066 if (vecmode == V4SFmode)
13067 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13069 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13073 input = gen_rtx_REG (vecmode, REGNO (input));
13074 emit_move_insn (value, CONST0_RTX (vecmode));
13075 if (vecmode == V4SFmode)
13076 emit_insn (gen_sse_movss (value, value, input));
13078 emit_insn (gen_sse2_movsd (value, value, input));
13081 emit_move_insn (large, two31);
13082 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13084 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13085 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13087 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13088 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13090 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13091 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13093 large = gen_rtx_REG (V4SImode, REGNO (large));
13094 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13096 x = gen_rtx_REG (V4SImode, REGNO (value));
13097 if (vecmode == V4SFmode)
13098 emit_insn (gen_sse2_cvttps2dq (x, value));
13100 emit_insn (gen_sse2_cvttpd2dq (x, value));
13103 emit_insn (gen_xorv4si3 (value, value, large));
13106 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13107 Expects the 64-bit DImode to be supplied in a pair of integral
13108 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13109 -mfpmath=sse, !optimize_size only. */
13112 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13114 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13115 rtx int_xmm, fp_xmm;
13116 rtx biases, exponents;
13119 int_xmm = gen_reg_rtx (V4SImode);
13120 if (TARGET_INTER_UNIT_MOVES)
13121 emit_insn (gen_movdi_to_sse (int_xmm, input));
13122 else if (TARGET_SSE_SPLIT_REGS)
13124 emit_clobber (int_xmm);
13125 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13129 x = gen_reg_rtx (V2DImode);
13130 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13131 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13134 x = gen_rtx_CONST_VECTOR (V4SImode,
13135 gen_rtvec (4, GEN_INT (0x43300000UL),
13136 GEN_INT (0x45300000UL),
13137 const0_rtx, const0_rtx));
13138 exponents = validize_mem (force_const_mem (V4SImode, x));
13140 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13141 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13143 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13144 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13145 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13146 (0x1.0p84 + double(fp_value_hi_xmm)).
13147 Note these exponents differ by 32. */
13149 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13151 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13152 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13153 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13154 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13155 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13156 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13157 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13158 biases = validize_mem (force_const_mem (V2DFmode, biases));
13159 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13161 /* Add the upper and lower DFmode values together. */
13163 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13166 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13167 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13168 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13171 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13174 /* Not used, but eases macroization of patterns. */
13176 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13177 rtx input ATTRIBUTE_UNUSED)
13179 gcc_unreachable ();
13182 /* Convert an unsigned SImode value into a DFmode. Only currently used
13183 for SSE, but applicable anywhere. */
13186 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13188 REAL_VALUE_TYPE TWO31r;
13191 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13192 NULL, 1, OPTAB_DIRECT);
13194 fp = gen_reg_rtx (DFmode);
13195 emit_insn (gen_floatsidf2 (fp, x));
13197 real_ldexp (&TWO31r, &dconst1, 31);
13198 x = const_double_from_real_value (TWO31r, DFmode);
13200 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13202 emit_move_insn (target, x);
13205 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13206 32-bit mode; otherwise we have a direct convert instruction. */
13209 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13211 REAL_VALUE_TYPE TWO32r;
13212 rtx fp_lo, fp_hi, x;
13214 fp_lo = gen_reg_rtx (DFmode);
13215 fp_hi = gen_reg_rtx (DFmode);
13217 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13219 real_ldexp (&TWO32r, &dconst1, 32);
13220 x = const_double_from_real_value (TWO32r, DFmode);
13221 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13223 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13225 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13228 emit_move_insn (target, x);
13231 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13232 For x86_32, -mfpmath=sse, !optimize_size only. */
13234 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13236 REAL_VALUE_TYPE ONE16r;
13237 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13239 real_ldexp (&ONE16r, &dconst1, 16);
13240 x = const_double_from_real_value (ONE16r, SFmode);
13241 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13242 NULL, 0, OPTAB_DIRECT);
13243 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13244 NULL, 0, OPTAB_DIRECT);
13245 fp_hi = gen_reg_rtx (SFmode);
13246 fp_lo = gen_reg_rtx (SFmode);
13247 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13248 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13249 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13251 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13253 if (!rtx_equal_p (target, fp_hi))
13254 emit_move_insn (target, fp_hi);
13257 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
13258 then replicate the value for all elements of the vector
13262 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13269 v = gen_rtvec (4, value, value, value, value);
13270 return gen_rtx_CONST_VECTOR (V4SImode, v);
13274 v = gen_rtvec (2, value, value);
13275 return gen_rtx_CONST_VECTOR (V2DImode, v);
13279 v = gen_rtvec (4, value, value, value, value);
13281 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13282 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13283 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13287 v = gen_rtvec (2, value, value);
13289 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13290 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13293 gcc_unreachable ();
13297 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13298 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13299 for an SSE register. If VECT is true, then replicate the mask for
13300 all elements of the vector register. If INVERT is true, then create
13301 a mask excluding the sign bit. */
13304 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13306 enum machine_mode vec_mode, imode;
13307 HOST_WIDE_INT hi, lo;
13312 /* Find the sign bit, sign extended to 2*HWI. */
13318 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13319 lo = 0x80000000, hi = lo < 0;
13325 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13326 if (HOST_BITS_PER_WIDE_INT >= 64)
13327 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13329 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13334 vec_mode = VOIDmode;
13335 if (HOST_BITS_PER_WIDE_INT >= 64)
13338 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13345 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13349 lo = ~lo, hi = ~hi;
13355 mask = immed_double_const (lo, hi, imode);
13357 vec = gen_rtvec (2, v, mask);
13358 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13359 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13366 gcc_unreachable ();
13370 lo = ~lo, hi = ~hi;
13372 /* Force this value into the low part of a fp vector constant. */
13373 mask = immed_double_const (lo, hi, imode);
13374 mask = gen_lowpart (mode, mask);
13376 if (vec_mode == VOIDmode)
13377 return force_reg (mode, mask);
13379 v = ix86_build_const_vector (mode, vect, mask);
13380 return force_reg (vec_mode, v);
13383 /* Generate code for floating point ABS or NEG. */
13386 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13389 rtx mask, set, use, clob, dst, src;
13390 bool use_sse = false;
13391 bool vector_mode = VECTOR_MODE_P (mode);
13392 enum machine_mode elt_mode = mode;
13396 elt_mode = GET_MODE_INNER (mode);
13399 else if (mode == TFmode)
13401 else if (TARGET_SSE_MATH)
13402 use_sse = SSE_FLOAT_MODE_P (mode);
13404 /* NEG and ABS performed with SSE use bitwise mask operations.
13405 Create the appropriate mask now. */
13407 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13416 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13417 set = gen_rtx_SET (VOIDmode, dst, set);
13422 set = gen_rtx_fmt_e (code, mode, src);
13423 set = gen_rtx_SET (VOIDmode, dst, set);
13426 use = gen_rtx_USE (VOIDmode, mask);
13427 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13428 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13429 gen_rtvec (3, set, use, clob)));
13436 /* Expand a copysign operation. Special case operand 0 being a constant. */
13439 ix86_expand_copysign (rtx operands[])
13441 enum machine_mode mode;
13442 rtx dest, op0, op1, mask, nmask;
13444 dest = operands[0];
13448 mode = GET_MODE (dest);
13450 if (GET_CODE (op0) == CONST_DOUBLE)
13452 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13454 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13455 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13457 if (mode == SFmode || mode == DFmode)
13459 enum machine_mode vmode;
13461 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13463 if (op0 == CONST0_RTX (mode))
13464 op0 = CONST0_RTX (vmode);
13469 if (mode == SFmode)
13470 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13471 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13473 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13475 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13478 else if (op0 != CONST0_RTX (mode))
13479 op0 = force_reg (mode, op0);
13481 mask = ix86_build_signbit_mask (mode, 0, 0);
13483 if (mode == SFmode)
13484 copysign_insn = gen_copysignsf3_const;
13485 else if (mode == DFmode)
13486 copysign_insn = gen_copysigndf3_const;
13488 copysign_insn = gen_copysigntf3_const;
13490 emit_insn (copysign_insn (dest, op0, op1, mask));
13494 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13496 nmask = ix86_build_signbit_mask (mode, 0, 1);
13497 mask = ix86_build_signbit_mask (mode, 0, 0);
13499 if (mode == SFmode)
13500 copysign_insn = gen_copysignsf3_var;
13501 else if (mode == DFmode)
13502 copysign_insn = gen_copysigndf3_var;
13504 copysign_insn = gen_copysigntf3_var;
13506 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13510 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13511 be a constant, and so has already been expanded into a vector constant. */
13514 ix86_split_copysign_const (rtx operands[])
13516 enum machine_mode mode, vmode;
13517 rtx dest, op0, op1, mask, x;
13519 dest = operands[0];
13522 mask = operands[3];
13524 mode = GET_MODE (dest);
13525 vmode = GET_MODE (mask);
13527 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13528 x = gen_rtx_AND (vmode, dest, mask);
13529 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13531 if (op0 != CONST0_RTX (vmode))
13533 x = gen_rtx_IOR (vmode, dest, op0);
13534 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13538 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13539 so we have to do two masks. */
13542 ix86_split_copysign_var (rtx operands[])
13544 enum machine_mode mode, vmode;
13545 rtx dest, scratch, op0, op1, mask, nmask, x;
13547 dest = operands[0];
13548 scratch = operands[1];
13551 nmask = operands[4];
13552 mask = operands[5];
13554 mode = GET_MODE (dest);
13555 vmode = GET_MODE (mask);
13557 if (rtx_equal_p (op0, op1))
13559 /* Shouldn't happen often (it's useless, obviously), but when it does
13560 we'd generate incorrect code if we continue below. */
13561 emit_move_insn (dest, op0);
13565 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13567 gcc_assert (REGNO (op1) == REGNO (scratch));
13569 x = gen_rtx_AND (vmode, scratch, mask);
13570 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13573 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13574 x = gen_rtx_NOT (vmode, dest);
13575 x = gen_rtx_AND (vmode, x, op0);
13576 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13580 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13582 x = gen_rtx_AND (vmode, scratch, mask);
13584 else /* alternative 2,4 */
13586 gcc_assert (REGNO (mask) == REGNO (scratch));
13587 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13588 x = gen_rtx_AND (vmode, scratch, op1);
13590 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13592 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13594 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13595 x = gen_rtx_AND (vmode, dest, nmask);
13597 else /* alternative 3,4 */
13599 gcc_assert (REGNO (nmask) == REGNO (dest));
13601 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13602 x = gen_rtx_AND (vmode, dest, op0);
13604 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13607 x = gen_rtx_IOR (vmode, dest, scratch);
13608 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13611 /* Return TRUE or FALSE depending on whether the first SET in INSN
13612 has source and destination with matching CC modes, and that the
13613 CC mode is at least as constrained as REQ_MODE. */
13616 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13619 enum machine_mode set_mode;
13621 set = PATTERN (insn);
13622 if (GET_CODE (set) == PARALLEL)
13623 set = XVECEXP (set, 0, 0);
13624 gcc_assert (GET_CODE (set) == SET);
13625 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13627 set_mode = GET_MODE (SET_DEST (set));
13631 if (req_mode != CCNOmode
13632 && (req_mode != CCmode
13633 || XEXP (SET_SRC (set), 1) != const0_rtx))
13637 if (req_mode == CCGCmode)
13641 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13645 if (req_mode == CCZmode)
13656 gcc_unreachable ();
13659 return (GET_MODE (SET_SRC (set)) == set_mode);
13662 /* Generate insn patterns to do an integer compare of OPERANDS. */
13665 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13667 enum machine_mode cmpmode;
13670 cmpmode = SELECT_CC_MODE (code, op0, op1);
13671 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13673 /* This is very simple, but making the interface the same as in the
13674 FP case makes the rest of the code easier. */
13675 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13676 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13678 /* Return the test that should be put into the flags user, i.e.
13679 the bcc, scc, or cmov instruction. */
13680 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13683 /* Figure out whether to use ordered or unordered fp comparisons.
13684 Return the appropriate mode to use. */
13687 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13689 /* ??? In order to make all comparisons reversible, we do all comparisons
13690 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13691 all forms trapping and nontrapping comparisons, we can make inequality
13692 comparisons trapping again, since it results in better code when using
13693 FCOM based compares. */
13694 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13698 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13700 enum machine_mode mode = GET_MODE (op0);
13702 if (SCALAR_FLOAT_MODE_P (mode))
13704 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13705 return ix86_fp_compare_mode (code);
13710 /* Only zero flag is needed. */
13711 case EQ: /* ZF=0 */
13712 case NE: /* ZF!=0 */
13714 /* Codes needing carry flag. */
13715 case GEU: /* CF=0 */
13716 case LTU: /* CF=1 */
13717 /* Detect overflow checks. They need just the carry flag. */
13718 if (GET_CODE (op0) == PLUS
13719 && rtx_equal_p (op1, XEXP (op0, 0)))
13723 case GTU: /* CF=0 & ZF=0 */
13724 case LEU: /* CF=1 | ZF=1 */
13725 /* Detect overflow checks. They need just the carry flag. */
13726 if (GET_CODE (op0) == MINUS
13727 && rtx_equal_p (op1, XEXP (op0, 0)))
13731 /* Codes possibly doable only with sign flag when
13732 comparing against zero. */
13733 case GE: /* SF=OF or SF=0 */
13734 case LT: /* SF<>OF or SF=1 */
13735 if (op1 == const0_rtx)
13738 /* For other cases Carry flag is not required. */
13740 /* Codes doable only with sign flag when comparing
13741 against zero, but we miss jump instruction for it
13742 so we need to use relational tests against overflow
13743 that thus needs to be zero. */
13744 case GT: /* ZF=0 & SF=OF */
13745 case LE: /* ZF=1 | SF<>OF */
13746 if (op1 == const0_rtx)
13750 /* strcmp pattern do (use flags) and combine may ask us for proper
13755 gcc_unreachable ();
13759 /* Return the fixed registers used for condition codes. */
13762 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13769 /* If two condition code modes are compatible, return a condition code
13770 mode which is compatible with both. Otherwise, return
13773 static enum machine_mode
13774 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13779 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13782 if ((m1 == CCGCmode && m2 == CCGOCmode)
13783 || (m1 == CCGOCmode && m2 == CCGCmode))
13789 gcc_unreachable ();
13819 /* These are only compatible with themselves, which we already
13825 /* Split comparison code CODE into comparisons we can do using branch
13826 instructions. BYPASS_CODE is comparison code for branch that will
13827 branch around FIRST_CODE and SECOND_CODE. If some of branches
13828 is not required, set value to UNKNOWN.
13829 We never require more than two branches. */
13832 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13833 enum rtx_code *first_code,
13834 enum rtx_code *second_code)
13836 *first_code = code;
13837 *bypass_code = UNKNOWN;
13838 *second_code = UNKNOWN;
13840 /* The fcomi comparison sets flags as follows:
13850 case GT: /* GTU - CF=0 & ZF=0 */
13851 case GE: /* GEU - CF=0 */
13852 case ORDERED: /* PF=0 */
13853 case UNORDERED: /* PF=1 */
13854 case UNEQ: /* EQ - ZF=1 */
13855 case UNLT: /* LTU - CF=1 */
13856 case UNLE: /* LEU - CF=1 | ZF=1 */
13857 case LTGT: /* EQ - ZF=0 */
13859 case LT: /* LTU - CF=1 - fails on unordered */
13860 *first_code = UNLT;
13861 *bypass_code = UNORDERED;
13863 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13864 *first_code = UNLE;
13865 *bypass_code = UNORDERED;
13867 case EQ: /* EQ - ZF=1 - fails on unordered */
13868 *first_code = UNEQ;
13869 *bypass_code = UNORDERED;
13871 case NE: /* NE - ZF=0 - fails on unordered */
13872 *first_code = LTGT;
13873 *second_code = UNORDERED;
13875 case UNGE: /* GEU - CF=0 - fails on unordered */
13877 *second_code = UNORDERED;
13879 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13881 *second_code = UNORDERED;
13884 gcc_unreachable ();
13886 if (!TARGET_IEEE_FP)
13888 *second_code = UNKNOWN;
13889 *bypass_code = UNKNOWN;
13893 /* Return cost of comparison done fcom + arithmetics operations on AX.
13894 All following functions do use number of instructions as a cost metrics.
13895 In future this should be tweaked to compute bytes for optimize_size and
13896 take into account performance of various instructions on various CPUs. */
13898 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13900 if (!TARGET_IEEE_FP)
13902 /* The cost of code output by ix86_expand_fp_compare. */
13926 gcc_unreachable ();
13930 /* Return cost of comparison done using fcomi operation.
13931 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13933 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13935 enum rtx_code bypass_code, first_code, second_code;
13936 /* Return arbitrarily high cost when instruction is not supported - this
13937 prevents gcc from using it. */
13940 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13941 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13944 /* Return cost of comparison done using sahf operation.
13945 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13947 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13949 enum rtx_code bypass_code, first_code, second_code;
13950 /* Return arbitrarily high cost when instruction is not preferred - this
13951 avoids gcc from using it. */
13952 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13954 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13955 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13958 /* Compute cost of the comparison done using any method.
13959 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13961 ix86_fp_comparison_cost (enum rtx_code code)
13963 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13966 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13967 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13969 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13970 if (min > sahf_cost)
13972 if (min > fcomi_cost)
13977 /* Return true if we should use an FCOMI instruction for this
13981 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13983 enum rtx_code swapped_code = swap_condition (code);
13985 return ((ix86_fp_comparison_cost (code)
13986 == ix86_fp_comparison_fcomi_cost (code))
13987 || (ix86_fp_comparison_cost (swapped_code)
13988 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13991 /* Swap, force into registers, or otherwise massage the two operands
13992 to a fp comparison. The operands are updated in place; the new
13993 comparison code is returned. */
13995 static enum rtx_code
13996 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13998 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13999 rtx op0 = *pop0, op1 = *pop1;
14000 enum machine_mode op_mode = GET_MODE (op0);
14001 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14003 /* All of the unordered compare instructions only work on registers.
14004 The same is true of the fcomi compare instructions. The XFmode
14005 compare instructions require registers except when comparing
14006 against zero or when converting operand 1 from fixed point to
14010 && (fpcmp_mode == CCFPUmode
14011 || (op_mode == XFmode
14012 && ! (standard_80387_constant_p (op0) == 1
14013 || standard_80387_constant_p (op1) == 1)
14014 && GET_CODE (op1) != FLOAT)
14015 || ix86_use_fcomi_compare (code)))
14017 op0 = force_reg (op_mode, op0);
14018 op1 = force_reg (op_mode, op1);
14022 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14023 things around if they appear profitable, otherwise force op0
14024 into a register. */
14026 if (standard_80387_constant_p (op0) == 0
14028 && ! (standard_80387_constant_p (op1) == 0
14032 tmp = op0, op0 = op1, op1 = tmp;
14033 code = swap_condition (code);
14037 op0 = force_reg (op_mode, op0);
14039 if (CONSTANT_P (op1))
14041 int tmp = standard_80387_constant_p (op1);
14043 op1 = validize_mem (force_const_mem (op_mode, op1));
14047 op1 = force_reg (op_mode, op1);
14050 op1 = force_reg (op_mode, op1);
14054 /* Try to rearrange the comparison to make it cheaper. */
14055 if (ix86_fp_comparison_cost (code)
14056 > ix86_fp_comparison_cost (swap_condition (code))
14057 && (REG_P (op1) || can_create_pseudo_p ()))
14060 tmp = op0, op0 = op1, op1 = tmp;
14061 code = swap_condition (code);
14063 op0 = force_reg (op_mode, op0);
14071 /* Convert comparison codes we use to represent FP comparison to integer
14072 code that will result in proper branch. Return UNKNOWN if no such code
14076 ix86_fp_compare_code_to_integer (enum rtx_code code)
14105 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14108 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
14109 rtx *second_test, rtx *bypass_test)
14111 enum machine_mode fpcmp_mode, intcmp_mode;
14113 int cost = ix86_fp_comparison_cost (code);
14114 enum rtx_code bypass_code, first_code, second_code;
14116 fpcmp_mode = ix86_fp_compare_mode (code);
14117 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14120 *second_test = NULL_RTX;
14122 *bypass_test = NULL_RTX;
14124 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14126 /* Do fcomi/sahf based test when profitable. */
14127 if (ix86_fp_comparison_arithmetics_cost (code) > cost
14128 && (bypass_code == UNKNOWN || bypass_test)
14129 && (second_code == UNKNOWN || second_test))
14131 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14132 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14138 gcc_assert (TARGET_SAHF);
14141 scratch = gen_reg_rtx (HImode);
14142 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14144 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14147 /* The FP codes work out to act like unsigned. */
14148 intcmp_mode = fpcmp_mode;
14150 if (bypass_code != UNKNOWN)
14151 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
14152 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14154 if (second_code != UNKNOWN)
14155 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
14156 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14161 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14162 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14163 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14165 scratch = gen_reg_rtx (HImode);
14166 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14168 /* In the unordered case, we have to check C2 for NaN's, which
14169 doesn't happen to work out to anything nice combination-wise.
14170 So do some bit twiddling on the value we've got in AH to come
14171 up with an appropriate set of condition codes. */
14173 intcmp_mode = CCNOmode;
14178 if (code == GT || !TARGET_IEEE_FP)
14180 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14185 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14186 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14187 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14188 intcmp_mode = CCmode;
14194 if (code == LT && TARGET_IEEE_FP)
14196 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14197 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14198 intcmp_mode = CCmode;
14203 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14209 if (code == GE || !TARGET_IEEE_FP)
14211 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14216 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14217 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14224 if (code == LE && TARGET_IEEE_FP)
14226 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14227 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14228 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14229 intcmp_mode = CCmode;
14234 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14240 if (code == EQ && TARGET_IEEE_FP)
14242 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14243 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14244 intcmp_mode = CCmode;
14249 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14256 if (code == NE && TARGET_IEEE_FP)
14258 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14259 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14265 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14271 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14275 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14280 gcc_unreachable ();
14284 /* Return the test that should be put into the flags user, i.e.
14285 the bcc, scc, or cmov instruction. */
14286 return gen_rtx_fmt_ee (code, VOIDmode,
14287 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14292 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14295 op0 = ix86_compare_op0;
14296 op1 = ix86_compare_op1;
14299 *second_test = NULL_RTX;
14301 *bypass_test = NULL_RTX;
14303 if (ix86_compare_emitted)
14305 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
14306 ix86_compare_emitted = NULL_RTX;
14308 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14310 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14311 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14312 second_test, bypass_test);
14315 ret = ix86_expand_int_compare (code, op0, op1);
14320 /* Return true if the CODE will result in nontrivial jump sequence. */
14322 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14324 enum rtx_code bypass_code, first_code, second_code;
14327 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14328 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14332 ix86_expand_branch (enum rtx_code code, rtx label)
14336 /* If we have emitted a compare insn, go straight to simple.
14337 ix86_expand_compare won't emit anything if ix86_compare_emitted
14339 if (ix86_compare_emitted)
14342 switch (GET_MODE (ix86_compare_op0))
14348 tmp = ix86_expand_compare (code, NULL, NULL);
14349 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14350 gen_rtx_LABEL_REF (VOIDmode, label),
14352 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14361 enum rtx_code bypass_code, first_code, second_code;
14363 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14364 &ix86_compare_op1);
14366 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14368 /* Check whether we will use the natural sequence with one jump. If
14369 so, we can expand jump early. Otherwise delay expansion by
14370 creating compound insn to not confuse optimizers. */
14371 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14373 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14374 gen_rtx_LABEL_REF (VOIDmode, label),
14375 pc_rtx, NULL_RTX, NULL_RTX);
14379 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14380 ix86_compare_op0, ix86_compare_op1);
14381 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14382 gen_rtx_LABEL_REF (VOIDmode, label),
14384 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14386 use_fcomi = ix86_use_fcomi_compare (code);
14387 vec = rtvec_alloc (3 + !use_fcomi);
14388 RTVEC_ELT (vec, 0) = tmp;
14390 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14392 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14395 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14397 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14406 /* Expand DImode branch into multiple compare+branch. */
14408 rtx lo[2], hi[2], label2;
14409 enum rtx_code code1, code2, code3;
14410 enum machine_mode submode;
14412 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14414 tmp = ix86_compare_op0;
14415 ix86_compare_op0 = ix86_compare_op1;
14416 ix86_compare_op1 = tmp;
14417 code = swap_condition (code);
14419 if (GET_MODE (ix86_compare_op0) == DImode)
14421 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14422 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14427 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14428 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14432 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14433 avoid two branches. This costs one extra insn, so disable when
14434 optimizing for size. */
14436 if ((code == EQ || code == NE)
14437 && (!optimize_insn_for_size_p ()
14438 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14443 if (hi[1] != const0_rtx)
14444 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14445 NULL_RTX, 0, OPTAB_WIDEN);
14448 if (lo[1] != const0_rtx)
14449 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14450 NULL_RTX, 0, OPTAB_WIDEN);
14452 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14453 NULL_RTX, 0, OPTAB_WIDEN);
14455 ix86_compare_op0 = tmp;
14456 ix86_compare_op1 = const0_rtx;
14457 ix86_expand_branch (code, label);
14461 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14462 op1 is a constant and the low word is zero, then we can just
14463 examine the high word. Similarly for low word -1 and
14464 less-or-equal-than or greater-than. */
14466 if (CONST_INT_P (hi[1]))
14469 case LT: case LTU: case GE: case GEU:
14470 if (lo[1] == const0_rtx)
14472 ix86_compare_op0 = hi[0];
14473 ix86_compare_op1 = hi[1];
14474 ix86_expand_branch (code, label);
14478 case LE: case LEU: case GT: case GTU:
14479 if (lo[1] == constm1_rtx)
14481 ix86_compare_op0 = hi[0];
14482 ix86_compare_op1 = hi[1];
14483 ix86_expand_branch (code, label);
14491 /* Otherwise, we need two or three jumps. */
14493 label2 = gen_label_rtx ();
14496 code2 = swap_condition (code);
14497 code3 = unsigned_condition (code);
14501 case LT: case GT: case LTU: case GTU:
14504 case LE: code1 = LT; code2 = GT; break;
14505 case GE: code1 = GT; code2 = LT; break;
14506 case LEU: code1 = LTU; code2 = GTU; break;
14507 case GEU: code1 = GTU; code2 = LTU; break;
14509 case EQ: code1 = UNKNOWN; code2 = NE; break;
14510 case NE: code2 = UNKNOWN; break;
14513 gcc_unreachable ();
14518 * if (hi(a) < hi(b)) goto true;
14519 * if (hi(a) > hi(b)) goto false;
14520 * if (lo(a) < lo(b)) goto true;
14524 ix86_compare_op0 = hi[0];
14525 ix86_compare_op1 = hi[1];
14527 if (code1 != UNKNOWN)
14528 ix86_expand_branch (code1, label);
14529 if (code2 != UNKNOWN)
14530 ix86_expand_branch (code2, label2);
14532 ix86_compare_op0 = lo[0];
14533 ix86_compare_op1 = lo[1];
14534 ix86_expand_branch (code3, label);
14536 if (code2 != UNKNOWN)
14537 emit_label (label2);
14542 gcc_unreachable ();
14546 /* Split branch based on floating point condition. */
14548 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14549 rtx target1, rtx target2, rtx tmp, rtx pushed)
14551 rtx second, bypass;
14552 rtx label = NULL_RTX;
14554 int bypass_probability = -1, second_probability = -1, probability = -1;
14557 if (target2 != pc_rtx)
14560 code = reverse_condition_maybe_unordered (code);
14565 condition = ix86_expand_fp_compare (code, op1, op2,
14566 tmp, &second, &bypass);
14568 /* Remove pushed operand from stack. */
14570 ix86_free_from_memory (GET_MODE (pushed));
14572 if (split_branch_probability >= 0)
14574 /* Distribute the probabilities across the jumps.
14575 Assume the BYPASS and SECOND to be always test
14577 probability = split_branch_probability;
14579 /* Value of 1 is low enough to make no need for probability
14580 to be updated. Later we may run some experiments and see
14581 if unordered values are more frequent in practice. */
14583 bypass_probability = 1;
14585 second_probability = 1;
14587 if (bypass != NULL_RTX)
14589 label = gen_label_rtx ();
14590 i = emit_jump_insn (gen_rtx_SET
14592 gen_rtx_IF_THEN_ELSE (VOIDmode,
14594 gen_rtx_LABEL_REF (VOIDmode,
14597 if (bypass_probability >= 0)
14599 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14600 GEN_INT (bypass_probability),
14603 i = emit_jump_insn (gen_rtx_SET
14605 gen_rtx_IF_THEN_ELSE (VOIDmode,
14606 condition, target1, target2)));
14607 if (probability >= 0)
14609 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14610 GEN_INT (probability),
14612 if (second != NULL_RTX)
14614 i = emit_jump_insn (gen_rtx_SET
14616 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14618 if (second_probability >= 0)
14620 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14621 GEN_INT (second_probability),
14624 if (label != NULL_RTX)
14625 emit_label (label);
14629 ix86_expand_setcc (enum rtx_code code, rtx dest)
14631 rtx ret, tmp, tmpreg, equiv;
14632 rtx second_test, bypass_test;
14634 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14635 return 0; /* FAIL */
14637 gcc_assert (GET_MODE (dest) == QImode);
14639 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14640 PUT_MODE (ret, QImode);
14645 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14646 if (bypass_test || second_test)
14648 rtx test = second_test;
14650 rtx tmp2 = gen_reg_rtx (QImode);
14653 gcc_assert (!second_test);
14654 test = bypass_test;
14656 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14658 PUT_MODE (test, QImode);
14659 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14662 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14664 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14667 /* Attach a REG_EQUAL note describing the comparison result. */
14668 if (ix86_compare_op0 && ix86_compare_op1)
14670 equiv = simplify_gen_relational (code, QImode,
14671 GET_MODE (ix86_compare_op0),
14672 ix86_compare_op0, ix86_compare_op1);
14673 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14676 return 1; /* DONE */
14679 /* Expand comparison setting or clearing carry flag. Return true when
14680 successful and set pop for the operation. */
14682 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14684 enum machine_mode mode =
14685 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14687 /* Do not handle DImode compares that go through special path. */
14688 if (mode == (TARGET_64BIT ? TImode : DImode))
14691 if (SCALAR_FLOAT_MODE_P (mode))
14693 rtx second_test = NULL, bypass_test = NULL;
14694 rtx compare_op, compare_seq;
14696 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14698 /* Shortcut: following common codes never translate
14699 into carry flag compares. */
14700 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14701 || code == ORDERED || code == UNORDERED)
14704 /* These comparisons require zero flag; swap operands so they won't. */
14705 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14706 && !TARGET_IEEE_FP)
14711 code = swap_condition (code);
14714 /* Try to expand the comparison and verify that we end up with
14715 carry flag based comparison. This fails to be true only when
14716 we decide to expand comparison using arithmetic that is not
14717 too common scenario. */
14719 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14720 &second_test, &bypass_test);
14721 compare_seq = get_insns ();
14724 if (second_test || bypass_test)
14727 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14728 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14729 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14731 code = GET_CODE (compare_op);
14733 if (code != LTU && code != GEU)
14736 emit_insn (compare_seq);
14741 if (!INTEGRAL_MODE_P (mode))
14750 /* Convert a==0 into (unsigned)a<1. */
14753 if (op1 != const0_rtx)
14756 code = (code == EQ ? LTU : GEU);
14759 /* Convert a>b into b<a or a>=b-1. */
14762 if (CONST_INT_P (op1))
14764 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14765 /* Bail out on overflow. We still can swap operands but that
14766 would force loading of the constant into register. */
14767 if (op1 == const0_rtx
14768 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14770 code = (code == GTU ? GEU : LTU);
14777 code = (code == GTU ? LTU : GEU);
14781 /* Convert a>=0 into (unsigned)a<0x80000000. */
14784 if (mode == DImode || op1 != const0_rtx)
14786 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14787 code = (code == LT ? GEU : LTU);
14791 if (mode == DImode || op1 != constm1_rtx)
14793 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14794 code = (code == LE ? GEU : LTU);
14800 /* Swapping operands may cause constant to appear as first operand. */
14801 if (!nonimmediate_operand (op0, VOIDmode))
14803 if (!can_create_pseudo_p ())
14805 op0 = force_reg (mode, op0);
14807 ix86_compare_op0 = op0;
14808 ix86_compare_op1 = op1;
14809 *pop = ix86_expand_compare (code, NULL, NULL);
14810 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14815 ix86_expand_int_movcc (rtx operands[])
14817 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14818 rtx compare_seq, compare_op;
14819 rtx second_test, bypass_test;
14820 enum machine_mode mode = GET_MODE (operands[0]);
14821 bool sign_bit_compare_p = false;;
14824 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14825 compare_seq = get_insns ();
14828 compare_code = GET_CODE (compare_op);
14830 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14831 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14832 sign_bit_compare_p = true;
14834 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14835 HImode insns, we'd be swallowed in word prefix ops. */
14837 if ((mode != HImode || TARGET_FAST_PREFIX)
14838 && (mode != (TARGET_64BIT ? TImode : DImode))
14839 && CONST_INT_P (operands[2])
14840 && CONST_INT_P (operands[3]))
14842 rtx out = operands[0];
14843 HOST_WIDE_INT ct = INTVAL (operands[2]);
14844 HOST_WIDE_INT cf = INTVAL (operands[3]);
14845 HOST_WIDE_INT diff;
14848 /* Sign bit compares are better done using shifts than we do by using
14850 if (sign_bit_compare_p
14851 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14852 ix86_compare_op1, &compare_op))
14854 /* Detect overlap between destination and compare sources. */
14857 if (!sign_bit_compare_p)
14859 bool fpcmp = false;
14861 compare_code = GET_CODE (compare_op);
14863 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14864 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14867 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14870 /* To simplify rest of code, restrict to the GEU case. */
14871 if (compare_code == LTU)
14873 HOST_WIDE_INT tmp = ct;
14876 compare_code = reverse_condition (compare_code);
14877 code = reverse_condition (code);
14882 PUT_CODE (compare_op,
14883 reverse_condition_maybe_unordered
14884 (GET_CODE (compare_op)));
14886 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14890 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14891 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14892 tmp = gen_reg_rtx (mode);
14894 if (mode == DImode)
14895 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14897 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14901 if (code == GT || code == GE)
14902 code = reverse_condition (code);
14905 HOST_WIDE_INT tmp = ct;
14910 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14911 ix86_compare_op1, VOIDmode, 0, -1);
14924 tmp = expand_simple_binop (mode, PLUS,
14926 copy_rtx (tmp), 1, OPTAB_DIRECT);
14937 tmp = expand_simple_binop (mode, IOR,
14939 copy_rtx (tmp), 1, OPTAB_DIRECT);
14941 else if (diff == -1 && ct)
14951 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14953 tmp = expand_simple_binop (mode, PLUS,
14954 copy_rtx (tmp), GEN_INT (cf),
14955 copy_rtx (tmp), 1, OPTAB_DIRECT);
14963 * andl cf - ct, dest
14973 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14976 tmp = expand_simple_binop (mode, AND,
14978 gen_int_mode (cf - ct, mode),
14979 copy_rtx (tmp), 1, OPTAB_DIRECT);
14981 tmp = expand_simple_binop (mode, PLUS,
14982 copy_rtx (tmp), GEN_INT (ct),
14983 copy_rtx (tmp), 1, OPTAB_DIRECT);
14986 if (!rtx_equal_p (tmp, out))
14987 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14989 return 1; /* DONE */
14994 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14997 tmp = ct, ct = cf, cf = tmp;
15000 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15002 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15004 /* We may be reversing unordered compare to normal compare, that
15005 is not valid in general (we may convert non-trapping condition
15006 to trapping one), however on i386 we currently emit all
15007 comparisons unordered. */
15008 compare_code = reverse_condition_maybe_unordered (compare_code);
15009 code = reverse_condition_maybe_unordered (code);
15013 compare_code = reverse_condition (compare_code);
15014 code = reverse_condition (code);
15018 compare_code = UNKNOWN;
15019 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15020 && CONST_INT_P (ix86_compare_op1))
15022 if (ix86_compare_op1 == const0_rtx
15023 && (code == LT || code == GE))
15024 compare_code = code;
15025 else if (ix86_compare_op1 == constm1_rtx)
15029 else if (code == GT)
15034 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15035 if (compare_code != UNKNOWN
15036 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15037 && (cf == -1 || ct == -1))
15039 /* If lea code below could be used, only optimize
15040 if it results in a 2 insn sequence. */
15042 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15043 || diff == 3 || diff == 5 || diff == 9)
15044 || (compare_code == LT && ct == -1)
15045 || (compare_code == GE && cf == -1))
15048 * notl op1 (if necessary)
15056 code = reverse_condition (code);
15059 out = emit_store_flag (out, code, ix86_compare_op0,
15060 ix86_compare_op1, VOIDmode, 0, -1);
15062 out = expand_simple_binop (mode, IOR,
15064 out, 1, OPTAB_DIRECT);
15065 if (out != operands[0])
15066 emit_move_insn (operands[0], out);
15068 return 1; /* DONE */
15073 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15074 || diff == 3 || diff == 5 || diff == 9)
15075 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15077 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15083 * lea cf(dest*(ct-cf)),dest
15087 * This also catches the degenerate setcc-only case.
15093 out = emit_store_flag (out, code, ix86_compare_op0,
15094 ix86_compare_op1, VOIDmode, 0, 1);
15097 /* On x86_64 the lea instruction operates on Pmode, so we need
15098 to get arithmetics done in proper mode to match. */
15100 tmp = copy_rtx (out);
15104 out1 = copy_rtx (out);
15105 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15109 tmp = gen_rtx_PLUS (mode, tmp, out1);
15115 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15118 if (!rtx_equal_p (tmp, out))
15121 out = force_operand (tmp, copy_rtx (out));
15123 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15125 if (!rtx_equal_p (out, operands[0]))
15126 emit_move_insn (operands[0], copy_rtx (out));
15128 return 1; /* DONE */
15132 * General case: Jumpful:
15133 * xorl dest,dest cmpl op1, op2
15134 * cmpl op1, op2 movl ct, dest
15135 * setcc dest jcc 1f
15136 * decl dest movl cf, dest
15137 * andl (cf-ct),dest 1:
15140 * Size 20. Size 14.
15142 * This is reasonably steep, but branch mispredict costs are
15143 * high on modern cpus, so consider failing only if optimizing
15147 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15148 && BRANCH_COST (optimize_insn_for_speed_p (),
15153 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15158 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15160 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15162 /* We may be reversing unordered compare to normal compare,
15163 that is not valid in general (we may convert non-trapping
15164 condition to trapping one), however on i386 we currently
15165 emit all comparisons unordered. */
15166 code = reverse_condition_maybe_unordered (code);
15170 code = reverse_condition (code);
15171 if (compare_code != UNKNOWN)
15172 compare_code = reverse_condition (compare_code);
15176 if (compare_code != UNKNOWN)
15178 /* notl op1 (if needed)
15183 For x < 0 (resp. x <= -1) there will be no notl,
15184 so if possible swap the constants to get rid of the
15186 True/false will be -1/0 while code below (store flag
15187 followed by decrement) is 0/-1, so the constants need
15188 to be exchanged once more. */
15190 if (compare_code == GE || !cf)
15192 code = reverse_condition (code);
15197 HOST_WIDE_INT tmp = cf;
15202 out = emit_store_flag (out, code, ix86_compare_op0,
15203 ix86_compare_op1, VOIDmode, 0, -1);
15207 out = emit_store_flag (out, code, ix86_compare_op0,
15208 ix86_compare_op1, VOIDmode, 0, 1);
15210 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15211 copy_rtx (out), 1, OPTAB_DIRECT);
15214 out = expand_simple_binop (mode, AND, copy_rtx (out),
15215 gen_int_mode (cf - ct, mode),
15216 copy_rtx (out), 1, OPTAB_DIRECT);
15218 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15219 copy_rtx (out), 1, OPTAB_DIRECT);
15220 if (!rtx_equal_p (out, operands[0]))
15221 emit_move_insn (operands[0], copy_rtx (out));
15223 return 1; /* DONE */
15227 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15229 /* Try a few things more with specific constants and a variable. */
15232 rtx var, orig_out, out, tmp;
15234 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15235 return 0; /* FAIL */
15237 /* If one of the two operands is an interesting constant, load a
15238 constant with the above and mask it in with a logical operation. */
15240 if (CONST_INT_P (operands[2]))
15243 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15244 operands[3] = constm1_rtx, op = and_optab;
15245 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15246 operands[3] = const0_rtx, op = ior_optab;
15248 return 0; /* FAIL */
15250 else if (CONST_INT_P (operands[3]))
15253 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15254 operands[2] = constm1_rtx, op = and_optab;
15255 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15256 operands[2] = const0_rtx, op = ior_optab;
15258 return 0; /* FAIL */
15261 return 0; /* FAIL */
15263 orig_out = operands[0];
15264 tmp = gen_reg_rtx (mode);
15267 /* Recurse to get the constant loaded. */
15268 if (ix86_expand_int_movcc (operands) == 0)
15269 return 0; /* FAIL */
15271 /* Mask in the interesting variable. */
15272 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15274 if (!rtx_equal_p (out, orig_out))
15275 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15277 return 1; /* DONE */
15281 * For comparison with above,
15291 if (! nonimmediate_operand (operands[2], mode))
15292 operands[2] = force_reg (mode, operands[2]);
15293 if (! nonimmediate_operand (operands[3], mode))
15294 operands[3] = force_reg (mode, operands[3]);
15296 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15298 rtx tmp = gen_reg_rtx (mode);
15299 emit_move_insn (tmp, operands[3]);
15302 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15304 rtx tmp = gen_reg_rtx (mode);
15305 emit_move_insn (tmp, operands[2]);
15309 if (! register_operand (operands[2], VOIDmode)
15311 || ! register_operand (operands[3], VOIDmode)))
15312 operands[2] = force_reg (mode, operands[2]);
15315 && ! register_operand (operands[3], VOIDmode))
15316 operands[3] = force_reg (mode, operands[3]);
15318 emit_insn (compare_seq);
15319 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15320 gen_rtx_IF_THEN_ELSE (mode,
15321 compare_op, operands[2],
15324 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15325 gen_rtx_IF_THEN_ELSE (mode,
15327 copy_rtx (operands[3]),
15328 copy_rtx (operands[0]))));
15330 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15331 gen_rtx_IF_THEN_ELSE (mode,
15333 copy_rtx (operands[2]),
15334 copy_rtx (operands[0]))));
15336 return 1; /* DONE */
15339 /* Swap, force into registers, or otherwise massage the two operands
15340 to an sse comparison with a mask result. Thus we differ a bit from
15341 ix86_prepare_fp_compare_args which expects to produce a flags result.
15343 The DEST operand exists to help determine whether to commute commutative
15344 operators. The POP0/POP1 operands are updated in place. The new
15345 comparison code is returned, or UNKNOWN if not implementable. */
15347 static enum rtx_code
15348 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15349 rtx *pop0, rtx *pop1)
15357 /* We have no LTGT as an operator. We could implement it with
15358 NE & ORDERED, but this requires an extra temporary. It's
15359 not clear that it's worth it. */
15366 /* These are supported directly. */
15373 /* For commutative operators, try to canonicalize the destination
15374 operand to be first in the comparison - this helps reload to
15375 avoid extra moves. */
15376 if (!dest || !rtx_equal_p (dest, *pop1))
15384 /* These are not supported directly. Swap the comparison operands
15385 to transform into something that is supported. */
15389 code = swap_condition (code);
15393 gcc_unreachable ();
15399 /* Detect conditional moves that exactly match min/max operational
15400 semantics. Note that this is IEEE safe, as long as we don't
15401 interchange the operands.
15403 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15404 and TRUE if the operation is successful and instructions are emitted. */
15407 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15408 rtx cmp_op1, rtx if_true, rtx if_false)
15410 enum machine_mode mode;
15416 else if (code == UNGE)
15419 if_true = if_false;
15425 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15427 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15432 mode = GET_MODE (dest);
15434 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15435 but MODE may be a vector mode and thus not appropriate. */
15436 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15438 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15441 if_true = force_reg (mode, if_true);
15442 v = gen_rtvec (2, if_true, if_false);
15443 tmp = gen_rtx_UNSPEC (mode, v, u);
15447 code = is_min ? SMIN : SMAX;
15448 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15451 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15455 /* Expand an sse vector comparison. Return the register with the result. */
15458 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15459 rtx op_true, rtx op_false)
15461 enum machine_mode mode = GET_MODE (dest);
15464 cmp_op0 = force_reg (mode, cmp_op0);
15465 if (!nonimmediate_operand (cmp_op1, mode))
15466 cmp_op1 = force_reg (mode, cmp_op1);
15469 || reg_overlap_mentioned_p (dest, op_true)
15470 || reg_overlap_mentioned_p (dest, op_false))
15471 dest = gen_reg_rtx (mode);
15473 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15474 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15479 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15480 operations. This is used for both scalar and vector conditional moves. */
15483 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15485 enum machine_mode mode = GET_MODE (dest);
15488 if (op_false == CONST0_RTX (mode))
15490 op_true = force_reg (mode, op_true);
15491 x = gen_rtx_AND (mode, cmp, op_true);
15492 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15494 else if (op_true == CONST0_RTX (mode))
15496 op_false = force_reg (mode, op_false);
15497 x = gen_rtx_NOT (mode, cmp);
15498 x = gen_rtx_AND (mode, x, op_false);
15499 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15501 else if (TARGET_SSE5)
15503 rtx pcmov = gen_rtx_SET (mode, dest,
15504 gen_rtx_IF_THEN_ELSE (mode, cmp,
15511 op_true = force_reg (mode, op_true);
15512 op_false = force_reg (mode, op_false);
15514 t2 = gen_reg_rtx (mode);
15516 t3 = gen_reg_rtx (mode);
15520 x = gen_rtx_AND (mode, op_true, cmp);
15521 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15523 x = gen_rtx_NOT (mode, cmp);
15524 x = gen_rtx_AND (mode, x, op_false);
15525 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15527 x = gen_rtx_IOR (mode, t3, t2);
15528 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15532 /* Expand a floating-point conditional move. Return true if successful. */
15535 ix86_expand_fp_movcc (rtx operands[])
15537 enum machine_mode mode = GET_MODE (operands[0]);
15538 enum rtx_code code = GET_CODE (operands[1]);
15539 rtx tmp, compare_op, second_test, bypass_test;
15541 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15543 enum machine_mode cmode;
15545 /* Since we've no cmove for sse registers, don't force bad register
15546 allocation just to gain access to it. Deny movcc when the
15547 comparison mode doesn't match the move mode. */
15548 cmode = GET_MODE (ix86_compare_op0);
15549 if (cmode == VOIDmode)
15550 cmode = GET_MODE (ix86_compare_op1);
15554 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15556 &ix86_compare_op1);
15557 if (code == UNKNOWN)
15560 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15561 ix86_compare_op1, operands[2],
15565 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15566 ix86_compare_op1, operands[2], operands[3]);
15567 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15571 /* The floating point conditional move instructions don't directly
15572 support conditions resulting from a signed integer comparison. */
15574 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15576 /* The floating point conditional move instructions don't directly
15577 support signed integer comparisons. */
15579 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15581 gcc_assert (!second_test && !bypass_test);
15582 tmp = gen_reg_rtx (QImode);
15583 ix86_expand_setcc (code, tmp);
15585 ix86_compare_op0 = tmp;
15586 ix86_compare_op1 = const0_rtx;
15587 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15589 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15591 tmp = gen_reg_rtx (mode);
15592 emit_move_insn (tmp, operands[3]);
15595 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15597 tmp = gen_reg_rtx (mode);
15598 emit_move_insn (tmp, operands[2]);
15602 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15603 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15604 operands[2], operands[3])));
15606 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15607 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15608 operands[3], operands[0])));
15610 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15611 gen_rtx_IF_THEN_ELSE (mode, second_test,
15612 operands[2], operands[0])));
15617 /* Expand a floating-point vector conditional move; a vcond operation
15618 rather than a movcc operation. */
15621 ix86_expand_fp_vcond (rtx operands[])
15623 enum rtx_code code = GET_CODE (operands[3]);
15626 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15627 &operands[4], &operands[5]);
15628 if (code == UNKNOWN)
15631 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15632 operands[5], operands[1], operands[2]))
15635 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15636 operands[1], operands[2]);
15637 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15641 /* Expand a signed/unsigned integral vector conditional move. */
15644 ix86_expand_int_vcond (rtx operands[])
15646 enum machine_mode mode = GET_MODE (operands[0]);
15647 enum rtx_code code = GET_CODE (operands[3]);
15648 bool negate = false;
15651 cop0 = operands[4];
15652 cop1 = operands[5];
15654 /* SSE5 supports all of the comparisons on all vector int types. */
15657 /* Canonicalize the comparison to EQ, GT, GTU. */
15668 code = reverse_condition (code);
15674 code = reverse_condition (code);
15680 code = swap_condition (code);
15681 x = cop0, cop0 = cop1, cop1 = x;
15685 gcc_unreachable ();
15688 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15689 if (mode == V2DImode)
15694 /* SSE4.1 supports EQ. */
15695 if (!TARGET_SSE4_1)
15701 /* SSE4.2 supports GT/GTU. */
15702 if (!TARGET_SSE4_2)
15707 gcc_unreachable ();
15711 /* Unsigned parallel compare is not supported by the hardware.
15712 Play some tricks to turn this into a signed comparison
15716 cop0 = force_reg (mode, cop0);
15724 rtx (*gen_sub3) (rtx, rtx, rtx);
15726 /* Subtract (-(INT MAX) - 1) from both operands to make
15728 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15730 gen_sub3 = (mode == V4SImode
15731 ? gen_subv4si3 : gen_subv2di3);
15732 t1 = gen_reg_rtx (mode);
15733 emit_insn (gen_sub3 (t1, cop0, mask));
15735 t2 = gen_reg_rtx (mode);
15736 emit_insn (gen_sub3 (t2, cop1, mask));
15746 /* Perform a parallel unsigned saturating subtraction. */
15747 x = gen_reg_rtx (mode);
15748 emit_insn (gen_rtx_SET (VOIDmode, x,
15749 gen_rtx_US_MINUS (mode, cop0, cop1)));
15752 cop1 = CONST0_RTX (mode);
15758 gcc_unreachable ();
15763 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15764 operands[1+negate], operands[2-negate]);
15766 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15767 operands[2-negate]);
15771 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15772 true if we should do zero extension, else sign extension. HIGH_P is
15773 true if we want the N/2 high elements, else the low elements. */
15776 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15778 enum machine_mode imode = GET_MODE (operands[1]);
15779 rtx (*unpack)(rtx, rtx, rtx);
15786 unpack = gen_vec_interleave_highv16qi;
15788 unpack = gen_vec_interleave_lowv16qi;
15792 unpack = gen_vec_interleave_highv8hi;
15794 unpack = gen_vec_interleave_lowv8hi;
15798 unpack = gen_vec_interleave_highv4si;
15800 unpack = gen_vec_interleave_lowv4si;
15803 gcc_unreachable ();
15806 dest = gen_lowpart (imode, operands[0]);
15809 se = force_reg (imode, CONST0_RTX (imode));
15811 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15812 operands[1], pc_rtx, pc_rtx);
15814 emit_insn (unpack (dest, operands[1], se));
15817 /* This function performs the same task as ix86_expand_sse_unpack,
15818 but with SSE4.1 instructions. */
15821 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15823 enum machine_mode imode = GET_MODE (operands[1]);
15824 rtx (*unpack)(rtx, rtx);
15831 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15833 unpack = gen_sse4_1_extendv8qiv8hi2;
15837 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15839 unpack = gen_sse4_1_extendv4hiv4si2;
15843 unpack = gen_sse4_1_zero_extendv2siv2di2;
15845 unpack = gen_sse4_1_extendv2siv2di2;
15848 gcc_unreachable ();
15851 dest = operands[0];
15854 /* Shift higher 8 bytes to lower 8 bytes. */
15855 src = gen_reg_rtx (imode);
15856 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15857 gen_lowpart (TImode, operands[1]),
15863 emit_insn (unpack (dest, src));
15866 /* This function performs the same task as ix86_expand_sse_unpack,
15867 but with sse5 instructions. */
15870 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15872 enum machine_mode imode = GET_MODE (operands[1]);
15873 int pperm_bytes[16];
15875 int h = (high_p) ? 8 : 0;
15878 rtvec v = rtvec_alloc (16);
15881 rtx op0 = operands[0], op1 = operands[1];
15886 vs = rtvec_alloc (8);
15887 h2 = (high_p) ? 8 : 0;
15888 for (i = 0; i < 8; i++)
15890 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15891 pperm_bytes[2*i+1] = ((unsigned_p)
15893 : PPERM_SIGN | PPERM_SRC2 | i | h);
15896 for (i = 0; i < 16; i++)
15897 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15899 for (i = 0; i < 8; i++)
15900 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15902 p = gen_rtx_PARALLEL (VOIDmode, vs);
15903 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15905 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15907 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15911 vs = rtvec_alloc (4);
15912 h2 = (high_p) ? 4 : 0;
15913 for (i = 0; i < 4; i++)
15915 sign_extend = ((unsigned_p)
15917 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15918 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15919 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15920 pperm_bytes[4*i+2] = sign_extend;
15921 pperm_bytes[4*i+3] = sign_extend;
15924 for (i = 0; i < 16; i++)
15925 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15927 for (i = 0; i < 4; i++)
15928 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15930 p = gen_rtx_PARALLEL (VOIDmode, vs);
15931 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15933 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15935 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15939 vs = rtvec_alloc (2);
15940 h2 = (high_p) ? 2 : 0;
15941 for (i = 0; i < 2; i++)
15943 sign_extend = ((unsigned_p)
15945 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15946 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15947 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15948 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15949 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15950 pperm_bytes[8*i+4] = sign_extend;
15951 pperm_bytes[8*i+5] = sign_extend;
15952 pperm_bytes[8*i+6] = sign_extend;
15953 pperm_bytes[8*i+7] = sign_extend;
15956 for (i = 0; i < 16; i++)
15957 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15959 for (i = 0; i < 2; i++)
15960 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15962 p = gen_rtx_PARALLEL (VOIDmode, vs);
15963 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15965 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15967 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15971 gcc_unreachable ();
15977 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15978 next narrower integer vector type */
15980 ix86_expand_sse5_pack (rtx operands[3])
15982 enum machine_mode imode = GET_MODE (operands[0]);
15983 int pperm_bytes[16];
15985 rtvec v = rtvec_alloc (16);
15987 rtx op0 = operands[0];
15988 rtx op1 = operands[1];
15989 rtx op2 = operands[2];
15994 for (i = 0; i < 8; i++)
15996 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15997 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
16000 for (i = 0; i < 16; i++)
16001 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16003 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16004 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
16008 for (i = 0; i < 4; i++)
16010 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
16011 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
16012 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
16013 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
16016 for (i = 0; i < 16; i++)
16017 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16019 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16020 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
16024 for (i = 0; i < 2; i++)
16026 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
16027 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
16028 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
16029 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
16030 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
16031 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
16032 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
16033 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
16036 for (i = 0; i < 16; i++)
16037 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16039 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16040 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
16044 gcc_unreachable ();
16050 /* Expand conditional increment or decrement using adb/sbb instructions.
16051 The default case using setcc followed by the conditional move can be
16052 done by generic code. */
16054 ix86_expand_int_addcc (rtx operands[])
16056 enum rtx_code code = GET_CODE (operands[1]);
16058 rtx val = const0_rtx;
16059 bool fpcmp = false;
16060 enum machine_mode mode = GET_MODE (operands[0]);
16062 if (operands[3] != const1_rtx
16063 && operands[3] != constm1_rtx)
16065 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16066 ix86_compare_op1, &compare_op))
16068 code = GET_CODE (compare_op);
16070 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16071 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16074 code = ix86_fp_compare_code_to_integer (code);
16081 PUT_CODE (compare_op,
16082 reverse_condition_maybe_unordered
16083 (GET_CODE (compare_op)));
16085 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16087 PUT_MODE (compare_op, mode);
16089 /* Construct either adc or sbb insn. */
16090 if ((code == LTU) == (operands[3] == constm1_rtx))
16092 switch (GET_MODE (operands[0]))
16095 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
16098 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
16101 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
16104 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16107 gcc_unreachable ();
16112 switch (GET_MODE (operands[0]))
16115 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
16118 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
16121 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
16124 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16127 gcc_unreachable ();
16130 return 1; /* DONE */
16134 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16135 works for floating pointer parameters and nonoffsetable memories.
16136 For pushes, it returns just stack offsets; the values will be saved
16137 in the right order. Maximally three parts are generated. */
16140 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16145 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16147 size = (GET_MODE_SIZE (mode) + 4) / 8;
16149 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16150 gcc_assert (size >= 2 && size <= 4);
16152 /* Optimize constant pool reference to immediates. This is used by fp
16153 moves, that force all constants to memory to allow combining. */
16154 if (MEM_P (operand) && MEM_READONLY_P (operand))
16156 rtx tmp = maybe_get_pool_constant (operand);
16161 if (MEM_P (operand) && !offsettable_memref_p (operand))
16163 /* The only non-offsetable memories we handle are pushes. */
16164 int ok = push_operand (operand, VOIDmode);
16168 operand = copy_rtx (operand);
16169 PUT_MODE (operand, Pmode);
16170 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16174 if (GET_CODE (operand) == CONST_VECTOR)
16176 enum machine_mode imode = int_mode_for_mode (mode);
16177 /* Caution: if we looked through a constant pool memory above,
16178 the operand may actually have a different mode now. That's
16179 ok, since we want to pun this all the way back to an integer. */
16180 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16181 gcc_assert (operand != NULL);
16187 if (mode == DImode)
16188 split_di (&operand, 1, &parts[0], &parts[1]);
16193 if (REG_P (operand))
16195 gcc_assert (reload_completed);
16196 for (i = 0; i < size; i++)
16197 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16199 else if (offsettable_memref_p (operand))
16201 operand = adjust_address (operand, SImode, 0);
16202 parts[0] = operand;
16203 for (i = 1; i < size; i++)
16204 parts[i] = adjust_address (operand, SImode, 4 * i);
16206 else if (GET_CODE (operand) == CONST_DOUBLE)
16211 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16215 real_to_target (l, &r, mode);
16216 parts[3] = gen_int_mode (l[3], SImode);
16217 parts[2] = gen_int_mode (l[2], SImode);
16220 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16221 parts[2] = gen_int_mode (l[2], SImode);
16224 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16227 gcc_unreachable ();
16229 parts[1] = gen_int_mode (l[1], SImode);
16230 parts[0] = gen_int_mode (l[0], SImode);
16233 gcc_unreachable ();
16238 if (mode == TImode)
16239 split_ti (&operand, 1, &parts[0], &parts[1]);
16240 if (mode == XFmode || mode == TFmode)
16242 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16243 if (REG_P (operand))
16245 gcc_assert (reload_completed);
16246 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16247 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16249 else if (offsettable_memref_p (operand))
16251 operand = adjust_address (operand, DImode, 0);
16252 parts[0] = operand;
16253 parts[1] = adjust_address (operand, upper_mode, 8);
16255 else if (GET_CODE (operand) == CONST_DOUBLE)
16260 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16261 real_to_target (l, &r, mode);
16263 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16264 if (HOST_BITS_PER_WIDE_INT >= 64)
16267 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16268 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16271 parts[0] = immed_double_const (l[0], l[1], DImode);
16273 if (upper_mode == SImode)
16274 parts[1] = gen_int_mode (l[2], SImode);
16275 else if (HOST_BITS_PER_WIDE_INT >= 64)
16278 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16279 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16282 parts[1] = immed_double_const (l[2], l[3], DImode);
16285 gcc_unreachable ();
16292 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16293 Return false when normal moves are needed; true when all required
16294 insns have been emitted. Operands 2-4 contain the input values
16295 int the correct order; operands 5-7 contain the output values. */
16298 ix86_split_long_move (rtx operands[])
16303 int collisions = 0;
16304 enum machine_mode mode = GET_MODE (operands[0]);
16305 bool collisionparts[4];
16307 /* The DFmode expanders may ask us to move double.
16308 For 64bit target this is single move. By hiding the fact
16309 here we simplify i386.md splitters. */
16310 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16312 /* Optimize constant pool reference to immediates. This is used by
16313 fp moves, that force all constants to memory to allow combining. */
16315 if (MEM_P (operands[1])
16316 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16317 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16318 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16319 if (push_operand (operands[0], VOIDmode))
16321 operands[0] = copy_rtx (operands[0]);
16322 PUT_MODE (operands[0], Pmode);
16325 operands[0] = gen_lowpart (DImode, operands[0]);
16326 operands[1] = gen_lowpart (DImode, operands[1]);
16327 emit_move_insn (operands[0], operands[1]);
16331 /* The only non-offsettable memory we handle is push. */
16332 if (push_operand (operands[0], VOIDmode))
16335 gcc_assert (!MEM_P (operands[0])
16336 || offsettable_memref_p (operands[0]));
16338 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16339 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16341 /* When emitting push, take care for source operands on the stack. */
16342 if (push && MEM_P (operands[1])
16343 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16345 rtx src_base = XEXP (part[1][nparts - 1], 0);
16347 /* Compensate for the stack decrement by 4. */
16348 if (!TARGET_64BIT && nparts == 3
16349 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16350 src_base = plus_constant (src_base, 4);
16352 /* src_base refers to the stack pointer and is
16353 automatically decreased by emitted push. */
16354 for (i = 0; i < nparts; i++)
16355 part[1][i] = change_address (part[1][i],
16356 GET_MODE (part[1][i]), src_base);
16359 /* We need to do copy in the right order in case an address register
16360 of the source overlaps the destination. */
16361 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16365 for (i = 0; i < nparts; i++)
16368 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16369 if (collisionparts[i])
16373 /* Collision in the middle part can be handled by reordering. */
16374 if (collisions == 1 && nparts == 3 && collisionparts [1])
16376 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16377 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16379 else if (collisions == 1
16381 && (collisionparts [1] || collisionparts [2]))
16383 if (collisionparts [1])
16385 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16386 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16390 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16391 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16395 /* If there are more collisions, we can't handle it by reordering.
16396 Do an lea to the last part and use only one colliding move. */
16397 else if (collisions > 1)
16403 base = part[0][nparts - 1];
16405 /* Handle the case when the last part isn't valid for lea.
16406 Happens in 64-bit mode storing the 12-byte XFmode. */
16407 if (GET_MODE (base) != Pmode)
16408 base = gen_rtx_REG (Pmode, REGNO (base));
16410 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16411 part[1][0] = replace_equiv_address (part[1][0], base);
16412 for (i = 1; i < nparts; i++)
16414 tmp = plus_constant (base, UNITS_PER_WORD * i);
16415 part[1][i] = replace_equiv_address (part[1][i], tmp);
16426 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16427 emit_insn (gen_addsi3 (stack_pointer_rtx,
16428 stack_pointer_rtx, GEN_INT (-4)));
16429 emit_move_insn (part[0][2], part[1][2]);
16431 else if (nparts == 4)
16433 emit_move_insn (part[0][3], part[1][3]);
16434 emit_move_insn (part[0][2], part[1][2]);
16439 /* In 64bit mode we don't have 32bit push available. In case this is
16440 register, it is OK - we will just use larger counterpart. We also
16441 retype memory - these comes from attempt to avoid REX prefix on
16442 moving of second half of TFmode value. */
16443 if (GET_MODE (part[1][1]) == SImode)
16445 switch (GET_CODE (part[1][1]))
16448 part[1][1] = adjust_address (part[1][1], DImode, 0);
16452 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16456 gcc_unreachable ();
16459 if (GET_MODE (part[1][0]) == SImode)
16460 part[1][0] = part[1][1];
16463 emit_move_insn (part[0][1], part[1][1]);
16464 emit_move_insn (part[0][0], part[1][0]);
16468 /* Choose correct order to not overwrite the source before it is copied. */
16469 if ((REG_P (part[0][0])
16470 && REG_P (part[1][1])
16471 && (REGNO (part[0][0]) == REGNO (part[1][1])
16473 && REGNO (part[0][0]) == REGNO (part[1][2]))
16475 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16477 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16479 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16481 operands[2 + i] = part[0][j];
16482 operands[6 + i] = part[1][j];
16487 for (i = 0; i < nparts; i++)
16489 operands[2 + i] = part[0][i];
16490 operands[6 + i] = part[1][i];
16494 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16495 if (optimize_insn_for_size_p ())
16497 for (j = 0; j < nparts - 1; j++)
16498 if (CONST_INT_P (operands[6 + j])
16499 && operands[6 + j] != const0_rtx
16500 && REG_P (operands[2 + j]))
16501 for (i = j; i < nparts - 1; i++)
16502 if (CONST_INT_P (operands[7 + i])
16503 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16504 operands[7 + i] = operands[2 + j];
16507 for (i = 0; i < nparts; i++)
16508 emit_move_insn (operands[2 + i], operands[6 + i]);
16513 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16514 left shift by a constant, either using a single shift or
16515 a sequence of add instructions. */
16518 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16522 emit_insn ((mode == DImode
16524 : gen_adddi3) (operand, operand, operand));
16526 else if (!optimize_insn_for_size_p ()
16527 && count * ix86_cost->add <= ix86_cost->shift_const)
16530 for (i=0; i<count; i++)
16532 emit_insn ((mode == DImode
16534 : gen_adddi3) (operand, operand, operand));
16538 emit_insn ((mode == DImode
16540 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16544 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16546 rtx low[2], high[2];
16548 const int single_width = mode == DImode ? 32 : 64;
16550 if (CONST_INT_P (operands[2]))
16552 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16553 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16555 if (count >= single_width)
16557 emit_move_insn (high[0], low[1]);
16558 emit_move_insn (low[0], const0_rtx);
16560 if (count > single_width)
16561 ix86_expand_ashl_const (high[0], count - single_width, mode);
16565 if (!rtx_equal_p (operands[0], operands[1]))
16566 emit_move_insn (operands[0], operands[1]);
16567 emit_insn ((mode == DImode
16569 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16570 ix86_expand_ashl_const (low[0], count, mode);
16575 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16577 if (operands[1] == const1_rtx)
16579 /* Assuming we've chosen a QImode capable registers, then 1 << N
16580 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16581 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16583 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16585 ix86_expand_clear (low[0]);
16586 ix86_expand_clear (high[0]);
16587 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16589 d = gen_lowpart (QImode, low[0]);
16590 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16591 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16592 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16594 d = gen_lowpart (QImode, high[0]);
16595 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16596 s = gen_rtx_NE (QImode, flags, const0_rtx);
16597 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16600 /* Otherwise, we can get the same results by manually performing
16601 a bit extract operation on bit 5/6, and then performing the two
16602 shifts. The two methods of getting 0/1 into low/high are exactly
16603 the same size. Avoiding the shift in the bit extract case helps
16604 pentium4 a bit; no one else seems to care much either way. */
16609 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16610 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16612 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16613 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16615 emit_insn ((mode == DImode
16617 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16618 emit_insn ((mode == DImode
16620 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16621 emit_move_insn (low[0], high[0]);
16622 emit_insn ((mode == DImode
16624 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16627 emit_insn ((mode == DImode
16629 : gen_ashldi3) (low[0], low[0], operands[2]));
16630 emit_insn ((mode == DImode
16632 : gen_ashldi3) (high[0], high[0], operands[2]));
16636 if (operands[1] == constm1_rtx)
16638 /* For -1 << N, we can avoid the shld instruction, because we
16639 know that we're shifting 0...31/63 ones into a -1. */
16640 emit_move_insn (low[0], constm1_rtx);
16641 if (optimize_insn_for_size_p ())
16642 emit_move_insn (high[0], low[0]);
16644 emit_move_insn (high[0], constm1_rtx);
16648 if (!rtx_equal_p (operands[0], operands[1]))
16649 emit_move_insn (operands[0], operands[1]);
16651 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16652 emit_insn ((mode == DImode
16654 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16657 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16659 if (TARGET_CMOVE && scratch)
16661 ix86_expand_clear (scratch);
16662 emit_insn ((mode == DImode
16663 ? gen_x86_shift_adj_1
16664 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16668 emit_insn ((mode == DImode
16669 ? gen_x86_shift_adj_2
16670 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16674 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16676 rtx low[2], high[2];
16678 const int single_width = mode == DImode ? 32 : 64;
16680 if (CONST_INT_P (operands[2]))
16682 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16683 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16685 if (count == single_width * 2 - 1)
16687 emit_move_insn (high[0], high[1]);
16688 emit_insn ((mode == DImode
16690 : gen_ashrdi3) (high[0], high[0],
16691 GEN_INT (single_width - 1)));
16692 emit_move_insn (low[0], high[0]);
16695 else if (count >= single_width)
16697 emit_move_insn (low[0], high[1]);
16698 emit_move_insn (high[0], low[0]);
16699 emit_insn ((mode == DImode
16701 : gen_ashrdi3) (high[0], high[0],
16702 GEN_INT (single_width - 1)));
16703 if (count > single_width)
16704 emit_insn ((mode == DImode
16706 : gen_ashrdi3) (low[0], low[0],
16707 GEN_INT (count - single_width)));
16711 if (!rtx_equal_p (operands[0], operands[1]))
16712 emit_move_insn (operands[0], operands[1]);
16713 emit_insn ((mode == DImode
16715 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16716 emit_insn ((mode == DImode
16718 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16723 if (!rtx_equal_p (operands[0], operands[1]))
16724 emit_move_insn (operands[0], operands[1]);
16726 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16728 emit_insn ((mode == DImode
16730 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16731 emit_insn ((mode == DImode
16733 : gen_ashrdi3) (high[0], high[0], operands[2]));
16735 if (TARGET_CMOVE && scratch)
16737 emit_move_insn (scratch, high[0]);
16738 emit_insn ((mode == DImode
16740 : gen_ashrdi3) (scratch, scratch,
16741 GEN_INT (single_width - 1)));
16742 emit_insn ((mode == DImode
16743 ? gen_x86_shift_adj_1
16744 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16748 emit_insn ((mode == DImode
16749 ? gen_x86_shift_adj_3
16750 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16755 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16757 rtx low[2], high[2];
16759 const int single_width = mode == DImode ? 32 : 64;
16761 if (CONST_INT_P (operands[2]))
16763 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16764 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16766 if (count >= single_width)
16768 emit_move_insn (low[0], high[1]);
16769 ix86_expand_clear (high[0]);
16771 if (count > single_width)
16772 emit_insn ((mode == DImode
16774 : gen_lshrdi3) (low[0], low[0],
16775 GEN_INT (count - single_width)));
16779 if (!rtx_equal_p (operands[0], operands[1]))
16780 emit_move_insn (operands[0], operands[1]);
16781 emit_insn ((mode == DImode
16783 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16784 emit_insn ((mode == DImode
16786 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16791 if (!rtx_equal_p (operands[0], operands[1]))
16792 emit_move_insn (operands[0], operands[1]);
16794 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16796 emit_insn ((mode == DImode
16798 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16799 emit_insn ((mode == DImode
16801 : gen_lshrdi3) (high[0], high[0], operands[2]));
16803 /* Heh. By reversing the arguments, we can reuse this pattern. */
16804 if (TARGET_CMOVE && scratch)
16806 ix86_expand_clear (scratch);
16807 emit_insn ((mode == DImode
16808 ? gen_x86_shift_adj_1
16809 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16813 emit_insn ((mode == DImode
16814 ? gen_x86_shift_adj_2
16815 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16819 /* Predict just emitted jump instruction to be taken with probability PROB. */
16821 predict_jump (int prob)
16823 rtx insn = get_last_insn ();
16824 gcc_assert (JUMP_P (insn));
16826 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16831 /* Helper function for the string operations below. Dest VARIABLE whether
16832 it is aligned to VALUE bytes. If true, jump to the label. */
16834 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16836 rtx label = gen_label_rtx ();
16837 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16838 if (GET_MODE (variable) == DImode)
16839 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16841 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16842 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16845 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16847 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16851 /* Adjust COUNTER by the VALUE. */
16853 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16855 if (GET_MODE (countreg) == DImode)
16856 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16858 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16861 /* Zero extend possibly SImode EXP to Pmode register. */
16863 ix86_zero_extend_to_Pmode (rtx exp)
16866 if (GET_MODE (exp) == VOIDmode)
16867 return force_reg (Pmode, exp);
16868 if (GET_MODE (exp) == Pmode)
16869 return copy_to_mode_reg (Pmode, exp);
16870 r = gen_reg_rtx (Pmode);
16871 emit_insn (gen_zero_extendsidi2 (r, exp));
16875 /* Divide COUNTREG by SCALE. */
16877 scale_counter (rtx countreg, int scale)
16880 rtx piece_size_mask;
16884 if (CONST_INT_P (countreg))
16885 return GEN_INT (INTVAL (countreg) / scale);
16886 gcc_assert (REG_P (countreg));
16888 piece_size_mask = GEN_INT (scale - 1);
16889 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16890 GEN_INT (exact_log2 (scale)),
16891 NULL, 1, OPTAB_DIRECT);
16895 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16896 DImode for constant loop counts. */
16898 static enum machine_mode
16899 counter_mode (rtx count_exp)
16901 if (GET_MODE (count_exp) != VOIDmode)
16902 return GET_MODE (count_exp);
16903 if (GET_CODE (count_exp) != CONST_INT)
16905 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16910 /* When SRCPTR is non-NULL, output simple loop to move memory
16911 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16912 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16913 equivalent loop to set memory by VALUE (supposed to be in MODE).
16915 The size is rounded down to whole number of chunk size moved at once.
16916 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16920 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16921 rtx destptr, rtx srcptr, rtx value,
16922 rtx count, enum machine_mode mode, int unroll,
16925 rtx out_label, top_label, iter, tmp;
16926 enum machine_mode iter_mode = counter_mode (count);
16927 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16928 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16934 top_label = gen_label_rtx ();
16935 out_label = gen_label_rtx ();
16936 iter = gen_reg_rtx (iter_mode);
16938 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16939 NULL, 1, OPTAB_DIRECT);
16940 /* Those two should combine. */
16941 if (piece_size == const1_rtx)
16943 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16945 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16947 emit_move_insn (iter, const0_rtx);
16949 emit_label (top_label);
16951 tmp = convert_modes (Pmode, iter_mode, iter, true);
16952 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16953 destmem = change_address (destmem, mode, x_addr);
16957 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16958 srcmem = change_address (srcmem, mode, y_addr);
16960 /* When unrolling for chips that reorder memory reads and writes,
16961 we can save registers by using single temporary.
16962 Also using 4 temporaries is overkill in 32bit mode. */
16963 if (!TARGET_64BIT && 0)
16965 for (i = 0; i < unroll; i++)
16970 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16972 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16974 emit_move_insn (destmem, srcmem);
16980 gcc_assert (unroll <= 4);
16981 for (i = 0; i < unroll; i++)
16983 tmpreg[i] = gen_reg_rtx (mode);
16987 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16989 emit_move_insn (tmpreg[i], srcmem);
16991 for (i = 0; i < unroll; i++)
16996 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16998 emit_move_insn (destmem, tmpreg[i]);
17003 for (i = 0; i < unroll; i++)
17007 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17008 emit_move_insn (destmem, value);
17011 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17012 true, OPTAB_LIB_WIDEN);
17014 emit_move_insn (iter, tmp);
17016 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17018 if (expected_size != -1)
17020 expected_size /= GET_MODE_SIZE (mode) * unroll;
17021 if (expected_size == 0)
17023 else if (expected_size > REG_BR_PROB_BASE)
17024 predict_jump (REG_BR_PROB_BASE - 1);
17026 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17029 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17030 iter = ix86_zero_extend_to_Pmode (iter);
17031 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17032 true, OPTAB_LIB_WIDEN);
17033 if (tmp != destptr)
17034 emit_move_insn (destptr, tmp);
17037 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17038 true, OPTAB_LIB_WIDEN);
17040 emit_move_insn (srcptr, tmp);
17042 emit_label (out_label);
17045 /* Output "rep; mov" instruction.
17046 Arguments have same meaning as for previous function */
17048 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17049 rtx destptr, rtx srcptr,
17051 enum machine_mode mode)
17057 /* If the size is known, it is shorter to use rep movs. */
17058 if (mode == QImode && CONST_INT_P (count)
17059 && !(INTVAL (count) & 3))
17062 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17063 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17064 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17065 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17066 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17067 if (mode != QImode)
17069 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17070 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17071 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17072 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17073 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17074 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17078 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17079 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17081 if (CONST_INT_P (count))
17083 count = GEN_INT (INTVAL (count)
17084 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17085 destmem = shallow_copy_rtx (destmem);
17086 srcmem = shallow_copy_rtx (srcmem);
17087 set_mem_size (destmem, count);
17088 set_mem_size (srcmem, count);
17092 if (MEM_SIZE (destmem))
17093 set_mem_size (destmem, NULL_RTX);
17094 if (MEM_SIZE (srcmem))
17095 set_mem_size (srcmem, NULL_RTX);
17097 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17101 /* Output "rep; stos" instruction.
17102 Arguments have same meaning as for previous function */
17104 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17105 rtx count, enum machine_mode mode,
17111 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17112 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17113 value = force_reg (mode, gen_lowpart (mode, value));
17114 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17115 if (mode != QImode)
17117 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17118 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17119 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17122 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17123 if (orig_value == const0_rtx && CONST_INT_P (count))
17125 count = GEN_INT (INTVAL (count)
17126 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17127 destmem = shallow_copy_rtx (destmem);
17128 set_mem_size (destmem, count);
17130 else if (MEM_SIZE (destmem))
17131 set_mem_size (destmem, NULL_RTX);
17132 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17136 emit_strmov (rtx destmem, rtx srcmem,
17137 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17139 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17140 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17141 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17144 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17146 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17147 rtx destptr, rtx srcptr, rtx count, int max_size)
17150 if (CONST_INT_P (count))
17152 HOST_WIDE_INT countval = INTVAL (count);
17155 if ((countval & 0x10) && max_size > 16)
17159 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17160 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17163 gcc_unreachable ();
17166 if ((countval & 0x08) && max_size > 8)
17169 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17172 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17173 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17177 if ((countval & 0x04) && max_size > 4)
17179 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17182 if ((countval & 0x02) && max_size > 2)
17184 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17187 if ((countval & 0x01) && max_size > 1)
17189 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17196 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17197 count, 1, OPTAB_DIRECT);
17198 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17199 count, QImode, 1, 4);
17203 /* When there are stringops, we can cheaply increase dest and src pointers.
17204 Otherwise we save code size by maintaining offset (zero is readily
17205 available from preceding rep operation) and using x86 addressing modes.
17207 if (TARGET_SINGLE_STRINGOP)
17211 rtx label = ix86_expand_aligntest (count, 4, true);
17212 src = change_address (srcmem, SImode, srcptr);
17213 dest = change_address (destmem, SImode, destptr);
17214 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17215 emit_label (label);
17216 LABEL_NUSES (label) = 1;
17220 rtx label = ix86_expand_aligntest (count, 2, true);
17221 src = change_address (srcmem, HImode, srcptr);
17222 dest = change_address (destmem, HImode, destptr);
17223 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17224 emit_label (label);
17225 LABEL_NUSES (label) = 1;
17229 rtx label = ix86_expand_aligntest (count, 1, true);
17230 src = change_address (srcmem, QImode, srcptr);
17231 dest = change_address (destmem, QImode, destptr);
17232 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17233 emit_label (label);
17234 LABEL_NUSES (label) = 1;
17239 rtx offset = force_reg (Pmode, const0_rtx);
17244 rtx label = ix86_expand_aligntest (count, 4, true);
17245 src = change_address (srcmem, SImode, srcptr);
17246 dest = change_address (destmem, SImode, destptr);
17247 emit_move_insn (dest, src);
17248 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17249 true, OPTAB_LIB_WIDEN);
17251 emit_move_insn (offset, tmp);
17252 emit_label (label);
17253 LABEL_NUSES (label) = 1;
17257 rtx label = ix86_expand_aligntest (count, 2, true);
17258 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17259 src = change_address (srcmem, HImode, tmp);
17260 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17261 dest = change_address (destmem, HImode, tmp);
17262 emit_move_insn (dest, src);
17263 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17264 true, OPTAB_LIB_WIDEN);
17266 emit_move_insn (offset, tmp);
17267 emit_label (label);
17268 LABEL_NUSES (label) = 1;
17272 rtx label = ix86_expand_aligntest (count, 1, true);
17273 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17274 src = change_address (srcmem, QImode, tmp);
17275 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17276 dest = change_address (destmem, QImode, tmp);
17277 emit_move_insn (dest, src);
17278 emit_label (label);
17279 LABEL_NUSES (label) = 1;
17284 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17286 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17287 rtx count, int max_size)
17290 expand_simple_binop (counter_mode (count), AND, count,
17291 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17292 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17293 gen_lowpart (QImode, value), count, QImode,
17297 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17299 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17303 if (CONST_INT_P (count))
17305 HOST_WIDE_INT countval = INTVAL (count);
17308 if ((countval & 0x10) && max_size > 16)
17312 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17313 emit_insn (gen_strset (destptr, dest, value));
17314 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17315 emit_insn (gen_strset (destptr, dest, value));
17318 gcc_unreachable ();
17321 if ((countval & 0x08) && max_size > 8)
17325 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17326 emit_insn (gen_strset (destptr, dest, value));
17330 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17331 emit_insn (gen_strset (destptr, dest, value));
17332 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17333 emit_insn (gen_strset (destptr, dest, value));
17337 if ((countval & 0x04) && max_size > 4)
17339 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17340 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17343 if ((countval & 0x02) && max_size > 2)
17345 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17346 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17349 if ((countval & 0x01) && max_size > 1)
17351 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17352 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17359 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17364 rtx label = ix86_expand_aligntest (count, 16, true);
17367 dest = change_address (destmem, DImode, destptr);
17368 emit_insn (gen_strset (destptr, dest, value));
17369 emit_insn (gen_strset (destptr, dest, value));
17373 dest = change_address (destmem, SImode, destptr);
17374 emit_insn (gen_strset (destptr, dest, value));
17375 emit_insn (gen_strset (destptr, dest, value));
17376 emit_insn (gen_strset (destptr, dest, value));
17377 emit_insn (gen_strset (destptr, dest, value));
17379 emit_label (label);
17380 LABEL_NUSES (label) = 1;
17384 rtx label = ix86_expand_aligntest (count, 8, true);
17387 dest = change_address (destmem, DImode, destptr);
17388 emit_insn (gen_strset (destptr, dest, value));
17392 dest = change_address (destmem, SImode, destptr);
17393 emit_insn (gen_strset (destptr, dest, value));
17394 emit_insn (gen_strset (destptr, dest, value));
17396 emit_label (label);
17397 LABEL_NUSES (label) = 1;
17401 rtx label = ix86_expand_aligntest (count, 4, true);
17402 dest = change_address (destmem, SImode, destptr);
17403 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17404 emit_label (label);
17405 LABEL_NUSES (label) = 1;
17409 rtx label = ix86_expand_aligntest (count, 2, true);
17410 dest = change_address (destmem, HImode, destptr);
17411 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17412 emit_label (label);
17413 LABEL_NUSES (label) = 1;
17417 rtx label = ix86_expand_aligntest (count, 1, true);
17418 dest = change_address (destmem, QImode, destptr);
17419 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17420 emit_label (label);
17421 LABEL_NUSES (label) = 1;
17425 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17426 DESIRED_ALIGNMENT. */
17428 expand_movmem_prologue (rtx destmem, rtx srcmem,
17429 rtx destptr, rtx srcptr, rtx count,
17430 int align, int desired_alignment)
17432 if (align <= 1 && desired_alignment > 1)
17434 rtx label = ix86_expand_aligntest (destptr, 1, false);
17435 srcmem = change_address (srcmem, QImode, srcptr);
17436 destmem = change_address (destmem, QImode, destptr);
17437 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17438 ix86_adjust_counter (count, 1);
17439 emit_label (label);
17440 LABEL_NUSES (label) = 1;
17442 if (align <= 2 && desired_alignment > 2)
17444 rtx label = ix86_expand_aligntest (destptr, 2, false);
17445 srcmem = change_address (srcmem, HImode, srcptr);
17446 destmem = change_address (destmem, HImode, destptr);
17447 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17448 ix86_adjust_counter (count, 2);
17449 emit_label (label);
17450 LABEL_NUSES (label) = 1;
17452 if (align <= 4 && desired_alignment > 4)
17454 rtx label = ix86_expand_aligntest (destptr, 4, false);
17455 srcmem = change_address (srcmem, SImode, srcptr);
17456 destmem = change_address (destmem, SImode, destptr);
17457 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17458 ix86_adjust_counter (count, 4);
17459 emit_label (label);
17460 LABEL_NUSES (label) = 1;
17462 gcc_assert (desired_alignment <= 8);
17465 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17466 ALIGN_BYTES is how many bytes need to be copied. */
17468 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17469 int desired_align, int align_bytes)
17472 rtx src_size, dst_size;
17474 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17475 if (src_align_bytes >= 0)
17476 src_align_bytes = desired_align - src_align_bytes;
17477 src_size = MEM_SIZE (src);
17478 dst_size = MEM_SIZE (dst);
17479 if (align_bytes & 1)
17481 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17482 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17484 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17486 if (align_bytes & 2)
17488 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17489 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17490 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17491 set_mem_align (dst, 2 * BITS_PER_UNIT);
17492 if (src_align_bytes >= 0
17493 && (src_align_bytes & 1) == (align_bytes & 1)
17494 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17495 set_mem_align (src, 2 * BITS_PER_UNIT);
17497 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17499 if (align_bytes & 4)
17501 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17502 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17503 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17504 set_mem_align (dst, 4 * BITS_PER_UNIT);
17505 if (src_align_bytes >= 0)
17507 unsigned int src_align = 0;
17508 if ((src_align_bytes & 3) == (align_bytes & 3))
17510 else if ((src_align_bytes & 1) == (align_bytes & 1))
17512 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17513 set_mem_align (src, src_align * BITS_PER_UNIT);
17516 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17518 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17519 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17520 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17521 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17522 if (src_align_bytes >= 0)
17524 unsigned int src_align = 0;
17525 if ((src_align_bytes & 7) == (align_bytes & 7))
17527 else if ((src_align_bytes & 3) == (align_bytes & 3))
17529 else if ((src_align_bytes & 1) == (align_bytes & 1))
17531 if (src_align > (unsigned int) desired_align)
17532 src_align = desired_align;
17533 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17534 set_mem_align (src, src_align * BITS_PER_UNIT);
17537 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17539 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17544 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17545 DESIRED_ALIGNMENT. */
17547 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17548 int align, int desired_alignment)
17550 if (align <= 1 && desired_alignment > 1)
17552 rtx label = ix86_expand_aligntest (destptr, 1, false);
17553 destmem = change_address (destmem, QImode, destptr);
17554 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17555 ix86_adjust_counter (count, 1);
17556 emit_label (label);
17557 LABEL_NUSES (label) = 1;
17559 if (align <= 2 && desired_alignment > 2)
17561 rtx label = ix86_expand_aligntest (destptr, 2, false);
17562 destmem = change_address (destmem, HImode, destptr);
17563 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17564 ix86_adjust_counter (count, 2);
17565 emit_label (label);
17566 LABEL_NUSES (label) = 1;
17568 if (align <= 4 && desired_alignment > 4)
17570 rtx label = ix86_expand_aligntest (destptr, 4, false);
17571 destmem = change_address (destmem, SImode, destptr);
17572 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17573 ix86_adjust_counter (count, 4);
17574 emit_label (label);
17575 LABEL_NUSES (label) = 1;
17577 gcc_assert (desired_alignment <= 8);
17580 /* Set enough from DST to align DST known to by aligned by ALIGN to
17581 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17583 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17584 int desired_align, int align_bytes)
17587 rtx dst_size = MEM_SIZE (dst);
17588 if (align_bytes & 1)
17590 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17592 emit_insn (gen_strset (destreg, dst,
17593 gen_lowpart (QImode, value)));
17595 if (align_bytes & 2)
17597 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17598 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17599 set_mem_align (dst, 2 * BITS_PER_UNIT);
17601 emit_insn (gen_strset (destreg, dst,
17602 gen_lowpart (HImode, value)));
17604 if (align_bytes & 4)
17606 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17607 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17608 set_mem_align (dst, 4 * BITS_PER_UNIT);
17610 emit_insn (gen_strset (destreg, dst,
17611 gen_lowpart (SImode, value)));
17613 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17614 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17615 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17617 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17621 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17622 static enum stringop_alg
17623 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17624 int *dynamic_check)
17626 const struct stringop_algs * algs;
17627 bool optimize_for_speed;
17628 /* Algorithms using the rep prefix want at least edi and ecx;
17629 additionally, memset wants eax and memcpy wants esi. Don't
17630 consider such algorithms if the user has appropriated those
17631 registers for their own purposes. */
17632 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17634 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17636 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17637 || (alg != rep_prefix_1_byte \
17638 && alg != rep_prefix_4_byte \
17639 && alg != rep_prefix_8_byte))
17640 const struct processor_costs *cost;
17642 /* Even if the string operation call is cold, we still might spend a lot
17643 of time processing large blocks. */
17644 if (optimize_function_for_size_p (cfun)
17645 || (optimize_insn_for_size_p ()
17646 && expected_size != -1 && expected_size < 256))
17647 optimize_for_speed = false;
17649 optimize_for_speed = true;
17651 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17653 *dynamic_check = -1;
17655 algs = &cost->memset[TARGET_64BIT != 0];
17657 algs = &cost->memcpy[TARGET_64BIT != 0];
17658 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17659 return stringop_alg;
17660 /* rep; movq or rep; movl is the smallest variant. */
17661 else if (!optimize_for_speed)
17663 if (!count || (count & 3))
17664 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17666 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17668 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17670 else if (expected_size != -1 && expected_size < 4)
17671 return loop_1_byte;
17672 else if (expected_size != -1)
17675 enum stringop_alg alg = libcall;
17676 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17678 /* We get here if the algorithms that were not libcall-based
17679 were rep-prefix based and we are unable to use rep prefixes
17680 based on global register usage. Break out of the loop and
17681 use the heuristic below. */
17682 if (algs->size[i].max == 0)
17684 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17686 enum stringop_alg candidate = algs->size[i].alg;
17688 if (candidate != libcall && ALG_USABLE_P (candidate))
17690 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17691 last non-libcall inline algorithm. */
17692 if (TARGET_INLINE_ALL_STRINGOPS)
17694 /* When the current size is best to be copied by a libcall,
17695 but we are still forced to inline, run the heuristic below
17696 that will pick code for medium sized blocks. */
17697 if (alg != libcall)
17701 else if (ALG_USABLE_P (candidate))
17705 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17707 /* When asked to inline the call anyway, try to pick meaningful choice.
17708 We look for maximal size of block that is faster to copy by hand and
17709 take blocks of at most of that size guessing that average size will
17710 be roughly half of the block.
17712 If this turns out to be bad, we might simply specify the preferred
17713 choice in ix86_costs. */
17714 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17715 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17718 enum stringop_alg alg;
17720 bool any_alg_usable_p = true;
17722 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17724 enum stringop_alg candidate = algs->size[i].alg;
17725 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17727 if (candidate != libcall && candidate
17728 && ALG_USABLE_P (candidate))
17729 max = algs->size[i].max;
17731 /* If there aren't any usable algorithms, then recursing on
17732 smaller sizes isn't going to find anything. Just return the
17733 simple byte-at-a-time copy loop. */
17734 if (!any_alg_usable_p)
17736 /* Pick something reasonable. */
17737 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17738 *dynamic_check = 128;
17739 return loop_1_byte;
17743 alg = decide_alg (count, max / 2, memset, dynamic_check);
17744 gcc_assert (*dynamic_check == -1);
17745 gcc_assert (alg != libcall);
17746 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17747 *dynamic_check = max;
17750 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17751 #undef ALG_USABLE_P
17754 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17755 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17757 decide_alignment (int align,
17758 enum stringop_alg alg,
17761 int desired_align = 0;
17765 gcc_unreachable ();
17767 case unrolled_loop:
17768 desired_align = GET_MODE_SIZE (Pmode);
17770 case rep_prefix_8_byte:
17773 case rep_prefix_4_byte:
17774 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17775 copying whole cacheline at once. */
17776 if (TARGET_PENTIUMPRO)
17781 case rep_prefix_1_byte:
17782 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17783 copying whole cacheline at once. */
17784 if (TARGET_PENTIUMPRO)
17798 if (desired_align < align)
17799 desired_align = align;
17800 if (expected_size != -1 && expected_size < 4)
17801 desired_align = align;
17802 return desired_align;
17805 /* Return the smallest power of 2 greater than VAL. */
17807 smallest_pow2_greater_than (int val)
17815 /* Expand string move (memcpy) operation. Use i386 string operations when
17816 profitable. expand_setmem contains similar code. The code depends upon
17817 architecture, block size and alignment, but always has the same
17820 1) Prologue guard: Conditional that jumps up to epilogues for small
17821 blocks that can be handled by epilogue alone. This is faster but
17822 also needed for correctness, since prologue assume the block is larger
17823 than the desired alignment.
17825 Optional dynamic check for size and libcall for large
17826 blocks is emitted here too, with -minline-stringops-dynamically.
17828 2) Prologue: copy first few bytes in order to get destination aligned
17829 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17830 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17831 We emit either a jump tree on power of two sized blocks, or a byte loop.
17833 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17834 with specified algorithm.
17836 4) Epilogue: code copying tail of the block that is too small to be
17837 handled by main body (or up to size guarded by prologue guard). */
17840 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17841 rtx expected_align_exp, rtx expected_size_exp)
17847 rtx jump_around_label = NULL;
17848 HOST_WIDE_INT align = 1;
17849 unsigned HOST_WIDE_INT count = 0;
17850 HOST_WIDE_INT expected_size = -1;
17851 int size_needed = 0, epilogue_size_needed;
17852 int desired_align = 0, align_bytes = 0;
17853 enum stringop_alg alg;
17855 bool need_zero_guard = false;
17857 if (CONST_INT_P (align_exp))
17858 align = INTVAL (align_exp);
17859 /* i386 can do misaligned access on reasonably increased cost. */
17860 if (CONST_INT_P (expected_align_exp)
17861 && INTVAL (expected_align_exp) > align)
17862 align = INTVAL (expected_align_exp);
17863 /* ALIGN is the minimum of destination and source alignment, but we care here
17864 just about destination alignment. */
17865 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17866 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17868 if (CONST_INT_P (count_exp))
17869 count = expected_size = INTVAL (count_exp);
17870 if (CONST_INT_P (expected_size_exp) && count == 0)
17871 expected_size = INTVAL (expected_size_exp);
17873 /* Make sure we don't need to care about overflow later on. */
17874 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17877 /* Step 0: Decide on preferred algorithm, desired alignment and
17878 size of chunks to be copied by main loop. */
17880 alg = decide_alg (count, expected_size, false, &dynamic_check);
17881 desired_align = decide_alignment (align, alg, expected_size);
17883 if (!TARGET_ALIGN_STRINGOPS)
17884 align = desired_align;
17886 if (alg == libcall)
17888 gcc_assert (alg != no_stringop);
17890 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17891 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17892 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17897 gcc_unreachable ();
17899 need_zero_guard = true;
17900 size_needed = GET_MODE_SIZE (Pmode);
17902 case unrolled_loop:
17903 need_zero_guard = true;
17904 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17906 case rep_prefix_8_byte:
17909 case rep_prefix_4_byte:
17912 case rep_prefix_1_byte:
17916 need_zero_guard = true;
17921 epilogue_size_needed = size_needed;
17923 /* Step 1: Prologue guard. */
17925 /* Alignment code needs count to be in register. */
17926 if (CONST_INT_P (count_exp) && desired_align > align)
17928 if (INTVAL (count_exp) > desired_align
17929 && INTVAL (count_exp) > size_needed)
17932 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17933 if (align_bytes <= 0)
17936 align_bytes = desired_align - align_bytes;
17938 if (align_bytes == 0)
17939 count_exp = force_reg (counter_mode (count_exp), count_exp);
17941 gcc_assert (desired_align >= 1 && align >= 1);
17943 /* Ensure that alignment prologue won't copy past end of block. */
17944 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17946 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17947 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17948 Make sure it is power of 2. */
17949 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17953 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17955 /* If main algorithm works on QImode, no epilogue is needed.
17956 For small sizes just don't align anything. */
17957 if (size_needed == 1)
17958 desired_align = align;
17965 label = gen_label_rtx ();
17966 emit_cmp_and_jump_insns (count_exp,
17967 GEN_INT (epilogue_size_needed),
17968 LTU, 0, counter_mode (count_exp), 1, label);
17969 if (expected_size == -1 || expected_size < epilogue_size_needed)
17970 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17972 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17976 /* Emit code to decide on runtime whether library call or inline should be
17978 if (dynamic_check != -1)
17980 if (CONST_INT_P (count_exp))
17982 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17984 emit_block_move_via_libcall (dst, src, count_exp, false);
17985 count_exp = const0_rtx;
17991 rtx hot_label = gen_label_rtx ();
17992 jump_around_label = gen_label_rtx ();
17993 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17994 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17995 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17996 emit_block_move_via_libcall (dst, src, count_exp, false);
17997 emit_jump (jump_around_label);
17998 emit_label (hot_label);
18002 /* Step 2: Alignment prologue. */
18004 if (desired_align > align)
18006 if (align_bytes == 0)
18008 /* Except for the first move in epilogue, we no longer know
18009 constant offset in aliasing info. It don't seems to worth
18010 the pain to maintain it for the first move, so throw away
18012 src = change_address (src, BLKmode, srcreg);
18013 dst = change_address (dst, BLKmode, destreg);
18014 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18019 /* If we know how many bytes need to be stored before dst is
18020 sufficiently aligned, maintain aliasing info accurately. */
18021 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18022 desired_align, align_bytes);
18023 count_exp = plus_constant (count_exp, -align_bytes);
18024 count -= align_bytes;
18026 if (need_zero_guard
18027 && (count < (unsigned HOST_WIDE_INT) size_needed
18028 || (align_bytes == 0
18029 && count < ((unsigned HOST_WIDE_INT) size_needed
18030 + desired_align - align))))
18032 /* It is possible that we copied enough so the main loop will not
18034 gcc_assert (size_needed > 1);
18035 if (label == NULL_RTX)
18036 label = gen_label_rtx ();
18037 emit_cmp_and_jump_insns (count_exp,
18038 GEN_INT (size_needed),
18039 LTU, 0, counter_mode (count_exp), 1, label);
18040 if (expected_size == -1
18041 || expected_size < (desired_align - align) / 2 + size_needed)
18042 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18044 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18047 if (label && size_needed == 1)
18049 emit_label (label);
18050 LABEL_NUSES (label) = 1;
18052 epilogue_size_needed = 1;
18054 else if (label == NULL_RTX)
18055 epilogue_size_needed = size_needed;
18057 /* Step 3: Main loop. */
18063 gcc_unreachable ();
18065 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18066 count_exp, QImode, 1, expected_size);
18069 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18070 count_exp, Pmode, 1, expected_size);
18072 case unrolled_loop:
18073 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18074 registers for 4 temporaries anyway. */
18075 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18076 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18079 case rep_prefix_8_byte:
18080 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18083 case rep_prefix_4_byte:
18084 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18087 case rep_prefix_1_byte:
18088 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18092 /* Adjust properly the offset of src and dest memory for aliasing. */
18093 if (CONST_INT_P (count_exp))
18095 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18096 (count / size_needed) * size_needed);
18097 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18098 (count / size_needed) * size_needed);
18102 src = change_address (src, BLKmode, srcreg);
18103 dst = change_address (dst, BLKmode, destreg);
18106 /* Step 4: Epilogue to copy the remaining bytes. */
18110 /* When the main loop is done, COUNT_EXP might hold original count,
18111 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18112 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18113 bytes. Compensate if needed. */
18115 if (size_needed < epilogue_size_needed)
18118 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18119 GEN_INT (size_needed - 1), count_exp, 1,
18121 if (tmp != count_exp)
18122 emit_move_insn (count_exp, tmp);
18124 emit_label (label);
18125 LABEL_NUSES (label) = 1;
18128 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18129 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18130 epilogue_size_needed);
18131 if (jump_around_label)
18132 emit_label (jump_around_label);
18136 /* Helper function for memcpy. For QImode value 0xXY produce
18137 0xXYXYXYXY of wide specified by MODE. This is essentially
18138 a * 0x10101010, but we can do slightly better than
18139 synth_mult by unwinding the sequence by hand on CPUs with
18142 promote_duplicated_reg (enum machine_mode mode, rtx val)
18144 enum machine_mode valmode = GET_MODE (val);
18146 int nops = mode == DImode ? 3 : 2;
18148 gcc_assert (mode == SImode || mode == DImode);
18149 if (val == const0_rtx)
18150 return copy_to_mode_reg (mode, const0_rtx);
18151 if (CONST_INT_P (val))
18153 HOST_WIDE_INT v = INTVAL (val) & 255;
18157 if (mode == DImode)
18158 v |= (v << 16) << 16;
18159 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18162 if (valmode == VOIDmode)
18164 if (valmode != QImode)
18165 val = gen_lowpart (QImode, val);
18166 if (mode == QImode)
18168 if (!TARGET_PARTIAL_REG_STALL)
18170 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18171 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18172 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18173 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18175 rtx reg = convert_modes (mode, QImode, val, true);
18176 tmp = promote_duplicated_reg (mode, const1_rtx);
18177 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18182 rtx reg = convert_modes (mode, QImode, val, true);
18184 if (!TARGET_PARTIAL_REG_STALL)
18185 if (mode == SImode)
18186 emit_insn (gen_movsi_insv_1 (reg, reg));
18188 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18191 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18192 NULL, 1, OPTAB_DIRECT);
18194 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18196 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18197 NULL, 1, OPTAB_DIRECT);
18198 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18199 if (mode == SImode)
18201 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18202 NULL, 1, OPTAB_DIRECT);
18203 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18208 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18209 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18210 alignment from ALIGN to DESIRED_ALIGN. */
18212 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18217 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18218 promoted_val = promote_duplicated_reg (DImode, val);
18219 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18220 promoted_val = promote_duplicated_reg (SImode, val);
18221 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18222 promoted_val = promote_duplicated_reg (HImode, val);
18224 promoted_val = val;
18226 return promoted_val;
18229 /* Expand string clear operation (bzero). Use i386 string operations when
18230 profitable. See expand_movmem comment for explanation of individual
18231 steps performed. */
18233 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18234 rtx expected_align_exp, rtx expected_size_exp)
18239 rtx jump_around_label = NULL;
18240 HOST_WIDE_INT align = 1;
18241 unsigned HOST_WIDE_INT count = 0;
18242 HOST_WIDE_INT expected_size = -1;
18243 int size_needed = 0, epilogue_size_needed;
18244 int desired_align = 0, align_bytes = 0;
18245 enum stringop_alg alg;
18246 rtx promoted_val = NULL;
18247 bool force_loopy_epilogue = false;
18249 bool need_zero_guard = false;
18251 if (CONST_INT_P (align_exp))
18252 align = INTVAL (align_exp);
18253 /* i386 can do misaligned access on reasonably increased cost. */
18254 if (CONST_INT_P (expected_align_exp)
18255 && INTVAL (expected_align_exp) > align)
18256 align = INTVAL (expected_align_exp);
18257 if (CONST_INT_P (count_exp))
18258 count = expected_size = INTVAL (count_exp);
18259 if (CONST_INT_P (expected_size_exp) && count == 0)
18260 expected_size = INTVAL (expected_size_exp);
18262 /* Make sure we don't need to care about overflow later on. */
18263 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18266 /* Step 0: Decide on preferred algorithm, desired alignment and
18267 size of chunks to be copied by main loop. */
18269 alg = decide_alg (count, expected_size, true, &dynamic_check);
18270 desired_align = decide_alignment (align, alg, expected_size);
18272 if (!TARGET_ALIGN_STRINGOPS)
18273 align = desired_align;
18275 if (alg == libcall)
18277 gcc_assert (alg != no_stringop);
18279 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18280 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18285 gcc_unreachable ();
18287 need_zero_guard = true;
18288 size_needed = GET_MODE_SIZE (Pmode);
18290 case unrolled_loop:
18291 need_zero_guard = true;
18292 size_needed = GET_MODE_SIZE (Pmode) * 4;
18294 case rep_prefix_8_byte:
18297 case rep_prefix_4_byte:
18300 case rep_prefix_1_byte:
18304 need_zero_guard = true;
18308 epilogue_size_needed = size_needed;
18310 /* Step 1: Prologue guard. */
18312 /* Alignment code needs count to be in register. */
18313 if (CONST_INT_P (count_exp) && desired_align > align)
18315 if (INTVAL (count_exp) > desired_align
18316 && INTVAL (count_exp) > size_needed)
18319 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18320 if (align_bytes <= 0)
18323 align_bytes = desired_align - align_bytes;
18325 if (align_bytes == 0)
18327 enum machine_mode mode = SImode;
18328 if (TARGET_64BIT && (count & ~0xffffffff))
18330 count_exp = force_reg (mode, count_exp);
18333 /* Do the cheap promotion to allow better CSE across the
18334 main loop and epilogue (ie one load of the big constant in the
18335 front of all code. */
18336 if (CONST_INT_P (val_exp))
18337 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18338 desired_align, align);
18339 /* Ensure that alignment prologue won't copy past end of block. */
18340 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18342 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18343 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18344 Make sure it is power of 2. */
18345 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18347 /* To improve performance of small blocks, we jump around the VAL
18348 promoting mode. This mean that if the promoted VAL is not constant,
18349 we might not use it in the epilogue and have to use byte
18351 if (epilogue_size_needed > 2 && !promoted_val)
18352 force_loopy_epilogue = true;
18355 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18357 /* If main algorithm works on QImode, no epilogue is needed.
18358 For small sizes just don't align anything. */
18359 if (size_needed == 1)
18360 desired_align = align;
18367 label = gen_label_rtx ();
18368 emit_cmp_and_jump_insns (count_exp,
18369 GEN_INT (epilogue_size_needed),
18370 LTU, 0, counter_mode (count_exp), 1, label);
18371 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18372 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18374 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18377 if (dynamic_check != -1)
18379 rtx hot_label = gen_label_rtx ();
18380 jump_around_label = gen_label_rtx ();
18381 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18382 LEU, 0, counter_mode (count_exp), 1, hot_label);
18383 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18384 set_storage_via_libcall (dst, count_exp, val_exp, false);
18385 emit_jump (jump_around_label);
18386 emit_label (hot_label);
18389 /* Step 2: Alignment prologue. */
18391 /* Do the expensive promotion once we branched off the small blocks. */
18393 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18394 desired_align, align);
18395 gcc_assert (desired_align >= 1 && align >= 1);
18397 if (desired_align > align)
18399 if (align_bytes == 0)
18401 /* Except for the first move in epilogue, we no longer know
18402 constant offset in aliasing info. It don't seems to worth
18403 the pain to maintain it for the first move, so throw away
18405 dst = change_address (dst, BLKmode, destreg);
18406 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18411 /* If we know how many bytes need to be stored before dst is
18412 sufficiently aligned, maintain aliasing info accurately. */
18413 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18414 desired_align, align_bytes);
18415 count_exp = plus_constant (count_exp, -align_bytes);
18416 count -= align_bytes;
18418 if (need_zero_guard
18419 && (count < (unsigned HOST_WIDE_INT) size_needed
18420 || (align_bytes == 0
18421 && count < ((unsigned HOST_WIDE_INT) size_needed
18422 + desired_align - align))))
18424 /* It is possible that we copied enough so the main loop will not
18426 gcc_assert (size_needed > 1);
18427 if (label == NULL_RTX)
18428 label = gen_label_rtx ();
18429 emit_cmp_and_jump_insns (count_exp,
18430 GEN_INT (size_needed),
18431 LTU, 0, counter_mode (count_exp), 1, label);
18432 if (expected_size == -1
18433 || expected_size < (desired_align - align) / 2 + size_needed)
18434 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18436 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18439 if (label && size_needed == 1)
18441 emit_label (label);
18442 LABEL_NUSES (label) = 1;
18444 promoted_val = val_exp;
18445 epilogue_size_needed = 1;
18447 else if (label == NULL_RTX)
18448 epilogue_size_needed = size_needed;
18450 /* Step 3: Main loop. */
18456 gcc_unreachable ();
18458 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18459 count_exp, QImode, 1, expected_size);
18462 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18463 count_exp, Pmode, 1, expected_size);
18465 case unrolled_loop:
18466 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18467 count_exp, Pmode, 4, expected_size);
18469 case rep_prefix_8_byte:
18470 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18473 case rep_prefix_4_byte:
18474 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18477 case rep_prefix_1_byte:
18478 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18482 /* Adjust properly the offset of src and dest memory for aliasing. */
18483 if (CONST_INT_P (count_exp))
18484 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18485 (count / size_needed) * size_needed);
18487 dst = change_address (dst, BLKmode, destreg);
18489 /* Step 4: Epilogue to copy the remaining bytes. */
18493 /* When the main loop is done, COUNT_EXP might hold original count,
18494 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18495 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18496 bytes. Compensate if needed. */
18498 if (size_needed < epilogue_size_needed)
18501 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18502 GEN_INT (size_needed - 1), count_exp, 1,
18504 if (tmp != count_exp)
18505 emit_move_insn (count_exp, tmp);
18507 emit_label (label);
18508 LABEL_NUSES (label) = 1;
18511 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18513 if (force_loopy_epilogue)
18514 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18515 epilogue_size_needed);
18517 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18518 epilogue_size_needed);
18520 if (jump_around_label)
18521 emit_label (jump_around_label);
18525 /* Expand the appropriate insns for doing strlen if not just doing
18528 out = result, initialized with the start address
18529 align_rtx = alignment of the address.
18530 scratch = scratch register, initialized with the startaddress when
18531 not aligned, otherwise undefined
18533 This is just the body. It needs the initializations mentioned above and
18534 some address computing at the end. These things are done in i386.md. */
18537 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18541 rtx align_2_label = NULL_RTX;
18542 rtx align_3_label = NULL_RTX;
18543 rtx align_4_label = gen_label_rtx ();
18544 rtx end_0_label = gen_label_rtx ();
18546 rtx tmpreg = gen_reg_rtx (SImode);
18547 rtx scratch = gen_reg_rtx (SImode);
18551 if (CONST_INT_P (align_rtx))
18552 align = INTVAL (align_rtx);
18554 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18556 /* Is there a known alignment and is it less than 4? */
18559 rtx scratch1 = gen_reg_rtx (Pmode);
18560 emit_move_insn (scratch1, out);
18561 /* Is there a known alignment and is it not 2? */
18564 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18565 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18567 /* Leave just the 3 lower bits. */
18568 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18569 NULL_RTX, 0, OPTAB_WIDEN);
18571 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18572 Pmode, 1, align_4_label);
18573 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18574 Pmode, 1, align_2_label);
18575 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18576 Pmode, 1, align_3_label);
18580 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18581 check if is aligned to 4 - byte. */
18583 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18584 NULL_RTX, 0, OPTAB_WIDEN);
18586 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18587 Pmode, 1, align_4_label);
18590 mem = change_address (src, QImode, out);
18592 /* Now compare the bytes. */
18594 /* Compare the first n unaligned byte on a byte per byte basis. */
18595 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18596 QImode, 1, end_0_label);
18598 /* Increment the address. */
18599 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18601 /* Not needed with an alignment of 2 */
18604 emit_label (align_2_label);
18606 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18609 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18611 emit_label (align_3_label);
18614 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18617 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18620 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18621 align this loop. It gives only huge programs, but does not help to
18623 emit_label (align_4_label);
18625 mem = change_address (src, SImode, out);
18626 emit_move_insn (scratch, mem);
18627 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18629 /* This formula yields a nonzero result iff one of the bytes is zero.
18630 This saves three branches inside loop and many cycles. */
18632 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18633 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18634 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18635 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18636 gen_int_mode (0x80808080, SImode)));
18637 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18642 rtx reg = gen_reg_rtx (SImode);
18643 rtx reg2 = gen_reg_rtx (Pmode);
18644 emit_move_insn (reg, tmpreg);
18645 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18647 /* If zero is not in the first two bytes, move two bytes forward. */
18648 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18649 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18650 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18651 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18652 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18655 /* Emit lea manually to avoid clobbering of flags. */
18656 emit_insn (gen_rtx_SET (SImode, reg2,
18657 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18659 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18660 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18661 emit_insn (gen_rtx_SET (VOIDmode, out,
18662 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18669 rtx end_2_label = gen_label_rtx ();
18670 /* Is zero in the first two bytes? */
18672 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18673 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18674 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18675 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18676 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18678 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18679 JUMP_LABEL (tmp) = end_2_label;
18681 /* Not in the first two. Move two bytes forward. */
18682 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18683 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18685 emit_label (end_2_label);
18689 /* Avoid branch in fixing the byte. */
18690 tmpreg = gen_lowpart (QImode, tmpreg);
18691 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18692 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18693 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18695 emit_label (end_0_label);
18698 /* Expand strlen. */
18701 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18703 rtx addr, scratch1, scratch2, scratch3, scratch4;
18705 /* The generic case of strlen expander is long. Avoid it's
18706 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18708 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18709 && !TARGET_INLINE_ALL_STRINGOPS
18710 && !optimize_insn_for_size_p ()
18711 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18714 addr = force_reg (Pmode, XEXP (src, 0));
18715 scratch1 = gen_reg_rtx (Pmode);
18717 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18718 && !optimize_insn_for_size_p ())
18720 /* Well it seems that some optimizer does not combine a call like
18721 foo(strlen(bar), strlen(bar));
18722 when the move and the subtraction is done here. It does calculate
18723 the length just once when these instructions are done inside of
18724 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18725 often used and I use one fewer register for the lifetime of
18726 output_strlen_unroll() this is better. */
18728 emit_move_insn (out, addr);
18730 ix86_expand_strlensi_unroll_1 (out, src, align);
18732 /* strlensi_unroll_1 returns the address of the zero at the end of
18733 the string, like memchr(), so compute the length by subtracting
18734 the start address. */
18735 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18741 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18742 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18745 scratch2 = gen_reg_rtx (Pmode);
18746 scratch3 = gen_reg_rtx (Pmode);
18747 scratch4 = force_reg (Pmode, constm1_rtx);
18749 emit_move_insn (scratch3, addr);
18750 eoschar = force_reg (QImode, eoschar);
18752 src = replace_equiv_address_nv (src, scratch3);
18754 /* If .md starts supporting :P, this can be done in .md. */
18755 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18756 scratch4), UNSPEC_SCAS);
18757 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18758 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18759 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18764 /* For given symbol (function) construct code to compute address of it's PLT
18765 entry in large x86-64 PIC model. */
18767 construct_plt_address (rtx symbol)
18769 rtx tmp = gen_reg_rtx (Pmode);
18770 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18772 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18773 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18775 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18776 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18781 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18783 rtx pop, int sibcall)
18785 rtx use = NULL, call;
18787 if (pop == const0_rtx)
18789 gcc_assert (!TARGET_64BIT || !pop);
18791 if (TARGET_MACHO && !TARGET_64BIT)
18794 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18795 fnaddr = machopic_indirect_call_target (fnaddr);
18800 /* Static functions and indirect calls don't need the pic register. */
18801 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18802 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18803 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18804 use_reg (&use, pic_offset_table_rtx);
18807 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18809 rtx al = gen_rtx_REG (QImode, AX_REG);
18810 emit_move_insn (al, callarg2);
18811 use_reg (&use, al);
18814 if (ix86_cmodel == CM_LARGE_PIC
18815 && GET_CODE (fnaddr) == MEM
18816 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18817 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18818 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18820 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
18821 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
18823 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18824 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18827 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18829 call = gen_rtx_SET (VOIDmode, retval, call);
18832 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18833 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18834 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18837 && ix86_cfun_abi () == MS_ABI
18838 && (!callarg2 || INTVAL (callarg2) != -2))
18840 /* We need to represent that SI and DI registers are clobbered
18842 static int clobbered_registers[] = {
18843 XMM6_REG, XMM7_REG, XMM8_REG,
18844 XMM9_REG, XMM10_REG, XMM11_REG,
18845 XMM12_REG, XMM13_REG, XMM14_REG,
18846 XMM15_REG, SI_REG, DI_REG
18849 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18850 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18851 UNSPEC_MS_TO_SYSV_CALL);
18855 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18856 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18859 (SSE_REGNO_P (clobbered_registers[i])
18861 clobbered_registers[i]));
18863 call = gen_rtx_PARALLEL (VOIDmode,
18864 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18868 call = emit_call_insn (call);
18870 CALL_INSN_FUNCTION_USAGE (call) = use;
18874 /* Clear stack slot assignments remembered from previous functions.
18875 This is called from INIT_EXPANDERS once before RTL is emitted for each
18878 static struct machine_function *
18879 ix86_init_machine_status (void)
18881 struct machine_function *f;
18883 f = GGC_CNEW (struct machine_function);
18884 f->use_fast_prologue_epilogue_nregs = -1;
18885 f->tls_descriptor_call_expanded_p = 0;
18886 f->call_abi = DEFAULT_ABI;
18891 /* Return a MEM corresponding to a stack slot with mode MODE.
18892 Allocate a new slot if necessary.
18894 The RTL for a function can have several slots available: N is
18895 which slot to use. */
18898 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18900 struct stack_local_entry *s;
18902 gcc_assert (n < MAX_386_STACK_LOCALS);
18904 /* Virtual slot is valid only before vregs are instantiated. */
18905 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18907 for (s = ix86_stack_locals; s; s = s->next)
18908 if (s->mode == mode && s->n == n)
18909 return copy_rtx (s->rtl);
18911 s = (struct stack_local_entry *)
18912 ggc_alloc (sizeof (struct stack_local_entry));
18915 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18917 s->next = ix86_stack_locals;
18918 ix86_stack_locals = s;
18922 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18924 static GTY(()) rtx ix86_tls_symbol;
18926 ix86_tls_get_addr (void)
18929 if (!ix86_tls_symbol)
18931 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18932 (TARGET_ANY_GNU_TLS
18934 ? "___tls_get_addr"
18935 : "__tls_get_addr");
18938 return ix86_tls_symbol;
18941 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18943 static GTY(()) rtx ix86_tls_module_base_symbol;
18945 ix86_tls_module_base (void)
18948 if (!ix86_tls_module_base_symbol)
18950 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18951 "_TLS_MODULE_BASE_");
18952 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18953 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18956 return ix86_tls_module_base_symbol;
18959 /* Calculate the length of the memory address in the instruction
18960 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18963 memory_address_length (rtx addr)
18965 struct ix86_address parts;
18966 rtx base, index, disp;
18970 if (GET_CODE (addr) == PRE_DEC
18971 || GET_CODE (addr) == POST_INC
18972 || GET_CODE (addr) == PRE_MODIFY
18973 || GET_CODE (addr) == POST_MODIFY)
18976 ok = ix86_decompose_address (addr, &parts);
18979 if (parts.base && GET_CODE (parts.base) == SUBREG)
18980 parts.base = SUBREG_REG (parts.base);
18981 if (parts.index && GET_CODE (parts.index) == SUBREG)
18982 parts.index = SUBREG_REG (parts.index);
18985 index = parts.index;
18990 - esp as the base always wants an index,
18991 - ebp as the base always wants a displacement. */
18993 /* Register Indirect. */
18994 if (base && !index && !disp)
18996 /* esp (for its index) and ebp (for its displacement) need
18997 the two-byte modrm form. */
18998 if (addr == stack_pointer_rtx
18999 || addr == arg_pointer_rtx
19000 || addr == frame_pointer_rtx
19001 || addr == hard_frame_pointer_rtx)
19005 /* Direct Addressing. */
19006 else if (disp && !base && !index)
19011 /* Find the length of the displacement constant. */
19014 if (base && satisfies_constraint_K (disp))
19019 /* ebp always wants a displacement. */
19020 else if (base == hard_frame_pointer_rtx)
19023 /* An index requires the two-byte modrm form.... */
19025 /* ...like esp, which always wants an index. */
19026 || base == stack_pointer_rtx
19027 || base == arg_pointer_rtx
19028 || base == frame_pointer_rtx)
19035 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19036 is set, expect that insn have 8bit immediate alternative. */
19038 ix86_attr_length_immediate_default (rtx insn, int shortform)
19042 extract_insn_cached (insn);
19043 for (i = recog_data.n_operands - 1; i >= 0; --i)
19044 if (CONSTANT_P (recog_data.operand[i]))
19047 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
19051 switch (get_attr_mode (insn))
19062 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19067 fatal_insn ("unknown insn mode", insn);
19073 /* Compute default value for "length_address" attribute. */
19075 ix86_attr_length_address_default (rtx insn)
19079 if (get_attr_type (insn) == TYPE_LEA)
19081 rtx set = PATTERN (insn);
19083 if (GET_CODE (set) == PARALLEL)
19084 set = XVECEXP (set, 0, 0);
19086 gcc_assert (GET_CODE (set) == SET);
19088 return memory_address_length (SET_SRC (set));
19091 extract_insn_cached (insn);
19092 for (i = recog_data.n_operands - 1; i >= 0; --i)
19093 if (MEM_P (recog_data.operand[i]))
19095 return memory_address_length (XEXP (recog_data.operand[i], 0));
19101 /* Compute default value for "length_vex" attribute. It includes
19102 2 or 3 byte VEX prefix and 1 opcode byte. */
19105 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19110 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19111 byte VEX prefix. */
19112 if (!has_0f_opcode || has_vex_w)
19115 /* We can always use 2 byte VEX prefix in 32bit. */
19119 extract_insn_cached (insn);
19121 for (i = recog_data.n_operands - 1; i >= 0; --i)
19122 if (REG_P (recog_data.operand[i]))
19124 /* REX.W bit uses 3 byte VEX prefix. */
19125 if (GET_MODE (recog_data.operand[i]) == DImode)
19130 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19131 if (MEM_P (recog_data.operand[i])
19132 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19139 /* Return the maximum number of instructions a cpu can issue. */
19142 ix86_issue_rate (void)
19146 case PROCESSOR_PENTIUM:
19150 case PROCESSOR_PENTIUMPRO:
19151 case PROCESSOR_PENTIUM4:
19152 case PROCESSOR_ATHLON:
19154 case PROCESSOR_AMDFAM10:
19155 case PROCESSOR_NOCONA:
19156 case PROCESSOR_GENERIC32:
19157 case PROCESSOR_GENERIC64:
19160 case PROCESSOR_CORE2:
19168 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19169 by DEP_INSN and nothing set by DEP_INSN. */
19172 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19176 /* Simplify the test for uninteresting insns. */
19177 if (insn_type != TYPE_SETCC
19178 && insn_type != TYPE_ICMOV
19179 && insn_type != TYPE_FCMOV
19180 && insn_type != TYPE_IBR)
19183 if ((set = single_set (dep_insn)) != 0)
19185 set = SET_DEST (set);
19188 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19189 && XVECLEN (PATTERN (dep_insn), 0) == 2
19190 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19191 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19193 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19194 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19199 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19202 /* This test is true if the dependent insn reads the flags but
19203 not any other potentially set register. */
19204 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19207 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19213 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
19214 address with operands set by DEP_INSN. */
19217 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19221 if (insn_type == TYPE_LEA
19224 addr = PATTERN (insn);
19226 if (GET_CODE (addr) == PARALLEL)
19227 addr = XVECEXP (addr, 0, 0);
19229 gcc_assert (GET_CODE (addr) == SET);
19231 addr = SET_SRC (addr);
19236 extract_insn_cached (insn);
19237 for (i = recog_data.n_operands - 1; i >= 0; --i)
19238 if (MEM_P (recog_data.operand[i]))
19240 addr = XEXP (recog_data.operand[i], 0);
19247 return modified_in_p (addr, dep_insn);
19251 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19253 enum attr_type insn_type, dep_insn_type;
19254 enum attr_memory memory;
19256 int dep_insn_code_number;
19258 /* Anti and output dependencies have zero cost on all CPUs. */
19259 if (REG_NOTE_KIND (link) != 0)
19262 dep_insn_code_number = recog_memoized (dep_insn);
19264 /* If we can't recognize the insns, we can't really do anything. */
19265 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19268 insn_type = get_attr_type (insn);
19269 dep_insn_type = get_attr_type (dep_insn);
19273 case PROCESSOR_PENTIUM:
19274 /* Address Generation Interlock adds a cycle of latency. */
19275 if (ix86_agi_dependent (insn, dep_insn, insn_type))
19278 /* ??? Compares pair with jump/setcc. */
19279 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19282 /* Floating point stores require value to be ready one cycle earlier. */
19283 if (insn_type == TYPE_FMOV
19284 && get_attr_memory (insn) == MEMORY_STORE
19285 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19289 case PROCESSOR_PENTIUMPRO:
19290 memory = get_attr_memory (insn);
19292 /* INT->FP conversion is expensive. */
19293 if (get_attr_fp_int_src (dep_insn))
19296 /* There is one cycle extra latency between an FP op and a store. */
19297 if (insn_type == TYPE_FMOV
19298 && (set = single_set (dep_insn)) != NULL_RTX
19299 && (set2 = single_set (insn)) != NULL_RTX
19300 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19301 && MEM_P (SET_DEST (set2)))
19304 /* Show ability of reorder buffer to hide latency of load by executing
19305 in parallel with previous instruction in case
19306 previous instruction is not needed to compute the address. */
19307 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19308 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19310 /* Claim moves to take one cycle, as core can issue one load
19311 at time and the next load can start cycle later. */
19312 if (dep_insn_type == TYPE_IMOV
19313 || dep_insn_type == TYPE_FMOV)
19321 memory = get_attr_memory (insn);
19323 /* The esp dependency is resolved before the instruction is really
19325 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19326 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19329 /* INT->FP conversion is expensive. */
19330 if (get_attr_fp_int_src (dep_insn))
19333 /* Show ability of reorder buffer to hide latency of load by executing
19334 in parallel with previous instruction in case
19335 previous instruction is not needed to compute the address. */
19336 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19337 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19339 /* Claim moves to take one cycle, as core can issue one load
19340 at time and the next load can start cycle later. */
19341 if (dep_insn_type == TYPE_IMOV
19342 || dep_insn_type == TYPE_FMOV)
19351 case PROCESSOR_ATHLON:
19353 case PROCESSOR_AMDFAM10:
19354 case PROCESSOR_GENERIC32:
19355 case PROCESSOR_GENERIC64:
19356 memory = get_attr_memory (insn);
19358 /* Show ability of reorder buffer to hide latency of load by executing
19359 in parallel with previous instruction in case
19360 previous instruction is not needed to compute the address. */
19361 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19362 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19364 enum attr_unit unit = get_attr_unit (insn);
19367 /* Because of the difference between the length of integer and
19368 floating unit pipeline preparation stages, the memory operands
19369 for floating point are cheaper.
19371 ??? For Athlon it the difference is most probably 2. */
19372 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19375 loadcost = TARGET_ATHLON ? 2 : 0;
19377 if (cost >= loadcost)
19390 /* How many alternative schedules to try. This should be as wide as the
19391 scheduling freedom in the DFA, but no wider. Making this value too
19392 large results extra work for the scheduler. */
19395 ia32_multipass_dfa_lookahead (void)
19399 case PROCESSOR_PENTIUM:
19402 case PROCESSOR_PENTIUMPRO:
19412 /* Compute the alignment given to a constant that is being placed in memory.
19413 EXP is the constant and ALIGN is the alignment that the object would
19415 The value of this function is used instead of that alignment to align
19419 ix86_constant_alignment (tree exp, int align)
19421 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19422 || TREE_CODE (exp) == INTEGER_CST)
19424 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19426 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19429 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19430 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19431 return BITS_PER_WORD;
19436 /* Compute the alignment for a static variable.
19437 TYPE is the data type, and ALIGN is the alignment that
19438 the object would ordinarily have. The value of this function is used
19439 instead of that alignment to align the object. */
19442 ix86_data_alignment (tree type, int align)
19444 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19446 if (AGGREGATE_TYPE_P (type)
19447 && TYPE_SIZE (type)
19448 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19449 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19450 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19451 && align < max_align)
19454 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19455 to 16byte boundary. */
19458 if (AGGREGATE_TYPE_P (type)
19459 && TYPE_SIZE (type)
19460 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19461 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19462 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19466 if (TREE_CODE (type) == ARRAY_TYPE)
19468 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19470 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19473 else if (TREE_CODE (type) == COMPLEX_TYPE)
19476 if (TYPE_MODE (type) == DCmode && align < 64)
19478 if ((TYPE_MODE (type) == XCmode
19479 || TYPE_MODE (type) == TCmode) && align < 128)
19482 else if ((TREE_CODE (type) == RECORD_TYPE
19483 || TREE_CODE (type) == UNION_TYPE
19484 || TREE_CODE (type) == QUAL_UNION_TYPE)
19485 && TYPE_FIELDS (type))
19487 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19489 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19492 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19493 || TREE_CODE (type) == INTEGER_TYPE)
19495 if (TYPE_MODE (type) == DFmode && align < 64)
19497 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19504 /* Compute the alignment for a local variable or a stack slot. EXP is
19505 the data type or decl itself, MODE is the widest mode available and
19506 ALIGN is the alignment that the object would ordinarily have. The
19507 value of this macro is used instead of that alignment to align the
19511 ix86_local_alignment (tree exp, enum machine_mode mode,
19512 unsigned int align)
19516 if (exp && DECL_P (exp))
19518 type = TREE_TYPE (exp);
19527 /* Don't do dynamic stack realignment for long long objects with
19528 -mpreferred-stack-boundary=2. */
19531 && ix86_preferred_stack_boundary < 64
19532 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19533 && (!type || !TYPE_USER_ALIGN (type))
19534 && (!decl || !DECL_USER_ALIGN (decl)))
19537 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19538 register in MODE. We will return the largest alignment of XF
19542 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19543 align = GET_MODE_ALIGNMENT (DFmode);
19547 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19548 to 16byte boundary. */
19551 if (AGGREGATE_TYPE_P (type)
19552 && TYPE_SIZE (type)
19553 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19554 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19555 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19558 if (TREE_CODE (type) == ARRAY_TYPE)
19560 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19562 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19565 else if (TREE_CODE (type) == COMPLEX_TYPE)
19567 if (TYPE_MODE (type) == DCmode && align < 64)
19569 if ((TYPE_MODE (type) == XCmode
19570 || TYPE_MODE (type) == TCmode) && align < 128)
19573 else if ((TREE_CODE (type) == RECORD_TYPE
19574 || TREE_CODE (type) == UNION_TYPE
19575 || TREE_CODE (type) == QUAL_UNION_TYPE)
19576 && TYPE_FIELDS (type))
19578 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19580 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19583 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19584 || TREE_CODE (type) == INTEGER_TYPE)
19587 if (TYPE_MODE (type) == DFmode && align < 64)
19589 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19595 /* Compute the minimum required alignment for dynamic stack realignment
19596 purposes for a local variable, parameter or a stack slot. EXP is
19597 the data type or decl itself, MODE is its mode and ALIGN is the
19598 alignment that the object would ordinarily have. */
19601 ix86_minimum_alignment (tree exp, enum machine_mode mode,
19602 unsigned int align)
19606 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
19609 if (exp && DECL_P (exp))
19611 type = TREE_TYPE (exp);
19620 /* Don't do dynamic stack realignment for long long objects with
19621 -mpreferred-stack-boundary=2. */
19622 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
19623 && (!type || !TYPE_USER_ALIGN (type))
19624 && (!decl || !DECL_USER_ALIGN (decl)))
19630 /* Emit RTL insns to initialize the variable parts of a trampoline.
19631 FNADDR is an RTX for the address of the function's pure code.
19632 CXT is an RTX for the static chain value for the function. */
19634 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19638 /* Compute offset from the end of the jmp to the target function. */
19639 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19640 plus_constant (tramp, 10),
19641 NULL_RTX, 1, OPTAB_DIRECT);
19642 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19643 gen_int_mode (0xb9, QImode));
19644 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19645 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19646 gen_int_mode (0xe9, QImode));
19647 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19652 /* Try to load address using shorter movl instead of movabs.
19653 We may want to support movq for kernel mode, but kernel does not use
19654 trampolines at the moment. */
19655 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19657 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19658 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19659 gen_int_mode (0xbb41, HImode));
19660 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19661 gen_lowpart (SImode, fnaddr));
19666 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19667 gen_int_mode (0xbb49, HImode));
19668 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19672 /* Load static chain using movabs to r10. */
19673 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19674 gen_int_mode (0xba49, HImode));
19675 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19678 /* Jump to the r11 */
19679 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19680 gen_int_mode (0xff49, HImode));
19681 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19682 gen_int_mode (0xe3, QImode));
19684 gcc_assert (offset <= TRAMPOLINE_SIZE);
19687 #ifdef ENABLE_EXECUTE_STACK
19688 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19689 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19693 /* Codes for all the SSE/MMX builtins. */
19696 IX86_BUILTIN_ADDPS,
19697 IX86_BUILTIN_ADDSS,
19698 IX86_BUILTIN_DIVPS,
19699 IX86_BUILTIN_DIVSS,
19700 IX86_BUILTIN_MULPS,
19701 IX86_BUILTIN_MULSS,
19702 IX86_BUILTIN_SUBPS,
19703 IX86_BUILTIN_SUBSS,
19705 IX86_BUILTIN_CMPEQPS,
19706 IX86_BUILTIN_CMPLTPS,
19707 IX86_BUILTIN_CMPLEPS,
19708 IX86_BUILTIN_CMPGTPS,
19709 IX86_BUILTIN_CMPGEPS,
19710 IX86_BUILTIN_CMPNEQPS,
19711 IX86_BUILTIN_CMPNLTPS,
19712 IX86_BUILTIN_CMPNLEPS,
19713 IX86_BUILTIN_CMPNGTPS,
19714 IX86_BUILTIN_CMPNGEPS,
19715 IX86_BUILTIN_CMPORDPS,
19716 IX86_BUILTIN_CMPUNORDPS,
19717 IX86_BUILTIN_CMPEQSS,
19718 IX86_BUILTIN_CMPLTSS,
19719 IX86_BUILTIN_CMPLESS,
19720 IX86_BUILTIN_CMPNEQSS,
19721 IX86_BUILTIN_CMPNLTSS,
19722 IX86_BUILTIN_CMPNLESS,
19723 IX86_BUILTIN_CMPNGTSS,
19724 IX86_BUILTIN_CMPNGESS,
19725 IX86_BUILTIN_CMPORDSS,
19726 IX86_BUILTIN_CMPUNORDSS,
19728 IX86_BUILTIN_COMIEQSS,
19729 IX86_BUILTIN_COMILTSS,
19730 IX86_BUILTIN_COMILESS,
19731 IX86_BUILTIN_COMIGTSS,
19732 IX86_BUILTIN_COMIGESS,
19733 IX86_BUILTIN_COMINEQSS,
19734 IX86_BUILTIN_UCOMIEQSS,
19735 IX86_BUILTIN_UCOMILTSS,
19736 IX86_BUILTIN_UCOMILESS,
19737 IX86_BUILTIN_UCOMIGTSS,
19738 IX86_BUILTIN_UCOMIGESS,
19739 IX86_BUILTIN_UCOMINEQSS,
19741 IX86_BUILTIN_CVTPI2PS,
19742 IX86_BUILTIN_CVTPS2PI,
19743 IX86_BUILTIN_CVTSI2SS,
19744 IX86_BUILTIN_CVTSI642SS,
19745 IX86_BUILTIN_CVTSS2SI,
19746 IX86_BUILTIN_CVTSS2SI64,
19747 IX86_BUILTIN_CVTTPS2PI,
19748 IX86_BUILTIN_CVTTSS2SI,
19749 IX86_BUILTIN_CVTTSS2SI64,
19751 IX86_BUILTIN_MAXPS,
19752 IX86_BUILTIN_MAXSS,
19753 IX86_BUILTIN_MINPS,
19754 IX86_BUILTIN_MINSS,
19756 IX86_BUILTIN_LOADUPS,
19757 IX86_BUILTIN_STOREUPS,
19758 IX86_BUILTIN_MOVSS,
19760 IX86_BUILTIN_MOVHLPS,
19761 IX86_BUILTIN_MOVLHPS,
19762 IX86_BUILTIN_LOADHPS,
19763 IX86_BUILTIN_LOADLPS,
19764 IX86_BUILTIN_STOREHPS,
19765 IX86_BUILTIN_STORELPS,
19767 IX86_BUILTIN_MASKMOVQ,
19768 IX86_BUILTIN_MOVMSKPS,
19769 IX86_BUILTIN_PMOVMSKB,
19771 IX86_BUILTIN_MOVNTPS,
19772 IX86_BUILTIN_MOVNTQ,
19774 IX86_BUILTIN_LOADDQU,
19775 IX86_BUILTIN_STOREDQU,
19777 IX86_BUILTIN_PACKSSWB,
19778 IX86_BUILTIN_PACKSSDW,
19779 IX86_BUILTIN_PACKUSWB,
19781 IX86_BUILTIN_PADDB,
19782 IX86_BUILTIN_PADDW,
19783 IX86_BUILTIN_PADDD,
19784 IX86_BUILTIN_PADDQ,
19785 IX86_BUILTIN_PADDSB,
19786 IX86_BUILTIN_PADDSW,
19787 IX86_BUILTIN_PADDUSB,
19788 IX86_BUILTIN_PADDUSW,
19789 IX86_BUILTIN_PSUBB,
19790 IX86_BUILTIN_PSUBW,
19791 IX86_BUILTIN_PSUBD,
19792 IX86_BUILTIN_PSUBQ,
19793 IX86_BUILTIN_PSUBSB,
19794 IX86_BUILTIN_PSUBSW,
19795 IX86_BUILTIN_PSUBUSB,
19796 IX86_BUILTIN_PSUBUSW,
19799 IX86_BUILTIN_PANDN,
19803 IX86_BUILTIN_PAVGB,
19804 IX86_BUILTIN_PAVGW,
19806 IX86_BUILTIN_PCMPEQB,
19807 IX86_BUILTIN_PCMPEQW,
19808 IX86_BUILTIN_PCMPEQD,
19809 IX86_BUILTIN_PCMPGTB,
19810 IX86_BUILTIN_PCMPGTW,
19811 IX86_BUILTIN_PCMPGTD,
19813 IX86_BUILTIN_PMADDWD,
19815 IX86_BUILTIN_PMAXSW,
19816 IX86_BUILTIN_PMAXUB,
19817 IX86_BUILTIN_PMINSW,
19818 IX86_BUILTIN_PMINUB,
19820 IX86_BUILTIN_PMULHUW,
19821 IX86_BUILTIN_PMULHW,
19822 IX86_BUILTIN_PMULLW,
19824 IX86_BUILTIN_PSADBW,
19825 IX86_BUILTIN_PSHUFW,
19827 IX86_BUILTIN_PSLLW,
19828 IX86_BUILTIN_PSLLD,
19829 IX86_BUILTIN_PSLLQ,
19830 IX86_BUILTIN_PSRAW,
19831 IX86_BUILTIN_PSRAD,
19832 IX86_BUILTIN_PSRLW,
19833 IX86_BUILTIN_PSRLD,
19834 IX86_BUILTIN_PSRLQ,
19835 IX86_BUILTIN_PSLLWI,
19836 IX86_BUILTIN_PSLLDI,
19837 IX86_BUILTIN_PSLLQI,
19838 IX86_BUILTIN_PSRAWI,
19839 IX86_BUILTIN_PSRADI,
19840 IX86_BUILTIN_PSRLWI,
19841 IX86_BUILTIN_PSRLDI,
19842 IX86_BUILTIN_PSRLQI,
19844 IX86_BUILTIN_PUNPCKHBW,
19845 IX86_BUILTIN_PUNPCKHWD,
19846 IX86_BUILTIN_PUNPCKHDQ,
19847 IX86_BUILTIN_PUNPCKLBW,
19848 IX86_BUILTIN_PUNPCKLWD,
19849 IX86_BUILTIN_PUNPCKLDQ,
19851 IX86_BUILTIN_SHUFPS,
19853 IX86_BUILTIN_RCPPS,
19854 IX86_BUILTIN_RCPSS,
19855 IX86_BUILTIN_RSQRTPS,
19856 IX86_BUILTIN_RSQRTPS_NR,
19857 IX86_BUILTIN_RSQRTSS,
19858 IX86_BUILTIN_RSQRTF,
19859 IX86_BUILTIN_SQRTPS,
19860 IX86_BUILTIN_SQRTPS_NR,
19861 IX86_BUILTIN_SQRTSS,
19863 IX86_BUILTIN_UNPCKHPS,
19864 IX86_BUILTIN_UNPCKLPS,
19866 IX86_BUILTIN_ANDPS,
19867 IX86_BUILTIN_ANDNPS,
19869 IX86_BUILTIN_XORPS,
19872 IX86_BUILTIN_LDMXCSR,
19873 IX86_BUILTIN_STMXCSR,
19874 IX86_BUILTIN_SFENCE,
19876 /* 3DNow! Original */
19877 IX86_BUILTIN_FEMMS,
19878 IX86_BUILTIN_PAVGUSB,
19879 IX86_BUILTIN_PF2ID,
19880 IX86_BUILTIN_PFACC,
19881 IX86_BUILTIN_PFADD,
19882 IX86_BUILTIN_PFCMPEQ,
19883 IX86_BUILTIN_PFCMPGE,
19884 IX86_BUILTIN_PFCMPGT,
19885 IX86_BUILTIN_PFMAX,
19886 IX86_BUILTIN_PFMIN,
19887 IX86_BUILTIN_PFMUL,
19888 IX86_BUILTIN_PFRCP,
19889 IX86_BUILTIN_PFRCPIT1,
19890 IX86_BUILTIN_PFRCPIT2,
19891 IX86_BUILTIN_PFRSQIT1,
19892 IX86_BUILTIN_PFRSQRT,
19893 IX86_BUILTIN_PFSUB,
19894 IX86_BUILTIN_PFSUBR,
19895 IX86_BUILTIN_PI2FD,
19896 IX86_BUILTIN_PMULHRW,
19898 /* 3DNow! Athlon Extensions */
19899 IX86_BUILTIN_PF2IW,
19900 IX86_BUILTIN_PFNACC,
19901 IX86_BUILTIN_PFPNACC,
19902 IX86_BUILTIN_PI2FW,
19903 IX86_BUILTIN_PSWAPDSI,
19904 IX86_BUILTIN_PSWAPDSF,
19907 IX86_BUILTIN_ADDPD,
19908 IX86_BUILTIN_ADDSD,
19909 IX86_BUILTIN_DIVPD,
19910 IX86_BUILTIN_DIVSD,
19911 IX86_BUILTIN_MULPD,
19912 IX86_BUILTIN_MULSD,
19913 IX86_BUILTIN_SUBPD,
19914 IX86_BUILTIN_SUBSD,
19916 IX86_BUILTIN_CMPEQPD,
19917 IX86_BUILTIN_CMPLTPD,
19918 IX86_BUILTIN_CMPLEPD,
19919 IX86_BUILTIN_CMPGTPD,
19920 IX86_BUILTIN_CMPGEPD,
19921 IX86_BUILTIN_CMPNEQPD,
19922 IX86_BUILTIN_CMPNLTPD,
19923 IX86_BUILTIN_CMPNLEPD,
19924 IX86_BUILTIN_CMPNGTPD,
19925 IX86_BUILTIN_CMPNGEPD,
19926 IX86_BUILTIN_CMPORDPD,
19927 IX86_BUILTIN_CMPUNORDPD,
19928 IX86_BUILTIN_CMPEQSD,
19929 IX86_BUILTIN_CMPLTSD,
19930 IX86_BUILTIN_CMPLESD,
19931 IX86_BUILTIN_CMPNEQSD,
19932 IX86_BUILTIN_CMPNLTSD,
19933 IX86_BUILTIN_CMPNLESD,
19934 IX86_BUILTIN_CMPORDSD,
19935 IX86_BUILTIN_CMPUNORDSD,
19937 IX86_BUILTIN_COMIEQSD,
19938 IX86_BUILTIN_COMILTSD,
19939 IX86_BUILTIN_COMILESD,
19940 IX86_BUILTIN_COMIGTSD,
19941 IX86_BUILTIN_COMIGESD,
19942 IX86_BUILTIN_COMINEQSD,
19943 IX86_BUILTIN_UCOMIEQSD,
19944 IX86_BUILTIN_UCOMILTSD,
19945 IX86_BUILTIN_UCOMILESD,
19946 IX86_BUILTIN_UCOMIGTSD,
19947 IX86_BUILTIN_UCOMIGESD,
19948 IX86_BUILTIN_UCOMINEQSD,
19950 IX86_BUILTIN_MAXPD,
19951 IX86_BUILTIN_MAXSD,
19952 IX86_BUILTIN_MINPD,
19953 IX86_BUILTIN_MINSD,
19955 IX86_BUILTIN_ANDPD,
19956 IX86_BUILTIN_ANDNPD,
19958 IX86_BUILTIN_XORPD,
19960 IX86_BUILTIN_SQRTPD,
19961 IX86_BUILTIN_SQRTSD,
19963 IX86_BUILTIN_UNPCKHPD,
19964 IX86_BUILTIN_UNPCKLPD,
19966 IX86_BUILTIN_SHUFPD,
19968 IX86_BUILTIN_LOADUPD,
19969 IX86_BUILTIN_STOREUPD,
19970 IX86_BUILTIN_MOVSD,
19972 IX86_BUILTIN_LOADHPD,
19973 IX86_BUILTIN_LOADLPD,
19975 IX86_BUILTIN_CVTDQ2PD,
19976 IX86_BUILTIN_CVTDQ2PS,
19978 IX86_BUILTIN_CVTPD2DQ,
19979 IX86_BUILTIN_CVTPD2PI,
19980 IX86_BUILTIN_CVTPD2PS,
19981 IX86_BUILTIN_CVTTPD2DQ,
19982 IX86_BUILTIN_CVTTPD2PI,
19984 IX86_BUILTIN_CVTPI2PD,
19985 IX86_BUILTIN_CVTSI2SD,
19986 IX86_BUILTIN_CVTSI642SD,
19988 IX86_BUILTIN_CVTSD2SI,
19989 IX86_BUILTIN_CVTSD2SI64,
19990 IX86_BUILTIN_CVTSD2SS,
19991 IX86_BUILTIN_CVTSS2SD,
19992 IX86_BUILTIN_CVTTSD2SI,
19993 IX86_BUILTIN_CVTTSD2SI64,
19995 IX86_BUILTIN_CVTPS2DQ,
19996 IX86_BUILTIN_CVTPS2PD,
19997 IX86_BUILTIN_CVTTPS2DQ,
19999 IX86_BUILTIN_MOVNTI,
20000 IX86_BUILTIN_MOVNTPD,
20001 IX86_BUILTIN_MOVNTDQ,
20003 IX86_BUILTIN_MOVQ128,
20006 IX86_BUILTIN_MASKMOVDQU,
20007 IX86_BUILTIN_MOVMSKPD,
20008 IX86_BUILTIN_PMOVMSKB128,
20010 IX86_BUILTIN_PACKSSWB128,
20011 IX86_BUILTIN_PACKSSDW128,
20012 IX86_BUILTIN_PACKUSWB128,
20014 IX86_BUILTIN_PADDB128,
20015 IX86_BUILTIN_PADDW128,
20016 IX86_BUILTIN_PADDD128,
20017 IX86_BUILTIN_PADDQ128,
20018 IX86_BUILTIN_PADDSB128,
20019 IX86_BUILTIN_PADDSW128,
20020 IX86_BUILTIN_PADDUSB128,
20021 IX86_BUILTIN_PADDUSW128,
20022 IX86_BUILTIN_PSUBB128,
20023 IX86_BUILTIN_PSUBW128,
20024 IX86_BUILTIN_PSUBD128,
20025 IX86_BUILTIN_PSUBQ128,
20026 IX86_BUILTIN_PSUBSB128,
20027 IX86_BUILTIN_PSUBSW128,
20028 IX86_BUILTIN_PSUBUSB128,
20029 IX86_BUILTIN_PSUBUSW128,
20031 IX86_BUILTIN_PAND128,
20032 IX86_BUILTIN_PANDN128,
20033 IX86_BUILTIN_POR128,
20034 IX86_BUILTIN_PXOR128,
20036 IX86_BUILTIN_PAVGB128,
20037 IX86_BUILTIN_PAVGW128,
20039 IX86_BUILTIN_PCMPEQB128,
20040 IX86_BUILTIN_PCMPEQW128,
20041 IX86_BUILTIN_PCMPEQD128,
20042 IX86_BUILTIN_PCMPGTB128,
20043 IX86_BUILTIN_PCMPGTW128,
20044 IX86_BUILTIN_PCMPGTD128,
20046 IX86_BUILTIN_PMADDWD128,
20048 IX86_BUILTIN_PMAXSW128,
20049 IX86_BUILTIN_PMAXUB128,
20050 IX86_BUILTIN_PMINSW128,
20051 IX86_BUILTIN_PMINUB128,
20053 IX86_BUILTIN_PMULUDQ,
20054 IX86_BUILTIN_PMULUDQ128,
20055 IX86_BUILTIN_PMULHUW128,
20056 IX86_BUILTIN_PMULHW128,
20057 IX86_BUILTIN_PMULLW128,
20059 IX86_BUILTIN_PSADBW128,
20060 IX86_BUILTIN_PSHUFHW,
20061 IX86_BUILTIN_PSHUFLW,
20062 IX86_BUILTIN_PSHUFD,
20064 IX86_BUILTIN_PSLLDQI128,
20065 IX86_BUILTIN_PSLLWI128,
20066 IX86_BUILTIN_PSLLDI128,
20067 IX86_BUILTIN_PSLLQI128,
20068 IX86_BUILTIN_PSRAWI128,
20069 IX86_BUILTIN_PSRADI128,
20070 IX86_BUILTIN_PSRLDQI128,
20071 IX86_BUILTIN_PSRLWI128,
20072 IX86_BUILTIN_PSRLDI128,
20073 IX86_BUILTIN_PSRLQI128,
20075 IX86_BUILTIN_PSLLDQ128,
20076 IX86_BUILTIN_PSLLW128,
20077 IX86_BUILTIN_PSLLD128,
20078 IX86_BUILTIN_PSLLQ128,
20079 IX86_BUILTIN_PSRAW128,
20080 IX86_BUILTIN_PSRAD128,
20081 IX86_BUILTIN_PSRLW128,
20082 IX86_BUILTIN_PSRLD128,
20083 IX86_BUILTIN_PSRLQ128,
20085 IX86_BUILTIN_PUNPCKHBW128,
20086 IX86_BUILTIN_PUNPCKHWD128,
20087 IX86_BUILTIN_PUNPCKHDQ128,
20088 IX86_BUILTIN_PUNPCKHQDQ128,
20089 IX86_BUILTIN_PUNPCKLBW128,
20090 IX86_BUILTIN_PUNPCKLWD128,
20091 IX86_BUILTIN_PUNPCKLDQ128,
20092 IX86_BUILTIN_PUNPCKLQDQ128,
20094 IX86_BUILTIN_CLFLUSH,
20095 IX86_BUILTIN_MFENCE,
20096 IX86_BUILTIN_LFENCE,
20099 IX86_BUILTIN_ADDSUBPS,
20100 IX86_BUILTIN_HADDPS,
20101 IX86_BUILTIN_HSUBPS,
20102 IX86_BUILTIN_MOVSHDUP,
20103 IX86_BUILTIN_MOVSLDUP,
20104 IX86_BUILTIN_ADDSUBPD,
20105 IX86_BUILTIN_HADDPD,
20106 IX86_BUILTIN_HSUBPD,
20107 IX86_BUILTIN_LDDQU,
20109 IX86_BUILTIN_MONITOR,
20110 IX86_BUILTIN_MWAIT,
20113 IX86_BUILTIN_PHADDW,
20114 IX86_BUILTIN_PHADDD,
20115 IX86_BUILTIN_PHADDSW,
20116 IX86_BUILTIN_PHSUBW,
20117 IX86_BUILTIN_PHSUBD,
20118 IX86_BUILTIN_PHSUBSW,
20119 IX86_BUILTIN_PMADDUBSW,
20120 IX86_BUILTIN_PMULHRSW,
20121 IX86_BUILTIN_PSHUFB,
20122 IX86_BUILTIN_PSIGNB,
20123 IX86_BUILTIN_PSIGNW,
20124 IX86_BUILTIN_PSIGND,
20125 IX86_BUILTIN_PALIGNR,
20126 IX86_BUILTIN_PABSB,
20127 IX86_BUILTIN_PABSW,
20128 IX86_BUILTIN_PABSD,
20130 IX86_BUILTIN_PHADDW128,
20131 IX86_BUILTIN_PHADDD128,
20132 IX86_BUILTIN_PHADDSW128,
20133 IX86_BUILTIN_PHSUBW128,
20134 IX86_BUILTIN_PHSUBD128,
20135 IX86_BUILTIN_PHSUBSW128,
20136 IX86_BUILTIN_PMADDUBSW128,
20137 IX86_BUILTIN_PMULHRSW128,
20138 IX86_BUILTIN_PSHUFB128,
20139 IX86_BUILTIN_PSIGNB128,
20140 IX86_BUILTIN_PSIGNW128,
20141 IX86_BUILTIN_PSIGND128,
20142 IX86_BUILTIN_PALIGNR128,
20143 IX86_BUILTIN_PABSB128,
20144 IX86_BUILTIN_PABSW128,
20145 IX86_BUILTIN_PABSD128,
20147 /* AMDFAM10 - SSE4A New Instructions. */
20148 IX86_BUILTIN_MOVNTSD,
20149 IX86_BUILTIN_MOVNTSS,
20150 IX86_BUILTIN_EXTRQI,
20151 IX86_BUILTIN_EXTRQ,
20152 IX86_BUILTIN_INSERTQI,
20153 IX86_BUILTIN_INSERTQ,
20156 IX86_BUILTIN_BLENDPD,
20157 IX86_BUILTIN_BLENDPS,
20158 IX86_BUILTIN_BLENDVPD,
20159 IX86_BUILTIN_BLENDVPS,
20160 IX86_BUILTIN_PBLENDVB128,
20161 IX86_BUILTIN_PBLENDW128,
20166 IX86_BUILTIN_INSERTPS128,
20168 IX86_BUILTIN_MOVNTDQA,
20169 IX86_BUILTIN_MPSADBW128,
20170 IX86_BUILTIN_PACKUSDW128,
20171 IX86_BUILTIN_PCMPEQQ,
20172 IX86_BUILTIN_PHMINPOSUW128,
20174 IX86_BUILTIN_PMAXSB128,
20175 IX86_BUILTIN_PMAXSD128,
20176 IX86_BUILTIN_PMAXUD128,
20177 IX86_BUILTIN_PMAXUW128,
20179 IX86_BUILTIN_PMINSB128,
20180 IX86_BUILTIN_PMINSD128,
20181 IX86_BUILTIN_PMINUD128,
20182 IX86_BUILTIN_PMINUW128,
20184 IX86_BUILTIN_PMOVSXBW128,
20185 IX86_BUILTIN_PMOVSXBD128,
20186 IX86_BUILTIN_PMOVSXBQ128,
20187 IX86_BUILTIN_PMOVSXWD128,
20188 IX86_BUILTIN_PMOVSXWQ128,
20189 IX86_BUILTIN_PMOVSXDQ128,
20191 IX86_BUILTIN_PMOVZXBW128,
20192 IX86_BUILTIN_PMOVZXBD128,
20193 IX86_BUILTIN_PMOVZXBQ128,
20194 IX86_BUILTIN_PMOVZXWD128,
20195 IX86_BUILTIN_PMOVZXWQ128,
20196 IX86_BUILTIN_PMOVZXDQ128,
20198 IX86_BUILTIN_PMULDQ128,
20199 IX86_BUILTIN_PMULLD128,
20201 IX86_BUILTIN_ROUNDPD,
20202 IX86_BUILTIN_ROUNDPS,
20203 IX86_BUILTIN_ROUNDSD,
20204 IX86_BUILTIN_ROUNDSS,
20206 IX86_BUILTIN_PTESTZ,
20207 IX86_BUILTIN_PTESTC,
20208 IX86_BUILTIN_PTESTNZC,
20210 IX86_BUILTIN_VEC_INIT_V2SI,
20211 IX86_BUILTIN_VEC_INIT_V4HI,
20212 IX86_BUILTIN_VEC_INIT_V8QI,
20213 IX86_BUILTIN_VEC_EXT_V2DF,
20214 IX86_BUILTIN_VEC_EXT_V2DI,
20215 IX86_BUILTIN_VEC_EXT_V4SF,
20216 IX86_BUILTIN_VEC_EXT_V4SI,
20217 IX86_BUILTIN_VEC_EXT_V8HI,
20218 IX86_BUILTIN_VEC_EXT_V2SI,
20219 IX86_BUILTIN_VEC_EXT_V4HI,
20220 IX86_BUILTIN_VEC_EXT_V16QI,
20221 IX86_BUILTIN_VEC_SET_V2DI,
20222 IX86_BUILTIN_VEC_SET_V4SF,
20223 IX86_BUILTIN_VEC_SET_V4SI,
20224 IX86_BUILTIN_VEC_SET_V8HI,
20225 IX86_BUILTIN_VEC_SET_V4HI,
20226 IX86_BUILTIN_VEC_SET_V16QI,
20228 IX86_BUILTIN_VEC_PACK_SFIX,
20231 IX86_BUILTIN_CRC32QI,
20232 IX86_BUILTIN_CRC32HI,
20233 IX86_BUILTIN_CRC32SI,
20234 IX86_BUILTIN_CRC32DI,
20236 IX86_BUILTIN_PCMPESTRI128,
20237 IX86_BUILTIN_PCMPESTRM128,
20238 IX86_BUILTIN_PCMPESTRA128,
20239 IX86_BUILTIN_PCMPESTRC128,
20240 IX86_BUILTIN_PCMPESTRO128,
20241 IX86_BUILTIN_PCMPESTRS128,
20242 IX86_BUILTIN_PCMPESTRZ128,
20243 IX86_BUILTIN_PCMPISTRI128,
20244 IX86_BUILTIN_PCMPISTRM128,
20245 IX86_BUILTIN_PCMPISTRA128,
20246 IX86_BUILTIN_PCMPISTRC128,
20247 IX86_BUILTIN_PCMPISTRO128,
20248 IX86_BUILTIN_PCMPISTRS128,
20249 IX86_BUILTIN_PCMPISTRZ128,
20251 IX86_BUILTIN_PCMPGTQ,
20253 /* AES instructions */
20254 IX86_BUILTIN_AESENC128,
20255 IX86_BUILTIN_AESENCLAST128,
20256 IX86_BUILTIN_AESDEC128,
20257 IX86_BUILTIN_AESDECLAST128,
20258 IX86_BUILTIN_AESIMC128,
20259 IX86_BUILTIN_AESKEYGENASSIST128,
20261 /* PCLMUL instruction */
20262 IX86_BUILTIN_PCLMULQDQ128,
20265 IX86_BUILTIN_ADDPD256,
20266 IX86_BUILTIN_ADDPS256,
20267 IX86_BUILTIN_ADDSUBPD256,
20268 IX86_BUILTIN_ADDSUBPS256,
20269 IX86_BUILTIN_ANDPD256,
20270 IX86_BUILTIN_ANDPS256,
20271 IX86_BUILTIN_ANDNPD256,
20272 IX86_BUILTIN_ANDNPS256,
20273 IX86_BUILTIN_BLENDPD256,
20274 IX86_BUILTIN_BLENDPS256,
20275 IX86_BUILTIN_BLENDVPD256,
20276 IX86_BUILTIN_BLENDVPS256,
20277 IX86_BUILTIN_DIVPD256,
20278 IX86_BUILTIN_DIVPS256,
20279 IX86_BUILTIN_DPPS256,
20280 IX86_BUILTIN_HADDPD256,
20281 IX86_BUILTIN_HADDPS256,
20282 IX86_BUILTIN_HSUBPD256,
20283 IX86_BUILTIN_HSUBPS256,
20284 IX86_BUILTIN_MAXPD256,
20285 IX86_BUILTIN_MAXPS256,
20286 IX86_BUILTIN_MINPD256,
20287 IX86_BUILTIN_MINPS256,
20288 IX86_BUILTIN_MULPD256,
20289 IX86_BUILTIN_MULPS256,
20290 IX86_BUILTIN_ORPD256,
20291 IX86_BUILTIN_ORPS256,
20292 IX86_BUILTIN_SHUFPD256,
20293 IX86_BUILTIN_SHUFPS256,
20294 IX86_BUILTIN_SUBPD256,
20295 IX86_BUILTIN_SUBPS256,
20296 IX86_BUILTIN_XORPD256,
20297 IX86_BUILTIN_XORPS256,
20298 IX86_BUILTIN_CMPSD,
20299 IX86_BUILTIN_CMPSS,
20300 IX86_BUILTIN_CMPPD,
20301 IX86_BUILTIN_CMPPS,
20302 IX86_BUILTIN_CMPPD256,
20303 IX86_BUILTIN_CMPPS256,
20304 IX86_BUILTIN_CVTDQ2PD256,
20305 IX86_BUILTIN_CVTDQ2PS256,
20306 IX86_BUILTIN_CVTPD2PS256,
20307 IX86_BUILTIN_CVTPS2DQ256,
20308 IX86_BUILTIN_CVTPS2PD256,
20309 IX86_BUILTIN_CVTTPD2DQ256,
20310 IX86_BUILTIN_CVTPD2DQ256,
20311 IX86_BUILTIN_CVTTPS2DQ256,
20312 IX86_BUILTIN_EXTRACTF128PD256,
20313 IX86_BUILTIN_EXTRACTF128PS256,
20314 IX86_BUILTIN_EXTRACTF128SI256,
20315 IX86_BUILTIN_VZEROALL,
20316 IX86_BUILTIN_VZEROUPPER,
20317 IX86_BUILTIN_VZEROUPPER_REX64,
20318 IX86_BUILTIN_VPERMILVARPD,
20319 IX86_BUILTIN_VPERMILVARPS,
20320 IX86_BUILTIN_VPERMILVARPD256,
20321 IX86_BUILTIN_VPERMILVARPS256,
20322 IX86_BUILTIN_VPERMILPD,
20323 IX86_BUILTIN_VPERMILPS,
20324 IX86_BUILTIN_VPERMILPD256,
20325 IX86_BUILTIN_VPERMILPS256,
20326 IX86_BUILTIN_VPERM2F128PD256,
20327 IX86_BUILTIN_VPERM2F128PS256,
20328 IX86_BUILTIN_VPERM2F128SI256,
20329 IX86_BUILTIN_VBROADCASTSS,
20330 IX86_BUILTIN_VBROADCASTSD256,
20331 IX86_BUILTIN_VBROADCASTSS256,
20332 IX86_BUILTIN_VBROADCASTPD256,
20333 IX86_BUILTIN_VBROADCASTPS256,
20334 IX86_BUILTIN_VINSERTF128PD256,
20335 IX86_BUILTIN_VINSERTF128PS256,
20336 IX86_BUILTIN_VINSERTF128SI256,
20337 IX86_BUILTIN_LOADUPD256,
20338 IX86_BUILTIN_LOADUPS256,
20339 IX86_BUILTIN_STOREUPD256,
20340 IX86_BUILTIN_STOREUPS256,
20341 IX86_BUILTIN_LDDQU256,
20342 IX86_BUILTIN_MOVNTDQ256,
20343 IX86_BUILTIN_MOVNTPD256,
20344 IX86_BUILTIN_MOVNTPS256,
20345 IX86_BUILTIN_LOADDQU256,
20346 IX86_BUILTIN_STOREDQU256,
20347 IX86_BUILTIN_MASKLOADPD,
20348 IX86_BUILTIN_MASKLOADPS,
20349 IX86_BUILTIN_MASKSTOREPD,
20350 IX86_BUILTIN_MASKSTOREPS,
20351 IX86_BUILTIN_MASKLOADPD256,
20352 IX86_BUILTIN_MASKLOADPS256,
20353 IX86_BUILTIN_MASKSTOREPD256,
20354 IX86_BUILTIN_MASKSTOREPS256,
20355 IX86_BUILTIN_MOVSHDUP256,
20356 IX86_BUILTIN_MOVSLDUP256,
20357 IX86_BUILTIN_MOVDDUP256,
20359 IX86_BUILTIN_SQRTPD256,
20360 IX86_BUILTIN_SQRTPS256,
20361 IX86_BUILTIN_SQRTPS_NR256,
20362 IX86_BUILTIN_RSQRTPS256,
20363 IX86_BUILTIN_RSQRTPS_NR256,
20365 IX86_BUILTIN_RCPPS256,
20367 IX86_BUILTIN_ROUNDPD256,
20368 IX86_BUILTIN_ROUNDPS256,
20370 IX86_BUILTIN_UNPCKHPD256,
20371 IX86_BUILTIN_UNPCKLPD256,
20372 IX86_BUILTIN_UNPCKHPS256,
20373 IX86_BUILTIN_UNPCKLPS256,
20375 IX86_BUILTIN_SI256_SI,
20376 IX86_BUILTIN_PS256_PS,
20377 IX86_BUILTIN_PD256_PD,
20378 IX86_BUILTIN_SI_SI256,
20379 IX86_BUILTIN_PS_PS256,
20380 IX86_BUILTIN_PD_PD256,
20382 IX86_BUILTIN_VTESTZPD,
20383 IX86_BUILTIN_VTESTCPD,
20384 IX86_BUILTIN_VTESTNZCPD,
20385 IX86_BUILTIN_VTESTZPS,
20386 IX86_BUILTIN_VTESTCPS,
20387 IX86_BUILTIN_VTESTNZCPS,
20388 IX86_BUILTIN_VTESTZPD256,
20389 IX86_BUILTIN_VTESTCPD256,
20390 IX86_BUILTIN_VTESTNZCPD256,
20391 IX86_BUILTIN_VTESTZPS256,
20392 IX86_BUILTIN_VTESTCPS256,
20393 IX86_BUILTIN_VTESTNZCPS256,
20394 IX86_BUILTIN_PTESTZ256,
20395 IX86_BUILTIN_PTESTC256,
20396 IX86_BUILTIN_PTESTNZC256,
20398 IX86_BUILTIN_MOVMSKPD256,
20399 IX86_BUILTIN_MOVMSKPS256,
20401 /* TFmode support builtins. */
20403 IX86_BUILTIN_FABSQ,
20404 IX86_BUILTIN_COPYSIGNQ,
20406 /* SSE5 instructions */
20407 IX86_BUILTIN_FMADDSS,
20408 IX86_BUILTIN_FMADDSD,
20409 IX86_BUILTIN_FMADDPS,
20410 IX86_BUILTIN_FMADDPD,
20411 IX86_BUILTIN_FMSUBSS,
20412 IX86_BUILTIN_FMSUBSD,
20413 IX86_BUILTIN_FMSUBPS,
20414 IX86_BUILTIN_FMSUBPD,
20415 IX86_BUILTIN_FNMADDSS,
20416 IX86_BUILTIN_FNMADDSD,
20417 IX86_BUILTIN_FNMADDPS,
20418 IX86_BUILTIN_FNMADDPD,
20419 IX86_BUILTIN_FNMSUBSS,
20420 IX86_BUILTIN_FNMSUBSD,
20421 IX86_BUILTIN_FNMSUBPS,
20422 IX86_BUILTIN_FNMSUBPD,
20423 IX86_BUILTIN_PCMOV,
20424 IX86_BUILTIN_PCMOV_V2DI,
20425 IX86_BUILTIN_PCMOV_V4SI,
20426 IX86_BUILTIN_PCMOV_V8HI,
20427 IX86_BUILTIN_PCMOV_V16QI,
20428 IX86_BUILTIN_PCMOV_V4SF,
20429 IX86_BUILTIN_PCMOV_V2DF,
20430 IX86_BUILTIN_PPERM,
20431 IX86_BUILTIN_PERMPS,
20432 IX86_BUILTIN_PERMPD,
20433 IX86_BUILTIN_PMACSSWW,
20434 IX86_BUILTIN_PMACSWW,
20435 IX86_BUILTIN_PMACSSWD,
20436 IX86_BUILTIN_PMACSWD,
20437 IX86_BUILTIN_PMACSSDD,
20438 IX86_BUILTIN_PMACSDD,
20439 IX86_BUILTIN_PMACSSDQL,
20440 IX86_BUILTIN_PMACSSDQH,
20441 IX86_BUILTIN_PMACSDQL,
20442 IX86_BUILTIN_PMACSDQH,
20443 IX86_BUILTIN_PMADCSSWD,
20444 IX86_BUILTIN_PMADCSWD,
20445 IX86_BUILTIN_PHADDBW,
20446 IX86_BUILTIN_PHADDBD,
20447 IX86_BUILTIN_PHADDBQ,
20448 IX86_BUILTIN_PHADDWD,
20449 IX86_BUILTIN_PHADDWQ,
20450 IX86_BUILTIN_PHADDDQ,
20451 IX86_BUILTIN_PHADDUBW,
20452 IX86_BUILTIN_PHADDUBD,
20453 IX86_BUILTIN_PHADDUBQ,
20454 IX86_BUILTIN_PHADDUWD,
20455 IX86_BUILTIN_PHADDUWQ,
20456 IX86_BUILTIN_PHADDUDQ,
20457 IX86_BUILTIN_PHSUBBW,
20458 IX86_BUILTIN_PHSUBWD,
20459 IX86_BUILTIN_PHSUBDQ,
20460 IX86_BUILTIN_PROTB,
20461 IX86_BUILTIN_PROTW,
20462 IX86_BUILTIN_PROTD,
20463 IX86_BUILTIN_PROTQ,
20464 IX86_BUILTIN_PROTB_IMM,
20465 IX86_BUILTIN_PROTW_IMM,
20466 IX86_BUILTIN_PROTD_IMM,
20467 IX86_BUILTIN_PROTQ_IMM,
20468 IX86_BUILTIN_PSHLB,
20469 IX86_BUILTIN_PSHLW,
20470 IX86_BUILTIN_PSHLD,
20471 IX86_BUILTIN_PSHLQ,
20472 IX86_BUILTIN_PSHAB,
20473 IX86_BUILTIN_PSHAW,
20474 IX86_BUILTIN_PSHAD,
20475 IX86_BUILTIN_PSHAQ,
20476 IX86_BUILTIN_FRCZSS,
20477 IX86_BUILTIN_FRCZSD,
20478 IX86_BUILTIN_FRCZPS,
20479 IX86_BUILTIN_FRCZPD,
20480 IX86_BUILTIN_CVTPH2PS,
20481 IX86_BUILTIN_CVTPS2PH,
20483 IX86_BUILTIN_COMEQSS,
20484 IX86_BUILTIN_COMNESS,
20485 IX86_BUILTIN_COMLTSS,
20486 IX86_BUILTIN_COMLESS,
20487 IX86_BUILTIN_COMGTSS,
20488 IX86_BUILTIN_COMGESS,
20489 IX86_BUILTIN_COMUEQSS,
20490 IX86_BUILTIN_COMUNESS,
20491 IX86_BUILTIN_COMULTSS,
20492 IX86_BUILTIN_COMULESS,
20493 IX86_BUILTIN_COMUGTSS,
20494 IX86_BUILTIN_COMUGESS,
20495 IX86_BUILTIN_COMORDSS,
20496 IX86_BUILTIN_COMUNORDSS,
20497 IX86_BUILTIN_COMFALSESS,
20498 IX86_BUILTIN_COMTRUESS,
20500 IX86_BUILTIN_COMEQSD,
20501 IX86_BUILTIN_COMNESD,
20502 IX86_BUILTIN_COMLTSD,
20503 IX86_BUILTIN_COMLESD,
20504 IX86_BUILTIN_COMGTSD,
20505 IX86_BUILTIN_COMGESD,
20506 IX86_BUILTIN_COMUEQSD,
20507 IX86_BUILTIN_COMUNESD,
20508 IX86_BUILTIN_COMULTSD,
20509 IX86_BUILTIN_COMULESD,
20510 IX86_BUILTIN_COMUGTSD,
20511 IX86_BUILTIN_COMUGESD,
20512 IX86_BUILTIN_COMORDSD,
20513 IX86_BUILTIN_COMUNORDSD,
20514 IX86_BUILTIN_COMFALSESD,
20515 IX86_BUILTIN_COMTRUESD,
20517 IX86_BUILTIN_COMEQPS,
20518 IX86_BUILTIN_COMNEPS,
20519 IX86_BUILTIN_COMLTPS,
20520 IX86_BUILTIN_COMLEPS,
20521 IX86_BUILTIN_COMGTPS,
20522 IX86_BUILTIN_COMGEPS,
20523 IX86_BUILTIN_COMUEQPS,
20524 IX86_BUILTIN_COMUNEPS,
20525 IX86_BUILTIN_COMULTPS,
20526 IX86_BUILTIN_COMULEPS,
20527 IX86_BUILTIN_COMUGTPS,
20528 IX86_BUILTIN_COMUGEPS,
20529 IX86_BUILTIN_COMORDPS,
20530 IX86_BUILTIN_COMUNORDPS,
20531 IX86_BUILTIN_COMFALSEPS,
20532 IX86_BUILTIN_COMTRUEPS,
20534 IX86_BUILTIN_COMEQPD,
20535 IX86_BUILTIN_COMNEPD,
20536 IX86_BUILTIN_COMLTPD,
20537 IX86_BUILTIN_COMLEPD,
20538 IX86_BUILTIN_COMGTPD,
20539 IX86_BUILTIN_COMGEPD,
20540 IX86_BUILTIN_COMUEQPD,
20541 IX86_BUILTIN_COMUNEPD,
20542 IX86_BUILTIN_COMULTPD,
20543 IX86_BUILTIN_COMULEPD,
20544 IX86_BUILTIN_COMUGTPD,
20545 IX86_BUILTIN_COMUGEPD,
20546 IX86_BUILTIN_COMORDPD,
20547 IX86_BUILTIN_COMUNORDPD,
20548 IX86_BUILTIN_COMFALSEPD,
20549 IX86_BUILTIN_COMTRUEPD,
20551 IX86_BUILTIN_PCOMEQUB,
20552 IX86_BUILTIN_PCOMNEUB,
20553 IX86_BUILTIN_PCOMLTUB,
20554 IX86_BUILTIN_PCOMLEUB,
20555 IX86_BUILTIN_PCOMGTUB,
20556 IX86_BUILTIN_PCOMGEUB,
20557 IX86_BUILTIN_PCOMFALSEUB,
20558 IX86_BUILTIN_PCOMTRUEUB,
20559 IX86_BUILTIN_PCOMEQUW,
20560 IX86_BUILTIN_PCOMNEUW,
20561 IX86_BUILTIN_PCOMLTUW,
20562 IX86_BUILTIN_PCOMLEUW,
20563 IX86_BUILTIN_PCOMGTUW,
20564 IX86_BUILTIN_PCOMGEUW,
20565 IX86_BUILTIN_PCOMFALSEUW,
20566 IX86_BUILTIN_PCOMTRUEUW,
20567 IX86_BUILTIN_PCOMEQUD,
20568 IX86_BUILTIN_PCOMNEUD,
20569 IX86_BUILTIN_PCOMLTUD,
20570 IX86_BUILTIN_PCOMLEUD,
20571 IX86_BUILTIN_PCOMGTUD,
20572 IX86_BUILTIN_PCOMGEUD,
20573 IX86_BUILTIN_PCOMFALSEUD,
20574 IX86_BUILTIN_PCOMTRUEUD,
20575 IX86_BUILTIN_PCOMEQUQ,
20576 IX86_BUILTIN_PCOMNEUQ,
20577 IX86_BUILTIN_PCOMLTUQ,
20578 IX86_BUILTIN_PCOMLEUQ,
20579 IX86_BUILTIN_PCOMGTUQ,
20580 IX86_BUILTIN_PCOMGEUQ,
20581 IX86_BUILTIN_PCOMFALSEUQ,
20582 IX86_BUILTIN_PCOMTRUEUQ,
20584 IX86_BUILTIN_PCOMEQB,
20585 IX86_BUILTIN_PCOMNEB,
20586 IX86_BUILTIN_PCOMLTB,
20587 IX86_BUILTIN_PCOMLEB,
20588 IX86_BUILTIN_PCOMGTB,
20589 IX86_BUILTIN_PCOMGEB,
20590 IX86_BUILTIN_PCOMFALSEB,
20591 IX86_BUILTIN_PCOMTRUEB,
20592 IX86_BUILTIN_PCOMEQW,
20593 IX86_BUILTIN_PCOMNEW,
20594 IX86_BUILTIN_PCOMLTW,
20595 IX86_BUILTIN_PCOMLEW,
20596 IX86_BUILTIN_PCOMGTW,
20597 IX86_BUILTIN_PCOMGEW,
20598 IX86_BUILTIN_PCOMFALSEW,
20599 IX86_BUILTIN_PCOMTRUEW,
20600 IX86_BUILTIN_PCOMEQD,
20601 IX86_BUILTIN_PCOMNED,
20602 IX86_BUILTIN_PCOMLTD,
20603 IX86_BUILTIN_PCOMLED,
20604 IX86_BUILTIN_PCOMGTD,
20605 IX86_BUILTIN_PCOMGED,
20606 IX86_BUILTIN_PCOMFALSED,
20607 IX86_BUILTIN_PCOMTRUED,
20608 IX86_BUILTIN_PCOMEQQ,
20609 IX86_BUILTIN_PCOMNEQ,
20610 IX86_BUILTIN_PCOMLTQ,
20611 IX86_BUILTIN_PCOMLEQ,
20612 IX86_BUILTIN_PCOMGTQ,
20613 IX86_BUILTIN_PCOMGEQ,
20614 IX86_BUILTIN_PCOMFALSEQ,
20615 IX86_BUILTIN_PCOMTRUEQ,
20620 /* Table for the ix86 builtin decls. */
20621 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20623 /* Table of all of the builtin functions that are possible with different ISA's
20624 but are waiting to be built until a function is declared to use that
20626 struct builtin_isa GTY(())
20628 tree type; /* builtin type to use in the declaration */
20629 const char *name; /* function name */
20630 int isa; /* isa_flags this builtin is defined for */
20631 bool const_p; /* true if the declaration is constant */
20634 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20637 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20638 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20639 * function decl in the ix86_builtins array. Returns the function decl or
20640 * NULL_TREE, if the builtin was not added.
20642 * If the front end has a special hook for builtin functions, delay adding
20643 * builtin functions that aren't in the current ISA until the ISA is changed
20644 * with function specific optimization. Doing so, can save about 300K for the
20645 * default compiler. When the builtin is expanded, check at that time whether
20648 * If the front end doesn't have a special hook, record all builtins, even if
20649 * it isn't an instruction set in the current ISA in case the user uses
20650 * function specific options for a different ISA, so that we don't get scope
20651 * errors if a builtin is added in the middle of a function scope. */
20654 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20656 tree decl = NULL_TREE;
20658 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20660 ix86_builtins_isa[(int) code].isa = mask;
20662 mask &= ~OPTION_MASK_ISA_64BIT;
20663 if ((mask & ix86_isa_flags) != 0
20664 || (lang_hooks.builtin_function
20665 == lang_hooks.builtin_function_ext_scope))
20668 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20670 ix86_builtins[(int) code] = decl;
20671 ix86_builtins_isa[(int) code].type = NULL_TREE;
20675 ix86_builtins[(int) code] = NULL_TREE;
20676 ix86_builtins_isa[(int) code].const_p = false;
20677 ix86_builtins_isa[(int) code].type = type;
20678 ix86_builtins_isa[(int) code].name = name;
20685 /* Like def_builtin, but also marks the function decl "const". */
20688 def_builtin_const (int mask, const char *name, tree type,
20689 enum ix86_builtins code)
20691 tree decl = def_builtin (mask, name, type, code);
20693 TREE_READONLY (decl) = 1;
20695 ix86_builtins_isa[(int) code].const_p = true;
20700 /* Add any new builtin functions for a given ISA that may not have been
20701 declared. This saves a bit of space compared to adding all of the
20702 declarations to the tree, even if we didn't use them. */
20705 ix86_add_new_builtins (int isa)
20710 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20712 if ((ix86_builtins_isa[i].isa & isa) != 0
20713 && ix86_builtins_isa[i].type != NULL_TREE)
20715 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20716 ix86_builtins_isa[i].type,
20717 i, BUILT_IN_MD, NULL,
20720 ix86_builtins[i] = decl;
20721 ix86_builtins_isa[i].type = NULL_TREE;
20722 if (ix86_builtins_isa[i].const_p)
20723 TREE_READONLY (decl) = 1;
20728 /* Bits for builtin_description.flag. */
20730 /* Set when we don't support the comparison natively, and should
20731 swap_comparison in order to support it. */
20732 #define BUILTIN_DESC_SWAP_OPERANDS 1
20734 struct builtin_description
20736 const unsigned int mask;
20737 const enum insn_code icode;
20738 const char *const name;
20739 const enum ix86_builtins code;
20740 const enum rtx_code comparison;
20744 static const struct builtin_description bdesc_comi[] =
20746 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20747 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20748 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20749 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20750 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20751 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20754 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20755 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20756 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20757 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20758 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20759 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20760 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20761 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20762 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20763 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20764 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20765 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20766 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20767 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20768 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20769 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20772 static const struct builtin_description bdesc_pcmpestr[] =
20775 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20776 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20777 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20778 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20779 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20780 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20781 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20784 static const struct builtin_description bdesc_pcmpistr[] =
20787 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20788 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20789 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20790 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20791 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20792 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20793 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20796 /* Special builtin types */
20797 enum ix86_special_builtin_type
20799 SPECIAL_FTYPE_UNKNOWN,
20801 V32QI_FTYPE_PCCHAR,
20802 V16QI_FTYPE_PCCHAR,
20804 V8SF_FTYPE_PCFLOAT,
20806 V4DF_FTYPE_PCDOUBLE,
20807 V4SF_FTYPE_PCFLOAT,
20808 V2DF_FTYPE_PCDOUBLE,
20809 V8SF_FTYPE_PCV8SF_V8SI,
20810 V4DF_FTYPE_PCV4DF_V4DI,
20811 V4SF_FTYPE_V4SF_PCV2SF,
20812 V4SF_FTYPE_PCV4SF_V4SI,
20813 V2DF_FTYPE_V2DF_PCDOUBLE,
20814 V2DF_FTYPE_PCV2DF_V2DI,
20816 VOID_FTYPE_PV2SF_V4SF,
20817 VOID_FTYPE_PV4DI_V4DI,
20818 VOID_FTYPE_PV2DI_V2DI,
20819 VOID_FTYPE_PCHAR_V32QI,
20820 VOID_FTYPE_PCHAR_V16QI,
20821 VOID_FTYPE_PFLOAT_V8SF,
20822 VOID_FTYPE_PFLOAT_V4SF,
20823 VOID_FTYPE_PDOUBLE_V4DF,
20824 VOID_FTYPE_PDOUBLE_V2DF,
20826 VOID_FTYPE_PINT_INT,
20827 VOID_FTYPE_PV8SF_V8SI_V8SF,
20828 VOID_FTYPE_PV4DF_V4DI_V4DF,
20829 VOID_FTYPE_PV4SF_V4SI_V4SF,
20830 VOID_FTYPE_PV2DF_V2DI_V2DF
20833 /* Builtin types */
20834 enum ix86_builtin_type
20837 FLOAT128_FTYPE_FLOAT128,
20839 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20840 INT_FTYPE_V8SF_V8SF_PTEST,
20841 INT_FTYPE_V4DI_V4DI_PTEST,
20842 INT_FTYPE_V4DF_V4DF_PTEST,
20843 INT_FTYPE_V4SF_V4SF_PTEST,
20844 INT_FTYPE_V2DI_V2DI_PTEST,
20845 INT_FTYPE_V2DF_V2DF_PTEST,
20877 V4SF_FTYPE_V4SF_VEC_MERGE,
20886 V2DF_FTYPE_V2DF_VEC_MERGE,
20897 V16QI_FTYPE_V16QI_V16QI,
20898 V16QI_FTYPE_V8HI_V8HI,
20899 V8QI_FTYPE_V8QI_V8QI,
20900 V8QI_FTYPE_V4HI_V4HI,
20901 V8HI_FTYPE_V8HI_V8HI,
20902 V8HI_FTYPE_V8HI_V8HI_COUNT,
20903 V8HI_FTYPE_V16QI_V16QI,
20904 V8HI_FTYPE_V4SI_V4SI,
20905 V8HI_FTYPE_V8HI_SI_COUNT,
20906 V8SF_FTYPE_V8SF_V8SF,
20907 V8SF_FTYPE_V8SF_V8SI,
20908 V4SI_FTYPE_V4SI_V4SI,
20909 V4SI_FTYPE_V4SI_V4SI_COUNT,
20910 V4SI_FTYPE_V8HI_V8HI,
20911 V4SI_FTYPE_V4SF_V4SF,
20912 V4SI_FTYPE_V2DF_V2DF,
20913 V4SI_FTYPE_V4SI_SI_COUNT,
20914 V4HI_FTYPE_V4HI_V4HI,
20915 V4HI_FTYPE_V4HI_V4HI_COUNT,
20916 V4HI_FTYPE_V8QI_V8QI,
20917 V4HI_FTYPE_V2SI_V2SI,
20918 V4HI_FTYPE_V4HI_SI_COUNT,
20919 V4DF_FTYPE_V4DF_V4DF,
20920 V4DF_FTYPE_V4DF_V4DI,
20921 V4SF_FTYPE_V4SF_V4SF,
20922 V4SF_FTYPE_V4SF_V4SF_SWAP,
20923 V4SF_FTYPE_V4SF_V4SI,
20924 V4SF_FTYPE_V4SF_V2SI,
20925 V4SF_FTYPE_V4SF_V2DF,
20926 V4SF_FTYPE_V4SF_DI,
20927 V4SF_FTYPE_V4SF_SI,
20928 V2DI_FTYPE_V2DI_V2DI,
20929 V2DI_FTYPE_V2DI_V2DI_COUNT,
20930 V2DI_FTYPE_V16QI_V16QI,
20931 V2DI_FTYPE_V4SI_V4SI,
20932 V2DI_FTYPE_V2DI_V16QI,
20933 V2DI_FTYPE_V2DF_V2DF,
20934 V2DI_FTYPE_V2DI_SI_COUNT,
20935 V2SI_FTYPE_V2SI_V2SI,
20936 V2SI_FTYPE_V2SI_V2SI_COUNT,
20937 V2SI_FTYPE_V4HI_V4HI,
20938 V2SI_FTYPE_V2SF_V2SF,
20939 V2SI_FTYPE_V2SI_SI_COUNT,
20940 V2DF_FTYPE_V2DF_V2DF,
20941 V2DF_FTYPE_V2DF_V2DF_SWAP,
20942 V2DF_FTYPE_V2DF_V4SF,
20943 V2DF_FTYPE_V2DF_V2DI,
20944 V2DF_FTYPE_V2DF_DI,
20945 V2DF_FTYPE_V2DF_SI,
20946 V2SF_FTYPE_V2SF_V2SF,
20947 V1DI_FTYPE_V1DI_V1DI,
20948 V1DI_FTYPE_V1DI_V1DI_COUNT,
20949 V1DI_FTYPE_V8QI_V8QI,
20950 V1DI_FTYPE_V2SI_V2SI,
20951 V1DI_FTYPE_V1DI_SI_COUNT,
20952 UINT64_FTYPE_UINT64_UINT64,
20953 UINT_FTYPE_UINT_UINT,
20954 UINT_FTYPE_UINT_USHORT,
20955 UINT_FTYPE_UINT_UCHAR,
20956 V8HI_FTYPE_V8HI_INT,
20957 V4SI_FTYPE_V4SI_INT,
20958 V4HI_FTYPE_V4HI_INT,
20959 V8SF_FTYPE_V8SF_INT,
20960 V4SI_FTYPE_V8SI_INT,
20961 V4SF_FTYPE_V8SF_INT,
20962 V2DF_FTYPE_V4DF_INT,
20963 V4DF_FTYPE_V4DF_INT,
20964 V4SF_FTYPE_V4SF_INT,
20965 V2DI_FTYPE_V2DI_INT,
20966 V2DI2TI_FTYPE_V2DI_INT,
20967 V2DF_FTYPE_V2DF_INT,
20968 V16QI_FTYPE_V16QI_V16QI_V16QI,
20969 V8SF_FTYPE_V8SF_V8SF_V8SF,
20970 V4DF_FTYPE_V4DF_V4DF_V4DF,
20971 V4SF_FTYPE_V4SF_V4SF_V4SF,
20972 V2DF_FTYPE_V2DF_V2DF_V2DF,
20973 V16QI_FTYPE_V16QI_V16QI_INT,
20974 V8SI_FTYPE_V8SI_V8SI_INT,
20975 V8SI_FTYPE_V8SI_V4SI_INT,
20976 V8HI_FTYPE_V8HI_V8HI_INT,
20977 V8SF_FTYPE_V8SF_V8SF_INT,
20978 V8SF_FTYPE_V8SF_V4SF_INT,
20979 V4SI_FTYPE_V4SI_V4SI_INT,
20980 V4DF_FTYPE_V4DF_V4DF_INT,
20981 V4DF_FTYPE_V4DF_V2DF_INT,
20982 V4SF_FTYPE_V4SF_V4SF_INT,
20983 V2DI_FTYPE_V2DI_V2DI_INT,
20984 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20985 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20986 V2DF_FTYPE_V2DF_V2DF_INT,
20987 V2DI_FTYPE_V2DI_UINT_UINT,
20988 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20991 /* Special builtins with variable number of arguments. */
20992 static const struct builtin_description bdesc_special_args[] =
20995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20998 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21001 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21002 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21003 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21005 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21006 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21007 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21008 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21010 /* SSE or 3DNow!A */
21011 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21012 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21015 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21016 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21017 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21018 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21019 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21020 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21021 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21022 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21023 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21025 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21026 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21029 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21032 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21035 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21036 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21039 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21040 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21041 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21043 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21044 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21045 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21047 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21049 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21050 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21052 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21053 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21054 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21055 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
21062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
21063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
21064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
21065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
21066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
21067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
21068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
21071 /* Builtins with variable number of arguments. */
21072 static const struct builtin_description bdesc_args[] =
21075 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21076 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21077 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21078 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21079 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21080 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21082 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21083 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21084 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21085 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21086 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21087 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21088 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21089 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21091 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21092 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21094 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21095 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21096 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21097 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21099 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21100 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21101 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21102 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21103 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21104 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21106 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21107 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21108 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21109 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21110 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21111 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21113 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21114 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21115 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21117 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21119 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21122 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21126 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21129 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21131 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21134 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21136 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21139 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21140 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21141 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21142 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21144 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21145 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21146 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21147 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21148 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21149 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21150 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21151 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21152 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21153 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21154 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21155 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21156 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21157 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21158 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21161 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21162 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21163 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21164 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21165 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21166 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21169 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21170 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21171 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21173 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21174 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21175 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21176 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21177 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21178 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21179 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21180 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21182 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21184 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21185 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21186 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21187 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21188 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21189 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21190 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21191 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21193 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21194 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21195 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21196 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21197 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21198 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21199 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21200 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21201 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21202 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21203 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21204 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21205 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21206 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21207 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21208 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21209 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21213 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21216 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21217 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21218 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21219 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21221 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21222 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21223 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21224 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21226 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21227 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21228 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21229 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21230 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21232 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21233 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21234 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21236 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21240 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21242 /* SSE MMX or 3Dnow!A */
21243 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21244 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21245 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21247 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21248 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21249 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21250 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21252 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21253 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21255 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21274 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21276 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21277 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21283 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21284 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21285 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21286 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21289 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21294 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21314 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21318 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21320 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21321 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21327 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21329 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21330 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21331 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21332 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21333 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21334 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21335 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21336 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21347 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21348 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21350 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21352 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21353 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21359 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21360 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21361 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21362 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21365 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21366 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21367 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21368 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21370 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21371 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21372 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21373 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21374 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21375 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21376 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21377 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21379 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21380 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21383 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21392 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21393 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21394 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21396 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21397 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21398 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21399 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21400 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21401 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21402 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21405 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21406 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21407 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21408 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21409 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21410 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21412 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21413 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21414 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21415 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21417 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21423 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21424 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21426 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21429 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21430 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21433 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21434 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21436 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21437 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21438 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21439 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21440 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21441 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21444 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21445 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21446 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21447 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21448 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21449 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21451 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21452 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21453 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21454 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21455 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21456 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21457 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21458 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21459 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21460 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21461 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21462 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21463 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21464 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21465 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21466 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21467 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21468 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21469 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21470 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21471 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21472 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21473 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21474 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21477 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21478 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21481 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21482 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21483 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21484 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21485 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21486 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21487 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21488 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21489 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21490 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21492 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21493 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21494 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21495 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21496 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21497 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21498 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21499 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21500 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21501 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21502 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21503 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21504 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21506 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21507 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21508 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21509 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21510 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21511 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21512 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21513 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21514 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21515 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21516 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21517 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21519 /* SSE4.1 and SSE5 */
21520 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21521 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21522 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21523 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21525 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21526 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21527 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21530 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21531 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21532 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21533 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21534 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21537 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21538 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21539 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21540 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21543 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21544 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21546 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21547 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21548 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21549 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21552 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21555 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21556 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21559 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21560 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21563 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21569 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21570 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21571 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21572 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21573 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21574 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21575 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21576 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21577 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21578 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21579 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21580 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21626 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21628 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21630 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21639 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21640 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21642 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21643 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21645 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21646 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21670 enum multi_arg_type {
21680 MULTI_ARG_3_PERMPS,
21681 MULTI_ARG_3_PERMPD,
21688 MULTI_ARG_2_DI_IMM,
21689 MULTI_ARG_2_SI_IMM,
21690 MULTI_ARG_2_HI_IMM,
21691 MULTI_ARG_2_QI_IMM,
21692 MULTI_ARG_2_SF_CMP,
21693 MULTI_ARG_2_DF_CMP,
21694 MULTI_ARG_2_DI_CMP,
21695 MULTI_ARG_2_SI_CMP,
21696 MULTI_ARG_2_HI_CMP,
21697 MULTI_ARG_2_QI_CMP,
21720 static const struct builtin_description bdesc_multi_arg[] =
21722 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
21723 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
21724 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
21725 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
21726 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
21727 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
21728 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
21729 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
21730 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
21731 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
21732 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
21733 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
21734 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
21735 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
21736 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
21737 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
21738 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
21739 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
21740 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
21741 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
21742 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
21743 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
21744 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
21745 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
21746 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
21747 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
21748 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
21749 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
21750 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21751 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
21752 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
21753 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
21754 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21755 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21756 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21757 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21758 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21759 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21760 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21761 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21762 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21763 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21764 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21765 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21766 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21767 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21768 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21769 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21770 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21771 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21772 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21773 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21774 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21775 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21776 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21777 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21778 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21779 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21780 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21781 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21782 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21783 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21784 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21785 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21786 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21787 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21788 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21789 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21790 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21791 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21792 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21793 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21794 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21795 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21796 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21798 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21799 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21800 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21801 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21802 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21803 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21804 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21805 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21806 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21807 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21808 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21809 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21810 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21811 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21812 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21813 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21815 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21816 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21817 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21818 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21819 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21820 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21821 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21822 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21823 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21824 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21825 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21826 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21827 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21828 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21829 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21830 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21832 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21833 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21834 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21835 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21836 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21837 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21838 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21839 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21840 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21841 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21842 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21843 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21844 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21845 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21846 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21847 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21849 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21850 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21851 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21852 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21853 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21854 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21855 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21856 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21857 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21858 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21859 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21860 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21861 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21862 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21863 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21864 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21866 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21867 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21868 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21869 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21870 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21871 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21872 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21874 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21875 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21876 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21877 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21878 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21879 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21880 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21882 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21883 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21884 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21885 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21886 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21887 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21888 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21890 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21891 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21892 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21893 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21894 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21895 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21896 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21898 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21899 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21900 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21901 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21902 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21903 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21904 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21906 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21907 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21908 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21909 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21910 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21911 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21912 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21914 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21915 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21916 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21917 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21918 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21919 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21920 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21922 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21923 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21924 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21925 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21926 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21927 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21928 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21930 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21931 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21932 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21933 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21934 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21935 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21936 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21937 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21939 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21940 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21941 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21942 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21943 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21944 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21945 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21946 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21948 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21949 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21950 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21951 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21952 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21953 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21954 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21955 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21958 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21959 in the current target ISA to allow the user to compile particular modules
21960 with different target specific options that differ from the command line
21963 ix86_init_mmx_sse_builtins (void)
21965 const struct builtin_description * d;
21968 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21969 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21970 tree V1DI_type_node
21971 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21972 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21973 tree V2DI_type_node
21974 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21975 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21976 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21977 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21978 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21979 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21980 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21982 tree pchar_type_node = build_pointer_type (char_type_node);
21983 tree pcchar_type_node
21984 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21985 tree pfloat_type_node = build_pointer_type (float_type_node);
21986 tree pcfloat_type_node
21987 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21988 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21989 tree pcv2sf_type_node
21990 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21991 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21992 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21995 tree int_ftype_v4sf_v4sf
21996 = build_function_type_list (integer_type_node,
21997 V4SF_type_node, V4SF_type_node, NULL_TREE);
21998 tree v4si_ftype_v4sf_v4sf
21999 = build_function_type_list (V4SI_type_node,
22000 V4SF_type_node, V4SF_type_node, NULL_TREE);
22001 /* MMX/SSE/integer conversions. */
22002 tree int_ftype_v4sf
22003 = build_function_type_list (integer_type_node,
22004 V4SF_type_node, NULL_TREE);
22005 tree int64_ftype_v4sf
22006 = build_function_type_list (long_long_integer_type_node,
22007 V4SF_type_node, NULL_TREE);
22008 tree int_ftype_v8qi
22009 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
22010 tree v4sf_ftype_v4sf_int
22011 = build_function_type_list (V4SF_type_node,
22012 V4SF_type_node, integer_type_node, NULL_TREE);
22013 tree v4sf_ftype_v4sf_int64
22014 = build_function_type_list (V4SF_type_node,
22015 V4SF_type_node, long_long_integer_type_node,
22017 tree v4sf_ftype_v4sf_v2si
22018 = build_function_type_list (V4SF_type_node,
22019 V4SF_type_node, V2SI_type_node, NULL_TREE);
22021 /* Miscellaneous. */
22022 tree v8qi_ftype_v4hi_v4hi
22023 = build_function_type_list (V8QI_type_node,
22024 V4HI_type_node, V4HI_type_node, NULL_TREE);
22025 tree v4hi_ftype_v2si_v2si
22026 = build_function_type_list (V4HI_type_node,
22027 V2SI_type_node, V2SI_type_node, NULL_TREE);
22028 tree v4sf_ftype_v4sf_v4sf_int
22029 = build_function_type_list (V4SF_type_node,
22030 V4SF_type_node, V4SF_type_node,
22031 integer_type_node, NULL_TREE);
22032 tree v2si_ftype_v4hi_v4hi
22033 = build_function_type_list (V2SI_type_node,
22034 V4HI_type_node, V4HI_type_node, NULL_TREE);
22035 tree v4hi_ftype_v4hi_int
22036 = build_function_type_list (V4HI_type_node,
22037 V4HI_type_node, integer_type_node, NULL_TREE);
22038 tree v2si_ftype_v2si_int
22039 = build_function_type_list (V2SI_type_node,
22040 V2SI_type_node, integer_type_node, NULL_TREE);
22041 tree v1di_ftype_v1di_int
22042 = build_function_type_list (V1DI_type_node,
22043 V1DI_type_node, integer_type_node, NULL_TREE);
22045 tree void_ftype_void
22046 = build_function_type (void_type_node, void_list_node);
22047 tree void_ftype_unsigned
22048 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
22049 tree void_ftype_unsigned_unsigned
22050 = build_function_type_list (void_type_node, unsigned_type_node,
22051 unsigned_type_node, NULL_TREE);
22052 tree void_ftype_pcvoid_unsigned_unsigned
22053 = build_function_type_list (void_type_node, const_ptr_type_node,
22054 unsigned_type_node, unsigned_type_node,
22056 tree unsigned_ftype_void
22057 = build_function_type (unsigned_type_node, void_list_node);
22058 tree v2si_ftype_v4sf
22059 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
22060 /* Loads/stores. */
22061 tree void_ftype_v8qi_v8qi_pchar
22062 = build_function_type_list (void_type_node,
22063 V8QI_type_node, V8QI_type_node,
22064 pchar_type_node, NULL_TREE);
22065 tree v4sf_ftype_pcfloat
22066 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
22067 tree v4sf_ftype_v4sf_pcv2sf
22068 = build_function_type_list (V4SF_type_node,
22069 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
22070 tree void_ftype_pv2sf_v4sf
22071 = build_function_type_list (void_type_node,
22072 pv2sf_type_node, V4SF_type_node, NULL_TREE);
22073 tree void_ftype_pfloat_v4sf
22074 = build_function_type_list (void_type_node,
22075 pfloat_type_node, V4SF_type_node, NULL_TREE);
22076 tree void_ftype_pdi_di
22077 = build_function_type_list (void_type_node,
22078 pdi_type_node, long_long_unsigned_type_node,
22080 tree void_ftype_pv2di_v2di
22081 = build_function_type_list (void_type_node,
22082 pv2di_type_node, V2DI_type_node, NULL_TREE);
22083 /* Normal vector unops. */
22084 tree v4sf_ftype_v4sf
22085 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22086 tree v16qi_ftype_v16qi
22087 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22088 tree v8hi_ftype_v8hi
22089 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22090 tree v4si_ftype_v4si
22091 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22092 tree v8qi_ftype_v8qi
22093 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22094 tree v4hi_ftype_v4hi
22095 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22097 /* Normal vector binops. */
22098 tree v4sf_ftype_v4sf_v4sf
22099 = build_function_type_list (V4SF_type_node,
22100 V4SF_type_node, V4SF_type_node, NULL_TREE);
22101 tree v8qi_ftype_v8qi_v8qi
22102 = build_function_type_list (V8QI_type_node,
22103 V8QI_type_node, V8QI_type_node, NULL_TREE);
22104 tree v4hi_ftype_v4hi_v4hi
22105 = build_function_type_list (V4HI_type_node,
22106 V4HI_type_node, V4HI_type_node, NULL_TREE);
22107 tree v2si_ftype_v2si_v2si
22108 = build_function_type_list (V2SI_type_node,
22109 V2SI_type_node, V2SI_type_node, NULL_TREE);
22110 tree v1di_ftype_v1di_v1di
22111 = build_function_type_list (V1DI_type_node,
22112 V1DI_type_node, V1DI_type_node, NULL_TREE);
22113 tree v1di_ftype_v1di_v1di_int
22114 = build_function_type_list (V1DI_type_node,
22115 V1DI_type_node, V1DI_type_node,
22116 integer_type_node, NULL_TREE);
22117 tree v2si_ftype_v2sf
22118 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22119 tree v2sf_ftype_v2si
22120 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22121 tree v2si_ftype_v2si
22122 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22123 tree v2sf_ftype_v2sf
22124 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22125 tree v2sf_ftype_v2sf_v2sf
22126 = build_function_type_list (V2SF_type_node,
22127 V2SF_type_node, V2SF_type_node, NULL_TREE);
22128 tree v2si_ftype_v2sf_v2sf
22129 = build_function_type_list (V2SI_type_node,
22130 V2SF_type_node, V2SF_type_node, NULL_TREE);
22131 tree pint_type_node = build_pointer_type (integer_type_node);
22132 tree pdouble_type_node = build_pointer_type (double_type_node);
22133 tree pcdouble_type_node = build_pointer_type (
22134 build_type_variant (double_type_node, 1, 0));
22135 tree int_ftype_v2df_v2df
22136 = build_function_type_list (integer_type_node,
22137 V2DF_type_node, V2DF_type_node, NULL_TREE);
22139 tree void_ftype_pcvoid
22140 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22141 tree v4sf_ftype_v4si
22142 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22143 tree v4si_ftype_v4sf
22144 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22145 tree v2df_ftype_v4si
22146 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22147 tree v4si_ftype_v2df
22148 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22149 tree v4si_ftype_v2df_v2df
22150 = build_function_type_list (V4SI_type_node,
22151 V2DF_type_node, V2DF_type_node, NULL_TREE);
22152 tree v2si_ftype_v2df
22153 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22154 tree v4sf_ftype_v2df
22155 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22156 tree v2df_ftype_v2si
22157 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22158 tree v2df_ftype_v4sf
22159 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22160 tree int_ftype_v2df
22161 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22162 tree int64_ftype_v2df
22163 = build_function_type_list (long_long_integer_type_node,
22164 V2DF_type_node, NULL_TREE);
22165 tree v2df_ftype_v2df_int
22166 = build_function_type_list (V2DF_type_node,
22167 V2DF_type_node, integer_type_node, NULL_TREE);
22168 tree v2df_ftype_v2df_int64
22169 = build_function_type_list (V2DF_type_node,
22170 V2DF_type_node, long_long_integer_type_node,
22172 tree v4sf_ftype_v4sf_v2df
22173 = build_function_type_list (V4SF_type_node,
22174 V4SF_type_node, V2DF_type_node, NULL_TREE);
22175 tree v2df_ftype_v2df_v4sf
22176 = build_function_type_list (V2DF_type_node,
22177 V2DF_type_node, V4SF_type_node, NULL_TREE);
22178 tree v2df_ftype_v2df_v2df_int
22179 = build_function_type_list (V2DF_type_node,
22180 V2DF_type_node, V2DF_type_node,
22183 tree v2df_ftype_v2df_pcdouble
22184 = build_function_type_list (V2DF_type_node,
22185 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22186 tree void_ftype_pdouble_v2df
22187 = build_function_type_list (void_type_node,
22188 pdouble_type_node, V2DF_type_node, NULL_TREE);
22189 tree void_ftype_pint_int
22190 = build_function_type_list (void_type_node,
22191 pint_type_node, integer_type_node, NULL_TREE);
22192 tree void_ftype_v16qi_v16qi_pchar
22193 = build_function_type_list (void_type_node,
22194 V16QI_type_node, V16QI_type_node,
22195 pchar_type_node, NULL_TREE);
22196 tree v2df_ftype_pcdouble
22197 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22198 tree v2df_ftype_v2df_v2df
22199 = build_function_type_list (V2DF_type_node,
22200 V2DF_type_node, V2DF_type_node, NULL_TREE);
22201 tree v16qi_ftype_v16qi_v16qi
22202 = build_function_type_list (V16QI_type_node,
22203 V16QI_type_node, V16QI_type_node, NULL_TREE);
22204 tree v8hi_ftype_v8hi_v8hi
22205 = build_function_type_list (V8HI_type_node,
22206 V8HI_type_node, V8HI_type_node, NULL_TREE);
22207 tree v4si_ftype_v4si_v4si
22208 = build_function_type_list (V4SI_type_node,
22209 V4SI_type_node, V4SI_type_node, NULL_TREE);
22210 tree v2di_ftype_v2di_v2di
22211 = build_function_type_list (V2DI_type_node,
22212 V2DI_type_node, V2DI_type_node, NULL_TREE);
22213 tree v2di_ftype_v2df_v2df
22214 = build_function_type_list (V2DI_type_node,
22215 V2DF_type_node, V2DF_type_node, NULL_TREE);
22216 tree v2df_ftype_v2df
22217 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22218 tree v2di_ftype_v2di_int
22219 = build_function_type_list (V2DI_type_node,
22220 V2DI_type_node, integer_type_node, NULL_TREE);
22221 tree v2di_ftype_v2di_v2di_int
22222 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22223 V2DI_type_node, integer_type_node, NULL_TREE);
22224 tree v4si_ftype_v4si_int
22225 = build_function_type_list (V4SI_type_node,
22226 V4SI_type_node, integer_type_node, NULL_TREE);
22227 tree v8hi_ftype_v8hi_int
22228 = build_function_type_list (V8HI_type_node,
22229 V8HI_type_node, integer_type_node, NULL_TREE);
22230 tree v4si_ftype_v8hi_v8hi
22231 = build_function_type_list (V4SI_type_node,
22232 V8HI_type_node, V8HI_type_node, NULL_TREE);
22233 tree v1di_ftype_v8qi_v8qi
22234 = build_function_type_list (V1DI_type_node,
22235 V8QI_type_node, V8QI_type_node, NULL_TREE);
22236 tree v1di_ftype_v2si_v2si
22237 = build_function_type_list (V1DI_type_node,
22238 V2SI_type_node, V2SI_type_node, NULL_TREE);
22239 tree v2di_ftype_v16qi_v16qi
22240 = build_function_type_list (V2DI_type_node,
22241 V16QI_type_node, V16QI_type_node, NULL_TREE);
22242 tree v2di_ftype_v4si_v4si
22243 = build_function_type_list (V2DI_type_node,
22244 V4SI_type_node, V4SI_type_node, NULL_TREE);
22245 tree int_ftype_v16qi
22246 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22247 tree v16qi_ftype_pcchar
22248 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22249 tree void_ftype_pchar_v16qi
22250 = build_function_type_list (void_type_node,
22251 pchar_type_node, V16QI_type_node, NULL_TREE);
22253 tree v2di_ftype_v2di_unsigned_unsigned
22254 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22255 unsigned_type_node, unsigned_type_node,
22257 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22258 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22259 unsigned_type_node, unsigned_type_node,
22261 tree v2di_ftype_v2di_v16qi
22262 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22264 tree v2df_ftype_v2df_v2df_v2df
22265 = build_function_type_list (V2DF_type_node,
22266 V2DF_type_node, V2DF_type_node,
22267 V2DF_type_node, NULL_TREE);
22268 tree v4sf_ftype_v4sf_v4sf_v4sf
22269 = build_function_type_list (V4SF_type_node,
22270 V4SF_type_node, V4SF_type_node,
22271 V4SF_type_node, NULL_TREE);
22272 tree v8hi_ftype_v16qi
22273 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22275 tree v4si_ftype_v16qi
22276 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22278 tree v2di_ftype_v16qi
22279 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22281 tree v4si_ftype_v8hi
22282 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22284 tree v2di_ftype_v8hi
22285 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22287 tree v2di_ftype_v4si
22288 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22290 tree v2di_ftype_pv2di
22291 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22293 tree v16qi_ftype_v16qi_v16qi_int
22294 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22295 V16QI_type_node, integer_type_node,
22297 tree v16qi_ftype_v16qi_v16qi_v16qi
22298 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22299 V16QI_type_node, V16QI_type_node,
22301 tree v8hi_ftype_v8hi_v8hi_int
22302 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22303 V8HI_type_node, integer_type_node,
22305 tree v4si_ftype_v4si_v4si_int
22306 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22307 V4SI_type_node, integer_type_node,
22309 tree int_ftype_v2di_v2di
22310 = build_function_type_list (integer_type_node,
22311 V2DI_type_node, V2DI_type_node,
22313 tree int_ftype_v16qi_int_v16qi_int_int
22314 = build_function_type_list (integer_type_node,
22321 tree v16qi_ftype_v16qi_int_v16qi_int_int
22322 = build_function_type_list (V16QI_type_node,
22329 tree int_ftype_v16qi_v16qi_int
22330 = build_function_type_list (integer_type_node,
22336 /* SSE5 instructions */
22337 tree v2di_ftype_v2di_v2di_v2di
22338 = build_function_type_list (V2DI_type_node,
22344 tree v4si_ftype_v4si_v4si_v4si
22345 = build_function_type_list (V4SI_type_node,
22351 tree v4si_ftype_v4si_v4si_v2di
22352 = build_function_type_list (V4SI_type_node,
22358 tree v8hi_ftype_v8hi_v8hi_v8hi
22359 = build_function_type_list (V8HI_type_node,
22365 tree v8hi_ftype_v8hi_v8hi_v4si
22366 = build_function_type_list (V8HI_type_node,
22372 tree v2df_ftype_v2df_v2df_v16qi
22373 = build_function_type_list (V2DF_type_node,
22379 tree v4sf_ftype_v4sf_v4sf_v16qi
22380 = build_function_type_list (V4SF_type_node,
22386 tree v2di_ftype_v2di_si
22387 = build_function_type_list (V2DI_type_node,
22392 tree v4si_ftype_v4si_si
22393 = build_function_type_list (V4SI_type_node,
22398 tree v8hi_ftype_v8hi_si
22399 = build_function_type_list (V8HI_type_node,
22404 tree v16qi_ftype_v16qi_si
22405 = build_function_type_list (V16QI_type_node,
22409 tree v4sf_ftype_v4hi
22410 = build_function_type_list (V4SF_type_node,
22414 tree v4hi_ftype_v4sf
22415 = build_function_type_list (V4HI_type_node,
22419 tree v2di_ftype_v2di
22420 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22422 tree v16qi_ftype_v8hi_v8hi
22423 = build_function_type_list (V16QI_type_node,
22424 V8HI_type_node, V8HI_type_node,
22426 tree v8hi_ftype_v4si_v4si
22427 = build_function_type_list (V8HI_type_node,
22428 V4SI_type_node, V4SI_type_node,
22430 tree v8hi_ftype_v16qi_v16qi
22431 = build_function_type_list (V8HI_type_node,
22432 V16QI_type_node, V16QI_type_node,
22434 tree v4hi_ftype_v8qi_v8qi
22435 = build_function_type_list (V4HI_type_node,
22436 V8QI_type_node, V8QI_type_node,
22438 tree unsigned_ftype_unsigned_uchar
22439 = build_function_type_list (unsigned_type_node,
22440 unsigned_type_node,
22441 unsigned_char_type_node,
22443 tree unsigned_ftype_unsigned_ushort
22444 = build_function_type_list (unsigned_type_node,
22445 unsigned_type_node,
22446 short_unsigned_type_node,
22448 tree unsigned_ftype_unsigned_unsigned
22449 = build_function_type_list (unsigned_type_node,
22450 unsigned_type_node,
22451 unsigned_type_node,
22453 tree uint64_ftype_uint64_uint64
22454 = build_function_type_list (long_long_unsigned_type_node,
22455 long_long_unsigned_type_node,
22456 long_long_unsigned_type_node,
22458 tree float_ftype_float
22459 = build_function_type_list (float_type_node,
22464 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22466 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22468 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22470 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22472 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22474 tree v8sf_ftype_v8sf
22475 = build_function_type_list (V8SF_type_node,
22478 tree v8si_ftype_v8sf
22479 = build_function_type_list (V8SI_type_node,
22482 tree v8sf_ftype_v8si
22483 = build_function_type_list (V8SF_type_node,
22486 tree v4si_ftype_v4df
22487 = build_function_type_list (V4SI_type_node,
22490 tree v4df_ftype_v4df
22491 = build_function_type_list (V4DF_type_node,
22494 tree v4df_ftype_v4si
22495 = build_function_type_list (V4DF_type_node,
22498 tree v4df_ftype_v4sf
22499 = build_function_type_list (V4DF_type_node,
22502 tree v4sf_ftype_v4df
22503 = build_function_type_list (V4SF_type_node,
22506 tree v8sf_ftype_v8sf_v8sf
22507 = build_function_type_list (V8SF_type_node,
22508 V8SF_type_node, V8SF_type_node,
22510 tree v4df_ftype_v4df_v4df
22511 = build_function_type_list (V4DF_type_node,
22512 V4DF_type_node, V4DF_type_node,
22514 tree v8sf_ftype_v8sf_int
22515 = build_function_type_list (V8SF_type_node,
22516 V8SF_type_node, integer_type_node,
22518 tree v4si_ftype_v8si_int
22519 = build_function_type_list (V4SI_type_node,
22520 V8SI_type_node, integer_type_node,
22522 tree v4df_ftype_v4df_int
22523 = build_function_type_list (V4DF_type_node,
22524 V4DF_type_node, integer_type_node,
22526 tree v4sf_ftype_v8sf_int
22527 = build_function_type_list (V4SF_type_node,
22528 V8SF_type_node, integer_type_node,
22530 tree v2df_ftype_v4df_int
22531 = build_function_type_list (V2DF_type_node,
22532 V4DF_type_node, integer_type_node,
22534 tree v8sf_ftype_v8sf_v8sf_int
22535 = build_function_type_list (V8SF_type_node,
22536 V8SF_type_node, V8SF_type_node,
22539 tree v8sf_ftype_v8sf_v8sf_v8sf
22540 = build_function_type_list (V8SF_type_node,
22541 V8SF_type_node, V8SF_type_node,
22544 tree v4df_ftype_v4df_v4df_v4df
22545 = build_function_type_list (V4DF_type_node,
22546 V4DF_type_node, V4DF_type_node,
22549 tree v8si_ftype_v8si_v8si_int
22550 = build_function_type_list (V8SI_type_node,
22551 V8SI_type_node, V8SI_type_node,
22554 tree v4df_ftype_v4df_v4df_int
22555 = build_function_type_list (V4DF_type_node,
22556 V4DF_type_node, V4DF_type_node,
22559 tree v8sf_ftype_pcfloat
22560 = build_function_type_list (V8SF_type_node,
22563 tree v4df_ftype_pcdouble
22564 = build_function_type_list (V4DF_type_node,
22565 pcdouble_type_node,
22567 tree pcv4sf_type_node
22568 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22569 tree pcv2df_type_node
22570 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22571 tree v8sf_ftype_pcv4sf
22572 = build_function_type_list (V8SF_type_node,
22575 tree v4df_ftype_pcv2df
22576 = build_function_type_list (V4DF_type_node,
22579 tree v32qi_ftype_pcchar
22580 = build_function_type_list (V32QI_type_node,
22583 tree void_ftype_pchar_v32qi
22584 = build_function_type_list (void_type_node,
22585 pchar_type_node, V32QI_type_node,
22587 tree v8si_ftype_v8si_v4si_int
22588 = build_function_type_list (V8SI_type_node,
22589 V8SI_type_node, V4SI_type_node,
22592 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22593 tree void_ftype_pv4di_v4di
22594 = build_function_type_list (void_type_node,
22595 pv4di_type_node, V4DI_type_node,
22597 tree v8sf_ftype_v8sf_v4sf_int
22598 = build_function_type_list (V8SF_type_node,
22599 V8SF_type_node, V4SF_type_node,
22602 tree v4df_ftype_v4df_v2df_int
22603 = build_function_type_list (V4DF_type_node,
22604 V4DF_type_node, V2DF_type_node,
22607 tree void_ftype_pfloat_v8sf
22608 = build_function_type_list (void_type_node,
22609 pfloat_type_node, V8SF_type_node,
22611 tree void_ftype_pdouble_v4df
22612 = build_function_type_list (void_type_node,
22613 pdouble_type_node, V4DF_type_node,
22615 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22616 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22617 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22618 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22619 tree pcv8sf_type_node
22620 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22621 tree pcv4df_type_node
22622 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22623 tree v8sf_ftype_pcv8sf_v8si
22624 = build_function_type_list (V8SF_type_node,
22625 pcv8sf_type_node, V8SI_type_node,
22627 tree v4df_ftype_pcv4df_v4di
22628 = build_function_type_list (V4DF_type_node,
22629 pcv4df_type_node, V4DI_type_node,
22631 tree v4sf_ftype_pcv4sf_v4si
22632 = build_function_type_list (V4SF_type_node,
22633 pcv4sf_type_node, V4SI_type_node,
22635 tree v2df_ftype_pcv2df_v2di
22636 = build_function_type_list (V2DF_type_node,
22637 pcv2df_type_node, V2DI_type_node,
22639 tree void_ftype_pv8sf_v8si_v8sf
22640 = build_function_type_list (void_type_node,
22641 pv8sf_type_node, V8SI_type_node,
22644 tree void_ftype_pv4df_v4di_v4df
22645 = build_function_type_list (void_type_node,
22646 pv4df_type_node, V4DI_type_node,
22649 tree void_ftype_pv4sf_v4si_v4sf
22650 = build_function_type_list (void_type_node,
22651 pv4sf_type_node, V4SI_type_node,
22654 tree void_ftype_pv2df_v2di_v2df
22655 = build_function_type_list (void_type_node,
22656 pv2df_type_node, V2DI_type_node,
22659 tree v4df_ftype_v2df
22660 = build_function_type_list (V4DF_type_node,
22663 tree v8sf_ftype_v4sf
22664 = build_function_type_list (V8SF_type_node,
22667 tree v8si_ftype_v4si
22668 = build_function_type_list (V8SI_type_node,
22671 tree v2df_ftype_v4df
22672 = build_function_type_list (V2DF_type_node,
22675 tree v4sf_ftype_v8sf
22676 = build_function_type_list (V4SF_type_node,
22679 tree v4si_ftype_v8si
22680 = build_function_type_list (V4SI_type_node,
22683 tree int_ftype_v4df
22684 = build_function_type_list (integer_type_node,
22687 tree int_ftype_v8sf
22688 = build_function_type_list (integer_type_node,
22691 tree int_ftype_v8sf_v8sf
22692 = build_function_type_list (integer_type_node,
22693 V8SF_type_node, V8SF_type_node,
22695 tree int_ftype_v4di_v4di
22696 = build_function_type_list (integer_type_node,
22697 V4DI_type_node, V4DI_type_node,
22699 tree int_ftype_v4df_v4df
22700 = build_function_type_list (integer_type_node,
22701 V4DF_type_node, V4DF_type_node,
22703 tree v8sf_ftype_v8sf_v8si
22704 = build_function_type_list (V8SF_type_node,
22705 V8SF_type_node, V8SI_type_node,
22707 tree v4df_ftype_v4df_v4di
22708 = build_function_type_list (V4DF_type_node,
22709 V4DF_type_node, V4DI_type_node,
22711 tree v4sf_ftype_v4sf_v4si
22712 = build_function_type_list (V4SF_type_node,
22713 V4SF_type_node, V4SI_type_node, NULL_TREE);
22714 tree v2df_ftype_v2df_v2di
22715 = build_function_type_list (V2DF_type_node,
22716 V2DF_type_node, V2DI_type_node, NULL_TREE);
22720 /* Add all special builtins with variable number of operands. */
22721 for (i = 0, d = bdesc_special_args;
22722 i < ARRAY_SIZE (bdesc_special_args);
22730 switch ((enum ix86_special_builtin_type) d->flag)
22732 case VOID_FTYPE_VOID:
22733 type = void_ftype_void;
22735 case V32QI_FTYPE_PCCHAR:
22736 type = v32qi_ftype_pcchar;
22738 case V16QI_FTYPE_PCCHAR:
22739 type = v16qi_ftype_pcchar;
22741 case V8SF_FTYPE_PCV4SF:
22742 type = v8sf_ftype_pcv4sf;
22744 case V8SF_FTYPE_PCFLOAT:
22745 type = v8sf_ftype_pcfloat;
22747 case V4DF_FTYPE_PCV2DF:
22748 type = v4df_ftype_pcv2df;
22750 case V4DF_FTYPE_PCDOUBLE:
22751 type = v4df_ftype_pcdouble;
22753 case V4SF_FTYPE_PCFLOAT:
22754 type = v4sf_ftype_pcfloat;
22756 case V2DI_FTYPE_PV2DI:
22757 type = v2di_ftype_pv2di;
22759 case V2DF_FTYPE_PCDOUBLE:
22760 type = v2df_ftype_pcdouble;
22762 case V8SF_FTYPE_PCV8SF_V8SI:
22763 type = v8sf_ftype_pcv8sf_v8si;
22765 case V4DF_FTYPE_PCV4DF_V4DI:
22766 type = v4df_ftype_pcv4df_v4di;
22768 case V4SF_FTYPE_V4SF_PCV2SF:
22769 type = v4sf_ftype_v4sf_pcv2sf;
22771 case V4SF_FTYPE_PCV4SF_V4SI:
22772 type = v4sf_ftype_pcv4sf_v4si;
22774 case V2DF_FTYPE_V2DF_PCDOUBLE:
22775 type = v2df_ftype_v2df_pcdouble;
22777 case V2DF_FTYPE_PCV2DF_V2DI:
22778 type = v2df_ftype_pcv2df_v2di;
22780 case VOID_FTYPE_PV2SF_V4SF:
22781 type = void_ftype_pv2sf_v4sf;
22783 case VOID_FTYPE_PV4DI_V4DI:
22784 type = void_ftype_pv4di_v4di;
22786 case VOID_FTYPE_PV2DI_V2DI:
22787 type = void_ftype_pv2di_v2di;
22789 case VOID_FTYPE_PCHAR_V32QI:
22790 type = void_ftype_pchar_v32qi;
22792 case VOID_FTYPE_PCHAR_V16QI:
22793 type = void_ftype_pchar_v16qi;
22795 case VOID_FTYPE_PFLOAT_V8SF:
22796 type = void_ftype_pfloat_v8sf;
22798 case VOID_FTYPE_PFLOAT_V4SF:
22799 type = void_ftype_pfloat_v4sf;
22801 case VOID_FTYPE_PDOUBLE_V4DF:
22802 type = void_ftype_pdouble_v4df;
22804 case VOID_FTYPE_PDOUBLE_V2DF:
22805 type = void_ftype_pdouble_v2df;
22807 case VOID_FTYPE_PDI_DI:
22808 type = void_ftype_pdi_di;
22810 case VOID_FTYPE_PINT_INT:
22811 type = void_ftype_pint_int;
22813 case VOID_FTYPE_PV8SF_V8SI_V8SF:
22814 type = void_ftype_pv8sf_v8si_v8sf;
22816 case VOID_FTYPE_PV4DF_V4DI_V4DF:
22817 type = void_ftype_pv4df_v4di_v4df;
22819 case VOID_FTYPE_PV4SF_V4SI_V4SF:
22820 type = void_ftype_pv4sf_v4si_v4sf;
22822 case VOID_FTYPE_PV2DF_V2DI_V2DF:
22823 type = void_ftype_pv2df_v2di_v2df;
22826 gcc_unreachable ();
22829 def_builtin (d->mask, d->name, type, d->code);
22832 /* Add all builtins with variable number of operands. */
22833 for (i = 0, d = bdesc_args;
22834 i < ARRAY_SIZE (bdesc_args);
22842 switch ((enum ix86_builtin_type) d->flag)
22844 case FLOAT_FTYPE_FLOAT:
22845 type = float_ftype_float;
22847 case INT_FTYPE_V8SF_V8SF_PTEST:
22848 type = int_ftype_v8sf_v8sf;
22850 case INT_FTYPE_V4DI_V4DI_PTEST:
22851 type = int_ftype_v4di_v4di;
22853 case INT_FTYPE_V4DF_V4DF_PTEST:
22854 type = int_ftype_v4df_v4df;
22856 case INT_FTYPE_V4SF_V4SF_PTEST:
22857 type = int_ftype_v4sf_v4sf;
22859 case INT_FTYPE_V2DI_V2DI_PTEST:
22860 type = int_ftype_v2di_v2di;
22862 case INT_FTYPE_V2DF_V2DF_PTEST:
22863 type = int_ftype_v2df_v2df;
22865 case INT64_FTYPE_V4SF:
22866 type = int64_ftype_v4sf;
22868 case INT64_FTYPE_V2DF:
22869 type = int64_ftype_v2df;
22871 case INT_FTYPE_V16QI:
22872 type = int_ftype_v16qi;
22874 case INT_FTYPE_V8QI:
22875 type = int_ftype_v8qi;
22877 case INT_FTYPE_V8SF:
22878 type = int_ftype_v8sf;
22880 case INT_FTYPE_V4DF:
22881 type = int_ftype_v4df;
22883 case INT_FTYPE_V4SF:
22884 type = int_ftype_v4sf;
22886 case INT_FTYPE_V2DF:
22887 type = int_ftype_v2df;
22889 case V16QI_FTYPE_V16QI:
22890 type = v16qi_ftype_v16qi;
22892 case V8SI_FTYPE_V8SF:
22893 type = v8si_ftype_v8sf;
22895 case V8SI_FTYPE_V4SI:
22896 type = v8si_ftype_v4si;
22898 case V8HI_FTYPE_V8HI:
22899 type = v8hi_ftype_v8hi;
22901 case V8HI_FTYPE_V16QI:
22902 type = v8hi_ftype_v16qi;
22904 case V8QI_FTYPE_V8QI:
22905 type = v8qi_ftype_v8qi;
22907 case V8SF_FTYPE_V8SF:
22908 type = v8sf_ftype_v8sf;
22910 case V8SF_FTYPE_V8SI:
22911 type = v8sf_ftype_v8si;
22913 case V8SF_FTYPE_V4SF:
22914 type = v8sf_ftype_v4sf;
22916 case V4SI_FTYPE_V4DF:
22917 type = v4si_ftype_v4df;
22919 case V4SI_FTYPE_V4SI:
22920 type = v4si_ftype_v4si;
22922 case V4SI_FTYPE_V16QI:
22923 type = v4si_ftype_v16qi;
22925 case V4SI_FTYPE_V8SI:
22926 type = v4si_ftype_v8si;
22928 case V4SI_FTYPE_V8HI:
22929 type = v4si_ftype_v8hi;
22931 case V4SI_FTYPE_V4SF:
22932 type = v4si_ftype_v4sf;
22934 case V4SI_FTYPE_V2DF:
22935 type = v4si_ftype_v2df;
22937 case V4HI_FTYPE_V4HI:
22938 type = v4hi_ftype_v4hi;
22940 case V4DF_FTYPE_V4DF:
22941 type = v4df_ftype_v4df;
22943 case V4DF_FTYPE_V4SI:
22944 type = v4df_ftype_v4si;
22946 case V4DF_FTYPE_V4SF:
22947 type = v4df_ftype_v4sf;
22949 case V4DF_FTYPE_V2DF:
22950 type = v4df_ftype_v2df;
22952 case V4SF_FTYPE_V4SF:
22953 case V4SF_FTYPE_V4SF_VEC_MERGE:
22954 type = v4sf_ftype_v4sf;
22956 case V4SF_FTYPE_V8SF:
22957 type = v4sf_ftype_v8sf;
22959 case V4SF_FTYPE_V4SI:
22960 type = v4sf_ftype_v4si;
22962 case V4SF_FTYPE_V4DF:
22963 type = v4sf_ftype_v4df;
22965 case V4SF_FTYPE_V2DF:
22966 type = v4sf_ftype_v2df;
22968 case V2DI_FTYPE_V2DI:
22969 type = v2di_ftype_v2di;
22971 case V2DI_FTYPE_V16QI:
22972 type = v2di_ftype_v16qi;
22974 case V2DI_FTYPE_V8HI:
22975 type = v2di_ftype_v8hi;
22977 case V2DI_FTYPE_V4SI:
22978 type = v2di_ftype_v4si;
22980 case V2SI_FTYPE_V2SI:
22981 type = v2si_ftype_v2si;
22983 case V2SI_FTYPE_V4SF:
22984 type = v2si_ftype_v4sf;
22986 case V2SI_FTYPE_V2DF:
22987 type = v2si_ftype_v2df;
22989 case V2SI_FTYPE_V2SF:
22990 type = v2si_ftype_v2sf;
22992 case V2DF_FTYPE_V4DF:
22993 type = v2df_ftype_v4df;
22995 case V2DF_FTYPE_V4SF:
22996 type = v2df_ftype_v4sf;
22998 case V2DF_FTYPE_V2DF:
22999 case V2DF_FTYPE_V2DF_VEC_MERGE:
23000 type = v2df_ftype_v2df;
23002 case V2DF_FTYPE_V2SI:
23003 type = v2df_ftype_v2si;
23005 case V2DF_FTYPE_V4SI:
23006 type = v2df_ftype_v4si;
23008 case V2SF_FTYPE_V2SF:
23009 type = v2sf_ftype_v2sf;
23011 case V2SF_FTYPE_V2SI:
23012 type = v2sf_ftype_v2si;
23014 case V16QI_FTYPE_V16QI_V16QI:
23015 type = v16qi_ftype_v16qi_v16qi;
23017 case V16QI_FTYPE_V8HI_V8HI:
23018 type = v16qi_ftype_v8hi_v8hi;
23020 case V8QI_FTYPE_V8QI_V8QI:
23021 type = v8qi_ftype_v8qi_v8qi;
23023 case V8QI_FTYPE_V4HI_V4HI:
23024 type = v8qi_ftype_v4hi_v4hi;
23026 case V8HI_FTYPE_V8HI_V8HI:
23027 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23028 type = v8hi_ftype_v8hi_v8hi;
23030 case V8HI_FTYPE_V16QI_V16QI:
23031 type = v8hi_ftype_v16qi_v16qi;
23033 case V8HI_FTYPE_V4SI_V4SI:
23034 type = v8hi_ftype_v4si_v4si;
23036 case V8HI_FTYPE_V8HI_SI_COUNT:
23037 type = v8hi_ftype_v8hi_int;
23039 case V8SF_FTYPE_V8SF_V8SF:
23040 type = v8sf_ftype_v8sf_v8sf;
23042 case V8SF_FTYPE_V8SF_V8SI:
23043 type = v8sf_ftype_v8sf_v8si;
23045 case V4SI_FTYPE_V4SI_V4SI:
23046 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23047 type = v4si_ftype_v4si_v4si;
23049 case V4SI_FTYPE_V8HI_V8HI:
23050 type = v4si_ftype_v8hi_v8hi;
23052 case V4SI_FTYPE_V4SF_V4SF:
23053 type = v4si_ftype_v4sf_v4sf;
23055 case V4SI_FTYPE_V2DF_V2DF:
23056 type = v4si_ftype_v2df_v2df;
23058 case V4SI_FTYPE_V4SI_SI_COUNT:
23059 type = v4si_ftype_v4si_int;
23061 case V4HI_FTYPE_V4HI_V4HI:
23062 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23063 type = v4hi_ftype_v4hi_v4hi;
23065 case V4HI_FTYPE_V8QI_V8QI:
23066 type = v4hi_ftype_v8qi_v8qi;
23068 case V4HI_FTYPE_V2SI_V2SI:
23069 type = v4hi_ftype_v2si_v2si;
23071 case V4HI_FTYPE_V4HI_SI_COUNT:
23072 type = v4hi_ftype_v4hi_int;
23074 case V4DF_FTYPE_V4DF_V4DF:
23075 type = v4df_ftype_v4df_v4df;
23077 case V4DF_FTYPE_V4DF_V4DI:
23078 type = v4df_ftype_v4df_v4di;
23080 case V4SF_FTYPE_V4SF_V4SF:
23081 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23082 type = v4sf_ftype_v4sf_v4sf;
23084 case V4SF_FTYPE_V4SF_V4SI:
23085 type = v4sf_ftype_v4sf_v4si;
23087 case V4SF_FTYPE_V4SF_V2SI:
23088 type = v4sf_ftype_v4sf_v2si;
23090 case V4SF_FTYPE_V4SF_V2DF:
23091 type = v4sf_ftype_v4sf_v2df;
23093 case V4SF_FTYPE_V4SF_DI:
23094 type = v4sf_ftype_v4sf_int64;
23096 case V4SF_FTYPE_V4SF_SI:
23097 type = v4sf_ftype_v4sf_int;
23099 case V2DI_FTYPE_V2DI_V2DI:
23100 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23101 type = v2di_ftype_v2di_v2di;
23103 case V2DI_FTYPE_V16QI_V16QI:
23104 type = v2di_ftype_v16qi_v16qi;
23106 case V2DI_FTYPE_V4SI_V4SI:
23107 type = v2di_ftype_v4si_v4si;
23109 case V2DI_FTYPE_V2DI_V16QI:
23110 type = v2di_ftype_v2di_v16qi;
23112 case V2DI_FTYPE_V2DF_V2DF:
23113 type = v2di_ftype_v2df_v2df;
23115 case V2DI_FTYPE_V2DI_SI_COUNT:
23116 type = v2di_ftype_v2di_int;
23118 case V2SI_FTYPE_V2SI_V2SI:
23119 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23120 type = v2si_ftype_v2si_v2si;
23122 case V2SI_FTYPE_V4HI_V4HI:
23123 type = v2si_ftype_v4hi_v4hi;
23125 case V2SI_FTYPE_V2SF_V2SF:
23126 type = v2si_ftype_v2sf_v2sf;
23128 case V2SI_FTYPE_V2SI_SI_COUNT:
23129 type = v2si_ftype_v2si_int;
23131 case V2DF_FTYPE_V2DF_V2DF:
23132 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23133 type = v2df_ftype_v2df_v2df;
23135 case V2DF_FTYPE_V2DF_V4SF:
23136 type = v2df_ftype_v2df_v4sf;
23138 case V2DF_FTYPE_V2DF_V2DI:
23139 type = v2df_ftype_v2df_v2di;
23141 case V2DF_FTYPE_V2DF_DI:
23142 type = v2df_ftype_v2df_int64;
23144 case V2DF_FTYPE_V2DF_SI:
23145 type = v2df_ftype_v2df_int;
23147 case V2SF_FTYPE_V2SF_V2SF:
23148 type = v2sf_ftype_v2sf_v2sf;
23150 case V1DI_FTYPE_V1DI_V1DI:
23151 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23152 type = v1di_ftype_v1di_v1di;
23154 case V1DI_FTYPE_V8QI_V8QI:
23155 type = v1di_ftype_v8qi_v8qi;
23157 case V1DI_FTYPE_V2SI_V2SI:
23158 type = v1di_ftype_v2si_v2si;
23160 case V1DI_FTYPE_V1DI_SI_COUNT:
23161 type = v1di_ftype_v1di_int;
23163 case UINT64_FTYPE_UINT64_UINT64:
23164 type = uint64_ftype_uint64_uint64;
23166 case UINT_FTYPE_UINT_UINT:
23167 type = unsigned_ftype_unsigned_unsigned;
23169 case UINT_FTYPE_UINT_USHORT:
23170 type = unsigned_ftype_unsigned_ushort;
23172 case UINT_FTYPE_UINT_UCHAR:
23173 type = unsigned_ftype_unsigned_uchar;
23175 case V8HI_FTYPE_V8HI_INT:
23176 type = v8hi_ftype_v8hi_int;
23178 case V8SF_FTYPE_V8SF_INT:
23179 type = v8sf_ftype_v8sf_int;
23181 case V4SI_FTYPE_V4SI_INT:
23182 type = v4si_ftype_v4si_int;
23184 case V4SI_FTYPE_V8SI_INT:
23185 type = v4si_ftype_v8si_int;
23187 case V4HI_FTYPE_V4HI_INT:
23188 type = v4hi_ftype_v4hi_int;
23190 case V4DF_FTYPE_V4DF_INT:
23191 type = v4df_ftype_v4df_int;
23193 case V4SF_FTYPE_V4SF_INT:
23194 type = v4sf_ftype_v4sf_int;
23196 case V4SF_FTYPE_V8SF_INT:
23197 type = v4sf_ftype_v8sf_int;
23199 case V2DI_FTYPE_V2DI_INT:
23200 case V2DI2TI_FTYPE_V2DI_INT:
23201 type = v2di_ftype_v2di_int;
23203 case V2DF_FTYPE_V2DF_INT:
23204 type = v2df_ftype_v2df_int;
23206 case V2DF_FTYPE_V4DF_INT:
23207 type = v2df_ftype_v4df_int;
23209 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23210 type = v16qi_ftype_v16qi_v16qi_v16qi;
23212 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23213 type = v8sf_ftype_v8sf_v8sf_v8sf;
23215 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23216 type = v4df_ftype_v4df_v4df_v4df;
23218 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23219 type = v4sf_ftype_v4sf_v4sf_v4sf;
23221 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23222 type = v2df_ftype_v2df_v2df_v2df;
23224 case V16QI_FTYPE_V16QI_V16QI_INT:
23225 type = v16qi_ftype_v16qi_v16qi_int;
23227 case V8SI_FTYPE_V8SI_V8SI_INT:
23228 type = v8si_ftype_v8si_v8si_int;
23230 case V8SI_FTYPE_V8SI_V4SI_INT:
23231 type = v8si_ftype_v8si_v4si_int;
23233 case V8HI_FTYPE_V8HI_V8HI_INT:
23234 type = v8hi_ftype_v8hi_v8hi_int;
23236 case V8SF_FTYPE_V8SF_V8SF_INT:
23237 type = v8sf_ftype_v8sf_v8sf_int;
23239 case V8SF_FTYPE_V8SF_V4SF_INT:
23240 type = v8sf_ftype_v8sf_v4sf_int;
23242 case V4SI_FTYPE_V4SI_V4SI_INT:
23243 type = v4si_ftype_v4si_v4si_int;
23245 case V4DF_FTYPE_V4DF_V4DF_INT:
23246 type = v4df_ftype_v4df_v4df_int;
23248 case V4DF_FTYPE_V4DF_V2DF_INT:
23249 type = v4df_ftype_v4df_v2df_int;
23251 case V4SF_FTYPE_V4SF_V4SF_INT:
23252 type = v4sf_ftype_v4sf_v4sf_int;
23254 case V2DI_FTYPE_V2DI_V2DI_INT:
23255 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23256 type = v2di_ftype_v2di_v2di_int;
23258 case V2DF_FTYPE_V2DF_V2DF_INT:
23259 type = v2df_ftype_v2df_v2df_int;
23261 case V2DI_FTYPE_V2DI_UINT_UINT:
23262 type = v2di_ftype_v2di_unsigned_unsigned;
23264 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23265 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23267 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23268 type = v1di_ftype_v1di_v1di_int;
23271 gcc_unreachable ();
23274 def_builtin_const (d->mask, d->name, type, d->code);
23277 /* pcmpestr[im] insns. */
23278 for (i = 0, d = bdesc_pcmpestr;
23279 i < ARRAY_SIZE (bdesc_pcmpestr);
23282 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23283 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23285 ftype = int_ftype_v16qi_int_v16qi_int_int;
23286 def_builtin_const (d->mask, d->name, ftype, d->code);
23289 /* pcmpistr[im] insns. */
23290 for (i = 0, d = bdesc_pcmpistr;
23291 i < ARRAY_SIZE (bdesc_pcmpistr);
23294 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23295 ftype = v16qi_ftype_v16qi_v16qi_int;
23297 ftype = int_ftype_v16qi_v16qi_int;
23298 def_builtin_const (d->mask, d->name, ftype, d->code);
23301 /* comi/ucomi insns. */
23302 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23303 if (d->mask == OPTION_MASK_ISA_SSE2)
23304 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23306 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23309 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23310 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23312 /* SSE or 3DNow!A */
23313 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23316 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23318 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23319 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23322 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23323 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23326 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23327 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23328 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23329 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23330 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23331 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23334 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23337 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23338 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23340 /* Access to the vec_init patterns. */
23341 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23342 integer_type_node, NULL_TREE);
23343 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23345 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23346 short_integer_type_node,
23347 short_integer_type_node,
23348 short_integer_type_node, NULL_TREE);
23349 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23351 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23352 char_type_node, char_type_node,
23353 char_type_node, char_type_node,
23354 char_type_node, char_type_node,
23355 char_type_node, NULL_TREE);
23356 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23358 /* Access to the vec_extract patterns. */
23359 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23360 integer_type_node, NULL_TREE);
23361 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23363 ftype = build_function_type_list (long_long_integer_type_node,
23364 V2DI_type_node, integer_type_node,
23366 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23368 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23369 integer_type_node, NULL_TREE);
23370 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23372 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23373 integer_type_node, NULL_TREE);
23374 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23376 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23377 integer_type_node, NULL_TREE);
23378 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23380 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23381 integer_type_node, NULL_TREE);
23382 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23384 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23385 integer_type_node, NULL_TREE);
23386 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23388 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23389 integer_type_node, NULL_TREE);
23390 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23392 /* Access to the vec_set patterns. */
23393 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23395 integer_type_node, NULL_TREE);
23396 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23398 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23400 integer_type_node, NULL_TREE);
23401 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23403 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23405 integer_type_node, NULL_TREE);
23406 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23408 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23410 integer_type_node, NULL_TREE);
23411 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23413 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23415 integer_type_node, NULL_TREE);
23416 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23418 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23420 integer_type_node, NULL_TREE);
23421 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23423 /* Add SSE5 multi-arg argument instructions */
23424 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23426 tree mtype = NULL_TREE;
23431 switch ((enum multi_arg_type)d->flag)
23433 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23434 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23435 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23436 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23437 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23438 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23439 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23440 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23441 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23442 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23443 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23444 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23445 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23446 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23447 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23448 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23449 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23450 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23451 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23452 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23453 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23454 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23455 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23456 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23457 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23458 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23459 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23460 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23461 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23462 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23463 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23464 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23465 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23466 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23467 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23468 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23469 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23470 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23471 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23472 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23473 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23474 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23475 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23476 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23477 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23478 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23479 case MULTI_ARG_UNKNOWN:
23481 gcc_unreachable ();
23485 def_builtin_const (d->mask, d->name, mtype, d->code);
23489 /* Internal method for ix86_init_builtins. */
23492 ix86_init_builtins_va_builtins_abi (void)
23494 tree ms_va_ref, sysv_va_ref;
23495 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23496 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23497 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23498 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23502 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23503 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23504 ms_va_ref = build_reference_type (ms_va_list_type_node);
23506 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23509 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23510 fnvoid_va_start_ms =
23511 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23512 fnvoid_va_end_sysv =
23513 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23514 fnvoid_va_start_sysv =
23515 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23517 fnvoid_va_copy_ms =
23518 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23520 fnvoid_va_copy_sysv =
23521 build_function_type_list (void_type_node, sysv_va_ref,
23522 sysv_va_ref, NULL_TREE);
23524 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23525 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23526 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23527 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23528 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23529 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23530 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23531 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23532 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23533 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23534 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23535 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23539 ix86_init_builtins (void)
23541 tree float128_type_node = make_node (REAL_TYPE);
23544 /* The __float80 type. */
23545 if (TYPE_MODE (long_double_type_node) == XFmode)
23546 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23550 /* The __float80 type. */
23551 tree float80_type_node = make_node (REAL_TYPE);
23553 TYPE_PRECISION (float80_type_node) = 80;
23554 layout_type (float80_type_node);
23555 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23559 /* The __float128 type. */
23560 TYPE_PRECISION (float128_type_node) = 128;
23561 layout_type (float128_type_node);
23562 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23565 /* TFmode support builtins. */
23566 ftype = build_function_type (float128_type_node, void_list_node);
23567 decl = add_builtin_function ("__builtin_infq", ftype,
23568 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23570 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23572 /* We will expand them to normal call if SSE2 isn't available since
23573 they are used by libgcc. */
23574 ftype = build_function_type_list (float128_type_node,
23575 float128_type_node,
23577 decl = add_builtin_function ("__builtin_fabsq", ftype,
23578 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23579 "__fabstf2", NULL_TREE);
23580 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23581 TREE_READONLY (decl) = 1;
23583 ftype = build_function_type_list (float128_type_node,
23584 float128_type_node,
23585 float128_type_node,
23587 decl = add_builtin_function ("__builtin_copysignq", ftype,
23588 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23589 "__copysigntf3", NULL_TREE);
23590 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23591 TREE_READONLY (decl) = 1;
23593 ix86_init_mmx_sse_builtins ();
23595 ix86_init_builtins_va_builtins_abi ();
23598 /* Errors in the source file can cause expand_expr to return const0_rtx
23599 where we expect a vector. To avoid crashing, use one of the vector
23600 clear instructions. */
23602 safe_vector_operand (rtx x, enum machine_mode mode)
23604 if (x == const0_rtx)
23605 x = CONST0_RTX (mode);
23609 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23612 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23615 tree arg0 = CALL_EXPR_ARG (exp, 0);
23616 tree arg1 = CALL_EXPR_ARG (exp, 1);
23617 rtx op0 = expand_normal (arg0);
23618 rtx op1 = expand_normal (arg1);
23619 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23620 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23621 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23623 if (VECTOR_MODE_P (mode0))
23624 op0 = safe_vector_operand (op0, mode0);
23625 if (VECTOR_MODE_P (mode1))
23626 op1 = safe_vector_operand (op1, mode1);
23628 if (optimize || !target
23629 || GET_MODE (target) != tmode
23630 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23631 target = gen_reg_rtx (tmode);
23633 if (GET_MODE (op1) == SImode && mode1 == TImode)
23635 rtx x = gen_reg_rtx (V4SImode);
23636 emit_insn (gen_sse2_loadd (x, op1));
23637 op1 = gen_lowpart (TImode, x);
23640 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23641 op0 = copy_to_mode_reg (mode0, op0);
23642 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23643 op1 = copy_to_mode_reg (mode1, op1);
23645 pat = GEN_FCN (icode) (target, op0, op1);
23654 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23657 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23658 enum multi_arg_type m_type,
23659 enum insn_code sub_code)
23664 bool comparison_p = false;
23666 bool last_arg_constant = false;
23667 int num_memory = 0;
23670 enum machine_mode mode;
23673 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23677 case MULTI_ARG_3_SF:
23678 case MULTI_ARG_3_DF:
23679 case MULTI_ARG_3_DI:
23680 case MULTI_ARG_3_SI:
23681 case MULTI_ARG_3_SI_DI:
23682 case MULTI_ARG_3_HI:
23683 case MULTI_ARG_3_HI_SI:
23684 case MULTI_ARG_3_QI:
23685 case MULTI_ARG_3_PERMPS:
23686 case MULTI_ARG_3_PERMPD:
23690 case MULTI_ARG_2_SF:
23691 case MULTI_ARG_2_DF:
23692 case MULTI_ARG_2_DI:
23693 case MULTI_ARG_2_SI:
23694 case MULTI_ARG_2_HI:
23695 case MULTI_ARG_2_QI:
23699 case MULTI_ARG_2_DI_IMM:
23700 case MULTI_ARG_2_SI_IMM:
23701 case MULTI_ARG_2_HI_IMM:
23702 case MULTI_ARG_2_QI_IMM:
23704 last_arg_constant = true;
23707 case MULTI_ARG_1_SF:
23708 case MULTI_ARG_1_DF:
23709 case MULTI_ARG_1_DI:
23710 case MULTI_ARG_1_SI:
23711 case MULTI_ARG_1_HI:
23712 case MULTI_ARG_1_QI:
23713 case MULTI_ARG_1_SI_DI:
23714 case MULTI_ARG_1_HI_DI:
23715 case MULTI_ARG_1_HI_SI:
23716 case MULTI_ARG_1_QI_DI:
23717 case MULTI_ARG_1_QI_SI:
23718 case MULTI_ARG_1_QI_HI:
23719 case MULTI_ARG_1_PH2PS:
23720 case MULTI_ARG_1_PS2PH:
23724 case MULTI_ARG_2_SF_CMP:
23725 case MULTI_ARG_2_DF_CMP:
23726 case MULTI_ARG_2_DI_CMP:
23727 case MULTI_ARG_2_SI_CMP:
23728 case MULTI_ARG_2_HI_CMP:
23729 case MULTI_ARG_2_QI_CMP:
23731 comparison_p = true;
23734 case MULTI_ARG_2_SF_TF:
23735 case MULTI_ARG_2_DF_TF:
23736 case MULTI_ARG_2_DI_TF:
23737 case MULTI_ARG_2_SI_TF:
23738 case MULTI_ARG_2_HI_TF:
23739 case MULTI_ARG_2_QI_TF:
23744 case MULTI_ARG_UNKNOWN:
23746 gcc_unreachable ();
23749 if (optimize || !target
23750 || GET_MODE (target) != tmode
23751 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23752 target = gen_reg_rtx (tmode);
23754 gcc_assert (nargs <= 4);
23756 for (i = 0; i < nargs; i++)
23758 tree arg = CALL_EXPR_ARG (exp, i);
23759 rtx op = expand_normal (arg);
23760 int adjust = (comparison_p) ? 1 : 0;
23761 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23763 if (last_arg_constant && i == nargs-1)
23765 if (GET_CODE (op) != CONST_INT)
23767 error ("last argument must be an immediate");
23768 return gen_reg_rtx (tmode);
23773 if (VECTOR_MODE_P (mode))
23774 op = safe_vector_operand (op, mode);
23776 /* If we aren't optimizing, only allow one memory operand to be
23778 if (memory_operand (op, mode))
23781 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23784 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23786 op = force_reg (mode, op);
23790 args[i].mode = mode;
23796 pat = GEN_FCN (icode) (target, args[0].op);
23801 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23802 GEN_INT ((int)sub_code));
23803 else if (! comparison_p)
23804 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23807 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23811 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23816 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23820 gcc_unreachable ();
23830 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23831 insns with vec_merge. */
23834 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23838 tree arg0 = CALL_EXPR_ARG (exp, 0);
23839 rtx op1, op0 = expand_normal (arg0);
23840 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23841 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23843 if (optimize || !target
23844 || GET_MODE (target) != tmode
23845 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23846 target = gen_reg_rtx (tmode);
23848 if (VECTOR_MODE_P (mode0))
23849 op0 = safe_vector_operand (op0, mode0);
23851 if ((optimize && !register_operand (op0, mode0))
23852 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23853 op0 = copy_to_mode_reg (mode0, op0);
23856 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23857 op1 = copy_to_mode_reg (mode0, op1);
23859 pat = GEN_FCN (icode) (target, op0, op1);
23866 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23869 ix86_expand_sse_compare (const struct builtin_description *d,
23870 tree exp, rtx target, bool swap)
23873 tree arg0 = CALL_EXPR_ARG (exp, 0);
23874 tree arg1 = CALL_EXPR_ARG (exp, 1);
23875 rtx op0 = expand_normal (arg0);
23876 rtx op1 = expand_normal (arg1);
23878 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23879 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23880 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23881 enum rtx_code comparison = d->comparison;
23883 if (VECTOR_MODE_P (mode0))
23884 op0 = safe_vector_operand (op0, mode0);
23885 if (VECTOR_MODE_P (mode1))
23886 op1 = safe_vector_operand (op1, mode1);
23888 /* Swap operands if we have a comparison that isn't available in
23892 rtx tmp = gen_reg_rtx (mode1);
23893 emit_move_insn (tmp, op1);
23898 if (optimize || !target
23899 || GET_MODE (target) != tmode
23900 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23901 target = gen_reg_rtx (tmode);
23903 if ((optimize && !register_operand (op0, mode0))
23904 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23905 op0 = copy_to_mode_reg (mode0, op0);
23906 if ((optimize && !register_operand (op1, mode1))
23907 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23908 op1 = copy_to_mode_reg (mode1, op1);
23910 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23911 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23918 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23921 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23925 tree arg0 = CALL_EXPR_ARG (exp, 0);
23926 tree arg1 = CALL_EXPR_ARG (exp, 1);
23927 rtx op0 = expand_normal (arg0);
23928 rtx op1 = expand_normal (arg1);
23929 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23930 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23931 enum rtx_code comparison = d->comparison;
23933 if (VECTOR_MODE_P (mode0))
23934 op0 = safe_vector_operand (op0, mode0);
23935 if (VECTOR_MODE_P (mode1))
23936 op1 = safe_vector_operand (op1, mode1);
23938 /* Swap operands if we have a comparison that isn't available in
23940 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23947 target = gen_reg_rtx (SImode);
23948 emit_move_insn (target, const0_rtx);
23949 target = gen_rtx_SUBREG (QImode, target, 0);
23951 if ((optimize && !register_operand (op0, mode0))
23952 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23953 op0 = copy_to_mode_reg (mode0, op0);
23954 if ((optimize && !register_operand (op1, mode1))
23955 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23956 op1 = copy_to_mode_reg (mode1, op1);
23958 pat = GEN_FCN (d->icode) (op0, op1);
23962 emit_insn (gen_rtx_SET (VOIDmode,
23963 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23964 gen_rtx_fmt_ee (comparison, QImode,
23968 return SUBREG_REG (target);
23971 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23974 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23978 tree arg0 = CALL_EXPR_ARG (exp, 0);
23979 tree arg1 = CALL_EXPR_ARG (exp, 1);
23980 rtx op0 = expand_normal (arg0);
23981 rtx op1 = expand_normal (arg1);
23982 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23983 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23984 enum rtx_code comparison = d->comparison;
23986 if (VECTOR_MODE_P (mode0))
23987 op0 = safe_vector_operand (op0, mode0);
23988 if (VECTOR_MODE_P (mode1))
23989 op1 = safe_vector_operand (op1, mode1);
23991 target = gen_reg_rtx (SImode);
23992 emit_move_insn (target, const0_rtx);
23993 target = gen_rtx_SUBREG (QImode, target, 0);
23995 if ((optimize && !register_operand (op0, mode0))
23996 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23997 op0 = copy_to_mode_reg (mode0, op0);
23998 if ((optimize && !register_operand (op1, mode1))
23999 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24000 op1 = copy_to_mode_reg (mode1, op1);
24002 pat = GEN_FCN (d->icode) (op0, op1);
24006 emit_insn (gen_rtx_SET (VOIDmode,
24007 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24008 gen_rtx_fmt_ee (comparison, QImode,
24012 return SUBREG_REG (target);
24015 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
24018 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
24019 tree exp, rtx target)
24022 tree arg0 = CALL_EXPR_ARG (exp, 0);
24023 tree arg1 = CALL_EXPR_ARG (exp, 1);
24024 tree arg2 = CALL_EXPR_ARG (exp, 2);
24025 tree arg3 = CALL_EXPR_ARG (exp, 3);
24026 tree arg4 = CALL_EXPR_ARG (exp, 4);
24027 rtx scratch0, scratch1;
24028 rtx op0 = expand_normal (arg0);
24029 rtx op1 = expand_normal (arg1);
24030 rtx op2 = expand_normal (arg2);
24031 rtx op3 = expand_normal (arg3);
24032 rtx op4 = expand_normal (arg4);
24033 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
24035 tmode0 = insn_data[d->icode].operand[0].mode;
24036 tmode1 = insn_data[d->icode].operand[1].mode;
24037 modev2 = insn_data[d->icode].operand[2].mode;
24038 modei3 = insn_data[d->icode].operand[3].mode;
24039 modev4 = insn_data[d->icode].operand[4].mode;
24040 modei5 = insn_data[d->icode].operand[5].mode;
24041 modeimm = insn_data[d->icode].operand[6].mode;
24043 if (VECTOR_MODE_P (modev2))
24044 op0 = safe_vector_operand (op0, modev2);
24045 if (VECTOR_MODE_P (modev4))
24046 op2 = safe_vector_operand (op2, modev4);
24048 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24049 op0 = copy_to_mode_reg (modev2, op0);
24050 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
24051 op1 = copy_to_mode_reg (modei3, op1);
24052 if ((optimize && !register_operand (op2, modev4))
24053 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
24054 op2 = copy_to_mode_reg (modev4, op2);
24055 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
24056 op3 = copy_to_mode_reg (modei5, op3);
24058 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
24060 error ("the fifth argument must be a 8-bit immediate");
24064 if (d->code == IX86_BUILTIN_PCMPESTRI128)
24066 if (optimize || !target
24067 || GET_MODE (target) != tmode0
24068 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24069 target = gen_reg_rtx (tmode0);
24071 scratch1 = gen_reg_rtx (tmode1);
24073 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
24075 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
24077 if (optimize || !target
24078 || GET_MODE (target) != tmode1
24079 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24080 target = gen_reg_rtx (tmode1);
24082 scratch0 = gen_reg_rtx (tmode0);
24084 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
24088 gcc_assert (d->flag);
24090 scratch0 = gen_reg_rtx (tmode0);
24091 scratch1 = gen_reg_rtx (tmode1);
24093 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
24103 target = gen_reg_rtx (SImode);
24104 emit_move_insn (target, const0_rtx);
24105 target = gen_rtx_SUBREG (QImode, target, 0);
24108 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24109 gen_rtx_fmt_ee (EQ, QImode,
24110 gen_rtx_REG ((enum machine_mode) d->flag,
24113 return SUBREG_REG (target);
24120 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
24123 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
24124 tree exp, rtx target)
24127 tree arg0 = CALL_EXPR_ARG (exp, 0);
24128 tree arg1 = CALL_EXPR_ARG (exp, 1);
24129 tree arg2 = CALL_EXPR_ARG (exp, 2);
24130 rtx scratch0, scratch1;
24131 rtx op0 = expand_normal (arg0);
24132 rtx op1 = expand_normal (arg1);
24133 rtx op2 = expand_normal (arg2);
24134 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
24136 tmode0 = insn_data[d->icode].operand[0].mode;
24137 tmode1 = insn_data[d->icode].operand[1].mode;
24138 modev2 = insn_data[d->icode].operand[2].mode;
24139 modev3 = insn_data[d->icode].operand[3].mode;
24140 modeimm = insn_data[d->icode].operand[4].mode;
24142 if (VECTOR_MODE_P (modev2))
24143 op0 = safe_vector_operand (op0, modev2);
24144 if (VECTOR_MODE_P (modev3))
24145 op1 = safe_vector_operand (op1, modev3);
24147 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24148 op0 = copy_to_mode_reg (modev2, op0);
24149 if ((optimize && !register_operand (op1, modev3))
24150 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
24151 op1 = copy_to_mode_reg (modev3, op1);
24153 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
24155 error ("the third argument must be a 8-bit immediate");
24159 if (d->code == IX86_BUILTIN_PCMPISTRI128)
24161 if (optimize || !target
24162 || GET_MODE (target) != tmode0
24163 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24164 target = gen_reg_rtx (tmode0);
24166 scratch1 = gen_reg_rtx (tmode1);
24168 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24170 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24172 if (optimize || !target
24173 || GET_MODE (target) != tmode1
24174 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24175 target = gen_reg_rtx (tmode1);
24177 scratch0 = gen_reg_rtx (tmode0);
24179 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24183 gcc_assert (d->flag);
24185 scratch0 = gen_reg_rtx (tmode0);
24186 scratch1 = gen_reg_rtx (tmode1);
24188 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24198 target = gen_reg_rtx (SImode);
24199 emit_move_insn (target, const0_rtx);
24200 target = gen_rtx_SUBREG (QImode, target, 0);
24203 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24204 gen_rtx_fmt_ee (EQ, QImode,
24205 gen_rtx_REG ((enum machine_mode) d->flag,
24208 return SUBREG_REG (target);
24214 /* Subroutine of ix86_expand_builtin to take care of insns with
24215 variable number of operands. */
24218 ix86_expand_args_builtin (const struct builtin_description *d,
24219 tree exp, rtx target)
24221 rtx pat, real_target;
24222 unsigned int i, nargs;
24223 unsigned int nargs_constant = 0;
24224 int num_memory = 0;
24228 enum machine_mode mode;
24230 bool last_arg_count = false;
24231 enum insn_code icode = d->icode;
24232 const struct insn_data *insn_p = &insn_data[icode];
24233 enum machine_mode tmode = insn_p->operand[0].mode;
24234 enum machine_mode rmode = VOIDmode;
24236 enum rtx_code comparison = d->comparison;
24238 switch ((enum ix86_builtin_type) d->flag)
24240 case INT_FTYPE_V8SF_V8SF_PTEST:
24241 case INT_FTYPE_V4DI_V4DI_PTEST:
24242 case INT_FTYPE_V4DF_V4DF_PTEST:
24243 case INT_FTYPE_V4SF_V4SF_PTEST:
24244 case INT_FTYPE_V2DI_V2DI_PTEST:
24245 case INT_FTYPE_V2DF_V2DF_PTEST:
24246 return ix86_expand_sse_ptest (d, exp, target);
24247 case FLOAT128_FTYPE_FLOAT128:
24248 case FLOAT_FTYPE_FLOAT:
24249 case INT64_FTYPE_V4SF:
24250 case INT64_FTYPE_V2DF:
24251 case INT_FTYPE_V16QI:
24252 case INT_FTYPE_V8QI:
24253 case INT_FTYPE_V8SF:
24254 case INT_FTYPE_V4DF:
24255 case INT_FTYPE_V4SF:
24256 case INT_FTYPE_V2DF:
24257 case V16QI_FTYPE_V16QI:
24258 case V8SI_FTYPE_V8SF:
24259 case V8SI_FTYPE_V4SI:
24260 case V8HI_FTYPE_V8HI:
24261 case V8HI_FTYPE_V16QI:
24262 case V8QI_FTYPE_V8QI:
24263 case V8SF_FTYPE_V8SF:
24264 case V8SF_FTYPE_V8SI:
24265 case V8SF_FTYPE_V4SF:
24266 case V4SI_FTYPE_V4SI:
24267 case V4SI_FTYPE_V16QI:
24268 case V4SI_FTYPE_V4SF:
24269 case V4SI_FTYPE_V8SI:
24270 case V4SI_FTYPE_V8HI:
24271 case V4SI_FTYPE_V4DF:
24272 case V4SI_FTYPE_V2DF:
24273 case V4HI_FTYPE_V4HI:
24274 case V4DF_FTYPE_V4DF:
24275 case V4DF_FTYPE_V4SI:
24276 case V4DF_FTYPE_V4SF:
24277 case V4DF_FTYPE_V2DF:
24278 case V4SF_FTYPE_V4SF:
24279 case V4SF_FTYPE_V4SI:
24280 case V4SF_FTYPE_V8SF:
24281 case V4SF_FTYPE_V4DF:
24282 case V4SF_FTYPE_V2DF:
24283 case V2DI_FTYPE_V2DI:
24284 case V2DI_FTYPE_V16QI:
24285 case V2DI_FTYPE_V8HI:
24286 case V2DI_FTYPE_V4SI:
24287 case V2DF_FTYPE_V2DF:
24288 case V2DF_FTYPE_V4SI:
24289 case V2DF_FTYPE_V4DF:
24290 case V2DF_FTYPE_V4SF:
24291 case V2DF_FTYPE_V2SI:
24292 case V2SI_FTYPE_V2SI:
24293 case V2SI_FTYPE_V4SF:
24294 case V2SI_FTYPE_V2SF:
24295 case V2SI_FTYPE_V2DF:
24296 case V2SF_FTYPE_V2SF:
24297 case V2SF_FTYPE_V2SI:
24300 case V4SF_FTYPE_V4SF_VEC_MERGE:
24301 case V2DF_FTYPE_V2DF_VEC_MERGE:
24302 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24303 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24304 case V16QI_FTYPE_V16QI_V16QI:
24305 case V16QI_FTYPE_V8HI_V8HI:
24306 case V8QI_FTYPE_V8QI_V8QI:
24307 case V8QI_FTYPE_V4HI_V4HI:
24308 case V8HI_FTYPE_V8HI_V8HI:
24309 case V8HI_FTYPE_V16QI_V16QI:
24310 case V8HI_FTYPE_V4SI_V4SI:
24311 case V8SF_FTYPE_V8SF_V8SF:
24312 case V8SF_FTYPE_V8SF_V8SI:
24313 case V4SI_FTYPE_V4SI_V4SI:
24314 case V4SI_FTYPE_V8HI_V8HI:
24315 case V4SI_FTYPE_V4SF_V4SF:
24316 case V4SI_FTYPE_V2DF_V2DF:
24317 case V4HI_FTYPE_V4HI_V4HI:
24318 case V4HI_FTYPE_V8QI_V8QI:
24319 case V4HI_FTYPE_V2SI_V2SI:
24320 case V4DF_FTYPE_V4DF_V4DF:
24321 case V4DF_FTYPE_V4DF_V4DI:
24322 case V4SF_FTYPE_V4SF_V4SF:
24323 case V4SF_FTYPE_V4SF_V4SI:
24324 case V4SF_FTYPE_V4SF_V2SI:
24325 case V4SF_FTYPE_V4SF_V2DF:
24326 case V4SF_FTYPE_V4SF_DI:
24327 case V4SF_FTYPE_V4SF_SI:
24328 case V2DI_FTYPE_V2DI_V2DI:
24329 case V2DI_FTYPE_V16QI_V16QI:
24330 case V2DI_FTYPE_V4SI_V4SI:
24331 case V2DI_FTYPE_V2DI_V16QI:
24332 case V2DI_FTYPE_V2DF_V2DF:
24333 case V2SI_FTYPE_V2SI_V2SI:
24334 case V2SI_FTYPE_V4HI_V4HI:
24335 case V2SI_FTYPE_V2SF_V2SF:
24336 case V2DF_FTYPE_V2DF_V2DF:
24337 case V2DF_FTYPE_V2DF_V4SF:
24338 case V2DF_FTYPE_V2DF_V2DI:
24339 case V2DF_FTYPE_V2DF_DI:
24340 case V2DF_FTYPE_V2DF_SI:
24341 case V2SF_FTYPE_V2SF_V2SF:
24342 case V1DI_FTYPE_V1DI_V1DI:
24343 case V1DI_FTYPE_V8QI_V8QI:
24344 case V1DI_FTYPE_V2SI_V2SI:
24345 if (comparison == UNKNOWN)
24346 return ix86_expand_binop_builtin (icode, exp, target);
24349 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24350 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24351 gcc_assert (comparison != UNKNOWN);
24355 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24356 case V8HI_FTYPE_V8HI_SI_COUNT:
24357 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24358 case V4SI_FTYPE_V4SI_SI_COUNT:
24359 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24360 case V4HI_FTYPE_V4HI_SI_COUNT:
24361 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24362 case V2DI_FTYPE_V2DI_SI_COUNT:
24363 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24364 case V2SI_FTYPE_V2SI_SI_COUNT:
24365 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24366 case V1DI_FTYPE_V1DI_SI_COUNT:
24368 last_arg_count = true;
24370 case UINT64_FTYPE_UINT64_UINT64:
24371 case UINT_FTYPE_UINT_UINT:
24372 case UINT_FTYPE_UINT_USHORT:
24373 case UINT_FTYPE_UINT_UCHAR:
24376 case V2DI2TI_FTYPE_V2DI_INT:
24379 nargs_constant = 1;
24381 case V8HI_FTYPE_V8HI_INT:
24382 case V8SF_FTYPE_V8SF_INT:
24383 case V4SI_FTYPE_V4SI_INT:
24384 case V4SI_FTYPE_V8SI_INT:
24385 case V4HI_FTYPE_V4HI_INT:
24386 case V4DF_FTYPE_V4DF_INT:
24387 case V4SF_FTYPE_V4SF_INT:
24388 case V4SF_FTYPE_V8SF_INT:
24389 case V2DI_FTYPE_V2DI_INT:
24390 case V2DF_FTYPE_V2DF_INT:
24391 case V2DF_FTYPE_V4DF_INT:
24393 nargs_constant = 1;
24395 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24396 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24397 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24398 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24399 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24402 case V16QI_FTYPE_V16QI_V16QI_INT:
24403 case V8HI_FTYPE_V8HI_V8HI_INT:
24404 case V8SI_FTYPE_V8SI_V8SI_INT:
24405 case V8SI_FTYPE_V8SI_V4SI_INT:
24406 case V8SF_FTYPE_V8SF_V8SF_INT:
24407 case V8SF_FTYPE_V8SF_V4SF_INT:
24408 case V4SI_FTYPE_V4SI_V4SI_INT:
24409 case V4DF_FTYPE_V4DF_V4DF_INT:
24410 case V4DF_FTYPE_V4DF_V2DF_INT:
24411 case V4SF_FTYPE_V4SF_V4SF_INT:
24412 case V2DI_FTYPE_V2DI_V2DI_INT:
24413 case V2DF_FTYPE_V2DF_V2DF_INT:
24415 nargs_constant = 1;
24417 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24420 nargs_constant = 1;
24422 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24425 nargs_constant = 1;
24427 case V2DI_FTYPE_V2DI_UINT_UINT:
24429 nargs_constant = 2;
24431 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24433 nargs_constant = 2;
24436 gcc_unreachable ();
24439 gcc_assert (nargs <= ARRAY_SIZE (args));
24441 if (comparison != UNKNOWN)
24443 gcc_assert (nargs == 2);
24444 return ix86_expand_sse_compare (d, exp, target, swap);
24447 if (rmode == VOIDmode || rmode == tmode)
24451 || GET_MODE (target) != tmode
24452 || ! (*insn_p->operand[0].predicate) (target, tmode))
24453 target = gen_reg_rtx (tmode);
24454 real_target = target;
24458 target = gen_reg_rtx (rmode);
24459 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24462 for (i = 0; i < nargs; i++)
24464 tree arg = CALL_EXPR_ARG (exp, i);
24465 rtx op = expand_normal (arg);
24466 enum machine_mode mode = insn_p->operand[i + 1].mode;
24467 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24469 if (last_arg_count && (i + 1) == nargs)
24471 /* SIMD shift insns take either an 8-bit immediate or
24472 register as count. But builtin functions take int as
24473 count. If count doesn't match, we put it in register. */
24476 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24477 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24478 op = copy_to_reg (op);
24481 else if ((nargs - i) <= nargs_constant)
24486 case CODE_FOR_sse4_1_roundpd:
24487 case CODE_FOR_sse4_1_roundps:
24488 case CODE_FOR_sse4_1_roundsd:
24489 case CODE_FOR_sse4_1_roundss:
24490 case CODE_FOR_sse4_1_blendps:
24491 case CODE_FOR_avx_blendpd256:
24492 case CODE_FOR_avx_vpermilv4df:
24493 case CODE_FOR_avx_roundpd256:
24494 case CODE_FOR_avx_roundps256:
24495 error ("the last argument must be a 4-bit immediate");
24498 case CODE_FOR_sse4_1_blendpd:
24499 case CODE_FOR_avx_vpermilv2df:
24500 error ("the last argument must be a 2-bit immediate");
24503 case CODE_FOR_avx_vextractf128v4df:
24504 case CODE_FOR_avx_vextractf128v8sf:
24505 case CODE_FOR_avx_vextractf128v8si:
24506 case CODE_FOR_avx_vinsertf128v4df:
24507 case CODE_FOR_avx_vinsertf128v8sf:
24508 case CODE_FOR_avx_vinsertf128v8si:
24509 error ("the last argument must be a 1-bit immediate");
24512 case CODE_FOR_avx_cmpsdv2df3:
24513 case CODE_FOR_avx_cmpssv4sf3:
24514 case CODE_FOR_avx_cmppdv2df3:
24515 case CODE_FOR_avx_cmppsv4sf3:
24516 case CODE_FOR_avx_cmppdv4df3:
24517 case CODE_FOR_avx_cmppsv8sf3:
24518 error ("the last argument must be a 5-bit immediate");
24522 switch (nargs_constant)
24525 if ((nargs - i) == nargs_constant)
24527 error ("the next to last argument must be an 8-bit immediate");
24531 error ("the last argument must be an 8-bit immediate");
24534 gcc_unreachable ();
24541 if (VECTOR_MODE_P (mode))
24542 op = safe_vector_operand (op, mode);
24544 /* If we aren't optimizing, only allow one memory operand to
24546 if (memory_operand (op, mode))
24549 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24551 if (optimize || !match || num_memory > 1)
24552 op = copy_to_mode_reg (mode, op);
24556 op = copy_to_reg (op);
24557 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24562 args[i].mode = mode;
24568 pat = GEN_FCN (icode) (real_target, args[0].op);
24571 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24574 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24578 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24579 args[2].op, args[3].op);
24582 gcc_unreachable ();
24592 /* Subroutine of ix86_expand_builtin to take care of special insns
24593 with variable number of operands. */
24596 ix86_expand_special_args_builtin (const struct builtin_description *d,
24597 tree exp, rtx target)
24601 unsigned int i, nargs, arg_adjust, memory;
24605 enum machine_mode mode;
24607 enum insn_code icode = d->icode;
24608 bool last_arg_constant = false;
24609 const struct insn_data *insn_p = &insn_data[icode];
24610 enum machine_mode tmode = insn_p->operand[0].mode;
24611 enum { load, store } klass;
24613 switch ((enum ix86_special_builtin_type) d->flag)
24615 case VOID_FTYPE_VOID:
24616 emit_insn (GEN_FCN (icode) (target));
24618 case V2DI_FTYPE_PV2DI:
24619 case V32QI_FTYPE_PCCHAR:
24620 case V16QI_FTYPE_PCCHAR:
24621 case V8SF_FTYPE_PCV4SF:
24622 case V8SF_FTYPE_PCFLOAT:
24623 case V4SF_FTYPE_PCFLOAT:
24624 case V4DF_FTYPE_PCV2DF:
24625 case V4DF_FTYPE_PCDOUBLE:
24626 case V2DF_FTYPE_PCDOUBLE:
24631 case VOID_FTYPE_PV2SF_V4SF:
24632 case VOID_FTYPE_PV4DI_V4DI:
24633 case VOID_FTYPE_PV2DI_V2DI:
24634 case VOID_FTYPE_PCHAR_V32QI:
24635 case VOID_FTYPE_PCHAR_V16QI:
24636 case VOID_FTYPE_PFLOAT_V8SF:
24637 case VOID_FTYPE_PFLOAT_V4SF:
24638 case VOID_FTYPE_PDOUBLE_V4DF:
24639 case VOID_FTYPE_PDOUBLE_V2DF:
24640 case VOID_FTYPE_PDI_DI:
24641 case VOID_FTYPE_PINT_INT:
24644 /* Reserve memory operand for target. */
24645 memory = ARRAY_SIZE (args);
24647 case V4SF_FTYPE_V4SF_PCV2SF:
24648 case V2DF_FTYPE_V2DF_PCDOUBLE:
24653 case V8SF_FTYPE_PCV8SF_V8SI:
24654 case V4DF_FTYPE_PCV4DF_V4DI:
24655 case V4SF_FTYPE_PCV4SF_V4SI:
24656 case V2DF_FTYPE_PCV2DF_V2DI:
24661 case VOID_FTYPE_PV8SF_V8SI_V8SF:
24662 case VOID_FTYPE_PV4DF_V4DI_V4DF:
24663 case VOID_FTYPE_PV4SF_V4SI_V4SF:
24664 case VOID_FTYPE_PV2DF_V2DI_V2DF:
24667 /* Reserve memory operand for target. */
24668 memory = ARRAY_SIZE (args);
24671 gcc_unreachable ();
24674 gcc_assert (nargs <= ARRAY_SIZE (args));
24676 if (klass == store)
24678 arg = CALL_EXPR_ARG (exp, 0);
24679 op = expand_normal (arg);
24680 gcc_assert (target == 0);
24681 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24689 || GET_MODE (target) != tmode
24690 || ! (*insn_p->operand[0].predicate) (target, tmode))
24691 target = gen_reg_rtx (tmode);
24694 for (i = 0; i < nargs; i++)
24696 enum machine_mode mode = insn_p->operand[i + 1].mode;
24699 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24700 op = expand_normal (arg);
24701 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24703 if (last_arg_constant && (i + 1) == nargs)
24709 error ("the last argument must be an 8-bit immediate");
24717 /* This must be the memory operand. */
24718 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24719 gcc_assert (GET_MODE (op) == mode
24720 || GET_MODE (op) == VOIDmode);
24724 /* This must be register. */
24725 if (VECTOR_MODE_P (mode))
24726 op = safe_vector_operand (op, mode);
24728 gcc_assert (GET_MODE (op) == mode
24729 || GET_MODE (op) == VOIDmode);
24730 op = copy_to_mode_reg (mode, op);
24735 args[i].mode = mode;
24741 pat = GEN_FCN (icode) (target, args[0].op);
24744 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24747 gcc_unreachable ();
24753 return klass == store ? 0 : target;
24756 /* Return the integer constant in ARG. Constrain it to be in the range
24757 of the subparts of VEC_TYPE; issue an error if not. */
24760 get_element_number (tree vec_type, tree arg)
24762 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24764 if (!host_integerp (arg, 1)
24765 || (elt = tree_low_cst (arg, 1), elt > max))
24767 error ("selector must be an integer constant in the range 0..%wi", max);
24774 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24775 ix86_expand_vector_init. We DO have language-level syntax for this, in
24776 the form of (type){ init-list }. Except that since we can't place emms
24777 instructions from inside the compiler, we can't allow the use of MMX
24778 registers unless the user explicitly asks for it. So we do *not* define
24779 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24780 we have builtins invoked by mmintrin.h that gives us license to emit
24781 these sorts of instructions. */
24784 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24786 enum machine_mode tmode = TYPE_MODE (type);
24787 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24788 int i, n_elt = GET_MODE_NUNITS (tmode);
24789 rtvec v = rtvec_alloc (n_elt);
24791 gcc_assert (VECTOR_MODE_P (tmode));
24792 gcc_assert (call_expr_nargs (exp) == n_elt);
24794 for (i = 0; i < n_elt; ++i)
24796 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24797 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24800 if (!target || !register_operand (target, tmode))
24801 target = gen_reg_rtx (tmode);
24803 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24807 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24808 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24809 had a language-level syntax for referencing vector elements. */
24812 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24814 enum machine_mode tmode, mode0;
24819 arg0 = CALL_EXPR_ARG (exp, 0);
24820 arg1 = CALL_EXPR_ARG (exp, 1);
24822 op0 = expand_normal (arg0);
24823 elt = get_element_number (TREE_TYPE (arg0), arg1);
24825 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24826 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24827 gcc_assert (VECTOR_MODE_P (mode0));
24829 op0 = force_reg (mode0, op0);
24831 if (optimize || !target || !register_operand (target, tmode))
24832 target = gen_reg_rtx (tmode);
24834 ix86_expand_vector_extract (true, target, op0, elt);
24839 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24840 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24841 a language-level syntax for referencing vector elements. */
24844 ix86_expand_vec_set_builtin (tree exp)
24846 enum machine_mode tmode, mode1;
24847 tree arg0, arg1, arg2;
24849 rtx op0, op1, target;
24851 arg0 = CALL_EXPR_ARG (exp, 0);
24852 arg1 = CALL_EXPR_ARG (exp, 1);
24853 arg2 = CALL_EXPR_ARG (exp, 2);
24855 tmode = TYPE_MODE (TREE_TYPE (arg0));
24856 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24857 gcc_assert (VECTOR_MODE_P (tmode));
24859 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24860 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24861 elt = get_element_number (TREE_TYPE (arg0), arg2);
24863 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24864 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24866 op0 = force_reg (tmode, op0);
24867 op1 = force_reg (mode1, op1);
24869 /* OP0 is the source of these builtin functions and shouldn't be
24870 modified. Create a copy, use it and return it as target. */
24871 target = gen_reg_rtx (tmode);
24872 emit_move_insn (target, op0);
24873 ix86_expand_vector_set (true, target, op1, elt);
24878 /* Expand an expression EXP that calls a built-in function,
24879 with result going to TARGET if that's convenient
24880 (and in mode MODE if that's convenient).
24881 SUBTARGET may be used as the target for computing one of EXP's operands.
24882 IGNORE is nonzero if the value is to be ignored. */
24885 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24886 enum machine_mode mode ATTRIBUTE_UNUSED,
24887 int ignore ATTRIBUTE_UNUSED)
24889 const struct builtin_description *d;
24891 enum insn_code icode;
24892 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24893 tree arg0, arg1, arg2;
24894 rtx op0, op1, op2, pat;
24895 enum machine_mode mode0, mode1, mode2;
24896 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24898 /* Determine whether the builtin function is available under the current ISA.
24899 Originally the builtin was not created if it wasn't applicable to the
24900 current ISA based on the command line switches. With function specific
24901 options, we need to check in the context of the function making the call
24902 whether it is supported. */
24903 if (ix86_builtins_isa[fcode].isa
24904 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24906 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24907 NULL, NULL, false);
24910 error ("%qE needs unknown isa option", fndecl);
24913 gcc_assert (opts != NULL);
24914 error ("%qE needs isa option %s", fndecl, opts);
24922 case IX86_BUILTIN_MASKMOVQ:
24923 case IX86_BUILTIN_MASKMOVDQU:
24924 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24925 ? CODE_FOR_mmx_maskmovq
24926 : CODE_FOR_sse2_maskmovdqu);
24927 /* Note the arg order is different from the operand order. */
24928 arg1 = CALL_EXPR_ARG (exp, 0);
24929 arg2 = CALL_EXPR_ARG (exp, 1);
24930 arg0 = CALL_EXPR_ARG (exp, 2);
24931 op0 = expand_normal (arg0);
24932 op1 = expand_normal (arg1);
24933 op2 = expand_normal (arg2);
24934 mode0 = insn_data[icode].operand[0].mode;
24935 mode1 = insn_data[icode].operand[1].mode;
24936 mode2 = insn_data[icode].operand[2].mode;
24938 op0 = force_reg (Pmode, op0);
24939 op0 = gen_rtx_MEM (mode1, op0);
24941 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24942 op0 = copy_to_mode_reg (mode0, op0);
24943 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24944 op1 = copy_to_mode_reg (mode1, op1);
24945 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24946 op2 = copy_to_mode_reg (mode2, op2);
24947 pat = GEN_FCN (icode) (op0, op1, op2);
24953 case IX86_BUILTIN_LDMXCSR:
24954 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24955 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24956 emit_move_insn (target, op0);
24957 emit_insn (gen_sse_ldmxcsr (target));
24960 case IX86_BUILTIN_STMXCSR:
24961 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24962 emit_insn (gen_sse_stmxcsr (target));
24963 return copy_to_mode_reg (SImode, target);
24965 case IX86_BUILTIN_CLFLUSH:
24966 arg0 = CALL_EXPR_ARG (exp, 0);
24967 op0 = expand_normal (arg0);
24968 icode = CODE_FOR_sse2_clflush;
24969 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24970 op0 = copy_to_mode_reg (Pmode, op0);
24972 emit_insn (gen_sse2_clflush (op0));
24975 case IX86_BUILTIN_MONITOR:
24976 arg0 = CALL_EXPR_ARG (exp, 0);
24977 arg1 = CALL_EXPR_ARG (exp, 1);
24978 arg2 = CALL_EXPR_ARG (exp, 2);
24979 op0 = expand_normal (arg0);
24980 op1 = expand_normal (arg1);
24981 op2 = expand_normal (arg2);
24983 op0 = copy_to_mode_reg (Pmode, op0);
24985 op1 = copy_to_mode_reg (SImode, op1);
24987 op2 = copy_to_mode_reg (SImode, op2);
24988 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24991 case IX86_BUILTIN_MWAIT:
24992 arg0 = CALL_EXPR_ARG (exp, 0);
24993 arg1 = CALL_EXPR_ARG (exp, 1);
24994 op0 = expand_normal (arg0);
24995 op1 = expand_normal (arg1);
24997 op0 = copy_to_mode_reg (SImode, op0);
24999 op1 = copy_to_mode_reg (SImode, op1);
25000 emit_insn (gen_sse3_mwait (op0, op1));
25003 case IX86_BUILTIN_VEC_INIT_V2SI:
25004 case IX86_BUILTIN_VEC_INIT_V4HI:
25005 case IX86_BUILTIN_VEC_INIT_V8QI:
25006 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
25008 case IX86_BUILTIN_VEC_EXT_V2DF:
25009 case IX86_BUILTIN_VEC_EXT_V2DI:
25010 case IX86_BUILTIN_VEC_EXT_V4SF:
25011 case IX86_BUILTIN_VEC_EXT_V4SI:
25012 case IX86_BUILTIN_VEC_EXT_V8HI:
25013 case IX86_BUILTIN_VEC_EXT_V2SI:
25014 case IX86_BUILTIN_VEC_EXT_V4HI:
25015 case IX86_BUILTIN_VEC_EXT_V16QI:
25016 return ix86_expand_vec_ext_builtin (exp, target);
25018 case IX86_BUILTIN_VEC_SET_V2DI:
25019 case IX86_BUILTIN_VEC_SET_V4SF:
25020 case IX86_BUILTIN_VEC_SET_V4SI:
25021 case IX86_BUILTIN_VEC_SET_V8HI:
25022 case IX86_BUILTIN_VEC_SET_V4HI:
25023 case IX86_BUILTIN_VEC_SET_V16QI:
25024 return ix86_expand_vec_set_builtin (exp);
25026 case IX86_BUILTIN_INFQ:
25028 REAL_VALUE_TYPE inf;
25032 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
25034 tmp = validize_mem (force_const_mem (mode, tmp));
25037 target = gen_reg_rtx (mode);
25039 emit_move_insn (target, tmp);
25047 for (i = 0, d = bdesc_special_args;
25048 i < ARRAY_SIZE (bdesc_special_args);
25050 if (d->code == fcode)
25051 return ix86_expand_special_args_builtin (d, exp, target);
25053 for (i = 0, d = bdesc_args;
25054 i < ARRAY_SIZE (bdesc_args);
25056 if (d->code == fcode)
25059 case IX86_BUILTIN_FABSQ:
25060 case IX86_BUILTIN_COPYSIGNQ:
25062 /* Emit a normal call if SSE2 isn't available. */
25063 return expand_call (exp, target, ignore);
25065 return ix86_expand_args_builtin (d, exp, target);
25068 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
25069 if (d->code == fcode)
25070 return ix86_expand_sse_comi (d, exp, target);
25072 for (i = 0, d = bdesc_pcmpestr;
25073 i < ARRAY_SIZE (bdesc_pcmpestr);
25075 if (d->code == fcode)
25076 return ix86_expand_sse_pcmpestr (d, exp, target);
25078 for (i = 0, d = bdesc_pcmpistr;
25079 i < ARRAY_SIZE (bdesc_pcmpistr);
25081 if (d->code == fcode)
25082 return ix86_expand_sse_pcmpistr (d, exp, target);
25084 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
25085 if (d->code == fcode)
25086 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
25087 (enum multi_arg_type)d->flag,
25090 gcc_unreachable ();
25093 /* Returns a function decl for a vectorized version of the builtin function
25094 with builtin function code FN and the result vector type TYPE, or NULL_TREE
25095 if it is not available. */
25098 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
25101 enum machine_mode in_mode, out_mode;
25104 if (TREE_CODE (type_out) != VECTOR_TYPE
25105 || TREE_CODE (type_in) != VECTOR_TYPE)
25108 out_mode = TYPE_MODE (TREE_TYPE (type_out));
25109 out_n = TYPE_VECTOR_SUBPARTS (type_out);
25110 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25111 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25115 case BUILT_IN_SQRT:
25116 if (out_mode == DFmode && out_n == 2
25117 && in_mode == DFmode && in_n == 2)
25118 return ix86_builtins[IX86_BUILTIN_SQRTPD];
25121 case BUILT_IN_SQRTF:
25122 if (out_mode == SFmode && out_n == 4
25123 && in_mode == SFmode && in_n == 4)
25124 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
25127 case BUILT_IN_LRINT:
25128 if (out_mode == SImode && out_n == 4
25129 && in_mode == DFmode && in_n == 2)
25130 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
25133 case BUILT_IN_LRINTF:
25134 if (out_mode == SImode && out_n == 4
25135 && in_mode == SFmode && in_n == 4)
25136 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
25143 /* Dispatch to a handler for a vectorization library. */
25144 if (ix86_veclib_handler)
25145 return (*ix86_veclib_handler)(fn, type_out, type_in);
25150 /* Handler for an SVML-style interface to
25151 a library with vectorized intrinsics. */
25154 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
25157 tree fntype, new_fndecl, args;
25160 enum machine_mode el_mode, in_mode;
25163 /* The SVML is suitable for unsafe math only. */
25164 if (!flag_unsafe_math_optimizations)
25167 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25168 n = TYPE_VECTOR_SUBPARTS (type_out);
25169 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25170 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25171 if (el_mode != in_mode
25179 case BUILT_IN_LOG10:
25181 case BUILT_IN_TANH:
25183 case BUILT_IN_ATAN:
25184 case BUILT_IN_ATAN2:
25185 case BUILT_IN_ATANH:
25186 case BUILT_IN_CBRT:
25187 case BUILT_IN_SINH:
25189 case BUILT_IN_ASINH:
25190 case BUILT_IN_ASIN:
25191 case BUILT_IN_COSH:
25193 case BUILT_IN_ACOSH:
25194 case BUILT_IN_ACOS:
25195 if (el_mode != DFmode || n != 2)
25199 case BUILT_IN_EXPF:
25200 case BUILT_IN_LOGF:
25201 case BUILT_IN_LOG10F:
25202 case BUILT_IN_POWF:
25203 case BUILT_IN_TANHF:
25204 case BUILT_IN_TANF:
25205 case BUILT_IN_ATANF:
25206 case BUILT_IN_ATAN2F:
25207 case BUILT_IN_ATANHF:
25208 case BUILT_IN_CBRTF:
25209 case BUILT_IN_SINHF:
25210 case BUILT_IN_SINF:
25211 case BUILT_IN_ASINHF:
25212 case BUILT_IN_ASINF:
25213 case BUILT_IN_COSHF:
25214 case BUILT_IN_COSF:
25215 case BUILT_IN_ACOSHF:
25216 case BUILT_IN_ACOSF:
25217 if (el_mode != SFmode || n != 4)
25225 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25227 if (fn == BUILT_IN_LOGF)
25228 strcpy (name, "vmlsLn4");
25229 else if (fn == BUILT_IN_LOG)
25230 strcpy (name, "vmldLn2");
25233 sprintf (name, "vmls%s", bname+10);
25234 name[strlen (name)-1] = '4';
25237 sprintf (name, "vmld%s2", bname+10);
25239 /* Convert to uppercase. */
25243 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25244 args = TREE_CHAIN (args))
25248 fntype = build_function_type_list (type_out, type_in, NULL);
25250 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25252 /* Build a function declaration for the vectorized function. */
25253 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25254 TREE_PUBLIC (new_fndecl) = 1;
25255 DECL_EXTERNAL (new_fndecl) = 1;
25256 DECL_IS_NOVOPS (new_fndecl) = 1;
25257 TREE_READONLY (new_fndecl) = 1;
25262 /* Handler for an ACML-style interface to
25263 a library with vectorized intrinsics. */
25266 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25268 char name[20] = "__vr.._";
25269 tree fntype, new_fndecl, args;
25272 enum machine_mode el_mode, in_mode;
25275 /* The ACML is 64bits only and suitable for unsafe math only as
25276 it does not correctly support parts of IEEE with the required
25277 precision such as denormals. */
25279 || !flag_unsafe_math_optimizations)
25282 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25283 n = TYPE_VECTOR_SUBPARTS (type_out);
25284 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25285 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25286 if (el_mode != in_mode
25296 case BUILT_IN_LOG2:
25297 case BUILT_IN_LOG10:
25300 if (el_mode != DFmode
25305 case BUILT_IN_SINF:
25306 case BUILT_IN_COSF:
25307 case BUILT_IN_EXPF:
25308 case BUILT_IN_POWF:
25309 case BUILT_IN_LOGF:
25310 case BUILT_IN_LOG2F:
25311 case BUILT_IN_LOG10F:
25314 if (el_mode != SFmode
25323 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25324 sprintf (name + 7, "%s", bname+10);
25327 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25328 args = TREE_CHAIN (args))
25332 fntype = build_function_type_list (type_out, type_in, NULL);
25334 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25336 /* Build a function declaration for the vectorized function. */
25337 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25338 TREE_PUBLIC (new_fndecl) = 1;
25339 DECL_EXTERNAL (new_fndecl) = 1;
25340 DECL_IS_NOVOPS (new_fndecl) = 1;
25341 TREE_READONLY (new_fndecl) = 1;
25347 /* Returns a decl of a function that implements conversion of an integer vector
25348 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25349 side of the conversion.
25350 Return NULL_TREE if it is not available. */
25353 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25355 if (!TARGET_SSE2 || TREE_CODE (type) != VECTOR_TYPE
25356 /* There are only conversions from/to signed integers. */
25357 || TYPE_UNSIGNED (TREE_TYPE (type)))
25363 switch (TYPE_MODE (type))
25366 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25371 case FIX_TRUNC_EXPR:
25372 switch (TYPE_MODE (type))
25375 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25385 /* Returns a code for a target-specific builtin that implements
25386 reciprocal of the function, or NULL_TREE if not available. */
25389 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25390 bool sqrt ATTRIBUTE_UNUSED)
25392 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25393 && flag_finite_math_only && !flag_trapping_math
25394 && flag_unsafe_math_optimizations))
25398 /* Machine dependent builtins. */
25401 /* Vectorized version of sqrt to rsqrt conversion. */
25402 case IX86_BUILTIN_SQRTPS_NR:
25403 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25409 /* Normal builtins. */
25412 /* Sqrt to rsqrt conversion. */
25413 case BUILT_IN_SQRTF:
25414 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25421 /* Store OPERAND to the memory after reload is completed. This means
25422 that we can't easily use assign_stack_local. */
25424 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25428 gcc_assert (reload_completed);
25429 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25431 result = gen_rtx_MEM (mode,
25432 gen_rtx_PLUS (Pmode,
25434 GEN_INT (-RED_ZONE_SIZE)));
25435 emit_move_insn (result, operand);
25437 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25443 operand = gen_lowpart (DImode, operand);
25447 gen_rtx_SET (VOIDmode,
25448 gen_rtx_MEM (DImode,
25449 gen_rtx_PRE_DEC (DImode,
25450 stack_pointer_rtx)),
25454 gcc_unreachable ();
25456 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25465 split_di (&operand, 1, operands, operands + 1);
25467 gen_rtx_SET (VOIDmode,
25468 gen_rtx_MEM (SImode,
25469 gen_rtx_PRE_DEC (Pmode,
25470 stack_pointer_rtx)),
25473 gen_rtx_SET (VOIDmode,
25474 gen_rtx_MEM (SImode,
25475 gen_rtx_PRE_DEC (Pmode,
25476 stack_pointer_rtx)),
25481 /* Store HImodes as SImodes. */
25482 operand = gen_lowpart (SImode, operand);
25486 gen_rtx_SET (VOIDmode,
25487 gen_rtx_MEM (GET_MODE (operand),
25488 gen_rtx_PRE_DEC (SImode,
25489 stack_pointer_rtx)),
25493 gcc_unreachable ();
25495 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25500 /* Free operand from the memory. */
25502 ix86_free_from_memory (enum machine_mode mode)
25504 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25508 if (mode == DImode || TARGET_64BIT)
25512 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25513 to pop or add instruction if registers are available. */
25514 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25515 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25520 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25521 QImode must go into class Q_REGS.
25522 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25523 movdf to do mem-to-mem moves through integer regs. */
25525 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25527 enum machine_mode mode = GET_MODE (x);
25529 /* We're only allowed to return a subclass of CLASS. Many of the
25530 following checks fail for NO_REGS, so eliminate that early. */
25531 if (regclass == NO_REGS)
25534 /* All classes can load zeros. */
25535 if (x == CONST0_RTX (mode))
25538 /* Force constants into memory if we are loading a (nonzero) constant into
25539 an MMX or SSE register. This is because there are no MMX/SSE instructions
25540 to load from a constant. */
25542 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25545 /* Prefer SSE regs only, if we can use them for math. */
25546 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25547 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25549 /* Floating-point constants need more complex checks. */
25550 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25552 /* General regs can load everything. */
25553 if (reg_class_subset_p (regclass, GENERAL_REGS))
25556 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25557 zero above. We only want to wind up preferring 80387 registers if
25558 we plan on doing computation with them. */
25560 && standard_80387_constant_p (x))
25562 /* Limit class to non-sse. */
25563 if (regclass == FLOAT_SSE_REGS)
25565 if (regclass == FP_TOP_SSE_REGS)
25567 if (regclass == FP_SECOND_SSE_REGS)
25568 return FP_SECOND_REG;
25569 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25576 /* Generally when we see PLUS here, it's the function invariant
25577 (plus soft-fp const_int). Which can only be computed into general
25579 if (GET_CODE (x) == PLUS)
25580 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25582 /* QImode constants are easy to load, but non-constant QImode data
25583 must go into Q_REGS. */
25584 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25586 if (reg_class_subset_p (regclass, Q_REGS))
25588 if (reg_class_subset_p (Q_REGS, regclass))
25596 /* Discourage putting floating-point values in SSE registers unless
25597 SSE math is being used, and likewise for the 387 registers. */
25599 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25601 enum machine_mode mode = GET_MODE (x);
25603 /* Restrict the output reload class to the register bank that we are doing
25604 math on. If we would like not to return a subset of CLASS, reject this
25605 alternative: if reload cannot do this, it will still use its choice. */
25606 mode = GET_MODE (x);
25607 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25608 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25610 if (X87_FLOAT_MODE_P (mode))
25612 if (regclass == FP_TOP_SSE_REGS)
25614 else if (regclass == FP_SECOND_SSE_REGS)
25615 return FP_SECOND_REG;
25617 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25623 static enum reg_class
25624 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25625 enum machine_mode mode,
25626 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25628 /* QImode spills from non-QI registers require
25629 intermediate register on 32bit targets. */
25631 && !in_p && mode == QImode
25632 && (rclass == GENERAL_REGS
25633 || rclass == LEGACY_REGS
25634 || rclass == INDEX_REGS))
25643 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25644 regno = true_regnum (x);
25646 /* Return Q_REGS if the operand is in memory. */
25651 /* This condition handles corner case where an expression involving
25652 pointers gets vectorized. We're trying to use the address of a
25653 stack slot as a vector initializer.
25655 (set (reg:V2DI 74 [ vect_cst_.2 ])
25656 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
25658 Eventually frame gets turned into sp+offset like this:
25660 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
25661 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
25662 (const_int 392 [0x188]))))
25664 That later gets turned into:
25666 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
25667 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
25668 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
25670 We'll have the following reload recorded:
25672 Reload 0: reload_in (DI) =
25673 (plus:DI (reg/f:DI 7 sp)
25674 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
25675 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
25676 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
25677 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
25678 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
25679 reload_reg_rtx: (reg:V2DI 22 xmm1)
25681 Which isn't going to work since SSE instructions can't handle scalar
25682 additions. Returning GENERAL_REGS forces the addition into integer
25683 register and reload can handle subsequent reloads without problems. */
25685 if (in_p && GET_CODE (x) == PLUS
25686 && SSE_CLASS_P (rclass)
25687 && SCALAR_INT_MODE_P (mode))
25688 return GENERAL_REGS;
25693 /* If we are copying between general and FP registers, we need a memory
25694 location. The same is true for SSE and MMX registers.
25696 To optimize register_move_cost performance, allow inline variant.
25698 The macro can't work reliably when one of the CLASSES is class containing
25699 registers from multiple units (SSE, MMX, integer). We avoid this by never
25700 combining those units in single alternative in the machine description.
25701 Ensure that this constraint holds to avoid unexpected surprises.
25703 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25704 enforce these sanity checks. */
25707 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25708 enum machine_mode mode, int strict)
25710 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25711 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25712 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25713 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25714 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25715 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25717 gcc_assert (!strict);
25721 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25724 /* ??? This is a lie. We do have moves between mmx/general, and for
25725 mmx/sse2. But by saying we need secondary memory we discourage the
25726 register allocator from using the mmx registers unless needed. */
25727 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25730 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25732 /* SSE1 doesn't have any direct moves from other classes. */
25736 /* If the target says that inter-unit moves are more expensive
25737 than moving through memory, then don't generate them. */
25738 if (!TARGET_INTER_UNIT_MOVES)
25741 /* Between SSE and general, we have moves no larger than word size. */
25742 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25750 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25751 enum machine_mode mode, int strict)
25753 return inline_secondary_memory_needed (class1, class2, mode, strict);
25756 /* Return true if the registers in CLASS cannot represent the change from
25757 modes FROM to TO. */
25760 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25761 enum reg_class regclass)
25766 /* x87 registers can't do subreg at all, as all values are reformatted
25767 to extended precision. */
25768 if (MAYBE_FLOAT_CLASS_P (regclass))
25771 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25773 /* Vector registers do not support QI or HImode loads. If we don't
25774 disallow a change to these modes, reload will assume it's ok to
25775 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25776 the vec_dupv4hi pattern. */
25777 if (GET_MODE_SIZE (from) < 4)
25780 /* Vector registers do not support subreg with nonzero offsets, which
25781 are otherwise valid for integer registers. Since we can't see
25782 whether we have a nonzero offset from here, prohibit all
25783 nonparadoxical subregs changing size. */
25784 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25791 /* Return the cost of moving data of mode M between a
25792 register and memory. A value of 2 is the default; this cost is
25793 relative to those in `REGISTER_MOVE_COST'.
25795 This function is used extensively by register_move_cost that is used to
25796 build tables at startup. Make it inline in this case.
25797 When IN is 2, return maximum of in and out move cost.
25799 If moving between registers and memory is more expensive than
25800 between two registers, you should define this macro to express the
25803 Model also increased moving costs of QImode registers in non
25807 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25811 if (FLOAT_CLASS_P (regclass))
25829 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25830 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25832 if (SSE_CLASS_P (regclass))
25835 switch (GET_MODE_SIZE (mode))
25850 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25851 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25853 if (MMX_CLASS_P (regclass))
25856 switch (GET_MODE_SIZE (mode))
25868 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25869 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25871 switch (GET_MODE_SIZE (mode))
25874 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25877 return ix86_cost->int_store[0];
25878 if (TARGET_PARTIAL_REG_DEPENDENCY
25879 && optimize_function_for_speed_p (cfun))
25880 cost = ix86_cost->movzbl_load;
25882 cost = ix86_cost->int_load[0];
25884 return MAX (cost, ix86_cost->int_store[0]);
25890 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25892 return ix86_cost->movzbl_load;
25894 return ix86_cost->int_store[0] + 4;
25899 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25900 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25902 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25903 if (mode == TFmode)
25906 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25908 cost = ix86_cost->int_load[2];
25910 cost = ix86_cost->int_store[2];
25911 return (cost * (((int) GET_MODE_SIZE (mode)
25912 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25917 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25919 return inline_memory_move_cost (mode, regclass, in);
25923 /* Return the cost of moving data from a register in class CLASS1 to
25924 one in class CLASS2.
25926 It is not required that the cost always equal 2 when FROM is the same as TO;
25927 on some machines it is expensive to move between registers if they are not
25928 general registers. */
25931 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25932 enum reg_class class2)
25934 /* In case we require secondary memory, compute cost of the store followed
25935 by load. In order to avoid bad register allocation choices, we need
25936 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25938 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25942 cost += inline_memory_move_cost (mode, class1, 2);
25943 cost += inline_memory_move_cost (mode, class2, 2);
25945 /* In case of copying from general_purpose_register we may emit multiple
25946 stores followed by single load causing memory size mismatch stall.
25947 Count this as arbitrarily high cost of 20. */
25948 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25951 /* In the case of FP/MMX moves, the registers actually overlap, and we
25952 have to switch modes in order to treat them differently. */
25953 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25954 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25960 /* Moves between SSE/MMX and integer unit are expensive. */
25961 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25962 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25964 /* ??? By keeping returned value relatively high, we limit the number
25965 of moves between integer and MMX/SSE registers for all targets.
25966 Additionally, high value prevents problem with x86_modes_tieable_p(),
25967 where integer modes in MMX/SSE registers are not tieable
25968 because of missing QImode and HImode moves to, from or between
25969 MMX/SSE registers. */
25970 return MAX (8, ix86_cost->mmxsse_to_integer);
25972 if (MAYBE_FLOAT_CLASS_P (class1))
25973 return ix86_cost->fp_move;
25974 if (MAYBE_SSE_CLASS_P (class1))
25975 return ix86_cost->sse_move;
25976 if (MAYBE_MMX_CLASS_P (class1))
25977 return ix86_cost->mmx_move;
25981 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25984 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25986 /* Flags and only flags can only hold CCmode values. */
25987 if (CC_REGNO_P (regno))
25988 return GET_MODE_CLASS (mode) == MODE_CC;
25989 if (GET_MODE_CLASS (mode) == MODE_CC
25990 || GET_MODE_CLASS (mode) == MODE_RANDOM
25991 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25993 if (FP_REGNO_P (regno))
25994 return VALID_FP_MODE_P (mode);
25995 if (SSE_REGNO_P (regno))
25997 /* We implement the move patterns for all vector modes into and
25998 out of SSE registers, even when no operation instructions
25999 are available. OImode move is available only when AVX is
26001 return ((TARGET_AVX && mode == OImode)
26002 || VALID_AVX256_REG_MODE (mode)
26003 || VALID_SSE_REG_MODE (mode)
26004 || VALID_SSE2_REG_MODE (mode)
26005 || VALID_MMX_REG_MODE (mode)
26006 || VALID_MMX_REG_MODE_3DNOW (mode));
26008 if (MMX_REGNO_P (regno))
26010 /* We implement the move patterns for 3DNOW modes even in MMX mode,
26011 so if the register is available at all, then we can move data of
26012 the given mode into or out of it. */
26013 return (VALID_MMX_REG_MODE (mode)
26014 || VALID_MMX_REG_MODE_3DNOW (mode));
26017 if (mode == QImode)
26019 /* Take care for QImode values - they can be in non-QI regs,
26020 but then they do cause partial register stalls. */
26021 if (regno <= BX_REG || TARGET_64BIT)
26023 if (!TARGET_PARTIAL_REG_STALL)
26025 return reload_in_progress || reload_completed;
26027 /* We handle both integer and floats in the general purpose registers. */
26028 else if (VALID_INT_MODE_P (mode))
26030 else if (VALID_FP_MODE_P (mode))
26032 else if (VALID_DFP_MODE_P (mode))
26034 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
26035 on to use that value in smaller contexts, this can easily force a
26036 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
26037 supporting DImode, allow it. */
26038 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
26044 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
26045 tieable integer mode. */
26048 ix86_tieable_integer_mode_p (enum machine_mode mode)
26057 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
26060 return TARGET_64BIT;
26067 /* Return true if MODE1 is accessible in a register that can hold MODE2
26068 without copying. That is, all register classes that can hold MODE2
26069 can also hold MODE1. */
26072 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
26074 if (mode1 == mode2)
26077 if (ix86_tieable_integer_mode_p (mode1)
26078 && ix86_tieable_integer_mode_p (mode2))
26081 /* MODE2 being XFmode implies fp stack or general regs, which means we
26082 can tie any smaller floating point modes to it. Note that we do not
26083 tie this with TFmode. */
26084 if (mode2 == XFmode)
26085 return mode1 == SFmode || mode1 == DFmode;
26087 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
26088 that we can tie it with SFmode. */
26089 if (mode2 == DFmode)
26090 return mode1 == SFmode;
26092 /* If MODE2 is only appropriate for an SSE register, then tie with
26093 any other mode acceptable to SSE registers. */
26094 if (GET_MODE_SIZE (mode2) == 16
26095 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
26096 return (GET_MODE_SIZE (mode1) == 16
26097 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
26099 /* If MODE2 is appropriate for an MMX register, then tie
26100 with any other mode acceptable to MMX registers. */
26101 if (GET_MODE_SIZE (mode2) == 8
26102 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
26103 return (GET_MODE_SIZE (mode1) == 8
26104 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
26109 /* Compute a (partial) cost for rtx X. Return true if the complete
26110 cost has been computed, and false if subexpressions should be
26111 scanned. In either case, *TOTAL contains the cost result. */
26114 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
26116 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
26117 enum machine_mode mode = GET_MODE (x);
26118 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
26126 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
26128 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
26130 else if (flag_pic && SYMBOLIC_CONST (x)
26132 || (!GET_CODE (x) != LABEL_REF
26133 && (GET_CODE (x) != SYMBOL_REF
26134 || !SYMBOL_REF_LOCAL_P (x)))))
26141 if (mode == VOIDmode)
26144 switch (standard_80387_constant_p (x))
26149 default: /* Other constants */
26154 /* Start with (MEM (SYMBOL_REF)), since that's where
26155 it'll probably end up. Add a penalty for size. */
26156 *total = (COSTS_N_INSNS (1)
26157 + (flag_pic != 0 && !TARGET_64BIT)
26158 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
26164 /* The zero extensions is often completely free on x86_64, so make
26165 it as cheap as possible. */
26166 if (TARGET_64BIT && mode == DImode
26167 && GET_MODE (XEXP (x, 0)) == SImode)
26169 else if (TARGET_ZERO_EXTEND_WITH_AND)
26170 *total = cost->add;
26172 *total = cost->movzx;
26176 *total = cost->movsx;
26180 if (CONST_INT_P (XEXP (x, 1))
26181 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
26183 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26186 *total = cost->add;
26189 if ((value == 2 || value == 3)
26190 && cost->lea <= cost->shift_const)
26192 *total = cost->lea;
26202 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26204 if (CONST_INT_P (XEXP (x, 1)))
26206 if (INTVAL (XEXP (x, 1)) > 32)
26207 *total = cost->shift_const + COSTS_N_INSNS (2);
26209 *total = cost->shift_const * 2;
26213 if (GET_CODE (XEXP (x, 1)) == AND)
26214 *total = cost->shift_var * 2;
26216 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26221 if (CONST_INT_P (XEXP (x, 1)))
26222 *total = cost->shift_const;
26224 *total = cost->shift_var;
26229 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26231 /* ??? SSE scalar cost should be used here. */
26232 *total = cost->fmul;
26235 else if (X87_FLOAT_MODE_P (mode))
26237 *total = cost->fmul;
26240 else if (FLOAT_MODE_P (mode))
26242 /* ??? SSE vector cost should be used here. */
26243 *total = cost->fmul;
26248 rtx op0 = XEXP (x, 0);
26249 rtx op1 = XEXP (x, 1);
26251 if (CONST_INT_P (XEXP (x, 1)))
26253 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26254 for (nbits = 0; value != 0; value &= value - 1)
26258 /* This is arbitrary. */
26261 /* Compute costs correctly for widening multiplication. */
26262 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26263 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26264 == GET_MODE_SIZE (mode))
26266 int is_mulwiden = 0;
26267 enum machine_mode inner_mode = GET_MODE (op0);
26269 if (GET_CODE (op0) == GET_CODE (op1))
26270 is_mulwiden = 1, op1 = XEXP (op1, 0);
26271 else if (CONST_INT_P (op1))
26273 if (GET_CODE (op0) == SIGN_EXTEND)
26274 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26277 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26281 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26284 *total = (cost->mult_init[MODE_INDEX (mode)]
26285 + nbits * cost->mult_bit
26286 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26295 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26296 /* ??? SSE cost should be used here. */
26297 *total = cost->fdiv;
26298 else if (X87_FLOAT_MODE_P (mode))
26299 *total = cost->fdiv;
26300 else if (FLOAT_MODE_P (mode))
26301 /* ??? SSE vector cost should be used here. */
26302 *total = cost->fdiv;
26304 *total = cost->divide[MODE_INDEX (mode)];
26308 if (GET_MODE_CLASS (mode) == MODE_INT
26309 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26311 if (GET_CODE (XEXP (x, 0)) == PLUS
26312 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26313 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26314 && CONSTANT_P (XEXP (x, 1)))
26316 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26317 if (val == 2 || val == 4 || val == 8)
26319 *total = cost->lea;
26320 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26321 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26322 outer_code, speed);
26323 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26327 else if (GET_CODE (XEXP (x, 0)) == MULT
26328 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26330 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26331 if (val == 2 || val == 4 || val == 8)
26333 *total = cost->lea;
26334 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26335 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26339 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26341 *total = cost->lea;
26342 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26343 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26344 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26351 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26353 /* ??? SSE cost should be used here. */
26354 *total = cost->fadd;
26357 else if (X87_FLOAT_MODE_P (mode))
26359 *total = cost->fadd;
26362 else if (FLOAT_MODE_P (mode))
26364 /* ??? SSE vector cost should be used here. */
26365 *total = cost->fadd;
26373 if (!TARGET_64BIT && mode == DImode)
26375 *total = (cost->add * 2
26376 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26377 << (GET_MODE (XEXP (x, 0)) != DImode))
26378 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26379 << (GET_MODE (XEXP (x, 1)) != DImode)));
26385 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26387 /* ??? SSE cost should be used here. */
26388 *total = cost->fchs;
26391 else if (X87_FLOAT_MODE_P (mode))
26393 *total = cost->fchs;
26396 else if (FLOAT_MODE_P (mode))
26398 /* ??? SSE vector cost should be used here. */
26399 *total = cost->fchs;
26405 if (!TARGET_64BIT && mode == DImode)
26406 *total = cost->add * 2;
26408 *total = cost->add;
26412 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26413 && XEXP (XEXP (x, 0), 1) == const1_rtx
26414 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26415 && XEXP (x, 1) == const0_rtx)
26417 /* This kind of construct is implemented using test[bwl].
26418 Treat it as if we had an AND. */
26419 *total = (cost->add
26420 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26421 + rtx_cost (const1_rtx, outer_code, speed));
26427 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26432 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26433 /* ??? SSE cost should be used here. */
26434 *total = cost->fabs;
26435 else if (X87_FLOAT_MODE_P (mode))
26436 *total = cost->fabs;
26437 else if (FLOAT_MODE_P (mode))
26438 /* ??? SSE vector cost should be used here. */
26439 *total = cost->fabs;
26443 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26444 /* ??? SSE cost should be used here. */
26445 *total = cost->fsqrt;
26446 else if (X87_FLOAT_MODE_P (mode))
26447 *total = cost->fsqrt;
26448 else if (FLOAT_MODE_P (mode))
26449 /* ??? SSE vector cost should be used here. */
26450 *total = cost->fsqrt;
26454 if (XINT (x, 1) == UNSPEC_TP)
26465 static int current_machopic_label_num;
26467 /* Given a symbol name and its associated stub, write out the
26468 definition of the stub. */
26471 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26473 unsigned int length;
26474 char *binder_name, *symbol_name, lazy_ptr_name[32];
26475 int label = ++current_machopic_label_num;
26477 /* For 64-bit we shouldn't get here. */
26478 gcc_assert (!TARGET_64BIT);
26480 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26481 symb = (*targetm.strip_name_encoding) (symb);
26483 length = strlen (stub);
26484 binder_name = XALLOCAVEC (char, length + 32);
26485 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26487 length = strlen (symb);
26488 symbol_name = XALLOCAVEC (char, length + 32);
26489 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26491 sprintf (lazy_ptr_name, "L%d$lz", label);
26494 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26496 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26498 fprintf (file, "%s:\n", stub);
26499 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26503 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26504 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26505 fprintf (file, "\tjmp\t*%%edx\n");
26508 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26510 fprintf (file, "%s:\n", binder_name);
26514 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26515 fprintf (file, "\tpushl\t%%eax\n");
26518 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26520 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26522 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26523 fprintf (file, "%s:\n", lazy_ptr_name);
26524 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26525 fprintf (file, "\t.long %s\n", binder_name);
26529 darwin_x86_file_end (void)
26531 darwin_file_end ();
26534 #endif /* TARGET_MACHO */
26536 /* Order the registers for register allocator. */
26539 x86_order_regs_for_local_alloc (void)
26544 /* First allocate the local general purpose registers. */
26545 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26546 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26547 reg_alloc_order [pos++] = i;
26549 /* Global general purpose registers. */
26550 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26551 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26552 reg_alloc_order [pos++] = i;
26554 /* x87 registers come first in case we are doing FP math
26556 if (!TARGET_SSE_MATH)
26557 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26558 reg_alloc_order [pos++] = i;
26560 /* SSE registers. */
26561 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26562 reg_alloc_order [pos++] = i;
26563 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26564 reg_alloc_order [pos++] = i;
26566 /* x87 registers. */
26567 if (TARGET_SSE_MATH)
26568 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26569 reg_alloc_order [pos++] = i;
26571 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26572 reg_alloc_order [pos++] = i;
26574 /* Initialize the rest of array as we do not allocate some registers
26576 while (pos < FIRST_PSEUDO_REGISTER)
26577 reg_alloc_order [pos++] = 0;
26580 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26581 struct attribute_spec.handler. */
26583 ix86_handle_abi_attribute (tree *node, tree name,
26584 tree args ATTRIBUTE_UNUSED,
26585 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26587 if (TREE_CODE (*node) != FUNCTION_TYPE
26588 && TREE_CODE (*node) != METHOD_TYPE
26589 && TREE_CODE (*node) != FIELD_DECL
26590 && TREE_CODE (*node) != TYPE_DECL)
26592 warning (OPT_Wattributes, "%qs attribute only applies to functions",
26593 IDENTIFIER_POINTER (name));
26594 *no_add_attrs = true;
26599 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
26600 IDENTIFIER_POINTER (name));
26601 *no_add_attrs = true;
26605 /* Can combine regparm with all attributes but fastcall. */
26606 if (is_attribute_p ("ms_abi", name))
26608 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26610 error ("ms_abi and sysv_abi attributes are not compatible");
26615 else if (is_attribute_p ("sysv_abi", name))
26617 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26619 error ("ms_abi and sysv_abi attributes are not compatible");
26628 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26629 struct attribute_spec.handler. */
26631 ix86_handle_struct_attribute (tree *node, tree name,
26632 tree args ATTRIBUTE_UNUSED,
26633 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26636 if (DECL_P (*node))
26638 if (TREE_CODE (*node) == TYPE_DECL)
26639 type = &TREE_TYPE (*node);
26644 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26645 || TREE_CODE (*type) == UNION_TYPE)))
26647 warning (OPT_Wattributes, "%qs attribute ignored",
26648 IDENTIFIER_POINTER (name));
26649 *no_add_attrs = true;
26652 else if ((is_attribute_p ("ms_struct", name)
26653 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26654 || ((is_attribute_p ("gcc_struct", name)
26655 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26657 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
26658 IDENTIFIER_POINTER (name));
26659 *no_add_attrs = true;
26666 ix86_ms_bitfield_layout_p (const_tree record_type)
26668 return (TARGET_MS_BITFIELD_LAYOUT &&
26669 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26670 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26673 /* Returns an expression indicating where the this parameter is
26674 located on entry to the FUNCTION. */
26677 x86_this_parameter (tree function)
26679 tree type = TREE_TYPE (function);
26680 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26685 const int *parm_regs;
26687 if (ix86_function_type_abi (type) == MS_ABI)
26688 parm_regs = x86_64_ms_abi_int_parameter_registers;
26690 parm_regs = x86_64_int_parameter_registers;
26691 return gen_rtx_REG (DImode, parm_regs[aggr]);
26694 nregs = ix86_function_regparm (type, function);
26696 if (nregs > 0 && !stdarg_p (type))
26700 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26701 regno = aggr ? DX_REG : CX_REG;
26709 return gen_rtx_MEM (SImode,
26710 plus_constant (stack_pointer_rtx, 4));
26713 return gen_rtx_REG (SImode, regno);
26716 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26719 /* Determine whether x86_output_mi_thunk can succeed. */
26722 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26723 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26724 HOST_WIDE_INT vcall_offset, const_tree function)
26726 /* 64-bit can handle anything. */
26730 /* For 32-bit, everything's fine if we have one free register. */
26731 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26734 /* Need a free register for vcall_offset. */
26738 /* Need a free register for GOT references. */
26739 if (flag_pic && !(*targetm.binds_local_p) (function))
26742 /* Otherwise ok. */
26746 /* Output the assembler code for a thunk function. THUNK_DECL is the
26747 declaration for the thunk function itself, FUNCTION is the decl for
26748 the target function. DELTA is an immediate constant offset to be
26749 added to THIS. If VCALL_OFFSET is nonzero, the word at
26750 *(*this + vcall_offset) should be added to THIS. */
26753 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26754 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26755 HOST_WIDE_INT vcall_offset, tree function)
26758 rtx this_param = x86_this_parameter (function);
26761 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26762 pull it in now and let DELTA benefit. */
26763 if (REG_P (this_param))
26764 this_reg = this_param;
26765 else if (vcall_offset)
26767 /* Put the this parameter into %eax. */
26768 xops[0] = this_param;
26769 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26770 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26773 this_reg = NULL_RTX;
26775 /* Adjust the this parameter by a fixed constant. */
26778 xops[0] = GEN_INT (delta);
26779 xops[1] = this_reg ? this_reg : this_param;
26782 if (!x86_64_general_operand (xops[0], DImode))
26784 tmp = gen_rtx_REG (DImode, R10_REG);
26786 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26788 xops[1] = this_param;
26790 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26793 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26796 /* Adjust the this parameter by a value stored in the vtable. */
26800 tmp = gen_rtx_REG (DImode, R10_REG);
26803 int tmp_regno = CX_REG;
26804 if (lookup_attribute ("fastcall",
26805 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26806 tmp_regno = AX_REG;
26807 tmp = gen_rtx_REG (SImode, tmp_regno);
26810 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26812 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26814 /* Adjust the this parameter. */
26815 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26816 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26818 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26819 xops[0] = GEN_INT (vcall_offset);
26821 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26822 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26824 xops[1] = this_reg;
26825 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26828 /* If necessary, drop THIS back to its stack slot. */
26829 if (this_reg && this_reg != this_param)
26831 xops[0] = this_reg;
26832 xops[1] = this_param;
26833 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26836 xops[0] = XEXP (DECL_RTL (function), 0);
26839 if (!flag_pic || (*targetm.binds_local_p) (function))
26840 output_asm_insn ("jmp\t%P0", xops);
26841 /* All thunks should be in the same object as their target,
26842 and thus binds_local_p should be true. */
26843 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26844 gcc_unreachable ();
26847 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26848 tmp = gen_rtx_CONST (Pmode, tmp);
26849 tmp = gen_rtx_MEM (QImode, tmp);
26851 output_asm_insn ("jmp\t%A0", xops);
26856 if (!flag_pic || (*targetm.binds_local_p) (function))
26857 output_asm_insn ("jmp\t%P0", xops);
26862 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26863 tmp = (gen_rtx_SYMBOL_REF
26865 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26866 tmp = gen_rtx_MEM (QImode, tmp);
26868 output_asm_insn ("jmp\t%0", xops);
26871 #endif /* TARGET_MACHO */
26873 tmp = gen_rtx_REG (SImode, CX_REG);
26874 output_set_got (tmp, NULL_RTX);
26877 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26878 output_asm_insn ("jmp\t{*}%1", xops);
26884 x86_file_start (void)
26886 default_file_start ();
26888 darwin_file_start ();
26890 if (X86_FILE_START_VERSION_DIRECTIVE)
26891 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26892 if (X86_FILE_START_FLTUSED)
26893 fputs ("\t.global\t__fltused\n", asm_out_file);
26894 if (ix86_asm_dialect == ASM_INTEL)
26895 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26899 x86_field_alignment (tree field, int computed)
26901 enum machine_mode mode;
26902 tree type = TREE_TYPE (field);
26904 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26906 mode = TYPE_MODE (strip_array_types (type));
26907 if (mode == DFmode || mode == DCmode
26908 || GET_MODE_CLASS (mode) == MODE_INT
26909 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26910 return MIN (32, computed);
26914 /* Output assembler code to FILE to increment profiler label # LABELNO
26915 for profiling a function entry. */
26917 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26921 #ifndef NO_PROFILE_COUNTERS
26922 fprintf (file, "\tleaq\t%sP%d(%%rip),%%r11\n", LPREFIX, labelno);
26925 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26926 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26928 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26932 #ifndef NO_PROFILE_COUNTERS
26933 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26934 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26936 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26940 #ifndef NO_PROFILE_COUNTERS
26941 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26942 PROFILE_COUNT_REGISTER);
26944 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26948 /* We don't have exact information about the insn sizes, but we may assume
26949 quite safely that we are informed about all 1 byte insns and memory
26950 address sizes. This is enough to eliminate unnecessary padding in
26954 min_insn_size (rtx insn)
26958 if (!INSN_P (insn) || !active_insn_p (insn))
26961 /* Discard alignments we've emit and jump instructions. */
26962 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26963 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26966 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26967 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26970 /* Important case - calls are always 5 bytes.
26971 It is common to have many calls in the row. */
26973 && symbolic_reference_mentioned_p (PATTERN (insn))
26974 && !SIBLING_CALL_P (insn))
26976 if (get_attr_length (insn) <= 1)
26979 /* For normal instructions we may rely on the sizes of addresses
26980 and the presence of symbol to require 4 bytes of encoding.
26981 This is not the case for jumps where references are PC relative. */
26982 if (!JUMP_P (insn))
26984 l = get_attr_length_address (insn);
26985 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26994 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26998 ix86_avoid_jump_misspredicts (void)
27000 rtx insn, start = get_insns ();
27001 int nbytes = 0, njumps = 0;
27004 /* Look for all minimal intervals of instructions containing 4 jumps.
27005 The intervals are bounded by START and INSN. NBYTES is the total
27006 size of instructions in the interval including INSN and not including
27007 START. When the NBYTES is smaller than 16 bytes, it is possible
27008 that the end of START and INSN ends up in the same 16byte page.
27010 The smallest offset in the page INSN can start is the case where START
27011 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
27012 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
27014 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
27017 nbytes += min_insn_size (insn);
27019 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
27020 INSN_UID (insn), min_insn_size (insn));
27022 && GET_CODE (PATTERN (insn)) != ADDR_VEC
27023 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
27031 start = NEXT_INSN (start);
27032 if ((JUMP_P (start)
27033 && GET_CODE (PATTERN (start)) != ADDR_VEC
27034 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27036 njumps--, isjump = 1;
27039 nbytes -= min_insn_size (start);
27041 gcc_assert (njumps >= 0);
27043 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
27044 INSN_UID (start), INSN_UID (insn), nbytes);
27046 if (njumps == 3 && isjump && nbytes < 16)
27048 int padsize = 15 - nbytes + min_insn_size (insn);
27051 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
27052 INSN_UID (insn), padsize);
27053 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
27058 /* AMD Athlon works faster
27059 when RET is not destination of conditional jump or directly preceded
27060 by other jump instruction. We avoid the penalty by inserting NOP just
27061 before the RET instructions in such cases. */
27063 ix86_pad_returns (void)
27068 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
27070 basic_block bb = e->src;
27071 rtx ret = BB_END (bb);
27073 bool replace = false;
27075 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
27076 || optimize_bb_for_size_p (bb))
27078 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
27079 if (active_insn_p (prev) || LABEL_P (prev))
27081 if (prev && LABEL_P (prev))
27086 FOR_EACH_EDGE (e, ei, bb->preds)
27087 if (EDGE_FREQUENCY (e) && e->src->index >= 0
27088 && !(e->flags & EDGE_FALLTHRU))
27093 prev = prev_active_insn (ret);
27095 && ((JUMP_P (prev) && any_condjump_p (prev))
27098 /* Empty functions get branch mispredict even when the jump destination
27099 is not visible to us. */
27100 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
27105 emit_insn_before (gen_return_internal_long (), ret);
27111 /* Implement machine specific optimizations. We implement padding of returns
27112 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
27116 if (TARGET_PAD_RETURNS && optimize
27117 && optimize_function_for_speed_p (cfun))
27118 ix86_pad_returns ();
27119 if (TARGET_FOUR_JUMP_LIMIT && optimize
27120 && optimize_function_for_speed_p (cfun))
27121 ix86_avoid_jump_misspredicts ();
27124 /* Return nonzero when QImode register that must be represented via REX prefix
27127 x86_extended_QIreg_mentioned_p (rtx insn)
27130 extract_insn_cached (insn);
27131 for (i = 0; i < recog_data.n_operands; i++)
27132 if (REG_P (recog_data.operand[i])
27133 && REGNO (recog_data.operand[i]) > BX_REG)
27138 /* Return nonzero when P points to register encoded via REX prefix.
27139 Called via for_each_rtx. */
27141 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
27143 unsigned int regno;
27146 regno = REGNO (*p);
27147 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27150 /* Return true when INSN mentions register that must be encoded using REX
27153 x86_extended_reg_mentioned_p (rtx insn)
27155 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27156 extended_reg_mentioned_1, NULL);
27159 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27160 optabs would emit if we didn't have TFmode patterns. */
27163 x86_emit_floatuns (rtx operands[2])
27165 rtx neglab, donelab, i0, i1, f0, in, out;
27166 enum machine_mode mode, inmode;
27168 inmode = GET_MODE (operands[1]);
27169 gcc_assert (inmode == SImode || inmode == DImode);
27172 in = force_reg (inmode, operands[1]);
27173 mode = GET_MODE (out);
27174 neglab = gen_label_rtx ();
27175 donelab = gen_label_rtx ();
27176 f0 = gen_reg_rtx (mode);
27178 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27180 expand_float (out, in, 0);
27182 emit_jump_insn (gen_jump (donelab));
27185 emit_label (neglab);
27187 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27189 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27191 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27193 expand_float (f0, i0, 0);
27195 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27197 emit_label (donelab);
27200 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27201 with all elements equal to VAR. Return true if successful. */
27204 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27205 rtx target, rtx val)
27207 enum machine_mode hmode, smode, wsmode, wvmode;
27222 val = force_reg (GET_MODE_INNER (mode), val);
27223 x = gen_rtx_VEC_DUPLICATE (mode, val);
27224 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27230 if (TARGET_SSE || TARGET_3DNOW_A)
27232 val = gen_lowpart (SImode, val);
27233 x = gen_rtx_TRUNCATE (HImode, val);
27234 x = gen_rtx_VEC_DUPLICATE (mode, x);
27235 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27257 /* Extend HImode to SImode using a paradoxical SUBREG. */
27258 tmp1 = gen_reg_rtx (SImode);
27259 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27260 /* Insert the SImode value as low element of V4SImode vector. */
27261 tmp2 = gen_reg_rtx (V4SImode);
27262 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27263 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27264 CONST0_RTX (V4SImode),
27266 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27267 /* Cast the V4SImode vector back to a V8HImode vector. */
27268 tmp1 = gen_reg_rtx (V8HImode);
27269 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27270 /* Duplicate the low short through the whole low SImode word. */
27271 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27272 /* Cast the V8HImode vector back to a V4SImode vector. */
27273 tmp2 = gen_reg_rtx (V4SImode);
27274 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27275 /* Replicate the low element of the V4SImode vector. */
27276 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27277 /* Cast the V2SImode back to V8HImode, and store in target. */
27278 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27289 /* Extend QImode to SImode using a paradoxical SUBREG. */
27290 tmp1 = gen_reg_rtx (SImode);
27291 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27292 /* Insert the SImode value as low element of V4SImode vector. */
27293 tmp2 = gen_reg_rtx (V4SImode);
27294 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27295 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27296 CONST0_RTX (V4SImode),
27298 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27299 /* Cast the V4SImode vector back to a V16QImode vector. */
27300 tmp1 = gen_reg_rtx (V16QImode);
27301 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27302 /* Duplicate the low byte through the whole low SImode word. */
27303 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27304 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27305 /* Cast the V16QImode vector back to a V4SImode vector. */
27306 tmp2 = gen_reg_rtx (V4SImode);
27307 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27308 /* Replicate the low element of the V4SImode vector. */
27309 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27310 /* Cast the V2SImode back to V16QImode, and store in target. */
27311 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27319 /* Replicate the value once into the next wider mode and recurse. */
27320 val = convert_modes (wsmode, smode, val, true);
27321 x = expand_simple_binop (wsmode, ASHIFT, val,
27322 GEN_INT (GET_MODE_BITSIZE (smode)),
27323 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27324 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27326 x = gen_reg_rtx (wvmode);
27327 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27328 gcc_unreachable ();
27329 emit_move_insn (target, gen_lowpart (mode, x));
27352 rtx tmp = gen_reg_rtx (hmode);
27353 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27354 emit_insn (gen_rtx_SET (VOIDmode, target,
27355 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27364 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27365 whose ONE_VAR element is VAR, and other elements are zero. Return true
27369 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27370 rtx target, rtx var, int one_var)
27372 enum machine_mode vsimode;
27375 bool use_vector_set = false;
27380 /* For SSE4.1, we normally use vector set. But if the second
27381 element is zero and inter-unit moves are OK, we use movq
27383 use_vector_set = (TARGET_64BIT
27385 && !(TARGET_INTER_UNIT_MOVES
27391 use_vector_set = TARGET_SSE4_1;
27394 use_vector_set = TARGET_SSE2;
27397 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27404 use_vector_set = TARGET_AVX;
27407 /* Use ix86_expand_vector_set in 64bit mode only. */
27408 use_vector_set = TARGET_AVX && TARGET_64BIT;
27414 if (use_vector_set)
27416 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27417 var = force_reg (GET_MODE_INNER (mode), var);
27418 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27434 var = force_reg (GET_MODE_INNER (mode), var);
27435 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27436 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27441 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27442 new_target = gen_reg_rtx (mode);
27444 new_target = target;
27445 var = force_reg (GET_MODE_INNER (mode), var);
27446 x = gen_rtx_VEC_DUPLICATE (mode, var);
27447 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27448 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27451 /* We need to shuffle the value to the correct position, so
27452 create a new pseudo to store the intermediate result. */
27454 /* With SSE2, we can use the integer shuffle insns. */
27455 if (mode != V4SFmode && TARGET_SSE2)
27457 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27459 GEN_INT (one_var == 1 ? 0 : 1),
27460 GEN_INT (one_var == 2 ? 0 : 1),
27461 GEN_INT (one_var == 3 ? 0 : 1)));
27462 if (target != new_target)
27463 emit_move_insn (target, new_target);
27467 /* Otherwise convert the intermediate result to V4SFmode and
27468 use the SSE1 shuffle instructions. */
27469 if (mode != V4SFmode)
27471 tmp = gen_reg_rtx (V4SFmode);
27472 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27477 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27479 GEN_INT (one_var == 1 ? 0 : 1),
27480 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27481 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27483 if (mode != V4SFmode)
27484 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27485 else if (tmp != target)
27486 emit_move_insn (target, tmp);
27488 else if (target != new_target)
27489 emit_move_insn (target, new_target);
27494 vsimode = V4SImode;
27500 vsimode = V2SImode;
27506 /* Zero extend the variable element to SImode and recurse. */
27507 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27509 x = gen_reg_rtx (vsimode);
27510 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27512 gcc_unreachable ();
27514 emit_move_insn (target, gen_lowpart (mode, x));
27522 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27523 consisting of the values in VALS. It is known that all elements
27524 except ONE_VAR are constants. Return true if successful. */
27527 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27528 rtx target, rtx vals, int one_var)
27530 rtx var = XVECEXP (vals, 0, one_var);
27531 enum machine_mode wmode;
27534 const_vec = copy_rtx (vals);
27535 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27536 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27544 /* For the two element vectors, it's just as easy to use
27545 the general case. */
27549 /* Use ix86_expand_vector_set in 64bit mode only. */
27572 /* There's no way to set one QImode entry easily. Combine
27573 the variable value with its adjacent constant value, and
27574 promote to an HImode set. */
27575 x = XVECEXP (vals, 0, one_var ^ 1);
27578 var = convert_modes (HImode, QImode, var, true);
27579 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27580 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27581 x = GEN_INT (INTVAL (x) & 0xff);
27585 var = convert_modes (HImode, QImode, var, true);
27586 x = gen_int_mode (INTVAL (x) << 8, HImode);
27588 if (x != const0_rtx)
27589 var = expand_simple_binop (HImode, IOR, var, x, var,
27590 1, OPTAB_LIB_WIDEN);
27592 x = gen_reg_rtx (wmode);
27593 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27594 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27596 emit_move_insn (target, gen_lowpart (mode, x));
27603 emit_move_insn (target, const_vec);
27604 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27608 /* A subroutine of ix86_expand_vector_init_general. Use vector
27609 concatenate to handle the most general case: all values variable,
27610 and none identical. */
27613 ix86_expand_vector_init_concat (enum machine_mode mode,
27614 rtx target, rtx *ops, int n)
27616 enum machine_mode cmode, hmode = VOIDmode;
27617 rtx first[8], second[4];
27657 gcc_unreachable ();
27660 if (!register_operand (ops[1], cmode))
27661 ops[1] = force_reg (cmode, ops[1]);
27662 if (!register_operand (ops[0], cmode))
27663 ops[0] = force_reg (cmode, ops[0]);
27664 emit_insn (gen_rtx_SET (VOIDmode, target,
27665 gen_rtx_VEC_CONCAT (mode, ops[0],
27685 gcc_unreachable ();
27701 gcc_unreachable ();
27706 /* FIXME: We process inputs backward to help RA. PR 36222. */
27709 for (; i > 0; i -= 2, j--)
27711 first[j] = gen_reg_rtx (cmode);
27712 v = gen_rtvec (2, ops[i - 1], ops[i]);
27713 ix86_expand_vector_init (false, first[j],
27714 gen_rtx_PARALLEL (cmode, v));
27720 gcc_assert (hmode != VOIDmode);
27721 for (i = j = 0; i < n; i += 2, j++)
27723 second[j] = gen_reg_rtx (hmode);
27724 ix86_expand_vector_init_concat (hmode, second [j],
27728 ix86_expand_vector_init_concat (mode, target, second, n);
27731 ix86_expand_vector_init_concat (mode, target, first, n);
27735 gcc_unreachable ();
27739 /* A subroutine of ix86_expand_vector_init_general. Use vector
27740 interleave to handle the most general case: all values variable,
27741 and none identical. */
27744 ix86_expand_vector_init_interleave (enum machine_mode mode,
27745 rtx target, rtx *ops, int n)
27747 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27750 rtx (*gen_load_even) (rtx, rtx, rtx);
27751 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27752 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27757 gen_load_even = gen_vec_setv8hi;
27758 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27759 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27760 inner_mode = HImode;
27761 first_imode = V4SImode;
27762 second_imode = V2DImode;
27763 third_imode = VOIDmode;
27766 gen_load_even = gen_vec_setv16qi;
27767 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27768 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27769 inner_mode = QImode;
27770 first_imode = V8HImode;
27771 second_imode = V4SImode;
27772 third_imode = V2DImode;
27775 gcc_unreachable ();
27778 for (i = 0; i < n; i++)
27780 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27781 op0 = gen_reg_rtx (SImode);
27782 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27784 /* Insert the SImode value as low element of V4SImode vector. */
27785 op1 = gen_reg_rtx (V4SImode);
27786 op0 = gen_rtx_VEC_MERGE (V4SImode,
27787 gen_rtx_VEC_DUPLICATE (V4SImode,
27789 CONST0_RTX (V4SImode),
27791 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27793 /* Cast the V4SImode vector back to a vector in orignal mode. */
27794 op0 = gen_reg_rtx (mode);
27795 emit_move_insn (op0, gen_lowpart (mode, op1));
27797 /* Load even elements into the second positon. */
27798 emit_insn ((*gen_load_even) (op0,
27799 force_reg (inner_mode,
27803 /* Cast vector to FIRST_IMODE vector. */
27804 ops[i] = gen_reg_rtx (first_imode);
27805 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27808 /* Interleave low FIRST_IMODE vectors. */
27809 for (i = j = 0; i < n; i += 2, j++)
27811 op0 = gen_reg_rtx (first_imode);
27812 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27814 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27815 ops[j] = gen_reg_rtx (second_imode);
27816 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27819 /* Interleave low SECOND_IMODE vectors. */
27820 switch (second_imode)
27823 for (i = j = 0; i < n / 2; i += 2, j++)
27825 op0 = gen_reg_rtx (second_imode);
27826 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27829 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27831 ops[j] = gen_reg_rtx (third_imode);
27832 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27834 second_imode = V2DImode;
27835 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27839 op0 = gen_reg_rtx (second_imode);
27840 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27843 /* Cast the SECOND_IMODE vector back to a vector on original
27845 emit_insn (gen_rtx_SET (VOIDmode, target,
27846 gen_lowpart (mode, op0)));
27850 gcc_unreachable ();
27854 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27855 all values variable, and none identical. */
27858 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27859 rtx target, rtx vals)
27861 rtx ops[32], op0, op1;
27862 enum machine_mode half_mode = VOIDmode;
27869 if (!mmx_ok && !TARGET_SSE)
27881 n = GET_MODE_NUNITS (mode);
27882 for (i = 0; i < n; i++)
27883 ops[i] = XVECEXP (vals, 0, i);
27884 ix86_expand_vector_init_concat (mode, target, ops, n);
27888 half_mode = V16QImode;
27892 half_mode = V8HImode;
27896 n = GET_MODE_NUNITS (mode);
27897 for (i = 0; i < n; i++)
27898 ops[i] = XVECEXP (vals, 0, i);
27899 op0 = gen_reg_rtx (half_mode);
27900 op1 = gen_reg_rtx (half_mode);
27901 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27903 ix86_expand_vector_init_interleave (half_mode, op1,
27904 &ops [n >> 1], n >> 2);
27905 emit_insn (gen_rtx_SET (VOIDmode, target,
27906 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27910 if (!TARGET_SSE4_1)
27918 /* Don't use ix86_expand_vector_init_interleave if we can't
27919 move from GPR to SSE register directly. */
27920 if (!TARGET_INTER_UNIT_MOVES)
27923 n = GET_MODE_NUNITS (mode);
27924 for (i = 0; i < n; i++)
27925 ops[i] = XVECEXP (vals, 0, i);
27926 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27934 gcc_unreachable ();
27938 int i, j, n_elts, n_words, n_elt_per_word;
27939 enum machine_mode inner_mode;
27940 rtx words[4], shift;
27942 inner_mode = GET_MODE_INNER (mode);
27943 n_elts = GET_MODE_NUNITS (mode);
27944 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27945 n_elt_per_word = n_elts / n_words;
27946 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27948 for (i = 0; i < n_words; ++i)
27950 rtx word = NULL_RTX;
27952 for (j = 0; j < n_elt_per_word; ++j)
27954 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27955 elt = convert_modes (word_mode, inner_mode, elt, true);
27961 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27962 word, 1, OPTAB_LIB_WIDEN);
27963 word = expand_simple_binop (word_mode, IOR, word, elt,
27964 word, 1, OPTAB_LIB_WIDEN);
27972 emit_move_insn (target, gen_lowpart (mode, words[0]));
27973 else if (n_words == 2)
27975 rtx tmp = gen_reg_rtx (mode);
27976 emit_clobber (tmp);
27977 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27978 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27979 emit_move_insn (target, tmp);
27981 else if (n_words == 4)
27983 rtx tmp = gen_reg_rtx (V4SImode);
27984 gcc_assert (word_mode == SImode);
27985 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27986 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27987 emit_move_insn (target, gen_lowpart (mode, tmp));
27990 gcc_unreachable ();
27994 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27995 instructions unless MMX_OK is true. */
27998 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
28000 enum machine_mode mode = GET_MODE (target);
28001 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28002 int n_elts = GET_MODE_NUNITS (mode);
28003 int n_var = 0, one_var = -1;
28004 bool all_same = true, all_const_zero = true;
28008 for (i = 0; i < n_elts; ++i)
28010 x = XVECEXP (vals, 0, i);
28011 if (!(CONST_INT_P (x)
28012 || GET_CODE (x) == CONST_DOUBLE
28013 || GET_CODE (x) == CONST_FIXED))
28014 n_var++, one_var = i;
28015 else if (x != CONST0_RTX (inner_mode))
28016 all_const_zero = false;
28017 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
28021 /* Constants are best loaded from the constant pool. */
28024 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
28028 /* If all values are identical, broadcast the value. */
28030 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
28031 XVECEXP (vals, 0, 0)))
28034 /* Values where only one field is non-constant are best loaded from
28035 the pool and overwritten via move later. */
28039 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
28040 XVECEXP (vals, 0, one_var),
28044 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
28048 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
28052 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
28054 enum machine_mode mode = GET_MODE (target);
28055 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28056 enum machine_mode half_mode;
28057 bool use_vec_merge = false;
28059 static rtx (*gen_extract[6][2]) (rtx, rtx)
28061 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
28062 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
28063 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
28064 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
28065 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
28066 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
28068 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
28070 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
28071 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
28072 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
28073 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
28074 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
28075 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
28085 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
28086 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
28088 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
28090 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
28091 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28097 use_vec_merge = TARGET_SSE4_1;
28105 /* For the two element vectors, we implement a VEC_CONCAT with
28106 the extraction of the other element. */
28108 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
28109 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
28112 op0 = val, op1 = tmp;
28114 op0 = tmp, op1 = val;
28116 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
28117 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28122 use_vec_merge = TARGET_SSE4_1;
28129 use_vec_merge = true;
28133 /* tmp = target = A B C D */
28134 tmp = copy_to_reg (target);
28135 /* target = A A B B */
28136 emit_insn (gen_sse_unpcklps (target, target, target));
28137 /* target = X A B B */
28138 ix86_expand_vector_set (false, target, val, 0);
28139 /* target = A X C D */
28140 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28141 GEN_INT (1), GEN_INT (0),
28142 GEN_INT (2+4), GEN_INT (3+4)));
28146 /* tmp = target = A B C D */
28147 tmp = copy_to_reg (target);
28148 /* tmp = X B C D */
28149 ix86_expand_vector_set (false, tmp, val, 0);
28150 /* target = A B X D */
28151 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28152 GEN_INT (0), GEN_INT (1),
28153 GEN_INT (0+4), GEN_INT (3+4)));
28157 /* tmp = target = A B C D */
28158 tmp = copy_to_reg (target);
28159 /* tmp = X B C D */
28160 ix86_expand_vector_set (false, tmp, val, 0);
28161 /* target = A B X D */
28162 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28163 GEN_INT (0), GEN_INT (1),
28164 GEN_INT (2+4), GEN_INT (0+4)));
28168 gcc_unreachable ();
28173 use_vec_merge = TARGET_SSE4_1;
28177 /* Element 0 handled by vec_merge below. */
28180 use_vec_merge = true;
28186 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28187 store into element 0, then shuffle them back. */
28191 order[0] = GEN_INT (elt);
28192 order[1] = const1_rtx;
28193 order[2] = const2_rtx;
28194 order[3] = GEN_INT (3);
28195 order[elt] = const0_rtx;
28197 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28198 order[1], order[2], order[3]));
28200 ix86_expand_vector_set (false, target, val, 0);
28202 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28203 order[1], order[2], order[3]));
28207 /* For SSE1, we have to reuse the V4SF code. */
28208 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
28209 gen_lowpart (SFmode, val), elt);
28214 use_vec_merge = TARGET_SSE2;
28217 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28221 use_vec_merge = TARGET_SSE4_1;
28228 half_mode = V16QImode;
28234 half_mode = V8HImode;
28240 half_mode = V4SImode;
28246 half_mode = V2DImode;
28252 half_mode = V4SFmode;
28258 half_mode = V2DFmode;
28264 /* Compute offset. */
28268 gcc_assert (i <= 1);
28270 /* Extract the half. */
28271 tmp = gen_reg_rtx (half_mode);
28272 emit_insn ((*gen_extract[j][i]) (tmp, target));
28274 /* Put val in tmp at elt. */
28275 ix86_expand_vector_set (false, tmp, val, elt);
28278 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28287 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28288 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28289 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28293 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28295 emit_move_insn (mem, target);
28297 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28298 emit_move_insn (tmp, val);
28300 emit_move_insn (target, mem);
28305 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28307 enum machine_mode mode = GET_MODE (vec);
28308 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28309 bool use_vec_extr = false;
28322 use_vec_extr = true;
28326 use_vec_extr = TARGET_SSE4_1;
28338 tmp = gen_reg_rtx (mode);
28339 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28340 GEN_INT (elt), GEN_INT (elt),
28341 GEN_INT (elt+4), GEN_INT (elt+4)));
28345 tmp = gen_reg_rtx (mode);
28346 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28350 gcc_unreachable ();
28353 use_vec_extr = true;
28358 use_vec_extr = TARGET_SSE4_1;
28372 tmp = gen_reg_rtx (mode);
28373 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28374 GEN_INT (elt), GEN_INT (elt),
28375 GEN_INT (elt), GEN_INT (elt)));
28379 tmp = gen_reg_rtx (mode);
28380 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28384 gcc_unreachable ();
28387 use_vec_extr = true;
28392 /* For SSE1, we have to reuse the V4SF code. */
28393 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28394 gen_lowpart (V4SFmode, vec), elt);
28400 use_vec_extr = TARGET_SSE2;
28403 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28407 use_vec_extr = TARGET_SSE4_1;
28411 /* ??? Could extract the appropriate HImode element and shift. */
28418 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28419 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28421 /* Let the rtl optimizers know about the zero extension performed. */
28422 if (inner_mode == QImode || inner_mode == HImode)
28424 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28425 target = gen_lowpart (SImode, target);
28428 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28432 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28434 emit_move_insn (mem, vec);
28436 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28437 emit_move_insn (target, tmp);
28441 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28442 pattern to reduce; DEST is the destination; IN is the input vector. */
28445 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28447 rtx tmp1, tmp2, tmp3;
28449 tmp1 = gen_reg_rtx (V4SFmode);
28450 tmp2 = gen_reg_rtx (V4SFmode);
28451 tmp3 = gen_reg_rtx (V4SFmode);
28453 emit_insn (gen_sse_movhlps (tmp1, in, in));
28454 emit_insn (fn (tmp2, tmp1, in));
28456 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28457 GEN_INT (1), GEN_INT (1),
28458 GEN_INT (1+4), GEN_INT (1+4)));
28459 emit_insn (fn (dest, tmp2, tmp3));
28462 /* Target hook for scalar_mode_supported_p. */
28464 ix86_scalar_mode_supported_p (enum machine_mode mode)
28466 if (DECIMAL_FLOAT_MODE_P (mode))
28468 else if (mode == TFmode)
28471 return default_scalar_mode_supported_p (mode);
28474 /* Implements target hook vector_mode_supported_p. */
28476 ix86_vector_mode_supported_p (enum machine_mode mode)
28478 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28480 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28482 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28484 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28486 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28491 /* Target hook for c_mode_for_suffix. */
28492 static enum machine_mode
28493 ix86_c_mode_for_suffix (char suffix)
28503 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28505 We do this in the new i386 backend to maintain source compatibility
28506 with the old cc0-based compiler. */
28509 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28510 tree inputs ATTRIBUTE_UNUSED,
28513 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28515 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28520 /* Implements target vector targetm.asm.encode_section_info. This
28521 is not used by netware. */
28523 static void ATTRIBUTE_UNUSED
28524 ix86_encode_section_info (tree decl, rtx rtl, int first)
28526 default_encode_section_info (decl, rtl, first);
28528 if (TREE_CODE (decl) == VAR_DECL
28529 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28530 && ix86_in_large_data_p (decl))
28531 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28534 /* Worker function for REVERSE_CONDITION. */
28537 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28539 return (mode != CCFPmode && mode != CCFPUmode
28540 ? reverse_condition (code)
28541 : reverse_condition_maybe_unordered (code));
28544 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28548 output_387_reg_move (rtx insn, rtx *operands)
28550 if (REG_P (operands[0]))
28552 if (REG_P (operands[1])
28553 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28555 if (REGNO (operands[0]) == FIRST_STACK_REG)
28556 return output_387_ffreep (operands, 0);
28557 return "fstp\t%y0";
28559 if (STACK_TOP_P (operands[0]))
28560 return "fld%z1\t%y1";
28563 else if (MEM_P (operands[0]))
28565 gcc_assert (REG_P (operands[1]));
28566 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28567 return "fstp%z0\t%y0";
28570 /* There is no non-popping store to memory for XFmode.
28571 So if we need one, follow the store with a load. */
28572 if (GET_MODE (operands[0]) == XFmode)
28573 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
28575 return "fst%z0\t%y0";
28582 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28583 FP status register is set. */
28586 ix86_emit_fp_unordered_jump (rtx label)
28588 rtx reg = gen_reg_rtx (HImode);
28591 emit_insn (gen_x86_fnstsw_1 (reg));
28593 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28595 emit_insn (gen_x86_sahf_1 (reg));
28597 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28598 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28602 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28604 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28605 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28608 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28609 gen_rtx_LABEL_REF (VOIDmode, label),
28611 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28613 emit_jump_insn (temp);
28614 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28617 /* Output code to perform a log1p XFmode calculation. */
28619 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28621 rtx label1 = gen_label_rtx ();
28622 rtx label2 = gen_label_rtx ();
28624 rtx tmp = gen_reg_rtx (XFmode);
28625 rtx tmp2 = gen_reg_rtx (XFmode);
28627 emit_insn (gen_absxf2 (tmp, op1));
28628 emit_insn (gen_cmpxf (tmp,
28629 CONST_DOUBLE_FROM_REAL_VALUE (
28630 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28632 emit_jump_insn (gen_bge (label1));
28634 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28635 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28636 emit_jump (label2);
28638 emit_label (label1);
28639 emit_move_insn (tmp, CONST1_RTX (XFmode));
28640 emit_insn (gen_addxf3 (tmp, op1, tmp));
28641 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28642 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28644 emit_label (label2);
28647 /* Output code to perform a Newton-Rhapson approximation of a single precision
28648 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28650 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28652 rtx x0, x1, e0, e1, two;
28654 x0 = gen_reg_rtx (mode);
28655 e0 = gen_reg_rtx (mode);
28656 e1 = gen_reg_rtx (mode);
28657 x1 = gen_reg_rtx (mode);
28659 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28661 if (VECTOR_MODE_P (mode))
28662 two = ix86_build_const_vector (SFmode, true, two);
28664 two = force_reg (mode, two);
28666 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28668 /* x0 = rcp(b) estimate */
28669 emit_insn (gen_rtx_SET (VOIDmode, x0,
28670 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28673 emit_insn (gen_rtx_SET (VOIDmode, e0,
28674 gen_rtx_MULT (mode, x0, b)));
28676 emit_insn (gen_rtx_SET (VOIDmode, e1,
28677 gen_rtx_MINUS (mode, two, e0)));
28679 emit_insn (gen_rtx_SET (VOIDmode, x1,
28680 gen_rtx_MULT (mode, x0, e1)));
28682 emit_insn (gen_rtx_SET (VOIDmode, res,
28683 gen_rtx_MULT (mode, a, x1)));
28686 /* Output code to perform a Newton-Rhapson approximation of a
28687 single precision floating point [reciprocal] square root. */
28689 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28692 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28695 x0 = gen_reg_rtx (mode);
28696 e0 = gen_reg_rtx (mode);
28697 e1 = gen_reg_rtx (mode);
28698 e2 = gen_reg_rtx (mode);
28699 e3 = gen_reg_rtx (mode);
28701 real_from_integer (&r, VOIDmode, -3, -1, 0);
28702 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28704 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28705 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28707 if (VECTOR_MODE_P (mode))
28709 mthree = ix86_build_const_vector (SFmode, true, mthree);
28710 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28713 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28714 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28716 /* x0 = rsqrt(a) estimate */
28717 emit_insn (gen_rtx_SET (VOIDmode, x0,
28718 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28721 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28726 zero = gen_reg_rtx (mode);
28727 mask = gen_reg_rtx (mode);
28729 zero = force_reg (mode, CONST0_RTX(mode));
28730 emit_insn (gen_rtx_SET (VOIDmode, mask,
28731 gen_rtx_NE (mode, zero, a)));
28733 emit_insn (gen_rtx_SET (VOIDmode, x0,
28734 gen_rtx_AND (mode, x0, mask)));
28738 emit_insn (gen_rtx_SET (VOIDmode, e0,
28739 gen_rtx_MULT (mode, x0, a)));
28741 emit_insn (gen_rtx_SET (VOIDmode, e1,
28742 gen_rtx_MULT (mode, e0, x0)));
28745 mthree = force_reg (mode, mthree);
28746 emit_insn (gen_rtx_SET (VOIDmode, e2,
28747 gen_rtx_PLUS (mode, e1, mthree)));
28749 mhalf = force_reg (mode, mhalf);
28751 /* e3 = -.5 * x0 */
28752 emit_insn (gen_rtx_SET (VOIDmode, e3,
28753 gen_rtx_MULT (mode, x0, mhalf)));
28755 /* e3 = -.5 * e0 */
28756 emit_insn (gen_rtx_SET (VOIDmode, e3,
28757 gen_rtx_MULT (mode, e0, mhalf)));
28758 /* ret = e2 * e3 */
28759 emit_insn (gen_rtx_SET (VOIDmode, res,
28760 gen_rtx_MULT (mode, e2, e3)));
28763 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28765 static void ATTRIBUTE_UNUSED
28766 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28769 /* With Binutils 2.15, the "@unwind" marker must be specified on
28770 every occurrence of the ".eh_frame" section, not just the first
28773 && strcmp (name, ".eh_frame") == 0)
28775 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28776 flags & SECTION_WRITE ? "aw" : "a");
28779 default_elf_asm_named_section (name, flags, decl);
28782 /* Return the mangling of TYPE if it is an extended fundamental type. */
28784 static const char *
28785 ix86_mangle_type (const_tree type)
28787 type = TYPE_MAIN_VARIANT (type);
28789 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28790 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28793 switch (TYPE_MODE (type))
28796 /* __float128 is "g". */
28799 /* "long double" or __float80 is "e". */
28806 /* For 32-bit code we can save PIC register setup by using
28807 __stack_chk_fail_local hidden function instead of calling
28808 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28809 register, so it is better to call __stack_chk_fail directly. */
28812 ix86_stack_protect_fail (void)
28814 #if 0 /* XXX swildner */
28815 return TARGET_64BIT
28816 ? default_external_stack_protect_fail ()
28817 : default_hidden_stack_protect_fail ();
28819 return default_external_stack_protect_fail ();
28823 /* Select a format to encode pointers in exception handling data. CODE
28824 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28825 true if the symbol may be affected by dynamic relocations.
28827 ??? All x86 object file formats are capable of representing this.
28828 After all, the relocation needed is the same as for the call insn.
28829 Whether or not a particular assembler allows us to enter such, I
28830 guess we'll have to see. */
28832 asm_preferred_eh_data_format (int code, int global)
28836 int type = DW_EH_PE_sdata8;
28838 || ix86_cmodel == CM_SMALL_PIC
28839 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28840 type = DW_EH_PE_sdata4;
28841 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28843 if (ix86_cmodel == CM_SMALL
28844 || (ix86_cmodel == CM_MEDIUM && code))
28845 return DW_EH_PE_udata4;
28846 return DW_EH_PE_absptr;
28849 /* Expand copysign from SIGN to the positive value ABS_VALUE
28850 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28853 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28855 enum machine_mode mode = GET_MODE (sign);
28856 rtx sgn = gen_reg_rtx (mode);
28857 if (mask == NULL_RTX)
28859 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28860 if (!VECTOR_MODE_P (mode))
28862 /* We need to generate a scalar mode mask in this case. */
28863 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28864 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28865 mask = gen_reg_rtx (mode);
28866 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28870 mask = gen_rtx_NOT (mode, mask);
28871 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28872 gen_rtx_AND (mode, mask, sign)));
28873 emit_insn (gen_rtx_SET (VOIDmode, result,
28874 gen_rtx_IOR (mode, abs_value, sgn)));
28877 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28878 mask for masking out the sign-bit is stored in *SMASK, if that is
28881 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28883 enum machine_mode mode = GET_MODE (op0);
28886 xa = gen_reg_rtx (mode);
28887 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28888 if (!VECTOR_MODE_P (mode))
28890 /* We need to generate a scalar mode mask in this case. */
28891 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28892 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28893 mask = gen_reg_rtx (mode);
28894 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28896 emit_insn (gen_rtx_SET (VOIDmode, xa,
28897 gen_rtx_AND (mode, op0, mask)));
28905 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28906 swapping the operands if SWAP_OPERANDS is true. The expanded
28907 code is a forward jump to a newly created label in case the
28908 comparison is true. The generated label rtx is returned. */
28910 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28911 bool swap_operands)
28922 label = gen_label_rtx ();
28923 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28924 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28925 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28926 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28927 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28928 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28929 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28930 JUMP_LABEL (tmp) = label;
28935 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28936 using comparison code CODE. Operands are swapped for the comparison if
28937 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28939 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28940 bool swap_operands)
28942 enum machine_mode mode = GET_MODE (op0);
28943 rtx mask = gen_reg_rtx (mode);
28952 if (mode == DFmode)
28953 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28954 gen_rtx_fmt_ee (code, mode, op0, op1)));
28956 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28957 gen_rtx_fmt_ee (code, mode, op0, op1)));
28962 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28963 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28965 ix86_gen_TWO52 (enum machine_mode mode)
28967 REAL_VALUE_TYPE TWO52r;
28970 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28971 TWO52 = const_double_from_real_value (TWO52r, mode);
28972 TWO52 = force_reg (mode, TWO52);
28977 /* Expand SSE sequence for computing lround from OP1 storing
28980 ix86_expand_lround (rtx op0, rtx op1)
28982 /* C code for the stuff we're doing below:
28983 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28986 enum machine_mode mode = GET_MODE (op1);
28987 const struct real_format *fmt;
28988 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28991 /* load nextafter (0.5, 0.0) */
28992 fmt = REAL_MODE_FORMAT (mode);
28993 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28994 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28996 /* adj = copysign (0.5, op1) */
28997 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28998 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
29000 /* adj = op1 + adj */
29001 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
29003 /* op0 = (imode)adj */
29004 expand_fix (op0, adj, 0);
29007 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
29010 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
29012 /* C code for the stuff we're doing below (for do_floor):
29014 xi -= (double)xi > op1 ? 1 : 0;
29017 enum machine_mode fmode = GET_MODE (op1);
29018 enum machine_mode imode = GET_MODE (op0);
29019 rtx ireg, freg, label, tmp;
29021 /* reg = (long)op1 */
29022 ireg = gen_reg_rtx (imode);
29023 expand_fix (ireg, op1, 0);
29025 /* freg = (double)reg */
29026 freg = gen_reg_rtx (fmode);
29027 expand_float (freg, ireg, 0);
29029 /* ireg = (freg > op1) ? ireg - 1 : ireg */
29030 label = ix86_expand_sse_compare_and_jump (UNLE,
29031 freg, op1, !do_floor);
29032 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
29033 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
29034 emit_move_insn (ireg, tmp);
29036 emit_label (label);
29037 LABEL_NUSES (label) = 1;
29039 emit_move_insn (op0, ireg);
29042 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
29043 result in OPERAND0. */
29045 ix86_expand_rint (rtx operand0, rtx operand1)
29047 /* C code for the stuff we're doing below:
29048 xa = fabs (operand1);
29049 if (!isless (xa, 2**52))
29051 xa = xa + 2**52 - 2**52;
29052 return copysign (xa, operand1);
29054 enum machine_mode mode = GET_MODE (operand0);
29055 rtx res, xa, label, TWO52, mask;
29057 res = gen_reg_rtx (mode);
29058 emit_move_insn (res, operand1);
29060 /* xa = abs (operand1) */
29061 xa = ix86_expand_sse_fabs (res, &mask);
29063 /* if (!isless (xa, TWO52)) goto label; */
29064 TWO52 = ix86_gen_TWO52 (mode);
29065 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29067 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29068 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29070 ix86_sse_copysign_to_positive (res, xa, res, mask);
29072 emit_label (label);
29073 LABEL_NUSES (label) = 1;
29075 emit_move_insn (operand0, res);
29078 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29081 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
29083 /* C code for the stuff we expand below.
29084 double xa = fabs (x), x2;
29085 if (!isless (xa, TWO52))
29087 xa = xa + TWO52 - TWO52;
29088 x2 = copysign (xa, x);
29097 enum machine_mode mode = GET_MODE (operand0);
29098 rtx xa, TWO52, tmp, label, one, res, mask;
29100 TWO52 = ix86_gen_TWO52 (mode);
29102 /* Temporary for holding the result, initialized to the input
29103 operand to ease control flow. */
29104 res = gen_reg_rtx (mode);
29105 emit_move_insn (res, operand1);
29107 /* xa = abs (operand1) */
29108 xa = ix86_expand_sse_fabs (res, &mask);
29110 /* if (!isless (xa, TWO52)) goto label; */
29111 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29113 /* xa = xa + TWO52 - TWO52; */
29114 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29115 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29117 /* xa = copysign (xa, operand1) */
29118 ix86_sse_copysign_to_positive (xa, xa, res, mask);
29120 /* generate 1.0 or -1.0 */
29121 one = force_reg (mode,
29122 const_double_from_real_value (do_floor
29123 ? dconst1 : dconstm1, mode));
29125 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29126 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29127 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29128 gen_rtx_AND (mode, one, tmp)));
29129 /* We always need to subtract here to preserve signed zero. */
29130 tmp = expand_simple_binop (mode, MINUS,
29131 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29132 emit_move_insn (res, tmp);
29134 emit_label (label);
29135 LABEL_NUSES (label) = 1;
29137 emit_move_insn (operand0, res);
29140 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29143 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
29145 /* C code for the stuff we expand below.
29146 double xa = fabs (x), x2;
29147 if (!isless (xa, TWO52))
29149 x2 = (double)(long)x;
29156 if (HONOR_SIGNED_ZEROS (mode))
29157 return copysign (x2, x);
29160 enum machine_mode mode = GET_MODE (operand0);
29161 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29163 TWO52 = ix86_gen_TWO52 (mode);
29165 /* Temporary for holding the result, initialized to the input
29166 operand to ease control flow. */
29167 res = gen_reg_rtx (mode);
29168 emit_move_insn (res, operand1);
29170 /* xa = abs (operand1) */
29171 xa = ix86_expand_sse_fabs (res, &mask);
29173 /* if (!isless (xa, TWO52)) goto label; */
29174 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29176 /* xa = (double)(long)x */
29177 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29178 expand_fix (xi, res, 0);
29179 expand_float (xa, xi, 0);
29182 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29184 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29185 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29186 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29187 gen_rtx_AND (mode, one, tmp)));
29188 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29189 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29190 emit_move_insn (res, tmp);
29192 if (HONOR_SIGNED_ZEROS (mode))
29193 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29195 emit_label (label);
29196 LABEL_NUSES (label) = 1;
29198 emit_move_insn (operand0, res);
29201 /* Expand SSE sequence for computing round from OPERAND1 storing
29202 into OPERAND0. Sequence that works without relying on DImode truncation
29203 via cvttsd2siq that is only available on 64bit targets. */
29205 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29207 /* C code for the stuff we expand below.
29208 double xa = fabs (x), xa2, x2;
29209 if (!isless (xa, TWO52))
29211 Using the absolute value and copying back sign makes
29212 -0.0 -> -0.0 correct.
29213 xa2 = xa + TWO52 - TWO52;
29218 else if (dxa > 0.5)
29220 x2 = copysign (xa2, x);
29223 enum machine_mode mode = GET_MODE (operand0);
29224 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29226 TWO52 = ix86_gen_TWO52 (mode);
29228 /* Temporary for holding the result, initialized to the input
29229 operand to ease control flow. */
29230 res = gen_reg_rtx (mode);
29231 emit_move_insn (res, operand1);
29233 /* xa = abs (operand1) */
29234 xa = ix86_expand_sse_fabs (res, &mask);
29236 /* if (!isless (xa, TWO52)) goto label; */
29237 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29239 /* xa2 = xa + TWO52 - TWO52; */
29240 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29241 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29243 /* dxa = xa2 - xa; */
29244 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29246 /* generate 0.5, 1.0 and -0.5 */
29247 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29248 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29249 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29253 tmp = gen_reg_rtx (mode);
29254 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29255 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29256 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29257 gen_rtx_AND (mode, one, tmp)));
29258 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29259 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29260 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29261 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29262 gen_rtx_AND (mode, one, tmp)));
29263 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29265 /* res = copysign (xa2, operand1) */
29266 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29268 emit_label (label);
29269 LABEL_NUSES (label) = 1;
29271 emit_move_insn (operand0, res);
29274 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29277 ix86_expand_trunc (rtx operand0, rtx operand1)
29279 /* C code for SSE variant we expand below.
29280 double xa = fabs (x), x2;
29281 if (!isless (xa, TWO52))
29283 x2 = (double)(long)x;
29284 if (HONOR_SIGNED_ZEROS (mode))
29285 return copysign (x2, x);
29288 enum machine_mode mode = GET_MODE (operand0);
29289 rtx xa, xi, TWO52, label, res, mask;
29291 TWO52 = ix86_gen_TWO52 (mode);
29293 /* Temporary for holding the result, initialized to the input
29294 operand to ease control flow. */
29295 res = gen_reg_rtx (mode);
29296 emit_move_insn (res, operand1);
29298 /* xa = abs (operand1) */
29299 xa = ix86_expand_sse_fabs (res, &mask);
29301 /* if (!isless (xa, TWO52)) goto label; */
29302 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29304 /* x = (double)(long)x */
29305 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29306 expand_fix (xi, res, 0);
29307 expand_float (res, xi, 0);
29309 if (HONOR_SIGNED_ZEROS (mode))
29310 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29312 emit_label (label);
29313 LABEL_NUSES (label) = 1;
29315 emit_move_insn (operand0, res);
29318 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29321 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29323 enum machine_mode mode = GET_MODE (operand0);
29324 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29326 /* C code for SSE variant we expand below.
29327 double xa = fabs (x), x2;
29328 if (!isless (xa, TWO52))
29330 xa2 = xa + TWO52 - TWO52;
29334 x2 = copysign (xa2, x);
29338 TWO52 = ix86_gen_TWO52 (mode);
29340 /* Temporary for holding the result, initialized to the input
29341 operand to ease control flow. */
29342 res = gen_reg_rtx (mode);
29343 emit_move_insn (res, operand1);
29345 /* xa = abs (operand1) */
29346 xa = ix86_expand_sse_fabs (res, &smask);
29348 /* if (!isless (xa, TWO52)) goto label; */
29349 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29351 /* res = xa + TWO52 - TWO52; */
29352 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29353 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29354 emit_move_insn (res, tmp);
29357 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29359 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29360 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29361 emit_insn (gen_rtx_SET (VOIDmode, mask,
29362 gen_rtx_AND (mode, mask, one)));
29363 tmp = expand_simple_binop (mode, MINUS,
29364 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29365 emit_move_insn (res, tmp);
29367 /* res = copysign (res, operand1) */
29368 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29370 emit_label (label);
29371 LABEL_NUSES (label) = 1;
29373 emit_move_insn (operand0, res);
29376 /* Expand SSE sequence for computing round from OPERAND1 storing
29379 ix86_expand_round (rtx operand0, rtx operand1)
29381 /* C code for the stuff we're doing below:
29382 double xa = fabs (x);
29383 if (!isless (xa, TWO52))
29385 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29386 return copysign (xa, x);
29388 enum machine_mode mode = GET_MODE (operand0);
29389 rtx res, TWO52, xa, label, xi, half, mask;
29390 const struct real_format *fmt;
29391 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29393 /* Temporary for holding the result, initialized to the input
29394 operand to ease control flow. */
29395 res = gen_reg_rtx (mode);
29396 emit_move_insn (res, operand1);
29398 TWO52 = ix86_gen_TWO52 (mode);
29399 xa = ix86_expand_sse_fabs (res, &mask);
29400 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29402 /* load nextafter (0.5, 0.0) */
29403 fmt = REAL_MODE_FORMAT (mode);
29404 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29405 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29407 /* xa = xa + 0.5 */
29408 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29409 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29411 /* xa = (double)(int64_t)xa */
29412 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29413 expand_fix (xi, xa, 0);
29414 expand_float (xa, xi, 0);
29416 /* res = copysign (xa, operand1) */
29417 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29419 emit_label (label);
29420 LABEL_NUSES (label) = 1;
29422 emit_move_insn (operand0, res);
29426 /* Validate whether a SSE5 instruction is valid or not.
29427 OPERANDS is the array of operands.
29428 NUM is the number of operands.
29429 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29430 NUM_MEMORY is the maximum number of memory operands to accept.
29431 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29434 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29435 bool uses_oc0, int num_memory, bool commutative)
29441 /* Count the number of memory arguments */
29444 for (i = 0; i < num; i++)
29446 enum machine_mode mode = GET_MODE (operands[i]);
29447 if (register_operand (operands[i], mode))
29450 else if (memory_operand (operands[i], mode))
29452 mem_mask |= (1 << i);
29458 rtx pattern = PATTERN (insn);
29460 /* allow 0 for pcmov */
29461 if (GET_CODE (pattern) != SET
29462 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29464 || operands[i] != CONST0_RTX (mode))
29469 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29470 a memory operation. */
29471 if (num_memory < 0)
29473 num_memory = -num_memory;
29474 if ((mem_mask & (1 << (num-1))) != 0)
29476 mem_mask &= ~(1 << (num-1));
29481 /* If there were no memory operations, allow the insn */
29485 /* Do not allow the destination register to be a memory operand. */
29486 else if (mem_mask & (1 << 0))
29489 /* If there are too many memory operations, disallow the instruction. While
29490 the hardware only allows 1 memory reference, before register allocation
29491 for some insns, we allow two memory operations sometimes in order to allow
29492 code like the following to be optimized:
29494 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29496 or similar cases that are vectorized into using the fmaddss
29498 else if (mem_count > num_memory)
29501 /* Don't allow more than one memory operation if not optimizing. */
29502 else if (mem_count > 1 && !optimize)
29505 else if (num == 4 && mem_count == 1)
29507 /* formats (destination is the first argument), example fmaddss:
29508 xmm1, xmm1, xmm2, xmm3/mem
29509 xmm1, xmm1, xmm2/mem, xmm3
29510 xmm1, xmm2, xmm3/mem, xmm1
29511 xmm1, xmm2/mem, xmm3, xmm1 */
29513 return ((mem_mask == (1 << 1))
29514 || (mem_mask == (1 << 2))
29515 || (mem_mask == (1 << 3)));
29517 /* format, example pmacsdd:
29518 xmm1, xmm2, xmm3/mem, xmm1 */
29520 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29522 return (mem_mask == (1 << 2));
29525 else if (num == 4 && num_memory == 2)
29527 /* If there are two memory operations, we can load one of the memory ops
29528 into the destination register. This is for optimizing the
29529 multiply/add ops, which the combiner has optimized both the multiply
29530 and the add insns to have a memory operation. We have to be careful
29531 that the destination doesn't overlap with the inputs. */
29532 rtx op0 = operands[0];
29534 if (reg_mentioned_p (op0, operands[1])
29535 || reg_mentioned_p (op0, operands[2])
29536 || reg_mentioned_p (op0, operands[3]))
29539 /* formats (destination is the first argument), example fmaddss:
29540 xmm1, xmm1, xmm2, xmm3/mem
29541 xmm1, xmm1, xmm2/mem, xmm3
29542 xmm1, xmm2, xmm3/mem, xmm1
29543 xmm1, xmm2/mem, xmm3, xmm1
29545 For the oc0 case, we will load either operands[1] or operands[3] into
29546 operands[0], so any combination of 2 memory operands is ok. */
29550 /* format, example pmacsdd:
29551 xmm1, xmm2, xmm3/mem, xmm1
29553 For the integer multiply/add instructions be more restrictive and
29554 require operands[2] and operands[3] to be the memory operands. */
29556 return (mem_mask == ((1 << 1) | (1 << 3)) ||
29557 mem_mask == ((1 << 2) | (1 << 3)));
29559 return (mem_mask == ((1 << 2) | (1 << 3)));
29562 else if (num == 3 && num_memory == 1)
29564 /* formats, example protb:
29565 xmm1, xmm2, xmm3/mem
29566 xmm1, xmm2/mem, xmm3 */
29568 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29570 /* format, example comeq:
29571 xmm1, xmm2, xmm3/mem */
29573 return (mem_mask == (1 << 2));
29577 gcc_unreachable ();
29583 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29584 hardware will allow by using the destination register to load one of the
29585 memory operations. Presently this is used by the multiply/add routines to
29586 allow 2 memory references. */
29589 ix86_expand_sse5_multiple_memory (rtx operands[],
29591 enum machine_mode mode)
29593 rtx op0 = operands[0];
29595 || memory_operand (op0, mode)
29596 || reg_mentioned_p (op0, operands[1])
29597 || reg_mentioned_p (op0, operands[2])
29598 || reg_mentioned_p (op0, operands[3]))
29599 gcc_unreachable ();
29601 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29602 the destination register. */
29603 if (memory_operand (operands[1], mode))
29605 emit_move_insn (op0, operands[1]);
29608 else if (memory_operand (operands[3], mode))
29610 emit_move_insn (op0, operands[3]);
29614 gcc_unreachable ();
29620 /* Table of valid machine attributes. */
29621 static const struct attribute_spec ix86_attribute_table[] =
29623 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29624 /* Stdcall attribute says callee is responsible for popping arguments
29625 if they are not variable. */
29626 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29627 /* Fastcall attribute says callee is responsible for popping arguments
29628 if they are not variable. */
29629 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29630 /* Cdecl attribute says the callee is a normal C declaration */
29631 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29632 /* Regparm attribute specifies how many integer arguments are to be
29633 passed in registers. */
29634 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29635 /* Sseregparm attribute says we are using x86_64 calling conventions
29636 for FP arguments. */
29637 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29638 /* force_align_arg_pointer says this function realigns the stack at entry. */
29639 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29640 false, true, true, ix86_handle_cconv_attribute },
29641 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29642 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29643 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29644 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29646 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29647 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29648 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29649 SUBTARGET_ATTRIBUTE_TABLE,
29651 /* ms_abi and sysv_abi calling convention function attributes. */
29652 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29653 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29655 { NULL, 0, 0, false, false, false, NULL }
29658 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29660 x86_builtin_vectorization_cost (bool runtime_test)
29662 /* If the branch of the runtime test is taken - i.e. - the vectorized
29663 version is skipped - this incurs a misprediction cost (because the
29664 vectorized version is expected to be the fall-through). So we subtract
29665 the latency of a mispredicted branch from the costs that are incured
29666 when the vectorized version is executed.
29668 TODO: The values in individual target tables have to be tuned or new
29669 fields may be needed. For eg. on K8, the default branch path is the
29670 not-taken path. If the taken path is predicted correctly, the minimum
29671 penalty of going down the taken-path is 1 cycle. If the taken-path is
29672 not predicted correctly, then the minimum penalty is 10 cycles. */
29676 return (-(ix86_cost->cond_taken_branch_cost));
29682 /* This function returns the calling abi specific va_list type node.
29683 It returns the FNDECL specific va_list type. */
29686 ix86_fn_abi_va_list (tree fndecl)
29691 return va_list_type_node;
29692 gcc_assert (fndecl != NULL_TREE);
29693 abi = ix86_function_abi ((const_tree) fndecl);
29696 return ms_va_list_type_node;
29698 return sysv_va_list_type_node;
29701 /* Returns the canonical va_list type specified by TYPE. If there
29702 is no valid TYPE provided, it return NULL_TREE. */
29705 ix86_canonical_va_list_type (tree type)
29709 /* Resolve references and pointers to va_list type. */
29710 if (INDIRECT_REF_P (type))
29711 type = TREE_TYPE (type);
29712 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29713 type = TREE_TYPE (type);
29717 wtype = va_list_type_node;
29718 gcc_assert (wtype != NULL_TREE);
29720 if (TREE_CODE (wtype) == ARRAY_TYPE)
29722 /* If va_list is an array type, the argument may have decayed
29723 to a pointer type, e.g. by being passed to another function.
29724 In that case, unwrap both types so that we can compare the
29725 underlying records. */
29726 if (TREE_CODE (htype) == ARRAY_TYPE
29727 || POINTER_TYPE_P (htype))
29729 wtype = TREE_TYPE (wtype);
29730 htype = TREE_TYPE (htype);
29733 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29734 return va_list_type_node;
29735 wtype = sysv_va_list_type_node;
29736 gcc_assert (wtype != NULL_TREE);
29738 if (TREE_CODE (wtype) == ARRAY_TYPE)
29740 /* If va_list is an array type, the argument may have decayed
29741 to a pointer type, e.g. by being passed to another function.
29742 In that case, unwrap both types so that we can compare the
29743 underlying records. */
29744 if (TREE_CODE (htype) == ARRAY_TYPE
29745 || POINTER_TYPE_P (htype))
29747 wtype = TREE_TYPE (wtype);
29748 htype = TREE_TYPE (htype);
29751 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29752 return sysv_va_list_type_node;
29753 wtype = ms_va_list_type_node;
29754 gcc_assert (wtype != NULL_TREE);
29756 if (TREE_CODE (wtype) == ARRAY_TYPE)
29758 /* If va_list is an array type, the argument may have decayed
29759 to a pointer type, e.g. by being passed to another function.
29760 In that case, unwrap both types so that we can compare the
29761 underlying records. */
29762 if (TREE_CODE (htype) == ARRAY_TYPE
29763 || POINTER_TYPE_P (htype))
29765 wtype = TREE_TYPE (wtype);
29766 htype = TREE_TYPE (htype);
29769 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29770 return ms_va_list_type_node;
29773 return std_canonical_va_list_type (type);
29776 /* Iterate through the target-specific builtin types for va_list.
29777 IDX denotes the iterator, *PTREE is set to the result type of
29778 the va_list builtin, and *PNAME to its internal type.
29779 Returns zero if there is no element for this index, otherwise
29780 IDX should be increased upon the next call.
29781 Note, do not iterate a base builtin's name like __builtin_va_list.
29782 Used from c_common_nodes_and_builtins. */
29785 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29791 *ptree = ms_va_list_type_node;
29792 *pname = "__builtin_ms_va_list";
29795 *ptree = sysv_va_list_type_node;
29796 *pname = "__builtin_sysv_va_list";
29804 /* Initialize the GCC target structure. */
29805 #undef TARGET_RETURN_IN_MEMORY
29806 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29808 #undef TARGET_ATTRIBUTE_TABLE
29809 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29810 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29811 # undef TARGET_MERGE_DECL_ATTRIBUTES
29812 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29815 #undef TARGET_COMP_TYPE_ATTRIBUTES
29816 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29818 #undef TARGET_INIT_BUILTINS
29819 #define TARGET_INIT_BUILTINS ix86_init_builtins
29820 #undef TARGET_EXPAND_BUILTIN
29821 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29823 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29824 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29825 ix86_builtin_vectorized_function
29827 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29828 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29830 #undef TARGET_BUILTIN_RECIPROCAL
29831 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29833 #undef TARGET_ASM_FUNCTION_EPILOGUE
29834 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29836 #undef TARGET_ENCODE_SECTION_INFO
29837 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29838 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29840 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29843 #undef TARGET_ASM_OPEN_PAREN
29844 #define TARGET_ASM_OPEN_PAREN ""
29845 #undef TARGET_ASM_CLOSE_PAREN
29846 #define TARGET_ASM_CLOSE_PAREN ""
29848 #undef TARGET_ASM_ALIGNED_HI_OP
29849 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29850 #undef TARGET_ASM_ALIGNED_SI_OP
29851 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29853 #undef TARGET_ASM_ALIGNED_DI_OP
29854 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29857 #undef TARGET_ASM_UNALIGNED_HI_OP
29858 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29859 #undef TARGET_ASM_UNALIGNED_SI_OP
29860 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29861 #undef TARGET_ASM_UNALIGNED_DI_OP
29862 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29864 #undef TARGET_SCHED_ADJUST_COST
29865 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29866 #undef TARGET_SCHED_ISSUE_RATE
29867 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29868 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29869 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29870 ia32_multipass_dfa_lookahead
29872 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29873 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29876 #undef TARGET_HAVE_TLS
29877 #define TARGET_HAVE_TLS true
29879 #undef TARGET_CANNOT_FORCE_CONST_MEM
29880 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29881 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29882 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29884 #undef TARGET_DELEGITIMIZE_ADDRESS
29885 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29887 #undef TARGET_MS_BITFIELD_LAYOUT_P
29888 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29891 #undef TARGET_BINDS_LOCAL_P
29892 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29894 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29895 #undef TARGET_BINDS_LOCAL_P
29896 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29899 #undef TARGET_ASM_OUTPUT_MI_THUNK
29900 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29901 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29902 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29904 #undef TARGET_ASM_FILE_START
29905 #define TARGET_ASM_FILE_START x86_file_start
29907 #undef TARGET_DEFAULT_TARGET_FLAGS
29908 #define TARGET_DEFAULT_TARGET_FLAGS \
29910 | TARGET_SUBTARGET_DEFAULT \
29911 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29913 #undef TARGET_HANDLE_OPTION
29914 #define TARGET_HANDLE_OPTION ix86_handle_option
29916 #undef TARGET_RTX_COSTS
29917 #define TARGET_RTX_COSTS ix86_rtx_costs
29918 #undef TARGET_ADDRESS_COST
29919 #define TARGET_ADDRESS_COST ix86_address_cost
29921 #undef TARGET_FIXED_CONDITION_CODE_REGS
29922 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29923 #undef TARGET_CC_MODES_COMPATIBLE
29924 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29926 #undef TARGET_MACHINE_DEPENDENT_REORG
29927 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29929 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29930 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29932 #undef TARGET_BUILD_BUILTIN_VA_LIST
29933 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29935 #undef TARGET_FN_ABI_VA_LIST
29936 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29938 #undef TARGET_CANONICAL_VA_LIST_TYPE
29939 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29941 #undef TARGET_EXPAND_BUILTIN_VA_START
29942 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29944 #undef TARGET_MD_ASM_CLOBBERS
29945 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29947 #undef TARGET_PROMOTE_PROTOTYPES
29948 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29949 #undef TARGET_STRUCT_VALUE_RTX
29950 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29951 #undef TARGET_SETUP_INCOMING_VARARGS
29952 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29953 #undef TARGET_MUST_PASS_IN_STACK
29954 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29955 #undef TARGET_PASS_BY_REFERENCE
29956 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29957 #undef TARGET_INTERNAL_ARG_POINTER
29958 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29959 #undef TARGET_UPDATE_STACK_BOUNDARY
29960 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29961 #undef TARGET_GET_DRAP_RTX
29962 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29963 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29964 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29965 #undef TARGET_STRICT_ARGUMENT_NAMING
29966 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29968 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29969 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29971 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29972 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29974 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29975 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29977 #undef TARGET_C_MODE_FOR_SUFFIX
29978 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29981 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29982 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29985 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29986 #undef TARGET_INSERT_ATTRIBUTES
29987 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29990 #undef TARGET_MANGLE_TYPE
29991 #define TARGET_MANGLE_TYPE ix86_mangle_type
29993 #undef TARGET_STACK_PROTECT_FAIL
29994 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29996 #undef TARGET_FUNCTION_VALUE
29997 #define TARGET_FUNCTION_VALUE ix86_function_value
29999 #undef TARGET_SECONDARY_RELOAD
30000 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30002 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30003 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
30005 #undef TARGET_SET_CURRENT_FUNCTION
30006 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30008 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30009 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30011 #undef TARGET_OPTION_SAVE
30012 #define TARGET_OPTION_SAVE ix86_function_specific_save
30014 #undef TARGET_OPTION_RESTORE
30015 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30017 #undef TARGET_OPTION_PRINT
30018 #define TARGET_OPTION_PRINT ix86_function_specific_print
30020 #undef TARGET_OPTION_CAN_INLINE_P
30021 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
30023 #undef TARGET_EXPAND_TO_RTL_HOOK
30024 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30026 struct gcc_target targetm = TARGET_INITIALIZER;
30028 #include "gt-i386.h"
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