2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $
33 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
34 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.52 2006/12/22 23:26:22 swildner Exp $
38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
40 * Permission to use, copy, modify, and distribute this software for any
41 * purpose with or without fee is hereby granted, provided that the above
42 * copyright notice and this permission notice appear in all copies.
44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
57 * The XaQti XMAC II datasheet,
58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
73 * The SysKonnect gigabit ethernet adapters consist of two main
74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
76 * components and a PHY while the GEnesis controller provides a PCI
77 * interface with DMA support. Each card may have between 512K and
78 * 2MB of SRAM on board depending on the configuration.
80 * The SysKonnect GEnesis controller can have either one or two XMAC
81 * chips connected to it, allowing single or dual port NIC configurations.
82 * SysKonnect has the distinction of being the only vendor on the market
83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
85 * XMAC registers. This driver takes advantage of these features to allow
86 * both XMACs to operate as independent interfaces.
89 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/in_cksum.h>
93 #include <sys/kernel.h>
95 #include <sys/malloc.h>
96 #include <sys/queue.h>
98 #include <sys/serialize.h>
99 #include <sys/socket.h>
100 #include <sys/sockio.h>
103 #include <net/ethernet.h>
105 #include <net/if_arp.h>
106 #include <net/if_dl.h>
107 #include <net/if_media.h>
108 #include <net/ifq_var.h>
109 #include <net/vlan/if_vlan_var.h>
111 #include <netinet/ip.h>
112 #include <netinet/udp.h>
114 #include <dev/netif/mii_layer/mii.h>
115 #include <dev/netif/mii_layer/miivar.h>
116 #include <dev/netif/mii_layer/brgphyreg.h>
118 #include <bus/pci/pcireg.h>
119 #include <bus/pci/pcivar.h>
120 #include <bus/pci/pcidevs.h>
122 #include <dev/netif/sk/if_skreg.h>
123 #include <dev/netif/sk/yukonreg.h>
124 #include <dev/netif/sk/xmaciireg.h>
125 #include <dev/netif/sk/if_skvar.h>
127 #include "miibus_if.h"
137 /* supported device vendors */
138 static const struct skc_type {
141 const char *skc_name;
143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940,
145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B,
148 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD,
151 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_A1,
152 "D-Link DGE-530T A1" },
153 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_B1,
154 "D-Link DGE-530T B1" },
156 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
157 "Linksys EG1032 v2" },
158 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064,
161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON,
162 "Marvell Yukon 88E8001/8003/8010" },
163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN,
166 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE,
167 "SysKonnect SK-NET" },
168 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2,
169 "SysKonnect SK9821 v2" },
174 static int skc_probe(device_t);
175 static int skc_attach(device_t);
176 static int skc_detach(device_t);
177 static void skc_shutdown(device_t);
178 static int sk_probe(device_t);
179 static int sk_attach(device_t);
180 static int sk_detach(device_t);
181 static void sk_tick(void *);
182 static void sk_yukon_tick(void *);
183 static void sk_intr(void *);
184 static void sk_intr_bcom(struct sk_if_softc *);
185 static void sk_intr_xmac(struct sk_if_softc *);
186 static void sk_intr_yukon(struct sk_if_softc *);
187 static void sk_rxeof(struct sk_if_softc *);
188 static void sk_txeof(struct sk_if_softc *);
189 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *);
190 static void sk_start(struct ifnet *);
191 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
192 static void sk_init(void *);
193 static void sk_init_xmac(struct sk_if_softc *);
194 static void sk_init_yukon(struct sk_if_softc *);
195 static void sk_stop(struct sk_if_softc *);
196 static void sk_watchdog(struct ifnet *);
197 static int sk_ifmedia_upd(struct ifnet *);
198 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
199 static void sk_reset(struct sk_softc *);
200 static int sk_newbuf_jumbo(struct sk_if_softc *, int, int);
201 static int sk_newbuf_std(struct sk_if_softc *, int, int);
202 static int sk_jpool_alloc(device_t);
203 static void sk_jpool_free(struct sk_if_softc *);
204 static struct sk_jpool_entry
205 *sk_jalloc(struct sk_if_softc *);
206 static void sk_jfree(void *);
207 static void sk_jref(void *);
208 static int sk_init_rx_ring(struct sk_if_softc *);
209 static int sk_init_tx_ring(struct sk_if_softc *);
211 static int sk_miibus_readreg(device_t, int, int);
212 static int sk_miibus_writereg(device_t, int, int, int);
213 static void sk_miibus_statchg(device_t);
215 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
216 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
217 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
219 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
220 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
221 static void sk_marv_miibus_statchg(struct sk_if_softc *);
223 static void sk_setfilt(struct sk_if_softc *, caddr_t, int);
224 static void sk_setmulti(struct sk_if_softc *);
225 static void sk_setpromisc(struct sk_if_softc *);
228 static void sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t,
231 static int sk_dma_alloc(device_t);
232 static void sk_dma_free(device_t);
234 static void sk_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
236 static void sk_dmamem_addr(void *, bus_dma_segment_t *, int, int);
239 #define DPRINTF(x) if (skdebug) kprintf x
240 #define DPRINTFN(n,x) if (skdebug >= (n)) kprintf x
241 static int skdebug = 2;
243 static void sk_dump_txdesc(struct sk_tx_desc *, int);
244 static void sk_dump_mbuf(struct mbuf *);
245 static void sk_dump_bytes(const char *, int);
248 #define DPRINTFN(n,x)
252 * Note that we have newbus methods for both the GEnesis controller
253 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
254 * the miibus code is a child of the XMACs. We need to do it this way
255 * so that the miibus drivers can access the PHY registers on the
256 * right PHY. It's not quite what I had in mind, but it's the only
257 * design that achieves the desired effect.
259 static device_method_t skc_methods[] = {
260 /* Device interface */
261 DEVMETHOD(device_probe, skc_probe),
262 DEVMETHOD(device_attach, skc_attach),
263 DEVMETHOD(device_detach, skc_detach),
264 DEVMETHOD(device_shutdown, skc_shutdown),
267 DEVMETHOD(bus_print_child, bus_generic_print_child),
268 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
273 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
274 static devclass_t skc_devclass;
276 static device_method_t sk_methods[] = {
277 /* Device interface */
278 DEVMETHOD(device_probe, sk_probe),
279 DEVMETHOD(device_attach, sk_attach),
280 DEVMETHOD(device_detach, sk_detach),
281 DEVMETHOD(device_shutdown, bus_generic_shutdown),
284 DEVMETHOD(bus_print_child, bus_generic_print_child),
285 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
288 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
289 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
290 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
295 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
296 static devclass_t sk_devclass;
298 DECLARE_DUMMY_MODULE(if_sk);
299 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
300 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
301 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
303 static __inline uint32_t
304 sk_win_read_4(struct sk_softc *sc, uint32_t reg)
306 return CSR_READ_4(sc, reg);
309 static __inline uint16_t
310 sk_win_read_2(struct sk_softc *sc, uint32_t reg)
312 return CSR_READ_2(sc, reg);
315 static __inline uint8_t
316 sk_win_read_1(struct sk_softc *sc, uint32_t reg)
318 return CSR_READ_1(sc, reg);
322 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
324 CSR_WRITE_4(sc, reg, x);
328 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
330 CSR_WRITE_2(sc, reg, x);
334 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
336 CSR_WRITE_1(sc, reg, x);
340 sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait)
344 if (sc_if->sk_use_jumbo)
345 ret = sk_newbuf_jumbo(sc_if, idx, wait);
347 ret = sk_newbuf_std(sc_if, idx, wait);
352 sk_miibus_readreg(device_t dev, int phy, int reg)
354 struct sk_if_softc *sc_if = device_get_softc(dev);
356 if (SK_IS_GENESIS(sc_if->sk_softc))
357 return sk_xmac_miibus_readreg(sc_if, phy, reg);
359 return sk_marv_miibus_readreg(sc_if, phy, reg);
363 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
365 struct sk_if_softc *sc_if = device_get_softc(dev);
367 if (SK_IS_GENESIS(sc_if->sk_softc))
368 return sk_xmac_miibus_writereg(sc_if, phy, reg, val);
370 return sk_marv_miibus_writereg(sc_if, phy, reg, val);
374 sk_miibus_statchg(device_t dev)
376 struct sk_if_softc *sc_if = device_get_softc(dev);
378 if (SK_IS_GENESIS(sc_if->sk_softc))
379 sk_xmac_miibus_statchg(sc_if);
381 sk_marv_miibus_statchg(sc_if);
385 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
389 DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
391 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
394 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
395 SK_XM_READ_2(sc_if, XM_PHY_DATA);
396 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
397 for (i = 0; i < SK_TIMEOUT; i++) {
399 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
400 XM_MMUCMD_PHYDATARDY)
404 if (i == SK_TIMEOUT) {
405 if_printf(&sc_if->arpcom.ac_if,
406 "phy failed to come ready\n");
411 return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
415 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
419 DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
421 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
422 for (i = 0; i < SK_TIMEOUT; i++) {
423 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
427 if (i == SK_TIMEOUT) {
428 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
432 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
433 for (i = 0; i < SK_TIMEOUT; i++) {
435 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
440 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
445 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
447 struct mii_data *mii;
449 mii = device_get_softc(sc_if->sk_miibus);
450 DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
453 * If this is a GMII PHY, manually set the XMAC's
454 * duplex mode accordingly.
456 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
457 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
458 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
460 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
465 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
471 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
472 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
473 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
478 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
479 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
481 for (i = 0; i < SK_TIMEOUT; i++) {
483 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
484 if (val & YU_SMICR_READ_VALID)
488 if (i == SK_TIMEOUT) {
489 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
493 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
496 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
498 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
505 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
509 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
512 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
513 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
514 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
516 for (i = 0; i < SK_TIMEOUT; i++) {
518 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
523 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
529 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
531 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
532 SK_YU_READ_2(sc_if, YUKON_GPCR)));
538 sk_xmac_hash(caddr_t addr)
542 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
543 return (~crc & ((1 << HASH_BITS) - 1));
547 sk_yukon_hash(caddr_t addr)
551 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
552 return (crc & ((1 << HASH_BITS) - 1));
556 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
560 base = XM_RXFILT_ENTRY(slot);
562 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
563 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
564 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
568 sk_setmulti(struct sk_if_softc *sc_if)
570 struct sk_softc *sc = sc_if->sk_softc;
571 struct ifnet *ifp = &sc_if->arpcom.ac_if;
572 uint32_t hashes[2] = { 0, 0 };
574 struct ifmultiaddr *ifma;
575 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
577 /* First, zot all the existing filters. */
578 switch(sc->sk_type) {
580 for (i = 1; i < XM_RXFILT_MAX; i++)
581 sk_setfilt(sc_if, (caddr_t)&dummy, i);
583 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
584 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
589 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
590 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
591 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
592 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
596 /* Now program new ones. */
597 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
598 hashes[0] = 0xFFFFFFFF;
599 hashes[1] = 0xFFFFFFFF;
602 /* First find the tail of the list. */
603 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
604 if (ifma->ifma_link.le_next == NULL)
607 /* Now traverse the list backwards. */
608 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
609 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
612 if (ifma->ifma_addr->sa_family != AF_LINK)
615 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
618 * Program the first XM_RXFILT_MAX multicast groups
619 * into the perfect filter. For all others,
620 * use the hash table.
622 if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) {
623 sk_setfilt(sc_if, maddr, i);
628 switch(sc->sk_type) {
630 h = sk_xmac_hash(maddr);
636 h = sk_yukon_hash(maddr);
640 hashes[0] |= (1 << h);
642 hashes[1] |= (1 << (h - 32));
646 switch(sc->sk_type) {
648 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
649 XM_MODE_RX_USE_PERFECT);
650 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
651 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
656 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
657 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
658 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
659 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
665 sk_setpromisc(struct sk_if_softc *sc_if)
667 struct sk_softc *sc = sc_if->sk_softc;
668 struct ifnet *ifp = &sc_if->arpcom.ac_if;
670 switch(sc->sk_type) {
672 if (ifp->if_flags & IFF_PROMISC)
673 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
675 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
680 if (ifp->if_flags & IFF_PROMISC) {
681 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
682 YU_RCR_UFLEN | YU_RCR_MUFLEN);
684 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
685 YU_RCR_UFLEN | YU_RCR_MUFLEN);
692 sk_init_rx_ring(struct sk_if_softc *sc_if)
694 struct sk_chain_data *cd = &sc_if->sk_cdata;
695 struct sk_ring_data *rd = sc_if->sk_rdata;
698 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
700 for (i = 0; i < SK_RX_RING_CNT; i++) {
701 if (i == (SK_RX_RING_CNT - 1))
705 rd->sk_rx_ring[i].sk_next =
706 htole32(SK_RX_RING_ADDR(sc_if, nexti));
707 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN);
708 rd->sk_rx_ring[i].sk_csum2_start =
709 htole16(ETHER_HDR_LEN + sizeof(struct ip));
711 error = sk_newbuf(sc_if, i, 1);
713 if_printf(&sc_if->arpcom.ac_if,
714 "failed alloc of %dth mbuf\n", i);
722 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
723 BUS_DMASYNC_PREWRITE);
729 sk_init_tx_ring(struct sk_if_softc *sc_if)
731 struct sk_ring_data *rd = sc_if->sk_rdata;
734 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
736 for (i = 0; i < SK_TX_RING_CNT; i++) {
737 if (i == (SK_TX_RING_CNT - 1))
741 rd->sk_tx_ring[i].sk_next = htole32(SK_TX_RING_ADDR(sc_if, nexti));
744 sc_if->sk_cdata.sk_tx_prod = 0;
745 sc_if->sk_cdata.sk_tx_cons = 0;
746 sc_if->sk_cdata.sk_tx_cnt = 0;
748 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
749 BUS_DMASYNC_PREWRITE);
755 sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait)
757 struct sk_jpool_entry *entry;
758 struct mbuf *m_new = NULL;
759 struct sk_rx_desc *r;
761 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
763 MGETHDR(m_new, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
767 /* Allocate the jumbo buffer */
768 entry = sk_jalloc(sc_if);
771 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
772 "dropped!\n", sc_if->arpcom.ac_if.if_xname));
776 m_new->m_ext.ext_arg = entry;
777 m_new->m_ext.ext_buf = entry->buf;
778 m_new->m_ext.ext_free = sk_jfree;
779 m_new->m_ext.ext_ref = sk_jref;
780 m_new->m_ext.ext_size = SK_JLEN;
782 m_new->m_flags |= M_EXT;
784 m_new->m_data = m_new->m_ext.ext_buf;
785 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
788 * Adjust alignment so packet payload begins on a
789 * longword boundary. Mandatory for Alpha, useful on
792 m_adj(m_new, ETHER_ALIGN);
794 sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new;
796 r = &sc_if->sk_rdata->sk_rx_ring[idx];
797 r->sk_data_lo = htole32(entry->paddr + ETHER_ALIGN);
798 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
804 sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait)
806 struct mbuf *m_new = NULL;
807 struct sk_chain_data *cd = &sc_if->sk_cdata;
808 struct sk_rx_desc *r;
809 struct sk_dma_ctx ctx;
810 bus_dma_segment_t seg;
814 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
816 m_new = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
820 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
823 * Adjust alignment so packet payload begins on a
824 * longword boundary. Mandatory for Alpha, useful on
827 m_adj(m_new, ETHER_ALIGN);
829 bzero(&ctx, sizeof(ctx));
832 error = bus_dmamap_load_mbuf(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp,
833 m_new, sk_buf_dma_addr, &ctx,
834 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
836 if_printf(&sc_if->arpcom.ac_if, "could not map RX mbuf\n");
841 /* Unload originally mapped mbuf */
842 if (cd->sk_rx_mbuf[idx] != NULL)
843 bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]);
845 /* Switch DMA map with tmp DMA map */
846 map = cd->sk_rx_dmap_tmp;
847 cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx];
848 cd->sk_rx_dmap[idx] = map;
850 cd->sk_rx_mbuf[idx] = m_new;
852 r = &sc_if->sk_rdata->sk_rx_ring[idx];
853 r->sk_data_lo = htole32(seg.ds_addr);
854 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
860 * Allocate a jumbo buffer.
862 struct sk_jpool_entry *
863 sk_jalloc(struct sk_if_softc *sc_if)
865 struct sk_chain_data *cd = &sc_if->sk_cdata;
866 struct sk_jpool_entry *entry;
868 lwkt_serialize_enter(&cd->sk_jpool_serializer);
870 entry = SLIST_FIRST(&cd->sk_jpool_free_ent);
872 SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next);
875 DPRINTF(("no free jumbo buffer\n"));
878 lwkt_serialize_exit(&cd->sk_jpool_serializer);
883 * Release a jumbo buffer.
888 struct sk_jpool_entry *entry = arg;
889 struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
891 if (&cd->sk_jpool_ent[entry->slot] != entry)
892 panic("%s: free wrong jumbo buffer\n", __func__);
893 else if (entry->inuse == 0)
894 panic("%s: jumbo buffer already freed\n", __func__);
896 lwkt_serialize_enter(&cd->sk_jpool_serializer);
898 atomic_subtract_int(&entry->inuse, 1);
899 if (entry->inuse == 0)
900 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
902 lwkt_serialize_exit(&cd->sk_jpool_serializer);
908 struct sk_jpool_entry *entry = arg;
909 struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
911 if (&cd->sk_jpool_ent[entry->slot] != entry)
912 panic("%s: free wrong jumbo buffer\n", __func__);
913 else if (entry->inuse == 0)
914 panic("%s: jumbo buffer already freed\n", __func__);
916 atomic_add_int(&entry->inuse, 1);
923 sk_ifmedia_upd(struct ifnet *ifp)
925 struct sk_if_softc *sc_if = ifp->if_softc;
926 struct mii_data *mii;
928 mii = device_get_softc(sc_if->sk_miibus);
936 * Report current media status.
939 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
941 struct sk_if_softc *sc_if;
942 struct mii_data *mii;
944 sc_if = ifp->if_softc;
945 mii = device_get_softc(sc_if->sk_miibus);
948 ifmr->ifm_active = mii->mii_media_active;
949 ifmr->ifm_status = mii->mii_media_status;
953 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
955 struct sk_if_softc *sc_if = ifp->if_softc;
956 struct ifreq *ifr = (struct ifreq *)data;
957 struct mii_data *mii;
960 ASSERT_SERIALIZED(ifp->if_serializer);
964 if (ifr->ifr_mtu > SK_JUMBO_MTU)
967 ifp->if_mtu = ifr->ifr_mtu;
968 ifp->if_flags &= ~IFF_RUNNING;
973 if (ifp->if_flags & IFF_UP) {
974 if (ifp->if_flags & IFF_RUNNING) {
975 if ((ifp->if_flags ^ sc_if->sk_if_flags)
977 sk_setpromisc(sc_if);
983 if (ifp->if_flags & IFF_RUNNING)
986 sc_if->sk_if_flags = ifp->if_flags;
994 mii = device_get_softc(sc_if->sk_miibus);
995 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
998 error = ether_ioctl(ifp, command, data);
1006 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1007 * IDs against our list and return a device name if we find a match.
1010 skc_probe(device_t dev)
1012 const struct skc_type *t;
1015 vid = pci_get_vendor(dev);
1016 did = pci_get_device(dev);
1019 * Only attach to rev.2 of the Linksys EG1032 adapter.
1020 * Rev.3 is supported by re(4).
1022 if (vid == PCI_VENDOR_LINKSYS &&
1023 did == PCI_PRODUCT_LINKSYS_EG1032 &&
1024 pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2)
1027 for (t = skc_devs; t->skc_name != NULL; t++) {
1028 if (vid == t->skc_vid && did == t->skc_did) {
1029 device_set_desc(dev, t->skc_name);
1037 * Force the GEnesis into reset, then bring it out of reset.
1040 sk_reset(struct sk_softc *sc)
1042 uint32_t imtimer_ticks;
1044 DPRINTFN(2, ("sk_reset\n"));
1046 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1047 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1048 if (SK_IS_YUKON(sc))
1049 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1052 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1054 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1055 if (SK_IS_YUKON(sc))
1056 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1058 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
1059 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
1060 CSR_READ_2(sc, SK_LINK_CTRL)));
1062 if (SK_IS_GENESIS(sc)) {
1063 /* Configure packet arbiter */
1064 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1065 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1066 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1067 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1068 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1071 /* Enable RAM interface */
1072 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1075 * Configure interrupt moderation. The moderation timer
1076 * defers interrupts specified in the interrupt moderation
1077 * timer mask based on the timeout specified in the interrupt
1078 * moderation timer init register. Each bit in the timer
1079 * register represents one tick, so to specify a timeout in
1080 * microseconds, we have to multiply by the correct number of
1081 * ticks-per-microsecond.
1083 switch (sc->sk_type) {
1085 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
1088 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1090 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100));
1091 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1092 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1093 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1097 sk_probe(device_t dev)
1099 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1100 const char *revstr = "", *name = NULL;
1103 switch (sc->sk_type) {
1105 name = "SysKonnect GEnesis";
1108 name = "Marvell Yukon";
1111 name = "Marvell Yukon Lite";
1112 switch (sc->sk_rev) {
1113 case SK_YUKON_LITE_REV_A0:
1116 case SK_YUKON_LITE_REV_A1:
1119 case SK_YUKON_LITE_REV_A3:
1125 name = "Marvell Yukon LP";
1131 ksnprintf(devname, sizeof(devname), "%s%s (0x%x)",
1132 name, revstr, sc->sk_rev);
1133 device_set_desc_copy(dev, devname);
1138 * Each XMAC chip is attached as a separate logical IP interface.
1139 * Single port cards will have only one logical interface of course.
1142 sk_attach(device_t dev)
1144 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1145 struct sk_if_softc *sc_if = device_get_softc(dev);
1146 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1149 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1151 sc_if->sk_port = *(int *)device_get_ivars(dev);
1152 KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B);
1154 sc_if->sk_softc = sc;
1155 sc->sk_if[sc_if->sk_port] = sc_if;
1157 kfree(device_get_ivars(dev), M_DEVBUF);
1158 device_set_ivars(dev, NULL);
1160 if (sc_if->sk_port == SK_PORT_A)
1161 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1162 if (sc_if->sk_port == SK_PORT_B)
1163 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1165 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1168 * Get station address for this interface. Note that
1169 * dual port cards actually come with three station
1170 * addresses: one for each port, plus an extra. The
1171 * extra one is used by the SysKonnect driver software
1172 * as a 'virtual' station address for when both ports
1173 * are operating in failover mode. Currently we don't
1174 * use this extra address.
1176 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1178 sc_if->arpcom.ac_enaddr[i] =
1179 sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i);
1183 * Set up RAM buffer addresses. The NIC will have a certain
1184 * amount of SRAM on it, somewhere between 512K and 2MB. We
1185 * need to divide this up a) between the transmitter and
1186 * receiver and b) between the two XMACs, if this is a
1187 * dual port NIC. Our algorithm is to divide up the memory
1188 * evenly so that everyone gets a fair share.
1190 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1191 uint32_t chunk, val;
1193 chunk = sc->sk_ramsize / 2;
1194 val = sc->sk_rboff / sizeof(uint64_t);
1195 sc_if->sk_rx_ramstart = val;
1196 val += (chunk / sizeof(uint64_t));
1197 sc_if->sk_rx_ramend = val - 1;
1198 sc_if->sk_tx_ramstart = val;
1199 val += (chunk / sizeof(uint64_t));
1200 sc_if->sk_tx_ramend = val - 1;
1202 uint32_t chunk, val;
1204 chunk = sc->sk_ramsize / 4;
1205 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1207 sc_if->sk_rx_ramstart = val;
1208 val += (chunk / sizeof(uint64_t));
1209 sc_if->sk_rx_ramend = val - 1;
1210 sc_if->sk_tx_ramstart = val;
1211 val += (chunk / sizeof(uint64_t));
1212 sc_if->sk_tx_ramend = val - 1;
1215 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1216 " tx_ramstart=%#x tx_ramend=%#x\n",
1217 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1218 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1220 /* Read and save PHY type */
1221 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1223 /* Set PHY address */
1224 if (SK_IS_GENESIS(sc)) {
1225 switch (sc_if->sk_phytype) {
1226 case SK_PHYTYPE_XMAC:
1227 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1229 case SK_PHYTYPE_BCOM:
1230 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1233 device_printf(dev, "unsupported PHY type: %d\n",
1240 if (SK_IS_YUKON(sc)) {
1241 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1242 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
1243 /* not initialized, punt */
1244 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1245 sc->sk_coppertype = 1;
1248 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1250 if (!(sc->sk_coppertype))
1251 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1254 error = sk_dma_alloc(dev);
1258 ifp->if_softc = sc_if;
1259 ifp->if_mtu = ETHERMTU;
1260 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1261 ifp->if_ioctl = sk_ioctl;
1262 ifp->if_start = sk_start;
1263 ifp->if_watchdog = sk_watchdog;
1264 ifp->if_init = sk_init;
1265 ifp->if_baudrate = 1000000000;
1266 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1267 ifq_set_ready(&ifp->if_snd);
1269 ifp->if_capabilities = IFCAP_VLAN_MTU;
1271 /* Don't use jumbo buffers by default */
1272 sc_if->sk_use_jumbo = 0;
1277 switch (sc->sk_type) {
1279 sk_init_xmac(sc_if);
1284 sk_init_yukon(sc_if);
1287 device_printf(dev, "unknown device type %d\n", sc->sk_type);
1292 DPRINTFN(2, ("sk_attach: 1\n"));
1294 error = mii_phy_probe(dev, &sc_if->sk_miibus,
1295 sk_ifmedia_upd, sk_ifmedia_sts);
1297 device_printf(dev, "no PHY found!\n");
1301 callout_init(&sc_if->sk_tick_timer);
1304 * Call MI attach routines.
1306 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer);
1308 DPRINTFN(2, ("sk_attach: end\n"));
1312 sc->sk_if[sc_if->sk_port] = NULL;
1317 * Attach the interface. Allocate softc structures, do ifmedia
1318 * setup and ethernet/BPF attach.
1321 skc_attach(device_t dev)
1323 struct sk_softc *sc = device_get_softc(dev);
1328 DPRINTFN(2, ("begin skc_attach\n"));
1330 lwkt_serialize_init(&sc->sk_serializer);
1332 #ifndef BURN_BRIDGES
1334 * Handle power management nonsense.
1336 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1337 uint32_t iobase, membase, irq;
1339 /* Save important PCI config data. */
1340 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1341 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1342 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1344 /* Reset the power state. */
1345 device_printf(dev, "chip is in D%d power mode "
1346 "-- setting to D0\n", pci_get_powerstate(dev));
1348 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1350 /* Restore PCI config data. */
1351 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1352 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1353 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1355 #endif /* BURN_BRIDGES */
1358 * Map control/status registers.
1360 pci_enable_busmaster(dev);
1362 sc->sk_res_rid = SK_PCI_LOMEM;
1363 sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1364 &sc->sk_res_rid, RF_ACTIVE);
1365 if (sc->sk_res == NULL) {
1366 device_printf(dev, "couldn't map memory\n");
1370 sc->sk_btag = rman_get_bustag(sc->sk_res);
1371 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1373 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1374 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1376 /* Bail out here if chip is not recognized */
1377 if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) {
1378 device_printf(dev, "unknown chip type: %d\n", sc->sk_type);
1383 DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
1385 /* Allocate interrupt */
1387 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid,
1388 RF_SHAREABLE | RF_ACTIVE);
1389 if (sc->sk_irq == NULL) {
1390 device_printf(dev, "couldn't map interrupt\n");
1395 /* Reset the adapter. */
1398 skrs = sk_win_read_1(sc, SK_EPROM0);
1399 if (SK_IS_GENESIS(sc)) {
1400 /* Read and save RAM size and RAMbuffer offset */
1402 case SK_RAMSIZE_512K_64:
1403 sc->sk_ramsize = 0x80000;
1404 sc->sk_rboff = SK_RBOFF_0;
1406 case SK_RAMSIZE_1024K_64:
1407 sc->sk_ramsize = 0x100000;
1408 sc->sk_rboff = SK_RBOFF_80000;
1410 case SK_RAMSIZE_1024K_128:
1411 sc->sk_ramsize = 0x100000;
1412 sc->sk_rboff = SK_RBOFF_0;
1414 case SK_RAMSIZE_2048K_128:
1415 sc->sk_ramsize = 0x200000;
1416 sc->sk_rboff = SK_RBOFF_0;
1419 device_printf(dev, "unknown ram size: %d\n", skrs);
1425 sc->sk_ramsize = 0x20000;
1427 sc->sk_ramsize = skrs * (1<<12);
1428 sc->sk_rboff = SK_RBOFF_0;
1431 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
1432 sc->sk_ramsize, sc->sk_ramsize / 1024,
1435 /* Read and save physical media type */
1436 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1438 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1439 sc->sk_coppertype = 1;
1441 sc->sk_coppertype = 0;
1443 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1444 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1448 flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1450 /* Test Flash-Address Register */
1451 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1452 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1454 if (testbyte != 0) {
1455 /* This is a Yukon Lite Rev A0 */
1456 sc->sk_type = SK_YUKON_LITE;
1457 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1458 /* Restore Flash-Address Register */
1459 sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1463 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1464 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1466 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1468 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1469 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1470 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1472 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1475 /* Turn on the 'driver is loaded' LED. */
1476 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1478 bus_generic_attach(dev);
1480 error = bus_setup_intr(dev, sc->sk_irq, INTR_NETSAFE, sk_intr, sc,
1481 &sc->sk_intrhand, &sc->sk_serializer);
1483 device_printf(dev, "couldn't set up irq\n");
1493 sk_detach(device_t dev)
1495 struct sk_if_softc *sc_if = device_get_softc(dev);
1496 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1498 if (device_is_attached(dev))
1499 ether_ifdetach(ifp);
1501 bus_generic_detach(dev);
1502 if (sc_if->sk_miibus != NULL)
1503 device_delete_child(dev, sc_if->sk_miibus);
1510 skc_detach(device_t dev)
1512 struct sk_softc *sc = device_get_softc(dev);
1515 if (device_is_attached(dev)) {
1516 lwkt_serialize_enter(&sc->sk_serializer);
1518 if (sc->sk_if[SK_PORT_A] != NULL)
1519 sk_stop(sc->sk_if[SK_PORT_A]);
1520 if (sc->sk_if[SK_PORT_B] != NULL)
1521 sk_stop(sc->sk_if[SK_PORT_B]);
1523 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1525 lwkt_serialize_exit(&sc->sk_serializer);
1528 bus_generic_detach(dev);
1529 if (sc->sk_devs[SK_PORT_A] != NULL) {
1530 port = device_get_ivars(sc->sk_devs[SK_PORT_A]);
1532 kfree(port, M_DEVBUF);
1533 device_set_ivars(sc->sk_devs[SK_PORT_A], NULL);
1535 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1537 if (sc->sk_devs[SK_PORT_B] != NULL) {
1538 port = device_get_ivars(sc->sk_devs[SK_PORT_B]);
1540 kfree(port, M_DEVBUF);
1541 device_set_ivars(sc->sk_devs[SK_PORT_B], NULL);
1543 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1546 if (sc->sk_irq != NULL) {
1547 bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid,
1550 if (sc->sk_res != NULL) {
1551 bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid,
1559 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx)
1561 struct sk_chain_data *cd = &sc_if->sk_cdata;
1562 struct sk_ring_data *rd = sc_if->sk_rdata;
1563 struct sk_tx_desc *f = NULL;
1564 uint32_t frag, cur, sk_ctl;
1565 struct sk_dma_ctx ctx;
1566 bus_dma_segment_t segs[SK_NTXSEG];
1570 DPRINTFN(2, ("sk_encap\n"));
1572 cur = frag = *txidx;
1576 sk_dump_mbuf(m_head);
1579 map = cd->sk_tx_dmap[*txidx];
1582 * Start packing the mbufs in this chain into
1583 * the fragment pointers. Stop when we run out
1584 * of fragments or hit the end of the mbuf chain.
1586 ctx.nsegs = SK_NTXSEG;
1588 error = bus_dmamap_load_mbuf(cd->sk_tx_dtag, map, m_head,
1589 sk_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1591 if_printf(&sc_if->arpcom.ac_if, "could not map TX mbuf\n");
1595 if ((SK_TX_RING_CNT - (cd->sk_tx_cnt + ctx.nsegs)) < 2) {
1596 bus_dmamap_unload(cd->sk_tx_dtag, map);
1597 DPRINTFN(2, ("sk_encap: too few descriptors free\n"));
1601 DPRINTFN(2, ("sk_encap: nsegs=%d\n", ctx.nsegs));
1603 /* Sync the DMA map. */
1604 bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE);
1606 for (i = 0; i < ctx.nsegs; i++) {
1607 f = &rd->sk_tx_ring[frag];
1608 f->sk_data_lo = htole32(segs[i].ds_addr);
1609 sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT;
1611 sk_ctl |= SK_TXCTL_FIRSTFRAG;
1613 sk_ctl |= SK_TXCTL_OWN;
1614 f->sk_ctl = htole32(sk_ctl);
1616 SK_INC(frag, SK_TX_RING_CNT);
1619 cd->sk_tx_mbuf[cur] = m_head;
1620 /* Switch DMA map */
1621 cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur];
1622 cd->sk_tx_dmap[cur] = map;
1624 rd->sk_tx_ring[cur].sk_ctl |=
1625 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
1626 rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN);
1628 /* Sync first descriptor to hand it off */
1629 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1630 BUS_DMASYNC_PREWRITE);
1632 sc_if->sk_cdata.sk_tx_cnt += ctx.nsegs;
1636 struct sk_tx_desc *desc;
1639 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1640 desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1641 sk_dump_txdesc(desc, idx);
1648 DPRINTFN(2, ("sk_encap: completed successfully\n"));
1654 sk_start(struct ifnet *ifp)
1656 struct sk_if_softc *sc_if = ifp->if_softc;
1657 struct sk_softc *sc = sc_if->sk_softc;
1658 struct mbuf *m_head = NULL;
1659 uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
1662 DPRINTFN(2, ("sk_start\n"));
1664 while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) {
1665 m_head = ifq_poll(&ifp->if_snd);
1670 * Pack the data into the transmit ring. If we
1671 * don't have room, set the OACTIVE flag and wait
1672 * for the NIC to drain the ring.
1674 if (sk_encap(sc_if, m_head, &idx)) {
1675 ifp->if_flags |= IFF_OACTIVE;
1679 /* now we are committed to transmit the packet */
1680 ifq_dequeue(&ifp->if_snd, m_head);
1683 BPF_MTAP(ifp, m_head);
1689 if (idx != sc_if->sk_cdata.sk_tx_prod) {
1690 sc_if->sk_cdata.sk_tx_prod = idx;
1691 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1693 /* Set a timeout in case the chip goes out to lunch. */
1699 sk_watchdog(struct ifnet *ifp)
1701 struct sk_if_softc *sc_if = ifp->if_softc;
1703 ASSERT_SERIALIZED(ifp->if_serializer);
1705 * Reclaim first as there is a possibility of losing Tx completion
1709 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1710 if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n");
1712 ifp->if_flags &= ~IFF_RUNNING;
1718 skc_shutdown(device_t dev)
1720 struct sk_softc *sc = device_get_softc(dev);
1722 DPRINTFN(2, ("sk_shutdown\n"));
1724 lwkt_serialize_enter(&sc->sk_serializer);
1726 /* Turn off the 'driver is loaded' LED. */
1727 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1730 * Reset the GEnesis controller. Doing this should also
1731 * assert the resets on the attached XMAC(s).
1735 lwkt_serialize_exit(&sc->sk_serializer);
1739 sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len)
1741 if (sc->sk_type == SK_GENESIS) {
1742 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
1743 XM_RXSTAT_BYTES(stat) != len)
1746 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1747 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1748 YU_RXSTAT_JABBER)) != 0 ||
1749 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1750 YU_RXSTAT_BYTES(stat) != len)
1758 sk_rxeof(struct sk_if_softc *sc_if)
1760 struct sk_softc *sc = sc_if->sk_softc;
1761 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1762 struct sk_chain_data *cd = &sc_if->sk_cdata;
1763 struct sk_ring_data *rd = sc_if->sk_rdata;
1764 int i, reap, max_frmlen;
1766 DPRINTFN(2, ("sk_rxeof\n"));
1770 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1771 BUS_DMASYNC_POSTREAD);
1772 if (sc_if->sk_use_jumbo) {
1773 bus_dmamap_sync(cd->sk_jpool_dtag, cd->sk_jpool_dmap,
1774 BUS_DMASYNC_POSTREAD);
1775 max_frmlen = SK_JUMBO_FRAMELEN;
1777 max_frmlen = ETHER_MAX_LEN;
1782 struct sk_rx_desc *cur_desc;
1783 uint32_t rxstat, sk_ctl;
1785 uint16_t csum1, csum2;
1791 cur_desc = &rd->sk_rx_ring[cur];
1793 sk_ctl = le32toh(cur_desc->sk_ctl);
1794 if (sk_ctl & SK_RXCTL_OWN) {
1795 /* Invalidate the descriptor -- it's not ready yet */
1796 cd->sk_rx_prod = cur;
1800 rxstat = le32toh(cur_desc->sk_xmac_rxstat);
1801 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl));
1804 csum1 = le16toh(cur_desc->sk_csum1);
1805 csum2 = le16toh(cur_desc->sk_csum2);
1808 m = cd->sk_rx_mbuf[cur];
1811 * Bump 'i' here, so we can keep going, even if the current
1812 * RX descriptor reaping fails later. 'i' shoult NOT be used
1813 * in the following processing any more.
1815 SK_INC(i, SK_RX_RING_CNT);
1818 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
1819 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
1820 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
1821 total_len < SK_MIN_FRAMELEN || total_len > max_frmlen ||
1822 sk_rxvalid(sc, rxstat, total_len) == 0) {
1824 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1828 if (!sc_if->sk_use_jumbo) {
1829 bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[cur],
1830 BUS_DMASYNC_POSTREAD);
1834 * Try to allocate a new RX buffer. If that fails,
1835 * copy the packet to mbufs and put the RX buffer
1836 * back in the ring so it can be re-used. If
1837 * allocating mbufs fails, then we have to drop
1840 if (sk_newbuf(sc_if, cur, 0)) {
1843 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1845 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1846 total_len + ETHER_ALIGN, 0, ifp, NULL);
1851 m_adj(m0, ETHER_ALIGN);
1854 m->m_pkthdr.rcvif = ifp;
1855 m->m_pkthdr.len = m->m_len = total_len;
1859 sk_rxcsum(ifp, m, csum1, csum2);
1863 ifp->if_input(ifp, m);
1867 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1868 BUS_DMASYNC_PREWRITE);
1874 sk_rxcsum(struct ifnet *ifp, struct mbuf *m,
1875 const uint16_t csum1, const uint16_t csum2)
1877 struct ether_header *eh;
1880 int hlen, len, plen;
1881 uint16_t iph_csum, ipo_csum, ipd_csum, csum;
1883 pp = mtod(m, uint8_t *);
1884 plen = m->m_pkthdr.len;
1885 if (plen < sizeof(*eh))
1887 eh = (struct ether_header *)pp;
1888 iph_csum = in_addword(csum1, (~csum2 & 0xffff));
1890 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1891 uint16_t *xp = (uint16_t *)pp;
1893 xp = (uint16_t *)pp;
1894 if (xp[1] != htons(ETHERTYPE_IP))
1896 iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff));
1897 iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff));
1898 xp = (uint16_t *)(pp + sizeof(struct ip));
1899 iph_csum = in_addword(iph_csum, xp[0]);
1900 iph_csum = in_addword(iph_csum, xp[1]);
1902 } else if (eh->ether_type != htons(ETHERTYPE_IP)) {
1907 plen -= sizeof(*eh);
1909 ip = (struct ip *)pp;
1911 if (ip->ip_v != IPVERSION)
1914 hlen = ip->ip_hl << 2;
1915 if (hlen < sizeof(struct ip))
1917 if (hlen > ntohs(ip->ip_len))
1920 /* Don't deal with truncated or padded packets. */
1921 if (plen != ntohs(ip->ip_len))
1924 len = hlen - sizeof(struct ip);
1928 p = (uint16_t *)(ip + 1);
1930 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++)
1931 ipo_csum = in_addword(ipo_csum, *p);
1932 iph_csum = in_addword(iph_csum, ipo_csum);
1933 ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff));
1938 if (iph_csum != 0xffff)
1940 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID;
1942 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1943 return; /* ip frag, we're done for now */
1947 /* Only know checksum protocol for udp/tcp */
1948 if (ip->ip_p == IPPROTO_UDP) {
1949 struct udphdr *uh = (struct udphdr *)pp;
1951 if (uh->uh_sum == 0) /* udp with no checksum */
1953 } else if (ip->ip_p != IPPROTO_TCP) {
1957 csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1958 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum);
1959 if (csum == 0xffff) {
1960 m->m_pkthdr.csum_data = csum;
1961 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1967 sk_txeof(struct sk_if_softc *sc_if)
1969 struct sk_chain_data *cd = &sc_if->sk_cdata;
1970 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1974 DPRINTFN(2, ("sk_txeof\n"));
1976 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1977 BUS_DMASYNC_POSTREAD);
1980 * Go through our tx ring and free mbufs for those
1981 * frames that have been sent.
1983 idx = cd->sk_tx_cons;
1984 while (idx != cd->sk_tx_prod) {
1985 struct sk_tx_desc *cur_tx;
1988 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1989 sk_ctl = le32toh(cur_tx->sk_ctl);
1992 sk_dump_txdesc(cur_tx, idx);
1994 if (sk_ctl & SK_TXCTL_OWN)
1996 if (sk_ctl & SK_TXCTL_LASTFRAG)
1998 if (cd->sk_tx_mbuf[idx] != NULL) {
1999 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]);
2000 m_freem(cd->sk_tx_mbuf[idx]);
2001 cd->sk_tx_mbuf[idx] = NULL;
2003 sc_if->sk_cdata.sk_tx_cnt--;
2005 SK_INC(idx, SK_TX_RING_CNT);
2007 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2009 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2)
2010 ifp->if_flags &= ~IFF_OACTIVE;
2012 sc_if->sk_cdata.sk_tx_cons = idx;
2015 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
2016 BUS_DMASYNC_PREWRITE);
2021 sk_tick(void *xsc_if)
2023 struct sk_if_softc *sc_if = xsc_if;
2024 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2025 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2028 DPRINTFN(2, ("sk_tick\n"));
2030 lwkt_serialize_enter(ifp->if_serializer);
2032 if ((ifp->if_flags & IFF_UP) == 0) {
2033 lwkt_serialize_exit(ifp->if_serializer);
2037 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2038 sk_intr_bcom(sc_if);
2039 lwkt_serialize_exit(ifp->if_serializer);
2044 * According to SysKonnect, the correct way to verify that
2045 * the link has come back up is to poll bit 0 of the GPIO
2046 * register three times. This pin has the signal from the
2047 * link sync pin connected to it; if we read the same link
2048 * state 3 times in a row, we know the link is up.
2050 for (i = 0; i < 3; i++) {
2051 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2056 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
2057 lwkt_serialize_exit(ifp->if_serializer);
2061 /* Turn the GP0 interrupt back on. */
2062 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2063 SK_XM_READ_2(sc_if, XM_ISR);
2065 callout_stop(&sc_if->sk_tick_timer);
2066 lwkt_serialize_exit(ifp->if_serializer);
2070 sk_yukon_tick(void *xsc_if)
2072 struct sk_if_softc *sc_if = xsc_if;
2073 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2074 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2076 lwkt_serialize_enter(ifp->if_serializer);
2078 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2079 lwkt_serialize_exit(ifp->if_serializer);
2083 sk_intr_bcom(struct sk_if_softc *sc_if)
2085 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2086 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2089 DPRINTFN(2, ("sk_intr_bcom\n"));
2091 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2094 * Read the PHY interrupt register to make sure
2095 * we clear any pending interrupts.
2097 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2099 if ((ifp->if_flags & IFF_RUNNING) == 0) {
2100 sk_init_xmac(sc_if);
2104 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2107 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2110 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2112 /* Turn off the link LED. */
2113 SK_IF_WRITE_1(sc_if, 0,
2114 SK_LINKLED1_CTL, SK_LINKLED_OFF);
2116 } else if (status & BRGPHY_ISR_LNK_CHG) {
2117 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2118 BRGPHY_MII_IMR, 0xFF00);
2121 /* Turn on the link LED. */
2122 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2123 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2124 SK_LINKLED_BLINK_OFF);
2127 callout_reset(&sc_if->sk_tick_timer, hz,
2132 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2136 sk_intr_xmac(struct sk_if_softc *sc_if)
2140 status = SK_XM_READ_2(sc_if, XM_ISR);
2141 DPRINTFN(2, ("sk_intr_xmac\n"));
2143 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC &&
2144 (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) {
2145 if (status & XM_ISR_GP0_SET)
2146 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2148 callout_reset(&sc_if->sk_tick_timer, hz,
2152 if (status & XM_IMR_TX_UNDERRUN)
2153 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2155 if (status & XM_IMR_RX_OVERRUN)
2156 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2160 sk_intr_yukon(struct sk_if_softc *sc_if)
2164 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2166 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2167 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2168 SK_RFCTL_RX_FIFO_OVER);
2171 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2172 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2173 SK_TFCTL_TX_FIFO_UNDER);
2176 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
2182 struct sk_softc *sc = xsc;
2183 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2184 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
2185 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2188 ASSERT_SERIALIZED(&sc->sk_serializer);
2190 status = CSR_READ_4(sc, SK_ISSR);
2191 if (status == 0 || status == 0xffffffff)
2195 ifp0 = &sc_if0->arpcom.ac_if;
2197 ifp1 = &sc_if1->arpcom.ac_if;
2199 for (; (status &= sc->sk_intrmask) != 0;) {
2200 /* Handle receive interrupts first. */
2201 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
2203 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2204 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2206 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
2208 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2209 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2212 /* Then transmit interrupts. */
2213 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
2215 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2216 SK_TXBMU_CLR_IRQ_EOF);
2218 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
2220 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2221 SK_TXBMU_CLR_IRQ_EOF);
2224 /* Then MAC interrupts. */
2225 if (sc_if0 && (status & SK_ISR_MAC1) &&
2226 (ifp0->if_flags & IFF_RUNNING)) {
2227 if (SK_IS_GENESIS(sc))
2228 sk_intr_xmac(sc_if0);
2230 sk_intr_yukon(sc_if0);
2233 if (sc_if1 && (status & SK_ISR_MAC2) &&
2234 (ifp1->if_flags & IFF_RUNNING)) {
2235 if (SK_IS_GENESIS(sc))
2236 sk_intr_xmac(sc_if1);
2238 sk_intr_yukon(sc_if1);
2241 if (status & SK_ISR_EXTERNAL_REG) {
2242 if (sc_if0 != NULL &&
2243 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2244 sk_intr_bcom(sc_if0);
2246 if (sc_if1 != NULL &&
2247 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2248 sk_intr_bcom(sc_if1);
2250 status = CSR_READ_4(sc, SK_ISSR);
2253 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2255 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2257 if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd))
2262 sk_init_xmac(struct sk_if_softc *sc_if)
2264 struct sk_softc *sc = sc_if->sk_softc;
2265 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2266 static const struct sk_bcom_hack bhack[] = {
2267 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2268 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2269 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2272 DPRINTFN(2, ("sk_init_xmac\n"));
2274 /* Unreset the XMAC. */
2275 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2278 /* Reset the XMAC's internal state. */
2279 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2281 /* Save the XMAC II revision */
2282 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2285 * Perform additional initialization for external PHYs,
2286 * namely for the 1000baseTX cards that use the XMAC's
2289 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2293 /* Take PHY out of reset. */
2294 val = sk_win_read_4(sc, SK_GPIO);
2295 if (sc_if->sk_port == SK_PORT_A)
2296 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2298 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2299 sk_win_write_4(sc, SK_GPIO, val);
2301 /* Enable GMII mode on the XMAC. */
2302 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2304 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2305 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2307 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2308 BRGPHY_MII_IMR, 0xFFF0);
2311 * Early versions of the BCM5400 apparently have
2312 * a bug that requires them to have their reserved
2313 * registers initialized to some magic values. I don't
2314 * know what the numbers do, I'm just the messenger.
2316 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2318 while(bhack[i].reg) {
2319 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2320 bhack[i].reg, bhack[i].val);
2326 /* Set station address */
2327 SK_XM_WRITE_2(sc_if, XM_PAR0,
2328 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2329 SK_XM_WRITE_2(sc_if, XM_PAR1,
2330 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2331 SK_XM_WRITE_2(sc_if, XM_PAR2,
2332 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2333 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2335 if (ifp->if_flags & IFF_BROADCAST)
2336 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2338 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2340 /* We don't need the FCS appended to the packet. */
2341 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2343 /* We want short frames padded to 60 bytes. */
2344 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2347 * Enable the reception of all error frames. This is
2348 * a necessary evil due to the design of the XMAC. The
2349 * XMAC's receive FIFO is only 8K in size, however jumbo
2350 * frames can be up to 9000 bytes in length. When bad
2351 * frame filtering is enabled, the XMAC's RX FIFO operates
2352 * in 'store and forward' mode. For this to work, the
2353 * entire frame has to fit into the FIFO, but that means
2354 * that jumbo frames larger than 8192 bytes will be
2355 * truncated. Disabling all bad frame filtering causes
2356 * the RX FIFO to operate in streaming mode, in which
2357 * case the XMAC will start transfering frames out of the
2358 * RX FIFO as soon as the FIFO threshold is reached.
2360 if (sc_if->sk_use_jumbo) {
2361 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2362 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2363 XM_MODE_RX_INRANGELEN);
2366 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2369 * Bump up the transmit threshold. This helps hold off transmit
2370 * underruns when we're blasting traffic from both ports at once.
2372 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2374 /* Set promiscuous mode */
2375 sk_setpromisc(sc_if);
2377 /* Set multicast filter */
2380 /* Clear and enable interrupts */
2381 SK_XM_READ_2(sc_if, XM_ISR);
2382 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2383 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2385 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2387 /* Configure MAC arbiter */
2388 switch(sc_if->sk_xmac_rev) {
2389 case XM_XMAC_REV_B2:
2390 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2391 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2392 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2393 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2394 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2395 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2396 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2397 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2398 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2400 case XM_XMAC_REV_C1:
2401 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2402 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2403 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2404 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2405 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2406 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2407 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2408 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2409 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2414 sk_win_write_2(sc, SK_MACARB_CTL,
2415 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2421 sk_init_yukon(struct sk_if_softc *sc_if)
2425 struct sk_softc *sc;
2428 sc = sc_if->sk_softc;
2430 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
2431 CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2433 if (sc->sk_type == SK_YUKON_LITE &&
2434 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2436 * Workaround code for COMA mode, set PHY reset.
2437 * Otherwise it will not correctly take chip out of
2440 v = sk_win_read_4(sc, SK_GPIO);
2441 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
2442 sk_win_write_4(sc, SK_GPIO, v);
2445 DPRINTFN(6, ("sk_init_yukon: 1\n"));
2447 /* GMAC and GPHY Reset */
2448 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2449 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2452 DPRINTFN(6, ("sk_init_yukon: 2\n"));
2454 if (sc->sk_type == SK_YUKON_LITE &&
2455 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2457 * Workaround code for COMA mode, clear PHY reset
2459 v = sk_win_read_4(sc, SK_GPIO);
2462 sk_win_write_4(sc, SK_GPIO, v);
2465 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2466 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2468 if (sc->sk_coppertype)
2469 phy |= SK_GPHY_COPPER;
2471 phy |= SK_GPHY_FIBER;
2473 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
2475 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2477 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2478 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2479 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2481 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2482 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2484 DPRINTFN(6, ("sk_init_yukon: 3\n"));
2486 /* unused read of the interrupt source register */
2487 DPRINTFN(6, ("sk_init_yukon: 4\n"));
2488 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2490 DPRINTFN(6, ("sk_init_yukon: 4a\n"));
2491 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2492 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2494 /* MIB Counter Clear Mode set */
2495 reg |= YU_PAR_MIB_CLR;
2496 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2497 DPRINTFN(6, ("sk_init_yukon: 4b\n"));
2498 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2500 /* MIB Counter Clear Mode clear */
2501 DPRINTFN(6, ("sk_init_yukon: 5\n"));
2502 reg &= ~YU_PAR_MIB_CLR;
2503 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2505 /* receive control reg */
2506 DPRINTFN(6, ("sk_init_yukon: 7\n"));
2507 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2509 /* transmit parameter register */
2510 DPRINTFN(6, ("sk_init_yukon: 8\n"));
2511 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2512 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2514 /* serial mode register */
2515 DPRINTFN(6, ("sk_init_yukon: 9\n"));
2516 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2517 if (sc_if->sk_use_jumbo)
2518 reg |= YU_SMR_MFL_JUMBO;
2519 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2521 DPRINTFN(6, ("sk_init_yukon: 10\n"));
2522 /* Setup Yukon's address */
2523 for (i = 0; i < 3; i++) {
2524 /* Write Source Address 1 (unicast filter) */
2525 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2526 sc_if->arpcom.ac_enaddr[i * 2] |
2527 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2530 for (i = 0; i < 3; i++) {
2531 reg = sk_win_read_2(sc_if->sk_softc,
2532 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2533 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2536 /* Set promiscuous mode */
2537 sk_setpromisc(sc_if);
2539 /* Set multicast filter */
2540 DPRINTFN(6, ("sk_init_yukon: 11\n"));
2543 /* enable interrupt mask for counter overflows */
2544 DPRINTFN(6, ("sk_init_yukon: 12\n"));
2545 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2546 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2547 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2549 /* Configure RX MAC FIFO Flush Mask */
2550 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2551 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2553 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2555 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
2556 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
2557 v = SK_TFCTL_OPERATION_ON;
2559 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
2560 /* Configure RX MAC FIFO */
2561 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2562 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2564 /* Increase flush threshould to 64 bytes */
2565 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2566 SK_RFCTL_FIFO_THRESHOLD + 1);
2568 /* Configure TX MAC FIFO */
2569 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2570 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2572 DPRINTFN(6, ("sk_init_yukon: end\n"));
2576 * Note that to properly initialize any part of the GEnesis chip,
2577 * you first have to take it out of reset mode.
2580 sk_init(void *xsc_if)
2582 struct sk_if_softc *sc_if = xsc_if;
2583 struct sk_softc *sc = sc_if->sk_softc;
2584 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2585 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2587 DPRINTFN(2, ("sk_init\n"));
2589 ASSERT_SERIALIZED(ifp->if_serializer);
2591 if (ifp->if_flags & IFF_RUNNING)
2594 /* Cancel pending I/O and free all RX/TX buffers. */
2598 * NOTE: Change sk_use_jumbo after sk_stop(),
2599 * but before real initialization.
2601 if (ifp->if_mtu > ETHER_MAX_LEN)
2602 sc_if->sk_use_jumbo = 1;
2604 sc_if->sk_use_jumbo = 0;
2605 DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO"));
2607 if (SK_IS_GENESIS(sc)) {
2608 /* Configure LINK_SYNC LED */
2609 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2610 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2611 SK_LINKLED_LINKSYNC_ON);
2613 /* Configure RX LED */
2614 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2615 SK_RXLEDCTL_COUNTER_START);
2617 /* Configure TX LED */
2618 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2619 SK_TXLEDCTL_COUNTER_START);
2623 * Configure descriptor poll timer
2625 * SK-NET GENESIS data sheet says that possibility of losing Start
2626 * transmit command due to CPU/cache related interim storage problems
2627 * under certain conditions. The document recommends a polling
2628 * mechanism to send a Start transmit command to initiate transfer
2629 * of ready descriptors regulary. To cope with this issue sk(4) now
2630 * enables descriptor poll timer to initiate descriptor processing
2631 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
2632 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
2633 * command instead of waiting for next descriptor polling time.
2634 * The same rule may apply to Rx side too but it seems that is not
2635 * needed at the moment.
2636 * Since sk(4) uses descriptor polling as a last resort there is no
2637 * need to set smaller polling time than maximum allowable one.
2639 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
2641 /* Configure I2C registers */
2643 /* Configure XMAC(s) */
2644 switch (sc->sk_type) {
2646 sk_init_xmac(sc_if);
2651 sk_init_yukon(sc_if);
2656 if (SK_IS_GENESIS(sc)) {
2657 /* Configure MAC FIFOs */
2658 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2659 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2660 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2662 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2663 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2664 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2667 /* Configure transmit arbiter(s) */
2668 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2669 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2671 /* Configure RAMbuffers */
2672 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2673 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2674 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2675 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2676 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2677 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2679 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2680 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2681 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2682 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2683 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2684 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2685 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2687 /* Configure BMUs */
2688 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2689 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2690 SK_RX_RING_ADDR(sc_if, 0));
2691 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2693 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2694 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2695 SK_TX_RING_ADDR(sc_if, 0));
2696 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2698 /* Init descriptors */
2699 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2700 if_printf(ifp, "initialization failed: "
2701 "no memory for rx buffers\n");
2706 if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2707 if_printf(ifp, "initialization failed: "
2708 "no memory for tx buffers\n");
2713 /* Configure interrupt handling */
2714 CSR_READ_4(sc, SK_ISSR);
2715 if (sc_if->sk_port == SK_PORT_A)
2716 sc->sk_intrmask |= SK_INTRS1;
2718 sc->sk_intrmask |= SK_INTRS2;
2720 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2722 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2725 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2727 if (SK_IS_GENESIS(sc)) {
2728 /* Enable XMACs TX and RX state machines */
2729 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2730 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2731 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2734 if (SK_IS_YUKON(sc)) {
2735 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2736 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2738 /* XXX disable 100Mbps and full duplex mode? */
2739 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
2741 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2744 /* Activate descriptor polling timer */
2745 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
2746 /* Start transfer of Tx descriptors */
2747 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2749 ifp->if_flags |= IFF_RUNNING;
2750 ifp->if_flags &= ~IFF_OACTIVE;
2752 if (SK_IS_YUKON(sc))
2753 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2757 sk_stop(struct sk_if_softc *sc_if)
2759 struct sk_softc *sc = sc_if->sk_softc;
2760 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2761 struct sk_chain_data *cd = &sc_if->sk_cdata;
2765 ASSERT_SERIALIZED(ifp->if_serializer);
2767 DPRINTFN(2, ("sk_stop\n"));
2769 callout_stop(&sc_if->sk_tick_timer);
2771 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2773 /* Stop Tx descriptor polling timer */
2774 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
2776 /* Stop transfer of Tx descriptors */
2777 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
2778 for (i = 0; i < SK_TIMEOUT; i++) {
2779 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
2780 if (!(val & SK_TXBMU_TX_STOP))
2784 if (i == SK_TIMEOUT)
2785 if_printf(ifp, "cannot stop transfer of Tx descriptors\n");
2787 /* Stop transfer of Rx descriptors */
2788 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
2789 for (i = 0; i < SK_TIMEOUT; i++) {
2790 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
2791 if (!(val & SK_RXBMU_RX_STOP))
2795 if (i == SK_TIMEOUT)
2796 if_printf(ifp, "cannot stop transfer of Rx descriptors\n");
2798 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2799 /* Put PHY back into reset. */
2800 val = sk_win_read_4(sc, SK_GPIO);
2801 if (sc_if->sk_port == SK_PORT_A) {
2802 val |= SK_GPIO_DIR0;
2803 val &= ~SK_GPIO_DAT0;
2805 val |= SK_GPIO_DIR2;
2806 val &= ~SK_GPIO_DAT2;
2808 sk_win_write_4(sc, SK_GPIO, val);
2811 /* Turn off various components of this interface. */
2812 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2813 switch (sc->sk_type) {
2815 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2816 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2821 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2822 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2825 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2826 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2827 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2828 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2829 SK_RBCTL_RESET | SK_RBCTL_OFF);
2830 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2831 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2832 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2833 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2834 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2836 /* Disable interrupts */
2837 if (sc_if->sk_port == SK_PORT_A)
2838 sc->sk_intrmask &= ~SK_INTRS1;
2840 sc->sk_intrmask &= ~SK_INTRS2;
2841 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2843 SK_XM_READ_2(sc_if, XM_ISR);
2844 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2846 /* Free RX and TX mbufs still in the queues. */
2847 for (i = 0; i < SK_RX_RING_CNT; i++) {
2848 if (cd->sk_rx_mbuf[i] != NULL) {
2849 if (!sc_if->sk_use_jumbo) {
2850 bus_dmamap_unload(cd->sk_rx_dtag,
2853 m_freem(cd->sk_rx_mbuf[i]);
2854 cd->sk_rx_mbuf[i] = NULL;
2857 for (i = 0; i < SK_TX_RING_CNT; i++) {
2858 if (cd->sk_tx_mbuf[i] != NULL) {
2859 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
2860 m_freem(cd->sk_tx_mbuf[i]);
2861 cd->sk_tx_mbuf[i] = NULL;
2868 sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
2870 #define DESC_PRINT(X) \
2872 kprintf("txdesc[%d]." #X "=%#x\n", \
2875 DESC_PRINT(le32toh(desc->sk_ctl));
2876 DESC_PRINT(le32toh(desc->sk_next));
2877 DESC_PRINT(le32toh(desc->sk_data_lo));
2878 DESC_PRINT(le32toh(desc->sk_data_hi));
2879 DESC_PRINT(le32toh(desc->sk_xmac_txstat));
2880 DESC_PRINT(le16toh(desc->sk_rsvd0));
2881 DESC_PRINT(le16toh(desc->sk_csum_startval));
2882 DESC_PRINT(le16toh(desc->sk_csum_startpos));
2883 DESC_PRINT(le16toh(desc->sk_csum_writepos));
2884 DESC_PRINT(le16toh(desc->sk_rsvd1));
2889 sk_dump_bytes(const char *data, int len)
2893 for (i = 0; i < len; i += 16) {
2894 kprintf("%08x ", i);
2898 for (j = 0; j < c; j++) {
2899 kprintf("%02x ", data[i + j] & 0xff);
2900 if ((j & 0xf) == 7 && j > 0)
2908 for (j = 0; j < c; j++) {
2909 int ch = data[i + j] & 0xff;
2910 kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2921 sk_dump_mbuf(struct mbuf *m)
2923 int count = m->m_pkthdr.len;
2925 kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2927 while (count > 0 && m) {
2928 kprintf("m=%p, m->m_data=%p, m->m_len=%d\n",
2929 m, m->m_data, m->m_len);
2930 sk_dump_bytes(mtod(m, char *), m->m_len);
2939 * Allocate jumbo buffer storage. The SysKonnect adapters support
2940 * "jumbograms" (9K frames), although SysKonnect doesn't currently
2941 * use them in their drivers. In order for us to use them, we need
2942 * large 9K receive buffers, however standard mbuf clusters are only
2943 * 2048 bytes in size. Consequently, we need to allocate and manage
2944 * our own jumbo buffer pool. Fortunately, this does not require an
2945 * excessive amount of additional code.
2948 sk_jpool_alloc(device_t dev)
2950 struct sk_if_softc *sc_if = device_get_softc(dev);
2951 struct sk_chain_data *cd = &sc_if->sk_cdata;
2956 lwkt_serialize_init(&cd->sk_jpool_serializer);
2958 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
2959 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
2960 NULL, NULL, SK_JMEM, 1, SK_JMEM,
2961 0, &cd->sk_jpool_dtag);
2963 device_printf(dev, "can't create jpool DMA tag\n");
2967 error = bus_dmamem_alloc(cd->sk_jpool_dtag, &cd->sk_jpool,
2968 BUS_DMA_WAITOK, &cd->sk_jpool_dmap);
2970 device_printf(dev, "can't alloc jpool DMA mem\n");
2971 bus_dma_tag_destroy(cd->sk_jpool_dtag);
2972 cd->sk_jpool_dtag = NULL;
2976 error = bus_dmamap_load(cd->sk_jpool_dtag, cd->sk_jpool_dmap,
2977 cd->sk_jpool, SK_JMEM,
2978 sk_dmamem_addr, &paddr, BUS_DMA_WAITOK);
2980 device_printf(dev, "can't load DMA mem\n");
2981 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
2983 bus_dma_tag_destroy(cd->sk_jpool_dtag);
2984 cd->sk_jpool_dtag = NULL;
2988 SLIST_INIT(&cd->sk_jpool_free_ent);
2992 * Now divide it up into SK_JLEN pieces.
2994 for (i = 0; i < SK_JSLOTS; i++) {
2995 struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i];
2997 entry->sc_if = sc_if;
3001 entry->paddr = paddr;
3003 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
3012 sk_jpool_free(struct sk_if_softc *sc_if)
3014 struct sk_chain_data *cd = &sc_if->sk_cdata;
3016 if (cd->sk_jpool_dtag != NULL) {
3017 bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap);
3018 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
3020 bus_dma_tag_destroy(cd->sk_jpool_dtag);
3021 cd->sk_jpool_dtag = NULL;
3026 sk_dma_alloc(device_t dev)
3028 struct sk_if_softc *sc_if = device_get_softc(dev);
3029 struct sk_chain_data *cd = &sc_if->sk_cdata;
3033 * Allocate the descriptor queues.
3034 * TODO: split into RX/TX rings
3036 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
3037 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3039 sizeof(struct sk_ring_data), 1,
3040 sizeof(struct sk_ring_data), 0,
3041 &sc_if->sk_rdata_dtag);
3043 device_printf(dev, "can't create desc DMA tag\n");
3047 error = bus_dmamem_alloc(sc_if->sk_rdata_dtag,
3048 (void **)&sc_if->sk_rdata,
3049 BUS_DMA_WAITOK | BUS_DMA_ZERO,
3050 &sc_if->sk_rdata_dmap);
3052 device_printf(dev, "can't alloc desc DMA mem\n");
3053 bus_dma_tag_destroy(sc_if->sk_rdata_dtag);
3054 sc_if->sk_rdata_dtag = NULL;
3058 error = bus_dmamap_load(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
3059 sc_if->sk_rdata, sizeof(struct sk_ring_data),
3060 sk_dmamem_addr, &sc_if->sk_rdata_paddr,
3063 device_printf(dev, "can't load desc DMA mem\n");
3064 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata,
3065 sc_if->sk_rdata_dmap);
3066 bus_dma_tag_destroy(sc_if->sk_rdata_dtag);
3067 sc_if->sk_rdata_dtag = NULL;
3071 /* Try to allocate memory for jumbo buffers. */
3072 error = sk_jpool_alloc(dev);
3074 device_printf(dev, "jumbo buffer allocation failed\n");
3078 /* Create DMA tag for TX. */
3079 error = bus_dma_tag_create(NULL, 1, 0,
3080 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3082 SK_JLEN, SK_NTXSEG, SK_JLEN,
3083 0, &cd->sk_tx_dtag);
3085 device_printf(dev, "can't create TX DMA tag\n");
3089 /* Create DMA maps for TX. */
3090 for (i = 0; i < SK_TX_RING_CNT; i++) {
3091 error = bus_dmamap_create(cd->sk_tx_dtag, 0,
3092 &cd->sk_tx_dmap[i]);
3094 device_printf(dev, "can't create %dth TX DMA map\n", i);
3096 for (j = 0; j < i; ++j) {
3097 bus_dmamap_destroy(cd->sk_tx_dtag,
3100 bus_dma_tag_destroy(cd->sk_tx_dtag);
3101 cd->sk_tx_dtag = NULL;
3106 /* Create DMA tag for RX. */
3107 error = bus_dma_tag_create(NULL, 1, 0,
3108 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3109 NULL, NULL, MCLBYTES, 1, MCLBYTES,
3110 0, &cd->sk_rx_dtag);
3112 device_printf(dev, "can't create RX DMA tag\n");
3116 /* Create a spare RX DMA map. */
3117 error = bus_dmamap_create(cd->sk_rx_dtag, 0, &cd->sk_rx_dmap_tmp);
3119 device_printf(dev, "can't create spare RX DMA map\n");
3120 bus_dma_tag_destroy(cd->sk_rx_dtag);
3121 cd->sk_rx_dtag = NULL;
3125 /* Create DMA maps for RX. */
3126 for (i = 0; i < SK_RX_RING_CNT; ++i) {
3127 error = bus_dmamap_create(cd->sk_rx_dtag, 0,
3128 &cd->sk_rx_dmap[i]);
3130 device_printf(dev, "can't create %dth RX DMA map\n", i);
3132 for (j = 0; j < i; ++j) {
3133 bus_dmamap_destroy(cd->sk_rx_dtag,
3136 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3137 bus_dma_tag_destroy(cd->sk_rx_dtag);
3138 cd->sk_rx_dtag = NULL;
3146 sk_dma_free(device_t dev)
3148 struct sk_if_softc *sc_if = device_get_softc(dev);
3149 struct sk_chain_data *cd = &sc_if->sk_cdata;
3152 if (cd->sk_tx_dtag != NULL) {
3153 for (i = 0; i < SK_TX_RING_CNT; ++i) {
3154 KASSERT(cd->sk_tx_mbuf[i] == NULL,
3155 ("sk_stop() is not called before %s()",
3157 bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
3159 bus_dma_tag_destroy(cd->sk_tx_dtag);
3160 cd->sk_tx_dtag = NULL;
3163 if (cd->sk_rx_dtag != NULL) {
3164 for (i = 0; i < SK_RX_RING_CNT; ++i) {
3165 KASSERT(cd->sk_rx_mbuf[i] == NULL,
3166 ("sk_stop() is not called before %s()",
3168 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]);
3170 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3171 bus_dma_tag_destroy(cd->sk_rx_dtag);
3172 cd->sk_rx_dtag = NULL;
3175 sk_jpool_free(sc_if);
3177 if (sc_if->sk_rdata_dtag != NULL) {
3178 bus_dmamap_unload(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap);
3179 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata,
3180 sc_if->sk_rdata_dmap);
3181 bus_dma_tag_destroy(sc_if->sk_rdata_dtag);
3182 sc_if->sk_rdata_dtag = NULL;
3187 sk_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
3188 bus_size_t mapsz __unused, int error)
3190 struct sk_dma_ctx *ctx = arg;
3196 KASSERT(nsegs <= ctx->nsegs,
3197 ("too many segments(%d), should be <= %d\n",
3198 nsegs, ctx->nsegs));
3201 for (i = 0; i < nsegs; ++i)
3202 ctx->segs[i] = segs[i];
3206 sk_dmamem_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3208 KASSERT(nseg == 1, ("too many segments %d", nseg));
3209 *((bus_addr_t *)arg) = seg->ds_addr;